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461b9befa776945cca24470932eb5430e3986830
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - tail;
56 if (space <= 0)
57 space += size;
58 return space - I915_RING_FREE_SPACE;
59 }
60
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62 {
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70 }
71
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
73 {
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
76 }
77
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
79 {
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82 }
83
84 void __intel_ring_advance(struct intel_engine_cs *ring)
85 {
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
89 return;
90 ring->write_tail(ring, ringbuf->tail);
91 }
92
93 static int
94 gen2_render_ring_flush(struct intel_engine_cs *ring,
95 u32 invalidate_domains,
96 u32 flush_domains)
97 {
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117 }
118
119 static int
120 gen4_render_ring_flush(struct intel_engine_cs *ring,
121 u32 invalidate_domains,
122 u32 flush_domains)
123 {
124 struct drm_device *dev = ring->dev;
125 u32 cmd;
126 int ret;
127
128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
158 cmd &= ~MI_NO_WRITE_FLUSH;
159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
161
162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
165
166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
169
170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
173
174 return 0;
175 }
176
177 /**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214 static int
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
216 {
217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247 }
248
249 static int
250 gen6_render_ring_flush(struct intel_engine_cs *ring,
251 u32 invalidate_domains, u32 flush_domains)
252 {
253 u32 flags = 0;
254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
255 int ret;
256
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
273 flags |= PIPE_CONTROL_CS_STALL;
274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
286 }
287
288 ret = intel_ring_begin(ring, 4);
289 if (ret)
290 return ret;
291
292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
295 intel_ring_emit(ring, 0);
296 intel_ring_advance(ring);
297
298 return 0;
299 }
300
301 static int
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
303 {
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318 }
319
320 static int
321 gen7_render_ring_flush(struct intel_engine_cs *ring,
322 u32 invalidate_domains, u32 flush_domains)
323 {
324 u32 flags = 0;
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
326 int ret;
327
328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
345 }
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
354 /*
355 * TLB invalidate requires a post-sync write.
356 */
357 flags |= PIPE_CONTROL_QW_WRITE;
358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
359
360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
361
362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
366 }
367
368 ret = intel_ring_begin(ring, 4);
369 if (ret)
370 return ret;
371
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
374 intel_ring_emit(ring, scratch_addr);
375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
377
378 return 0;
379 }
380
381 static int
382 gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
384 {
385 int ret;
386
387 ret = intel_ring_begin(ring, 6);
388 if (ret)
389 return ret;
390
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
398
399 return 0;
400 }
401
402 static int
403 gen8_render_ring_flush(struct intel_engine_cs *ring,
404 u32 invalidate_domains, u32 flush_domains)
405 {
406 u32 flags = 0;
407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
408 int ret;
409
410 flags |= PIPE_CONTROL_CS_STALL;
411
412 if (flush_domains) {
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
415 }
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
425
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
430 0);
431 if (ret)
432 return ret;
433 }
434
435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
436 }
437
438 static void ring_write_tail(struct intel_engine_cs *ring,
439 u32 value)
440 {
441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
442 I915_WRITE_TAIL(ring, value);
443 }
444
445 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
446 {
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
448 u64 acthd;
449
450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
455 else
456 acthd = I915_READ(ACTHD);
457
458 return acthd;
459 }
460
461 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
462 {
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
464 u32 addr;
465
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
470 }
471
472 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
473 {
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
476 u32 mmio = 0;
477
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
480 */
481 if (IS_GEN7(dev)) {
482 switch (ring->id) {
483 case RCS:
484 mmio = RENDER_HWS_PGA_GEN7;
485 break;
486 case BCS:
487 mmio = BLT_HWS_PGA_GEN7;
488 break;
489 /*
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
492 */
493 case VCS2:
494 case VCS:
495 mmio = BSD_HWS_PGA_GEN7;
496 break;
497 case VECS:
498 mmio = VEBOX_HWS_PGA_GEN7;
499 break;
500 }
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
503 } else {
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
506 }
507
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
509 POSTING_READ(mmio);
510
511 /*
512 * Flush the TLB for this page
513 *
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
517 */
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
520
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
523
524 I915_WRITE(reg,
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
526 INSTPM_SYNC_FLUSH));
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
528 1000))
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
530 ring->name);
531 }
532 }
533
534 static bool stop_ring(struct intel_engine_cs *ring)
535 {
536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
537
538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
545 */
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
547 return false;
548 }
549 }
550
551 I915_WRITE_CTL(ring, 0);
552 I915_WRITE_HEAD(ring, 0);
553 ring->write_tail(ring, 0);
554
555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
558 }
559
560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
561 }
562
563 static int init_ring_common(struct intel_engine_cs *ring)
564 {
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
569 int ret = 0;
570
571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
572
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 ring->name,
578 I915_READ_CTL(ring),
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
582
583 if (!stop_ring(ring)) {
584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 ring->name,
587 I915_READ_CTL(ring),
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
591 ret = -EIO;
592 goto out;
593 }
594 }
595
596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
598 else
599 ring_setup_phys_status_page(ring);
600
601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
603
604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
616
617 I915_WRITE_CTL(ring,
618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
619 | RING_VALID);
620
621 /* If the head is still not zero, the ring is dead */
622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
625 DRM_ERROR("%s initialization failed "
626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 ring->name,
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
631 ret = -EIO;
632 goto out;
633 }
634
635 ringbuf->last_retired_head = -1;
636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
638 intel_ring_update_space(ringbuf);
639
640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
641
642 out:
643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
644
645 return ret;
646 }
647
648 void
649 intel_fini_pipe_control(struct intel_engine_cs *ring)
650 {
651 struct drm_device *dev = ring->dev;
652
653 if (ring->scratch.obj == NULL)
654 return;
655
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(sg_page(ring->scratch.obj->pages->sgl));
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
659 }
660
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
663 }
664
665 int
666 intel_init_pipe_control(struct intel_engine_cs *ring)
667 {
668 int ret;
669
670 WARN_ON(ring->scratch.obj);
671
672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
674 DRM_ERROR("Failed to allocate seqno page\n");
675 ret = -ENOMEM;
676 goto err;
677 }
678
679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
680 if (ret)
681 goto err_unref;
682
683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
684 if (ret)
685 goto err_unref;
686
687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
689 if (ring->scratch.cpu_page == NULL) {
690 ret = -ENOMEM;
691 goto err_unpin;
692 }
693
694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
695 ring->name, ring->scratch.gtt_offset);
696 return 0;
697
698 err_unpin:
699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
700 err_unref:
701 drm_gem_object_unreference(&ring->scratch.obj->base);
702 err:
703 return ret;
704 }
705
706 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
708 {
709 int ret, i;
710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 struct i915_workarounds *w = &dev_priv->workarounds;
713
714 if (WARN_ON_ONCE(w->count == 0))
715 return 0;
716
717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
719 if (ret)
720 return ret;
721
722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
723 if (ret)
724 return ret;
725
726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
727 for (i = 0; i < w->count; i++) {
728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
730 }
731 intel_ring_emit(ring, MI_NOOP);
732
733 intel_ring_advance(ring);
734
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
737 if (ret)
738 return ret;
739
740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
741
742 return 0;
743 }
744
745 static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
747 {
748 int ret;
749
750 ret = intel_ring_workarounds_emit(ring, ctx);
751 if (ret != 0)
752 return ret;
753
754 ret = i915_gem_render_state_init(ring);
755 if (ret)
756 DRM_ERROR("init render state: %d\n", ret);
757
758 return ret;
759 }
760
761 static int wa_add(struct drm_i915_private *dev_priv,
762 const u32 addr, const u32 mask, const u32 val)
763 {
764 const u32 idx = dev_priv->workarounds.count;
765
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
767 return -ENOSPC;
768
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
772
773 dev_priv->workarounds.count++;
774
775 return 0;
776 }
777
778 #define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
780 if (r) \
781 return r; \
782 }
783
784 #define WA_SET_BIT_MASKED(addr, mask) \
785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
786
787 #define WA_CLR_BIT_MASKED(addr, mask) \
788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
789
790 #define WA_SET_FIELD_MASKED(addr, mask, value) \
791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
792
793 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
795
796 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
797
798 static int bdw_init_workarounds(struct intel_engine_cs *ring)
799 {
800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
802
803 /* WaDisablePartialInstShootdown:bdw */
804 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
805 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
806 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
807 STALL_DOP_GATING_DISABLE);
808
809 /* WaDisableDopClockGating:bdw */
810 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
811 DOP_CLOCK_GATING_DISABLE);
812
813 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
814 GEN8_SAMPLER_POWER_BYPASS_DIS);
815
816 /* Use Force Non-Coherent whenever executing a 3D context. This is a
817 * workaround for for a possible hang in the unlikely event a TLB
818 * invalidation occurs during a PSD flush.
819 */
820 WA_SET_BIT_MASKED(HDC_CHICKEN0,
821 /* WaForceEnableNonCoherent:bdw */
822 HDC_FORCE_NON_COHERENT |
823 /* WaForceContextSaveRestoreNonCoherent:bdw */
824 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
825 /* WaHdcDisableFetchWhenMasked:bdw */
826 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
827 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
828 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
829
830 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
831 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
832 * polygons in the same 8x4 pixel/sample area to be processed without
833 * stalling waiting for the earlier ones to write to Hierarchical Z
834 * buffer."
835 *
836 * This optimization is off by default for Broadwell; turn it on.
837 */
838 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
839
840 /* Wa4x4STCOptimizationDisable:bdw */
841 WA_SET_BIT_MASKED(CACHE_MODE_1,
842 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
843
844 /*
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
847 *
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
851 */
852 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
853 GEN6_WIZ_HASHING_MASK,
854 GEN6_WIZ_HASHING_16x4);
855
856 /* WaProgramL3SqcReg1Default:bdw */
857 WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
858
859 return 0;
860 }
861
862 static int chv_init_workarounds(struct intel_engine_cs *ring)
863 {
864 struct drm_device *dev = ring->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866
867 /* WaDisablePartialInstShootdown:chv */
868 /* WaDisableThreadStallDopClockGating:chv */
869 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
870 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
871 STALL_DOP_GATING_DISABLE);
872
873 /* Use Force Non-Coherent whenever executing a 3D context. This is a
874 * workaround for a possible hang in the unlikely event a TLB
875 * invalidation occurs during a PSD flush.
876 */
877 /* WaForceEnableNonCoherent:chv */
878 /* WaHdcDisableFetchWhenMasked:chv */
879 WA_SET_BIT_MASKED(HDC_CHICKEN0,
880 HDC_FORCE_NON_COHERENT |
881 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
882
883 /* According to the CACHE_MODE_0 default value documentation, some
884 * CHV platforms disable this optimization by default. Turn it on.
885 */
886 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
887
888 /* Wa4x4STCOptimizationDisable:chv */
889 WA_SET_BIT_MASKED(CACHE_MODE_1,
890 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
891
892 /* Improve HiZ throughput on CHV. */
893 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
894
895 /*
896 * BSpec recommends 8x4 when MSAA is used,
897 * however in practice 16x4 seems fastest.
898 *
899 * Note that PS/WM thread counts depend on the WIZ hashing
900 * disable bit, which we don't touch here, but it's good
901 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
902 */
903 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
904 GEN6_WIZ_HASHING_MASK,
905 GEN6_WIZ_HASHING_16x4);
906
907 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
908 INTEL_REVID(dev) == SKL_REVID_D0)
909 /* WaBarrierPerformanceFixDisable:skl */
910 WA_SET_BIT_MASKED(HDC_CHICKEN0,
911 HDC_FENCE_DEST_SLM_DISABLE |
912 HDC_BARRIER_PERFORMANCE_DISABLE);
913
914 return 0;
915 }
916
917 static int gen9_init_workarounds(struct intel_engine_cs *ring)
918 {
919 struct drm_device *dev = ring->dev;
920 struct drm_i915_private *dev_priv = dev->dev_private;
921
922 /* WaDisablePartialInstShootdown:skl,bxt */
923 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
924 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
925
926 /* Syncing dependencies between camera and graphics:skl,bxt */
927 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
928 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
929
930 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
931 INTEL_REVID(dev) == SKL_REVID_B0)) ||
932 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
933 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
935 GEN9_DG_MIRROR_FIX_ENABLE);
936 }
937
938 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
939 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
940 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
941 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
942 GEN9_RHWO_OPTIMIZATION_DISABLE);
943 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
944 DISABLE_PIXEL_MASK_CAMMING);
945 }
946
947 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
948 IS_BROXTON(dev)) {
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
950 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
951 GEN9_ENABLE_YV12_BUGFIX);
952 }
953
954 /* Wa4x4STCOptimizationDisable:skl,bxt */
955 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
956
957 /* WaDisablePartialResolveInVc:skl,bxt */
958 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
959
960 /* WaCcsTlbPrefetchDisable:skl,bxt */
961 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
962 GEN9_CCS_TLB_PREFETCH_ENABLE);
963
964 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
965 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
966 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
967 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
968 PIXEL_MASK_CAMMING_DISABLE);
969
970 return 0;
971 }
972
973 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
974 {
975 struct drm_device *dev = ring->dev;
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 u8 vals[3] = { 0, 0, 0 };
978 unsigned int i;
979
980 for (i = 0; i < 3; i++) {
981 u8 ss;
982
983 /*
984 * Only consider slices where one, and only one, subslice has 7
985 * EUs
986 */
987 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
988 continue;
989
990 /*
991 * subslice_7eu[i] != 0 (because of the check above) and
992 * ss_max == 4 (maximum number of subslices possible per slice)
993 *
994 * -> 0 <= ss <= 3;
995 */
996 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
997 vals[i] = 3 - ss;
998 }
999
1000 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1001 return 0;
1002
1003 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1004 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1005 GEN9_IZ_HASHING_MASK(2) |
1006 GEN9_IZ_HASHING_MASK(1) |
1007 GEN9_IZ_HASHING_MASK(0),
1008 GEN9_IZ_HASHING(2, vals[2]) |
1009 GEN9_IZ_HASHING(1, vals[1]) |
1010 GEN9_IZ_HASHING(0, vals[0]));
1011
1012 return 0;
1013 }
1014
1015
1016 static int skl_init_workarounds(struct intel_engine_cs *ring)
1017 {
1018 struct drm_device *dev = ring->dev;
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020
1021 gen9_init_workarounds(ring);
1022
1023 /* WaDisablePowerCompilerClockGating:skl */
1024 if (INTEL_REVID(dev) == SKL_REVID_B0)
1025 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1026 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1027
1028 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1029 /*
1030 *Use Force Non-Coherent whenever executing a 3D context. This
1031 * is a workaround for a possible hang in the unlikely event
1032 * a TLB invalidation occurs during a PSD flush.
1033 */
1034 /* WaForceEnableNonCoherent:skl */
1035 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1036 HDC_FORCE_NON_COHERENT);
1037 }
1038
1039 return skl_tune_iz_hashing(ring);
1040 }
1041
1042 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1043 {
1044 struct drm_device *dev = ring->dev;
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046
1047 gen9_init_workarounds(ring);
1048
1049 /* WaDisableThreadStallDopClockGating:bxt */
1050 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1051 STALL_DOP_GATING_DISABLE);
1052
1053 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1054 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1055 WA_SET_BIT_MASKED(
1056 GEN7_HALF_SLICE_CHICKEN1,
1057 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1058 }
1059
1060 /* WaForceContextSaveRestoreNonCoherent:bxt */
1061 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1062 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
1063
1064 return 0;
1065 }
1066
1067 int init_workarounds_ring(struct intel_engine_cs *ring)
1068 {
1069 struct drm_device *dev = ring->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072 WARN_ON(ring->id != RCS);
1073
1074 dev_priv->workarounds.count = 0;
1075
1076 if (IS_BROADWELL(dev))
1077 return bdw_init_workarounds(ring);
1078
1079 if (IS_CHERRYVIEW(dev))
1080 return chv_init_workarounds(ring);
1081
1082 if (IS_SKYLAKE(dev))
1083 return skl_init_workarounds(ring);
1084
1085 if (IS_BROXTON(dev))
1086 return bxt_init_workarounds(ring);
1087
1088 return 0;
1089 }
1090
1091 static int init_render_ring(struct intel_engine_cs *ring)
1092 {
1093 struct drm_device *dev = ring->dev;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret = init_ring_common(ring);
1096 if (ret)
1097 return ret;
1098
1099 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1100 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1101 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1102
1103 /* We need to disable the AsyncFlip performance optimisations in order
1104 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1105 * programmed to '1' on all products.
1106 *
1107 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1108 */
1109 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1110 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1111
1112 /* Required for the hardware to program scanline values for waiting */
1113 /* WaEnableFlushTlbInvalidationMode:snb */
1114 if (INTEL_INFO(dev)->gen == 6)
1115 I915_WRITE(GFX_MODE,
1116 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1117
1118 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1119 if (IS_GEN7(dev))
1120 I915_WRITE(GFX_MODE_GEN7,
1121 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1122 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1123
1124 if (IS_GEN6(dev)) {
1125 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1126 * "If this bit is set, STCunit will have LRA as replacement
1127 * policy. [...] This bit must be reset. LRA replacement
1128 * policy is not supported."
1129 */
1130 I915_WRITE(CACHE_MODE_0,
1131 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1132 }
1133
1134 if (INTEL_INFO(dev)->gen >= 6)
1135 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1136
1137 if (HAS_L3_DPF(dev))
1138 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1139
1140 return init_workarounds_ring(ring);
1141 }
1142
1143 static void render_ring_cleanup(struct intel_engine_cs *ring)
1144 {
1145 struct drm_device *dev = ring->dev;
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147
1148 if (dev_priv->semaphore_obj) {
1149 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1150 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1151 dev_priv->semaphore_obj = NULL;
1152 }
1153
1154 intel_fini_pipe_control(ring);
1155 }
1156
1157 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1158 unsigned int num_dwords)
1159 {
1160 #define MBOX_UPDATE_DWORDS 8
1161 struct drm_device *dev = signaller->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 struct intel_engine_cs *waiter;
1164 int i, ret, num_rings;
1165
1166 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1167 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1168 #undef MBOX_UPDATE_DWORDS
1169
1170 ret = intel_ring_begin(signaller, num_dwords);
1171 if (ret)
1172 return ret;
1173
1174 for_each_ring(waiter, dev_priv, i) {
1175 u32 seqno;
1176 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1177 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1178 continue;
1179
1180 seqno = i915_gem_request_get_seqno(
1181 signaller->outstanding_lazy_request);
1182 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1183 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1184 PIPE_CONTROL_QW_WRITE |
1185 PIPE_CONTROL_FLUSH_ENABLE);
1186 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1187 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1188 intel_ring_emit(signaller, seqno);
1189 intel_ring_emit(signaller, 0);
1190 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1191 MI_SEMAPHORE_TARGET(waiter->id));
1192 intel_ring_emit(signaller, 0);
1193 }
1194
1195 return 0;
1196 }
1197
1198 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1199 unsigned int num_dwords)
1200 {
1201 #define MBOX_UPDATE_DWORDS 6
1202 struct drm_device *dev = signaller->dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
1204 struct intel_engine_cs *waiter;
1205 int i, ret, num_rings;
1206
1207 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1208 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1209 #undef MBOX_UPDATE_DWORDS
1210
1211 ret = intel_ring_begin(signaller, num_dwords);
1212 if (ret)
1213 return ret;
1214
1215 for_each_ring(waiter, dev_priv, i) {
1216 u32 seqno;
1217 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1218 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1219 continue;
1220
1221 seqno = i915_gem_request_get_seqno(
1222 signaller->outstanding_lazy_request);
1223 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1224 MI_FLUSH_DW_OP_STOREDW);
1225 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1226 MI_FLUSH_DW_USE_GTT);
1227 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1228 intel_ring_emit(signaller, seqno);
1229 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1230 MI_SEMAPHORE_TARGET(waiter->id));
1231 intel_ring_emit(signaller, 0);
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int gen6_signal(struct intel_engine_cs *signaller,
1238 unsigned int num_dwords)
1239 {
1240 struct drm_device *dev = signaller->dev;
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 struct intel_engine_cs *useless;
1243 int i, ret, num_rings;
1244
1245 #define MBOX_UPDATE_DWORDS 3
1246 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1247 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1248 #undef MBOX_UPDATE_DWORDS
1249
1250 ret = intel_ring_begin(signaller, num_dwords);
1251 if (ret)
1252 return ret;
1253
1254 for_each_ring(useless, dev_priv, i) {
1255 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1256 if (mbox_reg != GEN6_NOSYNC) {
1257 u32 seqno = i915_gem_request_get_seqno(
1258 signaller->outstanding_lazy_request);
1259 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1260 intel_ring_emit(signaller, mbox_reg);
1261 intel_ring_emit(signaller, seqno);
1262 }
1263 }
1264
1265 /* If num_dwords was rounded, make sure the tail pointer is correct */
1266 if (num_rings % 2 == 0)
1267 intel_ring_emit(signaller, MI_NOOP);
1268
1269 return 0;
1270 }
1271
1272 /**
1273 * gen6_add_request - Update the semaphore mailbox registers
1274 *
1275 * @ring - ring that is adding a request
1276 * @seqno - return seqno stuck into the ring
1277 *
1278 * Update the mailbox registers in the *other* rings with the current seqno.
1279 * This acts like a signal in the canonical semaphore.
1280 */
1281 static int
1282 gen6_add_request(struct intel_engine_cs *ring)
1283 {
1284 int ret;
1285
1286 if (ring->semaphore.signal)
1287 ret = ring->semaphore.signal(ring, 4);
1288 else
1289 ret = intel_ring_begin(ring, 4);
1290
1291 if (ret)
1292 return ret;
1293
1294 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1295 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1296 intel_ring_emit(ring,
1297 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1298 intel_ring_emit(ring, MI_USER_INTERRUPT);
1299 __intel_ring_advance(ring);
1300
1301 return 0;
1302 }
1303
1304 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1305 u32 seqno)
1306 {
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 return dev_priv->last_seqno < seqno;
1309 }
1310
1311 /**
1312 * intel_ring_sync - sync the waiter to the signaller on seqno
1313 *
1314 * @waiter - ring that is waiting
1315 * @signaller - ring which has, or will signal
1316 * @seqno - seqno which the waiter will block on
1317 */
1318
1319 static int
1320 gen8_ring_sync(struct intel_engine_cs *waiter,
1321 struct intel_engine_cs *signaller,
1322 u32 seqno)
1323 {
1324 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1325 int ret;
1326
1327 ret = intel_ring_begin(waiter, 4);
1328 if (ret)
1329 return ret;
1330
1331 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1332 MI_SEMAPHORE_GLOBAL_GTT |
1333 MI_SEMAPHORE_POLL |
1334 MI_SEMAPHORE_SAD_GTE_SDD);
1335 intel_ring_emit(waiter, seqno);
1336 intel_ring_emit(waiter,
1337 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1338 intel_ring_emit(waiter,
1339 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1340 intel_ring_advance(waiter);
1341 return 0;
1342 }
1343
1344 static int
1345 gen6_ring_sync(struct intel_engine_cs *waiter,
1346 struct intel_engine_cs *signaller,
1347 u32 seqno)
1348 {
1349 u32 dw1 = MI_SEMAPHORE_MBOX |
1350 MI_SEMAPHORE_COMPARE |
1351 MI_SEMAPHORE_REGISTER;
1352 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1353 int ret;
1354
1355 /* Throughout all of the GEM code, seqno passed implies our current
1356 * seqno is >= the last seqno executed. However for hardware the
1357 * comparison is strictly greater than.
1358 */
1359 seqno -= 1;
1360
1361 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1362
1363 ret = intel_ring_begin(waiter, 4);
1364 if (ret)
1365 return ret;
1366
1367 /* If seqno wrap happened, omit the wait with no-ops */
1368 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1369 intel_ring_emit(waiter, dw1 | wait_mbox);
1370 intel_ring_emit(waiter, seqno);
1371 intel_ring_emit(waiter, 0);
1372 intel_ring_emit(waiter, MI_NOOP);
1373 } else {
1374 intel_ring_emit(waiter, MI_NOOP);
1375 intel_ring_emit(waiter, MI_NOOP);
1376 intel_ring_emit(waiter, MI_NOOP);
1377 intel_ring_emit(waiter, MI_NOOP);
1378 }
1379 intel_ring_advance(waiter);
1380
1381 return 0;
1382 }
1383
1384 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1385 do { \
1386 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1387 PIPE_CONTROL_DEPTH_STALL); \
1388 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1389 intel_ring_emit(ring__, 0); \
1390 intel_ring_emit(ring__, 0); \
1391 } while (0)
1392
1393 static int
1394 pc_render_add_request(struct intel_engine_cs *ring)
1395 {
1396 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1397 int ret;
1398
1399 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1400 * incoherent with writes to memory, i.e. completely fubar,
1401 * so we need to use PIPE_NOTIFY instead.
1402 *
1403 * However, we also need to workaround the qword write
1404 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1405 * memory before requesting an interrupt.
1406 */
1407 ret = intel_ring_begin(ring, 32);
1408 if (ret)
1409 return ret;
1410
1411 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1412 PIPE_CONTROL_WRITE_FLUSH |
1413 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1414 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1415 intel_ring_emit(ring,
1416 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1417 intel_ring_emit(ring, 0);
1418 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1419 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1420 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1421 scratch_addr += 2 * CACHELINE_BYTES;
1422 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1423 scratch_addr += 2 * CACHELINE_BYTES;
1424 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1425 scratch_addr += 2 * CACHELINE_BYTES;
1426 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1427 scratch_addr += 2 * CACHELINE_BYTES;
1428 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1429
1430 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1431 PIPE_CONTROL_WRITE_FLUSH |
1432 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1433 PIPE_CONTROL_NOTIFY);
1434 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1435 intel_ring_emit(ring,
1436 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1437 intel_ring_emit(ring, 0);
1438 __intel_ring_advance(ring);
1439
1440 return 0;
1441 }
1442
1443 static u32
1444 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1445 {
1446 /* Workaround to force correct ordering between irq and seqno writes on
1447 * ivb (and maybe also on snb) by reading from a CS register (like
1448 * ACTHD) before reading the status page. */
1449 if (!lazy_coherency) {
1450 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1451 POSTING_READ(RING_ACTHD(ring->mmio_base));
1452 }
1453
1454 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1455 }
1456
1457 static u32
1458 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1459 {
1460 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1461 }
1462
1463 static void
1464 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1465 {
1466 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1467 }
1468
1469 static u32
1470 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1471 {
1472 return ring->scratch.cpu_page[0];
1473 }
1474
1475 static void
1476 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1477 {
1478 ring->scratch.cpu_page[0] = seqno;
1479 }
1480
1481 static bool
1482 gen5_ring_get_irq(struct intel_engine_cs *ring)
1483 {
1484 struct drm_device *dev = ring->dev;
1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 unsigned long flags;
1487
1488 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1489 return false;
1490
1491 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1492 if (ring->irq_refcount++ == 0)
1493 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1494 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1495
1496 return true;
1497 }
1498
1499 static void
1500 gen5_ring_put_irq(struct intel_engine_cs *ring)
1501 {
1502 struct drm_device *dev = ring->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 unsigned long flags;
1505
1506 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1507 if (--ring->irq_refcount == 0)
1508 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1509 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1510 }
1511
1512 static bool
1513 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1514 {
1515 struct drm_device *dev = ring->dev;
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 unsigned long flags;
1518
1519 if (!intel_irqs_enabled(dev_priv))
1520 return false;
1521
1522 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1523 if (ring->irq_refcount++ == 0) {
1524 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1525 I915_WRITE(IMR, dev_priv->irq_mask);
1526 POSTING_READ(IMR);
1527 }
1528 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1529
1530 return true;
1531 }
1532
1533 static void
1534 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1535 {
1536 struct drm_device *dev = ring->dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 unsigned long flags;
1539
1540 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1541 if (--ring->irq_refcount == 0) {
1542 dev_priv->irq_mask |= ring->irq_enable_mask;
1543 I915_WRITE(IMR, dev_priv->irq_mask);
1544 POSTING_READ(IMR);
1545 }
1546 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1547 }
1548
1549 static bool
1550 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1551 {
1552 struct drm_device *dev = ring->dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 unsigned long flags;
1555
1556 if (!intel_irqs_enabled(dev_priv))
1557 return false;
1558
1559 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1560 if (ring->irq_refcount++ == 0) {
1561 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1562 I915_WRITE16(IMR, dev_priv->irq_mask);
1563 POSTING_READ16(IMR);
1564 }
1565 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1566
1567 return true;
1568 }
1569
1570 static void
1571 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1572 {
1573 struct drm_device *dev = ring->dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 unsigned long flags;
1576
1577 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1578 if (--ring->irq_refcount == 0) {
1579 dev_priv->irq_mask |= ring->irq_enable_mask;
1580 I915_WRITE16(IMR, dev_priv->irq_mask);
1581 POSTING_READ16(IMR);
1582 }
1583 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1584 }
1585
1586 static int
1587 bsd_ring_flush(struct intel_engine_cs *ring,
1588 u32 invalidate_domains,
1589 u32 flush_domains)
1590 {
1591 int ret;
1592
1593 ret = intel_ring_begin(ring, 2);
1594 if (ret)
1595 return ret;
1596
1597 intel_ring_emit(ring, MI_FLUSH);
1598 intel_ring_emit(ring, MI_NOOP);
1599 intel_ring_advance(ring);
1600 return 0;
1601 }
1602
1603 static int
1604 i9xx_add_request(struct intel_engine_cs *ring)
1605 {
1606 int ret;
1607
1608 ret = intel_ring_begin(ring, 4);
1609 if (ret)
1610 return ret;
1611
1612 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1613 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1614 intel_ring_emit(ring,
1615 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1616 intel_ring_emit(ring, MI_USER_INTERRUPT);
1617 __intel_ring_advance(ring);
1618
1619 return 0;
1620 }
1621
1622 static bool
1623 gen6_ring_get_irq(struct intel_engine_cs *ring)
1624 {
1625 struct drm_device *dev = ring->dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 unsigned long flags;
1628
1629 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1630 return false;
1631
1632 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1633 if (ring->irq_refcount++ == 0) {
1634 if (HAS_L3_DPF(dev) && ring->id == RCS)
1635 I915_WRITE_IMR(ring,
1636 ~(ring->irq_enable_mask |
1637 GT_PARITY_ERROR(dev)));
1638 else
1639 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1640 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1641 }
1642 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1643
1644 return true;
1645 }
1646
1647 static void
1648 gen6_ring_put_irq(struct intel_engine_cs *ring)
1649 {
1650 struct drm_device *dev = ring->dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 unsigned long flags;
1653
1654 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1655 if (--ring->irq_refcount == 0) {
1656 if (HAS_L3_DPF(dev) && ring->id == RCS)
1657 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1658 else
1659 I915_WRITE_IMR(ring, ~0);
1660 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1661 }
1662 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1663 }
1664
1665 static bool
1666 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1667 {
1668 struct drm_device *dev = ring->dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 unsigned long flags;
1671
1672 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1673 return false;
1674
1675 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1676 if (ring->irq_refcount++ == 0) {
1677 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1678 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1679 }
1680 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1681
1682 return true;
1683 }
1684
1685 static void
1686 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1687 {
1688 struct drm_device *dev = ring->dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 unsigned long flags;
1691
1692 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1693 if (--ring->irq_refcount == 0) {
1694 I915_WRITE_IMR(ring, ~0);
1695 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1696 }
1697 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1698 }
1699
1700 static bool
1701 gen8_ring_get_irq(struct intel_engine_cs *ring)
1702 {
1703 struct drm_device *dev = ring->dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 unsigned long flags;
1706
1707 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1708 return false;
1709
1710 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1711 if (ring->irq_refcount++ == 0) {
1712 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1713 I915_WRITE_IMR(ring,
1714 ~(ring->irq_enable_mask |
1715 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1716 } else {
1717 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1718 }
1719 POSTING_READ(RING_IMR(ring->mmio_base));
1720 }
1721 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1722
1723 return true;
1724 }
1725
1726 static void
1727 gen8_ring_put_irq(struct intel_engine_cs *ring)
1728 {
1729 struct drm_device *dev = ring->dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 unsigned long flags;
1732
1733 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1734 if (--ring->irq_refcount == 0) {
1735 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1736 I915_WRITE_IMR(ring,
1737 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1738 } else {
1739 I915_WRITE_IMR(ring, ~0);
1740 }
1741 POSTING_READ(RING_IMR(ring->mmio_base));
1742 }
1743 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1744 }
1745
1746 static int
1747 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1748 u64 offset, u32 length,
1749 unsigned dispatch_flags)
1750 {
1751 int ret;
1752
1753 ret = intel_ring_begin(ring, 2);
1754 if (ret)
1755 return ret;
1756
1757 intel_ring_emit(ring,
1758 MI_BATCH_BUFFER_START |
1759 MI_BATCH_GTT |
1760 (dispatch_flags & I915_DISPATCH_SECURE ?
1761 0 : MI_BATCH_NON_SECURE_I965));
1762 intel_ring_emit(ring, offset);
1763 intel_ring_advance(ring);
1764
1765 return 0;
1766 }
1767
1768 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1769 #define I830_BATCH_LIMIT (256*1024)
1770 #define I830_TLB_ENTRIES (2)
1771 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1772 static int
1773 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1774 u64 offset, u32 len,
1775 unsigned dispatch_flags)
1776 {
1777 u32 cs_offset = ring->scratch.gtt_offset;
1778 int ret;
1779
1780 ret = intel_ring_begin(ring, 6);
1781 if (ret)
1782 return ret;
1783
1784 /* Evict the invalid PTE TLBs */
1785 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1786 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1787 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1788 intel_ring_emit(ring, cs_offset);
1789 intel_ring_emit(ring, 0xdeadbeef);
1790 intel_ring_emit(ring, MI_NOOP);
1791 intel_ring_advance(ring);
1792
1793 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1794 if (len > I830_BATCH_LIMIT)
1795 return -ENOSPC;
1796
1797 ret = intel_ring_begin(ring, 6 + 2);
1798 if (ret)
1799 return ret;
1800
1801 /* Blit the batch (which has now all relocs applied) to the
1802 * stable batch scratch bo area (so that the CS never
1803 * stumbles over its tlb invalidation bug) ...
1804 */
1805 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1806 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1807 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1808 intel_ring_emit(ring, cs_offset);
1809 intel_ring_emit(ring, 4096);
1810 intel_ring_emit(ring, offset);
1811
1812 intel_ring_emit(ring, MI_FLUSH);
1813 intel_ring_emit(ring, MI_NOOP);
1814 intel_ring_advance(ring);
1815
1816 /* ... and execute it. */
1817 offset = cs_offset;
1818 }
1819
1820 ret = intel_ring_begin(ring, 4);
1821 if (ret)
1822 return ret;
1823
1824 intel_ring_emit(ring, MI_BATCH_BUFFER);
1825 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1826 0 : MI_BATCH_NON_SECURE));
1827 intel_ring_emit(ring, offset + len - 8);
1828 intel_ring_emit(ring, MI_NOOP);
1829 intel_ring_advance(ring);
1830
1831 return 0;
1832 }
1833
1834 static int
1835 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1836 u64 offset, u32 len,
1837 unsigned dispatch_flags)
1838 {
1839 int ret;
1840
1841 ret = intel_ring_begin(ring, 2);
1842 if (ret)
1843 return ret;
1844
1845 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1846 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1847 0 : MI_BATCH_NON_SECURE));
1848 intel_ring_advance(ring);
1849
1850 return 0;
1851 }
1852
1853 static void cleanup_status_page(struct intel_engine_cs *ring)
1854 {
1855 struct drm_i915_gem_object *obj;
1856
1857 obj = ring->status_page.obj;
1858 if (obj == NULL)
1859 return;
1860
1861 kunmap(sg_page(obj->pages->sgl));
1862 i915_gem_object_ggtt_unpin(obj);
1863 drm_gem_object_unreference(&obj->base);
1864 ring->status_page.obj = NULL;
1865 }
1866
1867 static int init_status_page(struct intel_engine_cs *ring)
1868 {
1869 struct drm_i915_gem_object *obj;
1870
1871 if ((obj = ring->status_page.obj) == NULL) {
1872 unsigned flags;
1873 int ret;
1874
1875 obj = i915_gem_alloc_object(ring->dev, 4096);
1876 if (obj == NULL) {
1877 DRM_ERROR("Failed to allocate status page\n");
1878 return -ENOMEM;
1879 }
1880
1881 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1882 if (ret)
1883 goto err_unref;
1884
1885 flags = 0;
1886 if (!HAS_LLC(ring->dev))
1887 /* On g33, we cannot place HWS above 256MiB, so
1888 * restrict its pinning to the low mappable arena.
1889 * Though this restriction is not documented for
1890 * gen4, gen5, or byt, they also behave similarly
1891 * and hang if the HWS is placed at the top of the
1892 * GTT. To generalise, it appears that all !llc
1893 * platforms have issues with us placing the HWS
1894 * above the mappable region (even though we never
1895 * actualy map it).
1896 */
1897 flags |= PIN_MAPPABLE;
1898 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1899 if (ret) {
1900 err_unref:
1901 drm_gem_object_unreference(&obj->base);
1902 return ret;
1903 }
1904
1905 ring->status_page.obj = obj;
1906 }
1907
1908 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1909 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1910 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1911
1912 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1913 ring->name, ring->status_page.gfx_addr);
1914
1915 return 0;
1916 }
1917
1918 static int init_phys_status_page(struct intel_engine_cs *ring)
1919 {
1920 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1921
1922 if (!dev_priv->status_page_dmah) {
1923 dev_priv->status_page_dmah =
1924 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1925 if (!dev_priv->status_page_dmah)
1926 return -ENOMEM;
1927 }
1928
1929 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1930 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1931
1932 return 0;
1933 }
1934
1935 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1936 {
1937 iounmap(ringbuf->virtual_start);
1938 ringbuf->virtual_start = NULL;
1939 i915_gem_object_ggtt_unpin(ringbuf->obj);
1940 }
1941
1942 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1943 struct intel_ringbuffer *ringbuf)
1944 {
1945 struct drm_i915_private *dev_priv = to_i915(dev);
1946 struct drm_i915_gem_object *obj = ringbuf->obj;
1947 int ret;
1948
1949 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1950 if (ret)
1951 return ret;
1952
1953 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1954 if (ret) {
1955 i915_gem_object_ggtt_unpin(obj);
1956 return ret;
1957 }
1958
1959 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1960 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1961 if (ringbuf->virtual_start == NULL) {
1962 i915_gem_object_ggtt_unpin(obj);
1963 return -EINVAL;
1964 }
1965
1966 return 0;
1967 }
1968
1969 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1970 {
1971 drm_gem_object_unreference(&ringbuf->obj->base);
1972 ringbuf->obj = NULL;
1973 }
1974
1975 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1976 struct intel_ringbuffer *ringbuf)
1977 {
1978 struct drm_i915_gem_object *obj;
1979
1980 obj = NULL;
1981 if (!HAS_LLC(dev))
1982 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1983 if (obj == NULL)
1984 obj = i915_gem_alloc_object(dev, ringbuf->size);
1985 if (obj == NULL)
1986 return -ENOMEM;
1987
1988 /* mark ring buffers as read-only from GPU side by default */
1989 obj->gt_ro = 1;
1990
1991 ringbuf->obj = obj;
1992
1993 return 0;
1994 }
1995
1996 static int intel_init_ring_buffer(struct drm_device *dev,
1997 struct intel_engine_cs *ring)
1998 {
1999 struct intel_ringbuffer *ringbuf;
2000 int ret;
2001
2002 WARN_ON(ring->buffer);
2003
2004 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2005 if (!ringbuf)
2006 return -ENOMEM;
2007 ring->buffer = ringbuf;
2008
2009 ring->dev = dev;
2010 INIT_LIST_HEAD(&ring->active_list);
2011 INIT_LIST_HEAD(&ring->request_list);
2012 INIT_LIST_HEAD(&ring->execlist_queue);
2013 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2014 ringbuf->size = 32 * PAGE_SIZE;
2015 ringbuf->ring = ring;
2016 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2017
2018 init_waitqueue_head(&ring->irq_queue);
2019
2020 if (I915_NEED_GFX_HWS(dev)) {
2021 ret = init_status_page(ring);
2022 if (ret)
2023 goto error;
2024 } else {
2025 BUG_ON(ring->id != RCS);
2026 ret = init_phys_status_page(ring);
2027 if (ret)
2028 goto error;
2029 }
2030
2031 WARN_ON(ringbuf->obj);
2032
2033 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2034 if (ret) {
2035 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2036 ring->name, ret);
2037 goto error;
2038 }
2039
2040 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2041 if (ret) {
2042 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2043 ring->name, ret);
2044 intel_destroy_ringbuffer_obj(ringbuf);
2045 goto error;
2046 }
2047
2048 /* Workaround an erratum on the i830 which causes a hang if
2049 * the TAIL pointer points to within the last 2 cachelines
2050 * of the buffer.
2051 */
2052 ringbuf->effective_size = ringbuf->size;
2053 if (IS_I830(dev) || IS_845G(dev))
2054 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2055
2056 ret = i915_cmd_parser_init_ring(ring);
2057 if (ret)
2058 goto error;
2059
2060 return 0;
2061
2062 error:
2063 kfree(ringbuf);
2064 ring->buffer = NULL;
2065 return ret;
2066 }
2067
2068 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2069 {
2070 struct drm_i915_private *dev_priv;
2071 struct intel_ringbuffer *ringbuf;
2072
2073 if (!intel_ring_initialized(ring))
2074 return;
2075
2076 dev_priv = to_i915(ring->dev);
2077 ringbuf = ring->buffer;
2078
2079 intel_stop_ring_buffer(ring);
2080 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2081
2082 intel_unpin_ringbuffer_obj(ringbuf);
2083 intel_destroy_ringbuffer_obj(ringbuf);
2084 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2085
2086 if (ring->cleanup)
2087 ring->cleanup(ring);
2088
2089 cleanup_status_page(ring);
2090
2091 i915_cmd_parser_fini_ring(ring);
2092 i915_gem_batch_pool_fini(&ring->batch_pool);
2093
2094 kfree(ringbuf);
2095 ring->buffer = NULL;
2096 }
2097
2098 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2099 {
2100 struct intel_ringbuffer *ringbuf = ring->buffer;
2101 struct drm_i915_gem_request *request;
2102 int ret, new_space;
2103
2104 if (intel_ring_space(ringbuf) >= n)
2105 return 0;
2106
2107 list_for_each_entry(request, &ring->request_list, list) {
2108 new_space = __intel_ring_space(request->postfix, ringbuf->tail,
2109 ringbuf->size);
2110 if (new_space >= n)
2111 break;
2112 }
2113
2114 if (WARN_ON(&request->list == &ring->request_list))
2115 return -ENOSPC;
2116
2117 ret = i915_wait_request(request);
2118 if (ret)
2119 return ret;
2120
2121 i915_gem_retire_requests_ring(ring);
2122
2123 WARN_ON(intel_ring_space(ringbuf) < new_space);
2124
2125 return 0;
2126 }
2127
2128 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2129 {
2130 uint32_t __iomem *virt;
2131 struct intel_ringbuffer *ringbuf = ring->buffer;
2132 int rem = ringbuf->size - ringbuf->tail;
2133
2134 if (ringbuf->space < rem) {
2135 int ret = ring_wait_for_space(ring, rem);
2136 if (ret)
2137 return ret;
2138 }
2139
2140 virt = ringbuf->virtual_start + ringbuf->tail;
2141 rem /= 4;
2142 while (rem--)
2143 iowrite32(MI_NOOP, virt++);
2144
2145 ringbuf->tail = 0;
2146 intel_ring_update_space(ringbuf);
2147
2148 return 0;
2149 }
2150
2151 int intel_ring_idle(struct intel_engine_cs *ring)
2152 {
2153 struct drm_i915_gem_request *req;
2154 int ret;
2155
2156 /* We need to add any requests required to flush the objects and ring */
2157 if (ring->outstanding_lazy_request) {
2158 ret = i915_add_request(ring);
2159 if (ret)
2160 return ret;
2161 }
2162
2163 /* Wait upon the last request to be completed */
2164 if (list_empty(&ring->request_list))
2165 return 0;
2166
2167 req = list_entry(ring->request_list.prev,
2168 struct drm_i915_gem_request,
2169 list);
2170
2171 return i915_wait_request(req);
2172 }
2173
2174 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2175 {
2176 request->ringbuf = request->ring->buffer;
2177 return 0;
2178 }
2179
2180 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2181 int bytes)
2182 {
2183 struct intel_ringbuffer *ringbuf = ring->buffer;
2184 int ret;
2185
2186 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2187 ret = intel_wrap_ring_buffer(ring);
2188 if (unlikely(ret))
2189 return ret;
2190 }
2191
2192 if (unlikely(ringbuf->space < bytes)) {
2193 ret = ring_wait_for_space(ring, bytes);
2194 if (unlikely(ret))
2195 return ret;
2196 }
2197
2198 return 0;
2199 }
2200
2201 int intel_ring_begin(struct intel_engine_cs *ring,
2202 int num_dwords)
2203 {
2204 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2205 int ret;
2206
2207 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2208 dev_priv->mm.interruptible);
2209 if (ret)
2210 return ret;
2211
2212 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2213 if (ret)
2214 return ret;
2215
2216 /* Preallocate the olr before touching the ring */
2217 ret = i915_gem_request_alloc(ring, ring->default_context);
2218 if (ret)
2219 return ret;
2220
2221 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2222 return 0;
2223 }
2224
2225 /* Align the ring tail to a cacheline boundary */
2226 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2227 {
2228 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2229 int ret;
2230
2231 if (num_dwords == 0)
2232 return 0;
2233
2234 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2235 ret = intel_ring_begin(ring, num_dwords);
2236 if (ret)
2237 return ret;
2238
2239 while (num_dwords--)
2240 intel_ring_emit(ring, MI_NOOP);
2241
2242 intel_ring_advance(ring);
2243
2244 return 0;
2245 }
2246
2247 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2248 {
2249 struct drm_device *dev = ring->dev;
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251
2252 BUG_ON(ring->outstanding_lazy_request);
2253
2254 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2255 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2256 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2257 if (HAS_VEBOX(dev))
2258 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2259 }
2260
2261 ring->set_seqno(ring, seqno);
2262 ring->hangcheck.seqno = seqno;
2263 }
2264
2265 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2266 u32 value)
2267 {
2268 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2269
2270 /* Every tail move must follow the sequence below */
2271
2272 /* Disable notification that the ring is IDLE. The GT
2273 * will then assume that it is busy and bring it out of rc6.
2274 */
2275 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2276 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2277
2278 /* Clear the context id. Here be magic! */
2279 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2280
2281 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2282 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2283 GEN6_BSD_SLEEP_INDICATOR) == 0,
2284 50))
2285 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2286
2287 /* Now that the ring is fully powered up, update the tail */
2288 I915_WRITE_TAIL(ring, value);
2289 POSTING_READ(RING_TAIL(ring->mmio_base));
2290
2291 /* Let the ring send IDLE messages to the GT again,
2292 * and so let it sleep to conserve power when idle.
2293 */
2294 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2295 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2296 }
2297
2298 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2299 u32 invalidate, u32 flush)
2300 {
2301 uint32_t cmd;
2302 int ret;
2303
2304 ret = intel_ring_begin(ring, 4);
2305 if (ret)
2306 return ret;
2307
2308 cmd = MI_FLUSH_DW;
2309 if (INTEL_INFO(ring->dev)->gen >= 8)
2310 cmd += 1;
2311
2312 /* We always require a command barrier so that subsequent
2313 * commands, such as breadcrumb interrupts, are strictly ordered
2314 * wrt the contents of the write cache being flushed to memory
2315 * (and thus being coherent from the CPU).
2316 */
2317 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2318
2319 /*
2320 * Bspec vol 1c.5 - video engine command streamer:
2321 * "If ENABLED, all TLBs will be invalidated once the flush
2322 * operation is complete. This bit is only valid when the
2323 * Post-Sync Operation field is a value of 1h or 3h."
2324 */
2325 if (invalidate & I915_GEM_GPU_DOMAINS)
2326 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2327
2328 intel_ring_emit(ring, cmd);
2329 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2330 if (INTEL_INFO(ring->dev)->gen >= 8) {
2331 intel_ring_emit(ring, 0); /* upper addr */
2332 intel_ring_emit(ring, 0); /* value */
2333 } else {
2334 intel_ring_emit(ring, 0);
2335 intel_ring_emit(ring, MI_NOOP);
2336 }
2337 intel_ring_advance(ring);
2338 return 0;
2339 }
2340
2341 static int
2342 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2343 u64 offset, u32 len,
2344 unsigned dispatch_flags)
2345 {
2346 bool ppgtt = USES_PPGTT(ring->dev) &&
2347 !(dispatch_flags & I915_DISPATCH_SECURE);
2348 int ret;
2349
2350 ret = intel_ring_begin(ring, 4);
2351 if (ret)
2352 return ret;
2353
2354 /* FIXME(BDW): Address space and security selectors. */
2355 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2356 intel_ring_emit(ring, lower_32_bits(offset));
2357 intel_ring_emit(ring, upper_32_bits(offset));
2358 intel_ring_emit(ring, MI_NOOP);
2359 intel_ring_advance(ring);
2360
2361 return 0;
2362 }
2363
2364 static int
2365 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2366 u64 offset, u32 len,
2367 unsigned dispatch_flags)
2368 {
2369 int ret;
2370
2371 ret = intel_ring_begin(ring, 2);
2372 if (ret)
2373 return ret;
2374
2375 intel_ring_emit(ring,
2376 MI_BATCH_BUFFER_START |
2377 (dispatch_flags & I915_DISPATCH_SECURE ?
2378 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2379 /* bit0-7 is the length on GEN6+ */
2380 intel_ring_emit(ring, offset);
2381 intel_ring_advance(ring);
2382
2383 return 0;
2384 }
2385
2386 static int
2387 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2388 u64 offset, u32 len,
2389 unsigned dispatch_flags)
2390 {
2391 int ret;
2392
2393 ret = intel_ring_begin(ring, 2);
2394 if (ret)
2395 return ret;
2396
2397 intel_ring_emit(ring,
2398 MI_BATCH_BUFFER_START |
2399 (dispatch_flags & I915_DISPATCH_SECURE ?
2400 0 : MI_BATCH_NON_SECURE_I965));
2401 /* bit0-7 is the length on GEN6+ */
2402 intel_ring_emit(ring, offset);
2403 intel_ring_advance(ring);
2404
2405 return 0;
2406 }
2407
2408 /* Blitter support (SandyBridge+) */
2409
2410 static int gen6_ring_flush(struct intel_engine_cs *ring,
2411 u32 invalidate, u32 flush)
2412 {
2413 struct drm_device *dev = ring->dev;
2414 uint32_t cmd;
2415 int ret;
2416
2417 ret = intel_ring_begin(ring, 4);
2418 if (ret)
2419 return ret;
2420
2421 cmd = MI_FLUSH_DW;
2422 if (INTEL_INFO(dev)->gen >= 8)
2423 cmd += 1;
2424
2425 /* We always require a command barrier so that subsequent
2426 * commands, such as breadcrumb interrupts, are strictly ordered
2427 * wrt the contents of the write cache being flushed to memory
2428 * (and thus being coherent from the CPU).
2429 */
2430 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2431
2432 /*
2433 * Bspec vol 1c.3 - blitter engine command streamer:
2434 * "If ENABLED, all TLBs will be invalidated once the flush
2435 * operation is complete. This bit is only valid when the
2436 * Post-Sync Operation field is a value of 1h or 3h."
2437 */
2438 if (invalidate & I915_GEM_DOMAIN_RENDER)
2439 cmd |= MI_INVALIDATE_TLB;
2440 intel_ring_emit(ring, cmd);
2441 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2442 if (INTEL_INFO(dev)->gen >= 8) {
2443 intel_ring_emit(ring, 0); /* upper addr */
2444 intel_ring_emit(ring, 0); /* value */
2445 } else {
2446 intel_ring_emit(ring, 0);
2447 intel_ring_emit(ring, MI_NOOP);
2448 }
2449 intel_ring_advance(ring);
2450
2451 return 0;
2452 }
2453
2454 int intel_init_render_ring_buffer(struct drm_device *dev)
2455 {
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2458 struct drm_i915_gem_object *obj;
2459 int ret;
2460
2461 ring->name = "render ring";
2462 ring->id = RCS;
2463 ring->mmio_base = RENDER_RING_BASE;
2464
2465 if (INTEL_INFO(dev)->gen >= 8) {
2466 if (i915_semaphore_is_enabled(dev)) {
2467 obj = i915_gem_alloc_object(dev, 4096);
2468 if (obj == NULL) {
2469 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2470 i915.semaphores = 0;
2471 } else {
2472 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2473 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2474 if (ret != 0) {
2475 drm_gem_object_unreference(&obj->base);
2476 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2477 i915.semaphores = 0;
2478 } else
2479 dev_priv->semaphore_obj = obj;
2480 }
2481 }
2482
2483 ring->init_context = intel_rcs_ctx_init;
2484 ring->add_request = gen6_add_request;
2485 ring->flush = gen8_render_ring_flush;
2486 ring->irq_get = gen8_ring_get_irq;
2487 ring->irq_put = gen8_ring_put_irq;
2488 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2489 ring->get_seqno = gen6_ring_get_seqno;
2490 ring->set_seqno = ring_set_seqno;
2491 if (i915_semaphore_is_enabled(dev)) {
2492 WARN_ON(!dev_priv->semaphore_obj);
2493 ring->semaphore.sync_to = gen8_ring_sync;
2494 ring->semaphore.signal = gen8_rcs_signal;
2495 GEN8_RING_SEMAPHORE_INIT;
2496 }
2497 } else if (INTEL_INFO(dev)->gen >= 6) {
2498 ring->add_request = gen6_add_request;
2499 ring->flush = gen7_render_ring_flush;
2500 if (INTEL_INFO(dev)->gen == 6)
2501 ring->flush = gen6_render_ring_flush;
2502 ring->irq_get = gen6_ring_get_irq;
2503 ring->irq_put = gen6_ring_put_irq;
2504 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2505 ring->get_seqno = gen6_ring_get_seqno;
2506 ring->set_seqno = ring_set_seqno;
2507 if (i915_semaphore_is_enabled(dev)) {
2508 ring->semaphore.sync_to = gen6_ring_sync;
2509 ring->semaphore.signal = gen6_signal;
2510 /*
2511 * The current semaphore is only applied on pre-gen8
2512 * platform. And there is no VCS2 ring on the pre-gen8
2513 * platform. So the semaphore between RCS and VCS2 is
2514 * initialized as INVALID. Gen8 will initialize the
2515 * sema between VCS2 and RCS later.
2516 */
2517 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2518 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2519 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2520 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2521 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2522 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2523 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2524 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2525 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2526 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2527 }
2528 } else if (IS_GEN5(dev)) {
2529 ring->add_request = pc_render_add_request;
2530 ring->flush = gen4_render_ring_flush;
2531 ring->get_seqno = pc_render_get_seqno;
2532 ring->set_seqno = pc_render_set_seqno;
2533 ring->irq_get = gen5_ring_get_irq;
2534 ring->irq_put = gen5_ring_put_irq;
2535 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2536 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2537 } else {
2538 ring->add_request = i9xx_add_request;
2539 if (INTEL_INFO(dev)->gen < 4)
2540 ring->flush = gen2_render_ring_flush;
2541 else
2542 ring->flush = gen4_render_ring_flush;
2543 ring->get_seqno = ring_get_seqno;
2544 ring->set_seqno = ring_set_seqno;
2545 if (IS_GEN2(dev)) {
2546 ring->irq_get = i8xx_ring_get_irq;
2547 ring->irq_put = i8xx_ring_put_irq;
2548 } else {
2549 ring->irq_get = i9xx_ring_get_irq;
2550 ring->irq_put = i9xx_ring_put_irq;
2551 }
2552 ring->irq_enable_mask = I915_USER_INTERRUPT;
2553 }
2554 ring->write_tail = ring_write_tail;
2555
2556 if (IS_HASWELL(dev))
2557 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2558 else if (IS_GEN8(dev))
2559 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2560 else if (INTEL_INFO(dev)->gen >= 6)
2561 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2562 else if (INTEL_INFO(dev)->gen >= 4)
2563 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2564 else if (IS_I830(dev) || IS_845G(dev))
2565 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2566 else
2567 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2568 ring->init_hw = init_render_ring;
2569 ring->cleanup = render_ring_cleanup;
2570
2571 /* Workaround batchbuffer to combat CS tlb bug. */
2572 if (HAS_BROKEN_CS_TLB(dev)) {
2573 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2574 if (obj == NULL) {
2575 DRM_ERROR("Failed to allocate batch bo\n");
2576 return -ENOMEM;
2577 }
2578
2579 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2580 if (ret != 0) {
2581 drm_gem_object_unreference(&obj->base);
2582 DRM_ERROR("Failed to ping batch bo\n");
2583 return ret;
2584 }
2585
2586 ring->scratch.obj = obj;
2587 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2588 }
2589
2590 ret = intel_init_ring_buffer(dev, ring);
2591 if (ret)
2592 return ret;
2593
2594 if (INTEL_INFO(dev)->gen >= 5) {
2595 ret = intel_init_pipe_control(ring);
2596 if (ret)
2597 return ret;
2598 }
2599
2600 return 0;
2601 }
2602
2603 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2604 {
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2607
2608 ring->name = "bsd ring";
2609 ring->id = VCS;
2610
2611 ring->write_tail = ring_write_tail;
2612 if (INTEL_INFO(dev)->gen >= 6) {
2613 ring->mmio_base = GEN6_BSD_RING_BASE;
2614 /* gen6 bsd needs a special wa for tail updates */
2615 if (IS_GEN6(dev))
2616 ring->write_tail = gen6_bsd_ring_write_tail;
2617 ring->flush = gen6_bsd_ring_flush;
2618 ring->add_request = gen6_add_request;
2619 ring->get_seqno = gen6_ring_get_seqno;
2620 ring->set_seqno = ring_set_seqno;
2621 if (INTEL_INFO(dev)->gen >= 8) {
2622 ring->irq_enable_mask =
2623 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2624 ring->irq_get = gen8_ring_get_irq;
2625 ring->irq_put = gen8_ring_put_irq;
2626 ring->dispatch_execbuffer =
2627 gen8_ring_dispatch_execbuffer;
2628 if (i915_semaphore_is_enabled(dev)) {
2629 ring->semaphore.sync_to = gen8_ring_sync;
2630 ring->semaphore.signal = gen8_xcs_signal;
2631 GEN8_RING_SEMAPHORE_INIT;
2632 }
2633 } else {
2634 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2635 ring->irq_get = gen6_ring_get_irq;
2636 ring->irq_put = gen6_ring_put_irq;
2637 ring->dispatch_execbuffer =
2638 gen6_ring_dispatch_execbuffer;
2639 if (i915_semaphore_is_enabled(dev)) {
2640 ring->semaphore.sync_to = gen6_ring_sync;
2641 ring->semaphore.signal = gen6_signal;
2642 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2643 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2644 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2645 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2646 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2647 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2648 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2649 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2650 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2651 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2652 }
2653 }
2654 } else {
2655 ring->mmio_base = BSD_RING_BASE;
2656 ring->flush = bsd_ring_flush;
2657 ring->add_request = i9xx_add_request;
2658 ring->get_seqno = ring_get_seqno;
2659 ring->set_seqno = ring_set_seqno;
2660 if (IS_GEN5(dev)) {
2661 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2662 ring->irq_get = gen5_ring_get_irq;
2663 ring->irq_put = gen5_ring_put_irq;
2664 } else {
2665 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2666 ring->irq_get = i9xx_ring_get_irq;
2667 ring->irq_put = i9xx_ring_put_irq;
2668 }
2669 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2670 }
2671 ring->init_hw = init_ring_common;
2672
2673 return intel_init_ring_buffer(dev, ring);
2674 }
2675
2676 /**
2677 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2678 */
2679 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2680 {
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2683
2684 ring->name = "bsd2 ring";
2685 ring->id = VCS2;
2686
2687 ring->write_tail = ring_write_tail;
2688 ring->mmio_base = GEN8_BSD2_RING_BASE;
2689 ring->flush = gen6_bsd_ring_flush;
2690 ring->add_request = gen6_add_request;
2691 ring->get_seqno = gen6_ring_get_seqno;
2692 ring->set_seqno = ring_set_seqno;
2693 ring->irq_enable_mask =
2694 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2695 ring->irq_get = gen8_ring_get_irq;
2696 ring->irq_put = gen8_ring_put_irq;
2697 ring->dispatch_execbuffer =
2698 gen8_ring_dispatch_execbuffer;
2699 if (i915_semaphore_is_enabled(dev)) {
2700 ring->semaphore.sync_to = gen8_ring_sync;
2701 ring->semaphore.signal = gen8_xcs_signal;
2702 GEN8_RING_SEMAPHORE_INIT;
2703 }
2704 ring->init_hw = init_ring_common;
2705
2706 return intel_init_ring_buffer(dev, ring);
2707 }
2708
2709 int intel_init_blt_ring_buffer(struct drm_device *dev)
2710 {
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2713
2714 ring->name = "blitter ring";
2715 ring->id = BCS;
2716
2717 ring->mmio_base = BLT_RING_BASE;
2718 ring->write_tail = ring_write_tail;
2719 ring->flush = gen6_ring_flush;
2720 ring->add_request = gen6_add_request;
2721 ring->get_seqno = gen6_ring_get_seqno;
2722 ring->set_seqno = ring_set_seqno;
2723 if (INTEL_INFO(dev)->gen >= 8) {
2724 ring->irq_enable_mask =
2725 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2726 ring->irq_get = gen8_ring_get_irq;
2727 ring->irq_put = gen8_ring_put_irq;
2728 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2729 if (i915_semaphore_is_enabled(dev)) {
2730 ring->semaphore.sync_to = gen8_ring_sync;
2731 ring->semaphore.signal = gen8_xcs_signal;
2732 GEN8_RING_SEMAPHORE_INIT;
2733 }
2734 } else {
2735 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2736 ring->irq_get = gen6_ring_get_irq;
2737 ring->irq_put = gen6_ring_put_irq;
2738 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2739 if (i915_semaphore_is_enabled(dev)) {
2740 ring->semaphore.signal = gen6_signal;
2741 ring->semaphore.sync_to = gen6_ring_sync;
2742 /*
2743 * The current semaphore is only applied on pre-gen8
2744 * platform. And there is no VCS2 ring on the pre-gen8
2745 * platform. So the semaphore between BCS and VCS2 is
2746 * initialized as INVALID. Gen8 will initialize the
2747 * sema between BCS and VCS2 later.
2748 */
2749 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2750 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2751 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2752 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2753 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2754 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2755 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2756 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2757 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2758 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2759 }
2760 }
2761 ring->init_hw = init_ring_common;
2762
2763 return intel_init_ring_buffer(dev, ring);
2764 }
2765
2766 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2767 {
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2770
2771 ring->name = "video enhancement ring";
2772 ring->id = VECS;
2773
2774 ring->mmio_base = VEBOX_RING_BASE;
2775 ring->write_tail = ring_write_tail;
2776 ring->flush = gen6_ring_flush;
2777 ring->add_request = gen6_add_request;
2778 ring->get_seqno = gen6_ring_get_seqno;
2779 ring->set_seqno = ring_set_seqno;
2780
2781 if (INTEL_INFO(dev)->gen >= 8) {
2782 ring->irq_enable_mask =
2783 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2784 ring->irq_get = gen8_ring_get_irq;
2785 ring->irq_put = gen8_ring_put_irq;
2786 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2787 if (i915_semaphore_is_enabled(dev)) {
2788 ring->semaphore.sync_to = gen8_ring_sync;
2789 ring->semaphore.signal = gen8_xcs_signal;
2790 GEN8_RING_SEMAPHORE_INIT;
2791 }
2792 } else {
2793 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2794 ring->irq_get = hsw_vebox_get_irq;
2795 ring->irq_put = hsw_vebox_put_irq;
2796 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2797 if (i915_semaphore_is_enabled(dev)) {
2798 ring->semaphore.sync_to = gen6_ring_sync;
2799 ring->semaphore.signal = gen6_signal;
2800 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2801 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2802 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2803 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2804 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2805 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2806 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2807 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2808 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2809 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2810 }
2811 }
2812 ring->init_hw = init_ring_common;
2813
2814 return intel_init_ring_buffer(dev, ring);
2815 }
2816
2817 int
2818 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2819 {
2820 int ret;
2821
2822 if (!ring->gpu_caches_dirty)
2823 return 0;
2824
2825 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2826 if (ret)
2827 return ret;
2828
2829 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2830
2831 ring->gpu_caches_dirty = false;
2832 return 0;
2833 }
2834
2835 int
2836 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2837 {
2838 uint32_t flush_domains;
2839 int ret;
2840
2841 flush_domains = 0;
2842 if (ring->gpu_caches_dirty)
2843 flush_domains = I915_GEM_GPU_DOMAINS;
2844
2845 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2846 if (ret)
2847 return ret;
2848
2849 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2850
2851 ring->gpu_caches_dirty = false;
2852 return 0;
2853 }
2854
2855 void
2856 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2857 {
2858 int ret;
2859
2860 if (!intel_ring_initialized(ring))
2861 return;
2862
2863 ret = intel_ring_idle(ring);
2864 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2865 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2866 ring->name, ret);
2867
2868 stop_ring(ring);
2869 }
Linux kernel - Deliverables
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