2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
41 struct drm_i915_gem_object
*obj
;
42 volatile u32
*cpu_page
;
46 static inline int ring_space(struct intel_ring_buffer
*ring
)
48 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 struct pipe_control
*pc
= ring
->private;
179 u32 scratch_addr
= pc
->gtt_offset
+ 128;
183 ret
= intel_ring_begin(ring
, 6);
187 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
189 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
190 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
191 intel_ring_emit(ring
, 0); /* low dword */
192 intel_ring_emit(ring
, 0); /* high dword */
193 intel_ring_emit(ring
, MI_NOOP
);
194 intel_ring_advance(ring
);
196 ret
= intel_ring_begin(ring
, 6);
200 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
202 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, MI_NOOP
);
206 intel_ring_advance(ring
);
212 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
213 u32 invalidate_domains
, u32 flush_domains
)
216 struct pipe_control
*pc
= ring
->private;
217 u32 scratch_addr
= pc
->gtt_offset
+ 128;
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret
= intel_emit_post_sync_nonzero_flush(ring
);
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
230 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
231 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
236 flags
|= PIPE_CONTROL_CS_STALL
;
238 if (invalidate_domains
) {
239 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
240 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
244 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
246 * TLB invalidate requires a post-sync write.
248 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
251 ret
= intel_ring_begin(ring
, 4);
255 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring
, flags
);
257 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
258 intel_ring_emit(ring
, 0);
259 intel_ring_advance(ring
);
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
269 ret
= intel_ring_begin(ring
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
275 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
276 intel_ring_emit(ring
, 0);
277 intel_ring_emit(ring
, 0);
278 intel_ring_advance(ring
);
284 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
285 u32 invalidate_domains
, u32 flush_domains
)
288 struct pipe_control
*pc
= ring
->private;
289 u32 scratch_addr
= pc
->gtt_offset
+ 128;
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
300 flags
|= PIPE_CONTROL_CS_STALL
;
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
307 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
308 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
310 if (invalidate_domains
) {
311 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
312 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
313 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
314 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
315 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
316 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
318 * TLB invalidate requires a post-sync write.
320 flags
|= PIPE_CONTROL_QW_WRITE
;
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring
);
328 ret
= intel_ring_begin(ring
, 4);
332 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring
, flags
);
334 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
335 intel_ring_emit(ring
, 0);
336 intel_ring_advance(ring
);
341 static void ring_write_tail(struct intel_ring_buffer
*ring
,
344 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
345 I915_WRITE_TAIL(ring
, value
);
348 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
350 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
351 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
352 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
354 return I915_READ(acthd_reg
);
357 static int init_ring_common(struct intel_ring_buffer
*ring
)
359 struct drm_device
*dev
= ring
->dev
;
360 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
361 struct drm_i915_gem_object
*obj
= ring
->obj
;
365 if (HAS_FORCE_WAKE(dev
))
366 gen6_gt_force_wake_get(dev_priv
);
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring
, 0);
370 I915_WRITE_HEAD(ring
, 0);
371 ring
->write_tail(ring
, 0);
373 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
375 /* G45 ring initialization fails to reset head to zero */
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
381 I915_READ_HEAD(ring
),
382 I915_READ_TAIL(ring
),
383 I915_READ_START(ring
));
385 I915_WRITE_HEAD(ring
, 0);
387 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
392 I915_READ_HEAD(ring
),
393 I915_READ_TAIL(ring
),
394 I915_READ_START(ring
));
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring
, obj
->gtt_offset
);
404 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
409 I915_READ_START(ring
) == obj
->gtt_offset
&&
410 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
415 I915_READ_HEAD(ring
),
416 I915_READ_TAIL(ring
),
417 I915_READ_START(ring
));
422 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
423 i915_kernel_lost_context(ring
->dev
);
425 ring
->head
= I915_READ_HEAD(ring
);
426 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
427 ring
->space
= ring_space(ring
);
428 ring
->last_retired_head
= -1;
432 if (HAS_FORCE_WAKE(dev
))
433 gen6_gt_force_wake_put(dev_priv
);
439 init_pipe_control(struct intel_ring_buffer
*ring
)
441 struct pipe_control
*pc
;
442 struct drm_i915_gem_object
*obj
;
448 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
452 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
454 DRM_ERROR("Failed to allocate seqno page\n");
459 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
461 ret
= i915_gem_object_pin(obj
, 4096, true, false);
465 pc
->gtt_offset
= obj
->gtt_offset
;
466 pc
->cpu_page
= kmap(sg_page(obj
->pages
->sgl
));
467 if (pc
->cpu_page
== NULL
)
475 i915_gem_object_unpin(obj
);
477 drm_gem_object_unreference(&obj
->base
);
484 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
486 struct pipe_control
*pc
= ring
->private;
487 struct drm_i915_gem_object
*obj
;
494 kunmap(sg_page(obj
->pages
->sgl
));
495 i915_gem_object_unpin(obj
);
496 drm_gem_object_unreference(&obj
->base
);
499 ring
->private = NULL
;
502 static int init_render_ring(struct intel_ring_buffer
*ring
)
504 struct drm_device
*dev
= ring
->dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 int ret
= init_ring_common(ring
);
508 if (INTEL_INFO(dev
)->gen
> 3) {
509 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
511 I915_WRITE(GFX_MODE_GEN7
,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
516 if (INTEL_INFO(dev
)->gen
>= 5) {
517 ret
= init_pipe_control(ring
);
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
528 I915_WRITE(CACHE_MODE_0
,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
535 ring
->itlb_before_ctx_switch
=
536 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
539 if (INTEL_INFO(dev
)->gen
>= 6)
540 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
542 if (HAS_L3_GPU_CACHE(dev
))
543 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
548 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
550 struct drm_device
*dev
= ring
->dev
;
555 if (HAS_BROKEN_CS_TLB(dev
))
556 drm_gem_object_unreference(to_gem_object(ring
->private));
558 cleanup_pipe_control(ring
);
562 update_mboxes(struct intel_ring_buffer
*ring
,
565 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
566 intel_ring_emit(ring
, mmio_offset
);
567 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
571 * gen6_add_request - Update the semaphore mailbox registers
573 * @ring - ring that is adding a request
574 * @seqno - return seqno stuck into the ring
576 * Update the mailbox registers in the *other* rings with the current seqno.
577 * This acts like a signal in the canonical semaphore.
580 gen6_add_request(struct intel_ring_buffer
*ring
)
586 ret
= intel_ring_begin(ring
, 10);
590 mbox1_reg
= ring
->signal_mbox
[0];
591 mbox2_reg
= ring
->signal_mbox
[1];
593 update_mboxes(ring
, mbox1_reg
);
594 update_mboxes(ring
, mbox2_reg
);
595 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
596 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
597 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
598 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
599 intel_ring_advance(ring
);
604 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
608 return dev_priv
->last_seqno
< seqno
;
612 * intel_ring_sync - sync the waiter to the signaller on seqno
614 * @waiter - ring that is waiting
615 * @signaller - ring which has, or will signal
616 * @seqno - seqno which the waiter will block on
619 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
620 struct intel_ring_buffer
*signaller
,
624 u32 dw1
= MI_SEMAPHORE_MBOX
|
625 MI_SEMAPHORE_COMPARE
|
626 MI_SEMAPHORE_REGISTER
;
628 /* Throughout all of the GEM code, seqno passed implies our current
629 * seqno is >= the last seqno executed. However for hardware the
630 * comparison is strictly greater than.
634 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
635 MI_SEMAPHORE_SYNC_INVALID
);
637 ret
= intel_ring_begin(waiter
, 4);
641 /* If seqno wrap happened, omit the wait with no-ops */
642 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
643 intel_ring_emit(waiter
,
645 signaller
->semaphore_register
[waiter
->id
]);
646 intel_ring_emit(waiter
, seqno
);
647 intel_ring_emit(waiter
, 0);
648 intel_ring_emit(waiter
, MI_NOOP
);
650 intel_ring_emit(waiter
, MI_NOOP
);
651 intel_ring_emit(waiter
, MI_NOOP
);
652 intel_ring_emit(waiter
, MI_NOOP
);
653 intel_ring_emit(waiter
, MI_NOOP
);
655 intel_ring_advance(waiter
);
660 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
662 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
663 PIPE_CONTROL_DEPTH_STALL); \
664 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
665 intel_ring_emit(ring__, 0); \
666 intel_ring_emit(ring__, 0); \
670 pc_render_add_request(struct intel_ring_buffer
*ring
)
672 struct pipe_control
*pc
= ring
->private;
673 u32 scratch_addr
= pc
->gtt_offset
+ 128;
676 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
677 * incoherent with writes to memory, i.e. completely fubar,
678 * so we need to use PIPE_NOTIFY instead.
680 * However, we also need to workaround the qword write
681 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
682 * memory before requesting an interrupt.
684 ret
= intel_ring_begin(ring
, 32);
688 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
689 PIPE_CONTROL_WRITE_FLUSH
|
690 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
691 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
692 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
693 intel_ring_emit(ring
, 0);
694 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
695 scratch_addr
+= 128; /* write to separate cachelines */
696 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
698 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
700 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
702 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
704 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
706 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
707 PIPE_CONTROL_WRITE_FLUSH
|
708 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
709 PIPE_CONTROL_NOTIFY
);
710 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
711 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
712 intel_ring_emit(ring
, 0);
713 intel_ring_advance(ring
);
719 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
721 /* Workaround to force correct ordering between irq and seqno writes on
722 * ivb (and maybe also on snb) by reading from a CS register (like
723 * ACTHD) before reading the status page. */
725 intel_ring_get_active_head(ring
);
726 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
730 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
732 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
736 ring_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
738 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
742 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
744 struct pipe_control
*pc
= ring
->private;
745 return pc
->cpu_page
[0];
749 pc_render_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
751 struct pipe_control
*pc
= ring
->private;
752 pc
->cpu_page
[0] = seqno
;
756 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
758 struct drm_device
*dev
= ring
->dev
;
759 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
762 if (!dev
->irq_enabled
)
765 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
766 if (ring
->irq_refcount
++ == 0) {
767 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
768 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
771 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
777 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
779 struct drm_device
*dev
= ring
->dev
;
780 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
783 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
784 if (--ring
->irq_refcount
== 0) {
785 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
786 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
789 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
793 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
795 struct drm_device
*dev
= ring
->dev
;
796 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
799 if (!dev
->irq_enabled
)
802 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
803 if (ring
->irq_refcount
++ == 0) {
804 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
805 I915_WRITE(IMR
, dev_priv
->irq_mask
);
808 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
814 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
816 struct drm_device
*dev
= ring
->dev
;
817 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
820 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
821 if (--ring
->irq_refcount
== 0) {
822 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
823 I915_WRITE(IMR
, dev_priv
->irq_mask
);
826 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
830 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
832 struct drm_device
*dev
= ring
->dev
;
833 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
836 if (!dev
->irq_enabled
)
839 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
840 if (ring
->irq_refcount
++ == 0) {
841 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
842 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
845 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
851 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
853 struct drm_device
*dev
= ring
->dev
;
854 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
857 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
858 if (--ring
->irq_refcount
== 0) {
859 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
860 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
863 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
866 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
868 struct drm_device
*dev
= ring
->dev
;
869 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
872 /* The ring status page addresses are no longer next to the rest of
873 * the ring registers as of gen7.
878 mmio
= RENDER_HWS_PGA_GEN7
;
881 mmio
= BLT_HWS_PGA_GEN7
;
884 mmio
= BSD_HWS_PGA_GEN7
;
887 } else if (IS_GEN6(ring
->dev
)) {
888 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
890 mmio
= RING_HWS_PGA(ring
->mmio_base
);
893 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
898 bsd_ring_flush(struct intel_ring_buffer
*ring
,
899 u32 invalidate_domains
,
904 ret
= intel_ring_begin(ring
, 2);
908 intel_ring_emit(ring
, MI_FLUSH
);
909 intel_ring_emit(ring
, MI_NOOP
);
910 intel_ring_advance(ring
);
915 i9xx_add_request(struct intel_ring_buffer
*ring
)
919 ret
= intel_ring_begin(ring
, 4);
923 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
924 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
925 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
926 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
927 intel_ring_advance(ring
);
933 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
935 struct drm_device
*dev
= ring
->dev
;
936 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
939 if (!dev
->irq_enabled
)
942 /* It looks like we need to prevent the gt from suspending while waiting
943 * for an notifiy irq, otherwise irqs seem to get lost on at least the
944 * blt/bsd rings on ivb. */
945 gen6_gt_force_wake_get(dev_priv
);
947 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
948 if (ring
->irq_refcount
++ == 0) {
949 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
950 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
|
951 GEN6_RENDER_L3_PARITY_ERROR
));
953 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
954 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
955 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
958 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
964 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
966 struct drm_device
*dev
= ring
->dev
;
967 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
970 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
971 if (--ring
->irq_refcount
== 0) {
972 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
973 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
975 I915_WRITE_IMR(ring
, ~0);
976 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
977 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
980 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
982 gen6_gt_force_wake_put(dev_priv
);
986 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
987 u32 offset
, u32 length
,
992 ret
= intel_ring_begin(ring
, 2);
996 intel_ring_emit(ring
,
997 MI_BATCH_BUFFER_START
|
999 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1000 intel_ring_emit(ring
, offset
);
1001 intel_ring_advance(ring
);
1006 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1007 #define I830_BATCH_LIMIT (256*1024)
1009 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1010 u32 offset
, u32 len
,
1015 if (flags
& I915_DISPATCH_PINNED
) {
1016 ret
= intel_ring_begin(ring
, 4);
1020 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1021 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1022 intel_ring_emit(ring
, offset
+ len
- 8);
1023 intel_ring_emit(ring
, MI_NOOP
);
1024 intel_ring_advance(ring
);
1026 struct drm_i915_gem_object
*obj
= ring
->private;
1027 u32 cs_offset
= obj
->gtt_offset
;
1029 if (len
> I830_BATCH_LIMIT
)
1032 ret
= intel_ring_begin(ring
, 9+3);
1035 /* Blit the batch (which has now all relocs applied) to the stable batch
1036 * scratch bo area (so that the CS never stumbles over its tlb
1037 * invalidation bug) ... */
1038 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1039 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1040 XY_SRC_COPY_BLT_WRITE_RGB
);
1041 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1042 intel_ring_emit(ring
, 0);
1043 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1044 intel_ring_emit(ring
, cs_offset
);
1045 intel_ring_emit(ring
, 0);
1046 intel_ring_emit(ring
, 4096);
1047 intel_ring_emit(ring
, offset
);
1048 intel_ring_emit(ring
, MI_FLUSH
);
1050 /* ... and execute it. */
1051 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1052 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1053 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1054 intel_ring_advance(ring
);
1061 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1062 u32 offset
, u32 len
,
1067 ret
= intel_ring_begin(ring
, 2);
1071 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1072 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1073 intel_ring_advance(ring
);
1078 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1080 struct drm_i915_gem_object
*obj
;
1082 obj
= ring
->status_page
.obj
;
1086 kunmap(sg_page(obj
->pages
->sgl
));
1087 i915_gem_object_unpin(obj
);
1088 drm_gem_object_unreference(&obj
->base
);
1089 ring
->status_page
.obj
= NULL
;
1092 static int init_status_page(struct intel_ring_buffer
*ring
)
1094 struct drm_device
*dev
= ring
->dev
;
1095 struct drm_i915_gem_object
*obj
;
1098 obj
= i915_gem_alloc_object(dev
, 4096);
1100 DRM_ERROR("Failed to allocate status page\n");
1105 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1107 ret
= i915_gem_object_pin(obj
, 4096, true, false);
1112 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
1113 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1114 if (ring
->status_page
.page_addr
== NULL
) {
1118 ring
->status_page
.obj
= obj
;
1119 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1121 intel_ring_setup_status_page(ring
);
1122 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1123 ring
->name
, ring
->status_page
.gfx_addr
);
1128 i915_gem_object_unpin(obj
);
1130 drm_gem_object_unreference(&obj
->base
);
1135 static int init_phys_hws_pga(struct intel_ring_buffer
*ring
)
1137 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1140 if (!dev_priv
->status_page_dmah
) {
1141 dev_priv
->status_page_dmah
=
1142 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1143 if (!dev_priv
->status_page_dmah
)
1147 addr
= dev_priv
->status_page_dmah
->busaddr
;
1148 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
1149 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
1150 I915_WRITE(HWS_PGA
, addr
);
1152 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1153 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1158 static int intel_init_ring_buffer(struct drm_device
*dev
,
1159 struct intel_ring_buffer
*ring
)
1161 struct drm_i915_gem_object
*obj
;
1162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1166 INIT_LIST_HEAD(&ring
->active_list
);
1167 INIT_LIST_HEAD(&ring
->request_list
);
1168 ring
->size
= 32 * PAGE_SIZE
;
1169 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1171 init_waitqueue_head(&ring
->irq_queue
);
1173 if (I915_NEED_GFX_HWS(dev
)) {
1174 ret
= init_status_page(ring
);
1178 BUG_ON(ring
->id
!= RCS
);
1179 ret
= init_phys_hws_pga(ring
);
1186 obj
= i915_gem_object_create_stolen(dev
, ring
->size
);
1188 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1190 DRM_ERROR("Failed to allocate ringbuffer\n");
1197 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true, false);
1201 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1205 ring
->virtual_start
=
1206 ioremap_wc(dev_priv
->mm
.gtt
->gma_bus_addr
+ obj
->gtt_offset
,
1208 if (ring
->virtual_start
== NULL
) {
1209 DRM_ERROR("Failed to map ringbuffer.\n");
1214 ret
= ring
->init(ring
);
1218 /* Workaround an erratum on the i830 which causes a hang if
1219 * the TAIL pointer points to within the last 2 cachelines
1222 ring
->effective_size
= ring
->size
;
1223 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1224 ring
->effective_size
-= 128;
1226 intel_ring_init_seqno(ring
, dev_priv
->last_seqno
);
1231 iounmap(ring
->virtual_start
);
1233 i915_gem_object_unpin(obj
);
1235 drm_gem_object_unreference(&obj
->base
);
1238 cleanup_status_page(ring
);
1242 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1244 struct drm_i915_private
*dev_priv
;
1247 if (ring
->obj
== NULL
)
1250 /* Disable the ring buffer. The ring must be idle at this point */
1251 dev_priv
= ring
->dev
->dev_private
;
1252 ret
= intel_ring_idle(ring
);
1254 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1257 I915_WRITE_CTL(ring
, 0);
1259 iounmap(ring
->virtual_start
);
1261 i915_gem_object_unpin(ring
->obj
);
1262 drm_gem_object_unreference(&ring
->obj
->base
);
1266 ring
->cleanup(ring
);
1268 cleanup_status_page(ring
);
1271 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1275 ret
= i915_wait_seqno(ring
, seqno
);
1277 i915_gem_retire_requests_ring(ring
);
1282 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1284 struct drm_i915_gem_request
*request
;
1288 i915_gem_retire_requests_ring(ring
);
1290 if (ring
->last_retired_head
!= -1) {
1291 ring
->head
= ring
->last_retired_head
;
1292 ring
->last_retired_head
= -1;
1293 ring
->space
= ring_space(ring
);
1294 if (ring
->space
>= n
)
1298 list_for_each_entry(request
, &ring
->request_list
, list
) {
1301 if (request
->tail
== -1)
1304 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1306 space
+= ring
->size
;
1308 seqno
= request
->seqno
;
1312 /* Consume this request in case we need more space than
1313 * is available and so need to prevent a race between
1314 * updating last_retired_head and direct reads of
1315 * I915_RING_HEAD. It also provides a nice sanity check.
1323 ret
= intel_ring_wait_seqno(ring
, seqno
);
1327 if (WARN_ON(ring
->last_retired_head
== -1))
1330 ring
->head
= ring
->last_retired_head
;
1331 ring
->last_retired_head
= -1;
1332 ring
->space
= ring_space(ring
);
1333 if (WARN_ON(ring
->space
< n
))
1339 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1341 struct drm_device
*dev
= ring
->dev
;
1342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1346 ret
= intel_ring_wait_request(ring
, n
);
1350 trace_i915_ring_wait_begin(ring
);
1351 /* With GEM the hangcheck timer should kick us out of the loop,
1352 * leaving it early runs the risk of corrupting GEM state (due
1353 * to running on almost untested codepaths). But on resume
1354 * timers don't work yet, so prevent a complete hang in that
1355 * case by choosing an insanely large timeout. */
1356 end
= jiffies
+ 60 * HZ
;
1359 ring
->head
= I915_READ_HEAD(ring
);
1360 ring
->space
= ring_space(ring
);
1361 if (ring
->space
>= n
) {
1362 trace_i915_ring_wait_end(ring
);
1366 if (dev
->primary
->master
) {
1367 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1368 if (master_priv
->sarea_priv
)
1369 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1374 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1377 } while (!time_after(jiffies
, end
));
1378 trace_i915_ring_wait_end(ring
);
1382 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1384 uint32_t __iomem
*virt
;
1385 int rem
= ring
->size
- ring
->tail
;
1387 if (ring
->space
< rem
) {
1388 int ret
= ring_wait_for_space(ring
, rem
);
1393 virt
= ring
->virtual_start
+ ring
->tail
;
1396 iowrite32(MI_NOOP
, virt
++);
1399 ring
->space
= ring_space(ring
);
1404 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1409 /* We need to add any requests required to flush the objects and ring */
1410 if (ring
->outstanding_lazy_request
) {
1411 ret
= i915_add_request(ring
, NULL
, NULL
);
1416 /* Wait upon the last request to be completed */
1417 if (list_empty(&ring
->request_list
))
1420 seqno
= list_entry(ring
->request_list
.prev
,
1421 struct drm_i915_gem_request
,
1424 return i915_wait_seqno(ring
, seqno
);
1428 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1430 if (ring
->outstanding_lazy_request
)
1433 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_request
);
1436 static int __intel_ring_begin(struct intel_ring_buffer
*ring
,
1441 if (unlikely(ring
->tail
+ bytes
> ring
->effective_size
)) {
1442 ret
= intel_wrap_ring_buffer(ring
);
1447 if (unlikely(ring
->space
< bytes
)) {
1448 ret
= ring_wait_for_space(ring
, bytes
);
1453 ring
->space
-= bytes
;
1457 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1460 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1463 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1467 /* Preallocate the olr before touching the ring */
1468 ret
= intel_ring_alloc_seqno(ring
);
1472 return __intel_ring_begin(ring
, num_dwords
* sizeof(uint32_t));
1475 void intel_ring_init_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1477 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1479 BUG_ON(ring
->outstanding_lazy_request
);
1481 if (INTEL_INFO(ring
->dev
)->gen
>= 6) {
1482 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
1483 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
1486 ring
->set_seqno(ring
, seqno
);
1489 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1491 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1493 ring
->tail
&= ring
->size
- 1;
1494 if (dev_priv
->stop_rings
& intel_ring_flag(ring
))
1496 ring
->write_tail(ring
, ring
->tail
);
1500 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1503 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1505 /* Every tail move must follow the sequence below */
1507 /* Disable notification that the ring is IDLE. The GT
1508 * will then assume that it is busy and bring it out of rc6.
1510 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1511 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1513 /* Clear the context id. Here be magic! */
1514 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1516 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1517 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1518 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1520 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1522 /* Now that the ring is fully powered up, update the tail */
1523 I915_WRITE_TAIL(ring
, value
);
1524 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1526 /* Let the ring send IDLE messages to the GT again,
1527 * and so let it sleep to conserve power when idle.
1529 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1530 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1533 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1534 u32 invalidate
, u32 flush
)
1539 ret
= intel_ring_begin(ring
, 4);
1545 * Bspec vol 1c.5 - video engine command streamer:
1546 * "If ENABLED, all TLBs will be invalidated once the flush
1547 * operation is complete. This bit is only valid when the
1548 * Post-Sync Operation field is a value of 1h or 3h."
1550 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1551 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1552 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1553 intel_ring_emit(ring
, cmd
);
1554 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1555 intel_ring_emit(ring
, 0);
1556 intel_ring_emit(ring
, MI_NOOP
);
1557 intel_ring_advance(ring
);
1562 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1563 u32 offset
, u32 len
,
1568 ret
= intel_ring_begin(ring
, 2);
1572 intel_ring_emit(ring
,
1573 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1574 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1575 /* bit0-7 is the length on GEN6+ */
1576 intel_ring_emit(ring
, offset
);
1577 intel_ring_advance(ring
);
1583 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1584 u32 offset
, u32 len
,
1589 ret
= intel_ring_begin(ring
, 2);
1593 intel_ring_emit(ring
,
1594 MI_BATCH_BUFFER_START
|
1595 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1596 /* bit0-7 is the length on GEN6+ */
1597 intel_ring_emit(ring
, offset
);
1598 intel_ring_advance(ring
);
1603 /* Blitter support (SandyBridge+) */
1605 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1606 u32 invalidate
, u32 flush
)
1611 ret
= intel_ring_begin(ring
, 4);
1617 * Bspec vol 1c.3 - blitter engine command streamer:
1618 * "If ENABLED, all TLBs will be invalidated once the flush
1619 * operation is complete. This bit is only valid when the
1620 * Post-Sync Operation field is a value of 1h or 3h."
1622 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1623 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1624 MI_FLUSH_DW_OP_STOREDW
;
1625 intel_ring_emit(ring
, cmd
);
1626 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1627 intel_ring_emit(ring
, 0);
1628 intel_ring_emit(ring
, MI_NOOP
);
1629 intel_ring_advance(ring
);
1633 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1635 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1636 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1638 ring
->name
= "render ring";
1640 ring
->mmio_base
= RENDER_RING_BASE
;
1642 if (INTEL_INFO(dev
)->gen
>= 6) {
1643 ring
->add_request
= gen6_add_request
;
1644 ring
->flush
= gen7_render_ring_flush
;
1645 if (INTEL_INFO(dev
)->gen
== 6)
1646 ring
->flush
= gen6_render_ring_flush
;
1647 ring
->irq_get
= gen6_ring_get_irq
;
1648 ring
->irq_put
= gen6_ring_put_irq
;
1649 ring
->irq_enable_mask
= GT_USER_INTERRUPT
;
1650 ring
->get_seqno
= gen6_ring_get_seqno
;
1651 ring
->set_seqno
= ring_set_seqno
;
1652 ring
->sync_to
= gen6_ring_sync
;
1653 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_INVALID
;
1654 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_RV
;
1655 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_RB
;
1656 ring
->signal_mbox
[0] = GEN6_VRSYNC
;
1657 ring
->signal_mbox
[1] = GEN6_BRSYNC
;
1658 } else if (IS_GEN5(dev
)) {
1659 ring
->add_request
= pc_render_add_request
;
1660 ring
->flush
= gen4_render_ring_flush
;
1661 ring
->get_seqno
= pc_render_get_seqno
;
1662 ring
->set_seqno
= pc_render_set_seqno
;
1663 ring
->irq_get
= gen5_ring_get_irq
;
1664 ring
->irq_put
= gen5_ring_put_irq
;
1665 ring
->irq_enable_mask
= GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
;
1667 ring
->add_request
= i9xx_add_request
;
1668 if (INTEL_INFO(dev
)->gen
< 4)
1669 ring
->flush
= gen2_render_ring_flush
;
1671 ring
->flush
= gen4_render_ring_flush
;
1672 ring
->get_seqno
= ring_get_seqno
;
1673 ring
->set_seqno
= ring_set_seqno
;
1675 ring
->irq_get
= i8xx_ring_get_irq
;
1676 ring
->irq_put
= i8xx_ring_put_irq
;
1678 ring
->irq_get
= i9xx_ring_get_irq
;
1679 ring
->irq_put
= i9xx_ring_put_irq
;
1681 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1683 ring
->write_tail
= ring_write_tail
;
1684 if (IS_HASWELL(dev
))
1685 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1686 else if (INTEL_INFO(dev
)->gen
>= 6)
1687 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1688 else if (INTEL_INFO(dev
)->gen
>= 4)
1689 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1690 else if (IS_I830(dev
) || IS_845G(dev
))
1691 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1693 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1694 ring
->init
= init_render_ring
;
1695 ring
->cleanup
= render_ring_cleanup
;
1697 /* Workaround batchbuffer to combat CS tlb bug. */
1698 if (HAS_BROKEN_CS_TLB(dev
)) {
1699 struct drm_i915_gem_object
*obj
;
1702 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
1704 DRM_ERROR("Failed to allocate batch bo\n");
1708 ret
= i915_gem_object_pin(obj
, 0, true, false);
1710 drm_gem_object_unreference(&obj
->base
);
1711 DRM_ERROR("Failed to ping batch bo\n");
1715 ring
->private = obj
;
1718 return intel_init_ring_buffer(dev
, ring
);
1721 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1724 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1727 ring
->name
= "render ring";
1729 ring
->mmio_base
= RENDER_RING_BASE
;
1731 if (INTEL_INFO(dev
)->gen
>= 6) {
1732 /* non-kms not supported on gen6+ */
1736 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1737 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1738 * the special gen5 functions. */
1739 ring
->add_request
= i9xx_add_request
;
1740 if (INTEL_INFO(dev
)->gen
< 4)
1741 ring
->flush
= gen2_render_ring_flush
;
1743 ring
->flush
= gen4_render_ring_flush
;
1744 ring
->get_seqno
= ring_get_seqno
;
1745 ring
->set_seqno
= ring_set_seqno
;
1747 ring
->irq_get
= i8xx_ring_get_irq
;
1748 ring
->irq_put
= i8xx_ring_put_irq
;
1750 ring
->irq_get
= i9xx_ring_get_irq
;
1751 ring
->irq_put
= i9xx_ring_put_irq
;
1753 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1754 ring
->write_tail
= ring_write_tail
;
1755 if (INTEL_INFO(dev
)->gen
>= 4)
1756 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1757 else if (IS_I830(dev
) || IS_845G(dev
))
1758 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1760 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1761 ring
->init
= init_render_ring
;
1762 ring
->cleanup
= render_ring_cleanup
;
1765 INIT_LIST_HEAD(&ring
->active_list
);
1766 INIT_LIST_HEAD(&ring
->request_list
);
1769 ring
->effective_size
= ring
->size
;
1770 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1771 ring
->effective_size
-= 128;
1773 ring
->virtual_start
= ioremap_wc(start
, size
);
1774 if (ring
->virtual_start
== NULL
) {
1775 DRM_ERROR("can not ioremap virtual address for"
1780 if (!I915_NEED_GFX_HWS(dev
)) {
1781 ret
= init_phys_hws_pga(ring
);
1789 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1791 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1792 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1794 ring
->name
= "bsd ring";
1797 ring
->write_tail
= ring_write_tail
;
1798 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1799 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1800 /* gen6 bsd needs a special wa for tail updates */
1802 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1803 ring
->flush
= gen6_ring_flush
;
1804 ring
->add_request
= gen6_add_request
;
1805 ring
->get_seqno
= gen6_ring_get_seqno
;
1806 ring
->set_seqno
= ring_set_seqno
;
1807 ring
->irq_enable_mask
= GEN6_BSD_USER_INTERRUPT
;
1808 ring
->irq_get
= gen6_ring_get_irq
;
1809 ring
->irq_put
= gen6_ring_put_irq
;
1810 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1811 ring
->sync_to
= gen6_ring_sync
;
1812 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_VR
;
1813 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_INVALID
;
1814 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_VB
;
1815 ring
->signal_mbox
[0] = GEN6_RVSYNC
;
1816 ring
->signal_mbox
[1] = GEN6_BVSYNC
;
1818 ring
->mmio_base
= BSD_RING_BASE
;
1819 ring
->flush
= bsd_ring_flush
;
1820 ring
->add_request
= i9xx_add_request
;
1821 ring
->get_seqno
= ring_get_seqno
;
1822 ring
->set_seqno
= ring_set_seqno
;
1824 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1825 ring
->irq_get
= gen5_ring_get_irq
;
1826 ring
->irq_put
= gen5_ring_put_irq
;
1828 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1829 ring
->irq_get
= i9xx_ring_get_irq
;
1830 ring
->irq_put
= i9xx_ring_put_irq
;
1832 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1834 ring
->init
= init_ring_common
;
1836 return intel_init_ring_buffer(dev
, ring
);
1839 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1841 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1842 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1844 ring
->name
= "blitter ring";
1847 ring
->mmio_base
= BLT_RING_BASE
;
1848 ring
->write_tail
= ring_write_tail
;
1849 ring
->flush
= blt_ring_flush
;
1850 ring
->add_request
= gen6_add_request
;
1851 ring
->get_seqno
= gen6_ring_get_seqno
;
1852 ring
->set_seqno
= ring_set_seqno
;
1853 ring
->irq_enable_mask
= GEN6_BLITTER_USER_INTERRUPT
;
1854 ring
->irq_get
= gen6_ring_get_irq
;
1855 ring
->irq_put
= gen6_ring_put_irq
;
1856 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1857 ring
->sync_to
= gen6_ring_sync
;
1858 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_BR
;
1859 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_BV
;
1860 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_INVALID
;
1861 ring
->signal_mbox
[0] = GEN6_RBSYNC
;
1862 ring
->signal_mbox
[1] = GEN6_VBSYNC
;
1863 ring
->init
= init_ring_common
;
1865 return intel_init_ring_buffer(dev
, ring
);
1869 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
1873 if (!ring
->gpu_caches_dirty
)
1876 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1880 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1882 ring
->gpu_caches_dirty
= false;
1887 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
1889 uint32_t flush_domains
;
1893 if (ring
->gpu_caches_dirty
)
1894 flush_domains
= I915_GEM_GPU_DOMAINS
;
1896 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1900 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1902 ring
->gpu_caches_dirty
= false;