2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 static inline int ring_space(struct intel_ring_buffer
*ring
)
39 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ 8);
45 static u32
i915_gem_get_seqno(struct drm_device
*dev
)
47 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
50 seqno
= dev_priv
->next_seqno
;
52 /* reserve 0 for non-seqno */
53 if (++dev_priv
->next_seqno
== 0)
54 dev_priv
->next_seqno
= 1;
60 render_ring_flush(struct intel_ring_buffer
*ring
,
61 u32 invalidate_domains
,
64 struct drm_device
*dev
= ring
->dev
;
65 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
70 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
71 invalidate_domains
, flush_domains
);
74 trace_i915_gem_request_flush(dev
, dev_priv
->next_seqno
,
75 invalidate_domains
, flush_domains
);
77 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
81 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
82 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
83 * also flushed at 2d versus 3d pipeline switches.
87 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
88 * MI_READ_FLUSH is set, and is always flushed on 965.
90 * I915_GEM_DOMAIN_COMMAND may not exist?
92 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
93 * invalidated when MI_EXE_FLUSH is set.
95 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
96 * invalidated with every MI_FLUSH.
100 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
101 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
102 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
103 * are flushed at any MI_FLUSH.
106 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
107 if ((invalidate_domains
|flush_domains
) &
108 I915_GEM_DOMAIN_RENDER
)
109 cmd
&= ~MI_NO_WRITE_FLUSH
;
110 if (INTEL_INFO(dev
)->gen
< 4) {
112 * On the 965, the sampler cache always gets flushed
113 * and this bit is reserved.
115 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
116 cmd
|= MI_READ_FLUSH
;
118 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
121 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
122 (IS_G4X(dev
) || IS_GEN5(dev
)))
123 cmd
|= MI_INVALIDATE_ISP
;
126 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
128 ret
= intel_ring_begin(ring
, 2);
132 intel_ring_emit(ring
, cmd
);
133 intel_ring_emit(ring
, MI_NOOP
);
134 intel_ring_advance(ring
);
140 static void ring_write_tail(struct intel_ring_buffer
*ring
,
143 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
144 I915_WRITE_TAIL(ring
, value
);
147 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
149 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
150 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
151 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
153 return I915_READ(acthd_reg
);
156 static int init_ring_common(struct intel_ring_buffer
*ring
)
158 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
159 struct drm_i915_gem_object
*obj
= ring
->obj
;
162 /* Stop the ring if it's running. */
163 I915_WRITE_CTL(ring
, 0);
164 I915_WRITE_HEAD(ring
, 0);
165 ring
->write_tail(ring
, 0);
167 /* Initialize the ring. */
168 I915_WRITE_START(ring
, obj
->gtt_offset
);
169 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
171 /* G45 ring initialization fails to reset head to zero */
173 DRM_DEBUG_KMS("%s head not reset to zero "
174 "ctl %08x head %08x tail %08x start %08x\n",
177 I915_READ_HEAD(ring
),
178 I915_READ_TAIL(ring
),
179 I915_READ_START(ring
));
181 I915_WRITE_HEAD(ring
, 0);
183 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
184 DRM_ERROR("failed to set %s head to zero "
185 "ctl %08x head %08x tail %08x start %08x\n",
188 I915_READ_HEAD(ring
),
189 I915_READ_TAIL(ring
),
190 I915_READ_START(ring
));
195 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
196 | RING_REPORT_64K
| RING_VALID
);
198 /* If the head is still not zero, the ring is dead */
199 if ((I915_READ_CTL(ring
) & RING_VALID
) == 0 ||
200 I915_READ_START(ring
) != obj
->gtt_offset
||
201 (I915_READ_HEAD(ring
) & HEAD_ADDR
) != 0) {
202 DRM_ERROR("%s initialization failed "
203 "ctl %08x head %08x tail %08x start %08x\n",
206 I915_READ_HEAD(ring
),
207 I915_READ_TAIL(ring
),
208 I915_READ_START(ring
));
212 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
213 i915_kernel_lost_context(ring
->dev
);
215 ring
->head
= I915_READ_HEAD(ring
);
216 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
217 ring
->space
= ring_space(ring
);
224 * 965+ support PIPE_CONTROL commands, which provide finer grained control
225 * over cache flushing.
227 struct pipe_control
{
228 struct drm_i915_gem_object
*obj
;
229 volatile u32
*cpu_page
;
234 init_pipe_control(struct intel_ring_buffer
*ring
)
236 struct pipe_control
*pc
;
237 struct drm_i915_gem_object
*obj
;
243 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
247 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
249 DRM_ERROR("Failed to allocate seqno page\n");
253 obj
->agp_type
= AGP_USER_CACHED_MEMORY
;
255 ret
= i915_gem_object_pin(obj
, 4096, true);
259 pc
->gtt_offset
= obj
->gtt_offset
;
260 pc
->cpu_page
= kmap(obj
->pages
[0]);
261 if (pc
->cpu_page
== NULL
)
269 i915_gem_object_unpin(obj
);
271 drm_gem_object_unreference(&obj
->base
);
278 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
280 struct pipe_control
*pc
= ring
->private;
281 struct drm_i915_gem_object
*obj
;
287 kunmap(obj
->pages
[0]);
288 i915_gem_object_unpin(obj
);
289 drm_gem_object_unreference(&obj
->base
);
292 ring
->private = NULL
;
295 static int init_render_ring(struct intel_ring_buffer
*ring
)
297 struct drm_device
*dev
= ring
->dev
;
298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
299 int ret
= init_ring_common(ring
);
301 if (INTEL_INFO(dev
)->gen
> 3) {
302 int mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
304 mode
|= MI_FLUSH_ENABLE
<< 16 | MI_FLUSH_ENABLE
;
305 I915_WRITE(MI_MODE
, mode
);
308 if (INTEL_INFO(dev
)->gen
>= 6) {
309 } else if (IS_GEN5(dev
)) {
310 ret
= init_pipe_control(ring
);
318 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
323 cleanup_pipe_control(ring
);
327 update_semaphore(struct intel_ring_buffer
*ring
, int i
, u32 seqno
)
329 struct drm_device
*dev
= ring
->dev
;
330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
334 * cs -> 1 = vcs, 0 = bcs
335 * vcs -> 1 = bcs, 0 = cs,
336 * bcs -> 1 = cs, 0 = vcs.
338 id
= ring
- dev_priv
->ring
;
342 intel_ring_emit(ring
,
344 MI_SEMAPHORE_REGISTER
|
345 MI_SEMAPHORE_UPDATE
);
346 intel_ring_emit(ring
, seqno
);
347 intel_ring_emit(ring
,
348 RING_SYNC_0(dev_priv
->ring
[id
].mmio_base
) + 4*i
);
352 gen6_add_request(struct intel_ring_buffer
*ring
,
358 ret
= intel_ring_begin(ring
, 10);
362 seqno
= i915_gem_get_seqno(ring
->dev
);
363 update_semaphore(ring
, 0, seqno
);
364 update_semaphore(ring
, 1, seqno
);
366 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
367 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
368 intel_ring_emit(ring
, seqno
);
369 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
370 intel_ring_advance(ring
);
377 intel_ring_sync(struct intel_ring_buffer
*ring
,
378 struct intel_ring_buffer
*to
,
383 ret
= intel_ring_begin(ring
, 4);
387 intel_ring_emit(ring
,
389 MI_SEMAPHORE_REGISTER
|
390 intel_ring_sync_index(ring
, to
) << 17 |
391 MI_SEMAPHORE_COMPARE
);
392 intel_ring_emit(ring
, seqno
);
393 intel_ring_emit(ring
, 0);
394 intel_ring_emit(ring
, MI_NOOP
);
395 intel_ring_advance(ring
);
400 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
402 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
403 PIPE_CONTROL_DEPTH_STALL | 2); \
404 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
405 intel_ring_emit(ring__, 0); \
406 intel_ring_emit(ring__, 0); \
410 pc_render_add_request(struct intel_ring_buffer
*ring
,
413 struct drm_device
*dev
= ring
->dev
;
414 u32 seqno
= i915_gem_get_seqno(dev
);
415 struct pipe_control
*pc
= ring
->private;
416 u32 scratch_addr
= pc
->gtt_offset
+ 128;
419 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
420 * incoherent with writes to memory, i.e. completely fubar,
421 * so we need to use PIPE_NOTIFY instead.
423 * However, we also need to workaround the qword write
424 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
425 * memory before requesting an interrupt.
427 ret
= intel_ring_begin(ring
, 32);
431 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL
| PIPE_CONTROL_QW_WRITE
|
432 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_TC_FLUSH
);
433 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
434 intel_ring_emit(ring
, seqno
);
435 intel_ring_emit(ring
, 0);
436 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
437 scratch_addr
+= 128; /* write to separate cachelines */
438 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
440 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
442 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
444 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
446 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
447 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL
| PIPE_CONTROL_QW_WRITE
|
448 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_TC_FLUSH
|
449 PIPE_CONTROL_NOTIFY
);
450 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
451 intel_ring_emit(ring
, seqno
);
452 intel_ring_emit(ring
, 0);
453 intel_ring_advance(ring
);
460 render_ring_add_request(struct intel_ring_buffer
*ring
,
463 struct drm_device
*dev
= ring
->dev
;
464 u32 seqno
= i915_gem_get_seqno(dev
);
467 ret
= intel_ring_begin(ring
, 4);
471 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
472 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
473 intel_ring_emit(ring
, seqno
);
474 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
475 intel_ring_advance(ring
);
482 ring_get_seqno(struct intel_ring_buffer
*ring
)
484 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
488 pc_render_get_seqno(struct intel_ring_buffer
*ring
)
490 struct pipe_control
*pc
= ring
->private;
491 return pc
->cpu_page
[0];
495 ironlake_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
497 dev_priv
->gt_irq_mask
&= ~mask
;
498 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
503 ironlake_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
505 dev_priv
->gt_irq_mask
|= mask
;
506 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
511 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
513 dev_priv
->irq_mask
&= ~mask
;
514 I915_WRITE(IMR
, dev_priv
->irq_mask
);
519 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
521 dev_priv
->irq_mask
|= mask
;
522 I915_WRITE(IMR
, dev_priv
->irq_mask
);
527 render_ring_get_irq(struct intel_ring_buffer
*ring
)
529 struct drm_device
*dev
= ring
->dev
;
530 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
532 if (!dev
->irq_enabled
)
535 spin_lock(&ring
->irq_lock
);
536 if (ring
->irq_refcount
++ == 0) {
537 if (HAS_PCH_SPLIT(dev
))
538 ironlake_enable_irq(dev_priv
,
539 GT_PIPE_NOTIFY
| GT_USER_INTERRUPT
);
541 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
543 spin_unlock(&ring
->irq_lock
);
549 render_ring_put_irq(struct intel_ring_buffer
*ring
)
551 struct drm_device
*dev
= ring
->dev
;
552 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
554 spin_lock(&ring
->irq_lock
);
555 if (--ring
->irq_refcount
== 0) {
556 if (HAS_PCH_SPLIT(dev
))
557 ironlake_disable_irq(dev_priv
,
561 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
563 spin_unlock(&ring
->irq_lock
);
566 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
568 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
569 u32 mmio
= IS_GEN6(ring
->dev
) ?
570 RING_HWS_PGA_GEN6(ring
->mmio_base
) :
571 RING_HWS_PGA(ring
->mmio_base
);
572 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
577 bsd_ring_flush(struct intel_ring_buffer
*ring
,
578 u32 invalidate_domains
,
583 if ((flush_domains
& I915_GEM_DOMAIN_RENDER
) == 0)
586 ret
= intel_ring_begin(ring
, 2);
590 intel_ring_emit(ring
, MI_FLUSH
);
591 intel_ring_emit(ring
, MI_NOOP
);
592 intel_ring_advance(ring
);
597 ring_add_request(struct intel_ring_buffer
*ring
,
603 ret
= intel_ring_begin(ring
, 4);
607 seqno
= i915_gem_get_seqno(ring
->dev
);
609 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
610 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
611 intel_ring_emit(ring
, seqno
);
612 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
613 intel_ring_advance(ring
);
615 DRM_DEBUG_DRIVER("%s %d\n", ring
->name
, seqno
);
621 ring_get_irq(struct intel_ring_buffer
*ring
, u32 flag
)
623 struct drm_device
*dev
= ring
->dev
;
624 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
626 if (!dev
->irq_enabled
)
629 spin_lock(&ring
->irq_lock
);
630 if (ring
->irq_refcount
++ == 0)
631 ironlake_enable_irq(dev_priv
, flag
);
632 spin_unlock(&ring
->irq_lock
);
638 ring_put_irq(struct intel_ring_buffer
*ring
, u32 flag
)
640 struct drm_device
*dev
= ring
->dev
;
641 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
643 spin_lock(&ring
->irq_lock
);
644 if (--ring
->irq_refcount
== 0)
645 ironlake_disable_irq(dev_priv
, flag
);
646 spin_unlock(&ring
->irq_lock
);
650 gen6_ring_get_irq(struct intel_ring_buffer
*ring
, u32 gflag
, u32 rflag
)
652 struct drm_device
*dev
= ring
->dev
;
653 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
655 if (!dev
->irq_enabled
)
658 spin_lock(&ring
->irq_lock
);
659 if (ring
->irq_refcount
++ == 0) {
660 ring
->irq_mask
&= ~rflag
;
661 I915_WRITE_IMR(ring
, ring
->irq_mask
);
662 ironlake_enable_irq(dev_priv
, gflag
);
664 spin_unlock(&ring
->irq_lock
);
670 gen6_ring_put_irq(struct intel_ring_buffer
*ring
, u32 gflag
, u32 rflag
)
672 struct drm_device
*dev
= ring
->dev
;
673 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
675 spin_lock(&ring
->irq_lock
);
676 if (--ring
->irq_refcount
== 0) {
677 ring
->irq_mask
|= rflag
;
678 I915_WRITE_IMR(ring
, ring
->irq_mask
);
679 ironlake_disable_irq(dev_priv
, gflag
);
681 spin_unlock(&ring
->irq_lock
);
685 bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
687 return ring_get_irq(ring
, GT_BSD_USER_INTERRUPT
);
690 bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
692 ring_put_irq(ring
, GT_BSD_USER_INTERRUPT
);
696 ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
, u32 offset
, u32 length
)
700 ret
= intel_ring_begin(ring
, 2);
704 intel_ring_emit(ring
,
705 MI_BATCH_BUFFER_START
| (2 << 6) |
706 MI_BATCH_NON_SECURE_I965
);
707 intel_ring_emit(ring
, offset
);
708 intel_ring_advance(ring
);
714 render_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
717 struct drm_device
*dev
= ring
->dev
;
718 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
721 trace_i915_gem_request_submit(dev
, dev_priv
->next_seqno
+ 1);
723 if (IS_I830(dev
) || IS_845G(dev
)) {
724 ret
= intel_ring_begin(ring
, 4);
728 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
729 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
730 intel_ring_emit(ring
, offset
+ len
- 8);
731 intel_ring_emit(ring
, 0);
733 ret
= intel_ring_begin(ring
, 2);
737 if (INTEL_INFO(dev
)->gen
>= 4) {
738 intel_ring_emit(ring
,
739 MI_BATCH_BUFFER_START
| (2 << 6) |
740 MI_BATCH_NON_SECURE_I965
);
741 intel_ring_emit(ring
, offset
);
743 intel_ring_emit(ring
,
744 MI_BATCH_BUFFER_START
| (2 << 6));
745 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
748 intel_ring_advance(ring
);
753 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
755 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
756 struct drm_i915_gem_object
*obj
;
758 obj
= ring
->status_page
.obj
;
762 kunmap(obj
->pages
[0]);
763 i915_gem_object_unpin(obj
);
764 drm_gem_object_unreference(&obj
->base
);
765 ring
->status_page
.obj
= NULL
;
767 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
770 static int init_status_page(struct intel_ring_buffer
*ring
)
772 struct drm_device
*dev
= ring
->dev
;
773 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
774 struct drm_i915_gem_object
*obj
;
777 obj
= i915_gem_alloc_object(dev
, 4096);
779 DRM_ERROR("Failed to allocate status page\n");
783 obj
->agp_type
= AGP_USER_CACHED_MEMORY
;
785 ret
= i915_gem_object_pin(obj
, 4096, true);
790 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
791 ring
->status_page
.page_addr
= kmap(obj
->pages
[0]);
792 if (ring
->status_page
.page_addr
== NULL
) {
793 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
796 ring
->status_page
.obj
= obj
;
797 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
799 intel_ring_setup_status_page(ring
);
800 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
801 ring
->name
, ring
->status_page
.gfx_addr
);
806 i915_gem_object_unpin(obj
);
808 drm_gem_object_unreference(&obj
->base
);
813 int intel_init_ring_buffer(struct drm_device
*dev
,
814 struct intel_ring_buffer
*ring
)
816 struct drm_i915_gem_object
*obj
;
820 INIT_LIST_HEAD(&ring
->active_list
);
821 INIT_LIST_HEAD(&ring
->request_list
);
822 INIT_LIST_HEAD(&ring
->gpu_write_list
);
824 spin_lock_init(&ring
->irq_lock
);
827 if (I915_NEED_GFX_HWS(dev
)) {
828 ret
= init_status_page(ring
);
833 obj
= i915_gem_alloc_object(dev
, ring
->size
);
835 DRM_ERROR("Failed to allocate ringbuffer\n");
842 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
846 ring
->map
.size
= ring
->size
;
847 ring
->map
.offset
= dev
->agp
->base
+ obj
->gtt_offset
;
852 drm_core_ioremap_wc(&ring
->map
, dev
);
853 if (ring
->map
.handle
== NULL
) {
854 DRM_ERROR("Failed to map ringbuffer.\n");
859 ring
->virtual_start
= ring
->map
.handle
;
860 ret
= ring
->init(ring
);
864 /* Workaround an erratum on the i830 which causes a hang if
865 * the TAIL pointer points to within the last 2 cachelines
868 ring
->effective_size
= ring
->size
;
869 if (IS_I830(ring
->dev
))
870 ring
->effective_size
-= 128;
875 drm_core_ioremapfree(&ring
->map
, dev
);
877 i915_gem_object_unpin(obj
);
879 drm_gem_object_unreference(&obj
->base
);
882 cleanup_status_page(ring
);
886 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
888 struct drm_i915_private
*dev_priv
;
891 if (ring
->obj
== NULL
)
894 /* Disable the ring buffer. The ring must be idle at this point */
895 dev_priv
= ring
->dev
->dev_private
;
896 ret
= intel_wait_ring_buffer(ring
, ring
->size
- 8);
897 I915_WRITE_CTL(ring
, 0);
899 drm_core_ioremapfree(&ring
->map
, ring
->dev
);
901 i915_gem_object_unpin(ring
->obj
);
902 drm_gem_object_unreference(&ring
->obj
->base
);
908 cleanup_status_page(ring
);
911 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
914 int rem
= ring
->size
- ring
->tail
;
916 if (ring
->space
< rem
) {
917 int ret
= intel_wait_ring_buffer(ring
, rem
);
922 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
930 ring
->space
= ring_space(ring
);
935 int intel_wait_ring_buffer(struct intel_ring_buffer
*ring
, int n
)
937 struct drm_device
*dev
= ring
->dev
;
938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
942 /* If the reported head position has wrapped or hasn't advanced,
943 * fallback to the slow and accurate path.
945 head
= intel_read_status_page(ring
, 4);
946 if (head
> ring
->head
) {
948 ring
->space
= ring_space(ring
);
949 if (ring
->space
>= n
)
953 trace_i915_ring_wait_begin (dev
);
954 end
= jiffies
+ 3 * HZ
;
956 ring
->head
= I915_READ_HEAD(ring
);
957 ring
->space
= ring_space(ring
);
958 if (ring
->space
>= n
) {
959 trace_i915_ring_wait_end(dev
);
963 if (dev
->primary
->master
) {
964 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
965 if (master_priv
->sarea_priv
)
966 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
970 if (atomic_read(&dev_priv
->mm
.wedged
))
972 } while (!time_after(jiffies
, end
));
973 trace_i915_ring_wait_end (dev
);
977 int intel_ring_begin(struct intel_ring_buffer
*ring
,
980 int n
= 4*num_dwords
;
983 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
984 ret
= intel_wrap_ring_buffer(ring
);
989 if (unlikely(ring
->space
< n
)) {
990 ret
= intel_wait_ring_buffer(ring
, n
);
999 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1001 ring
->tail
&= ring
->size
- 1;
1002 ring
->write_tail(ring
, ring
->tail
);
1005 static const struct intel_ring_buffer render_ring
= {
1006 .name
= "render ring",
1008 .mmio_base
= RENDER_RING_BASE
,
1009 .size
= 32 * PAGE_SIZE
,
1010 .init
= init_render_ring
,
1011 .write_tail
= ring_write_tail
,
1012 .flush
= render_ring_flush
,
1013 .add_request
= render_ring_add_request
,
1014 .get_seqno
= ring_get_seqno
,
1015 .irq_get
= render_ring_get_irq
,
1016 .irq_put
= render_ring_put_irq
,
1017 .dispatch_execbuffer
= render_ring_dispatch_execbuffer
,
1018 .cleanup
= render_ring_cleanup
,
1021 /* ring buffer for bit-stream decoder */
1023 static const struct intel_ring_buffer bsd_ring
= {
1026 .mmio_base
= BSD_RING_BASE
,
1027 .size
= 32 * PAGE_SIZE
,
1028 .init
= init_ring_common
,
1029 .write_tail
= ring_write_tail
,
1030 .flush
= bsd_ring_flush
,
1031 .add_request
= ring_add_request
,
1032 .get_seqno
= ring_get_seqno
,
1033 .irq_get
= bsd_ring_get_irq
,
1034 .irq_put
= bsd_ring_put_irq
,
1035 .dispatch_execbuffer
= ring_dispatch_execbuffer
,
1039 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1042 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1044 /* Every tail move must follow the sequence below */
1045 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1046 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1047 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE
);
1048 I915_WRITE(GEN6_BSD_RNCID
, 0x0);
1050 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1051 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR
) == 0,
1053 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1055 I915_WRITE_TAIL(ring
, value
);
1056 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1057 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1058 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE
);
1061 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1062 u32 invalidate_domains
,
1067 if ((flush_domains
& I915_GEM_DOMAIN_RENDER
) == 0)
1070 ret
= intel_ring_begin(ring
, 4);
1074 intel_ring_emit(ring
, MI_FLUSH_DW
);
1075 intel_ring_emit(ring
, 0);
1076 intel_ring_emit(ring
, 0);
1077 intel_ring_emit(ring
, 0);
1078 intel_ring_advance(ring
);
1083 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1084 u32 offset
, u32 len
)
1088 ret
= intel_ring_begin(ring
, 2);
1092 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
);
1093 /* bit0-7 is the length on GEN6+ */
1094 intel_ring_emit(ring
, offset
);
1095 intel_ring_advance(ring
);
1101 gen6_render_ring_get_irq(struct intel_ring_buffer
*ring
)
1103 return gen6_ring_get_irq(ring
,
1105 GEN6_RENDER_USER_INTERRUPT
);
1109 gen6_render_ring_put_irq(struct intel_ring_buffer
*ring
)
1111 return gen6_ring_put_irq(ring
,
1113 GEN6_RENDER_USER_INTERRUPT
);
1117 gen6_bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
1119 return gen6_ring_get_irq(ring
,
1120 GT_GEN6_BSD_USER_INTERRUPT
,
1121 GEN6_BSD_USER_INTERRUPT
);
1125 gen6_bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
1127 return gen6_ring_put_irq(ring
,
1128 GT_GEN6_BSD_USER_INTERRUPT
,
1129 GEN6_BSD_USER_INTERRUPT
);
1132 /* ring buffer for Video Codec for Gen6+ */
1133 static const struct intel_ring_buffer gen6_bsd_ring
= {
1134 .name
= "gen6 bsd ring",
1136 .mmio_base
= GEN6_BSD_RING_BASE
,
1137 .size
= 32 * PAGE_SIZE
,
1138 .init
= init_ring_common
,
1139 .write_tail
= gen6_bsd_ring_write_tail
,
1140 .flush
= gen6_ring_flush
,
1141 .add_request
= gen6_add_request
,
1142 .get_seqno
= ring_get_seqno
,
1143 .irq_get
= gen6_bsd_ring_get_irq
,
1144 .irq_put
= gen6_bsd_ring_put_irq
,
1145 .dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
,
1148 /* Blitter support (SandyBridge+) */
1151 blt_ring_get_irq(struct intel_ring_buffer
*ring
)
1153 return gen6_ring_get_irq(ring
,
1154 GT_BLT_USER_INTERRUPT
,
1155 GEN6_BLITTER_USER_INTERRUPT
);
1159 blt_ring_put_irq(struct intel_ring_buffer
*ring
)
1161 gen6_ring_put_irq(ring
,
1162 GT_BLT_USER_INTERRUPT
,
1163 GEN6_BLITTER_USER_INTERRUPT
);
1167 /* Workaround for some stepping of SNB,
1168 * each time when BLT engine ring tail moved,
1169 * the first command in the ring to be parsed
1170 * should be MI_BATCH_BUFFER_START
1172 #define NEED_BLT_WORKAROUND(dev) \
1173 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1175 static inline struct drm_i915_gem_object
*
1176 to_blt_workaround(struct intel_ring_buffer
*ring
)
1178 return ring
->private;
1181 static int blt_ring_init(struct intel_ring_buffer
*ring
)
1183 if (NEED_BLT_WORKAROUND(ring
->dev
)) {
1184 struct drm_i915_gem_object
*obj
;
1188 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1192 ret
= i915_gem_object_pin(obj
, 4096, true);
1194 drm_gem_object_unreference(&obj
->base
);
1198 ptr
= kmap(obj
->pages
[0]);
1199 *ptr
++ = MI_BATCH_BUFFER_END
;
1201 kunmap(obj
->pages
[0]);
1203 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1205 i915_gem_object_unpin(obj
);
1206 drm_gem_object_unreference(&obj
->base
);
1210 ring
->private = obj
;
1213 return init_ring_common(ring
);
1216 static int blt_ring_begin(struct intel_ring_buffer
*ring
,
1219 if (ring
->private) {
1220 int ret
= intel_ring_begin(ring
, num_dwords
+2);
1224 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
);
1225 intel_ring_emit(ring
, to_blt_workaround(ring
)->gtt_offset
);
1229 return intel_ring_begin(ring
, 4);
1232 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1233 u32 invalidate_domains
,
1238 if ((flush_domains
& I915_GEM_DOMAIN_RENDER
) == 0)
1241 ret
= blt_ring_begin(ring
, 4);
1245 intel_ring_emit(ring
, MI_FLUSH_DW
);
1246 intel_ring_emit(ring
, 0);
1247 intel_ring_emit(ring
, 0);
1248 intel_ring_emit(ring
, 0);
1249 intel_ring_advance(ring
);
1253 static void blt_ring_cleanup(struct intel_ring_buffer
*ring
)
1258 i915_gem_object_unpin(ring
->private);
1259 drm_gem_object_unreference(ring
->private);
1260 ring
->private = NULL
;
1263 static const struct intel_ring_buffer gen6_blt_ring
= {
1266 .mmio_base
= BLT_RING_BASE
,
1267 .size
= 32 * PAGE_SIZE
,
1268 .init
= blt_ring_init
,
1269 .write_tail
= ring_write_tail
,
1270 .flush
= blt_ring_flush
,
1271 .add_request
= gen6_add_request
,
1272 .get_seqno
= ring_get_seqno
,
1273 .irq_get
= blt_ring_get_irq
,
1274 .irq_put
= blt_ring_put_irq
,
1275 .dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
,
1276 .cleanup
= blt_ring_cleanup
,
1279 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1281 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1282 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1284 *ring
= render_ring
;
1285 if (INTEL_INFO(dev
)->gen
>= 6) {
1286 ring
->add_request
= gen6_add_request
;
1287 ring
->irq_get
= gen6_render_ring_get_irq
;
1288 ring
->irq_put
= gen6_render_ring_put_irq
;
1289 } else if (IS_GEN5(dev
)) {
1290 ring
->add_request
= pc_render_add_request
;
1291 ring
->get_seqno
= pc_render_get_seqno
;
1294 if (!I915_NEED_GFX_HWS(dev
)) {
1295 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1296 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1299 return intel_init_ring_buffer(dev
, ring
);
1302 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1304 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1305 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1307 *ring
= render_ring
;
1308 if (INTEL_INFO(dev
)->gen
>= 6) {
1309 ring
->add_request
= gen6_add_request
;
1310 ring
->irq_get
= gen6_render_ring_get_irq
;
1311 ring
->irq_put
= gen6_render_ring_put_irq
;
1312 } else if (IS_GEN5(dev
)) {
1313 ring
->add_request
= pc_render_add_request
;
1314 ring
->get_seqno
= pc_render_get_seqno
;
1318 INIT_LIST_HEAD(&ring
->active_list
);
1319 INIT_LIST_HEAD(&ring
->request_list
);
1320 INIT_LIST_HEAD(&ring
->gpu_write_list
);
1323 ring
->effective_size
= ring
->size
;
1324 if (IS_I830(ring
->dev
))
1325 ring
->effective_size
-= 128;
1327 ring
->map
.offset
= start
;
1328 ring
->map
.size
= size
;
1330 ring
->map
.flags
= 0;
1333 drm_core_ioremap_wc(&ring
->map
, dev
);
1334 if (ring
->map
.handle
== NULL
) {
1335 DRM_ERROR("can not ioremap virtual address for"
1340 ring
->virtual_start
= (void __force __iomem
*)ring
->map
.handle
;
1344 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1346 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1347 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1350 *ring
= gen6_bsd_ring
;
1354 return intel_init_ring_buffer(dev
, ring
);
1357 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1359 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1360 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1362 *ring
= gen6_blt_ring
;
1364 return intel_init_ring_buffer(dev
, ring
);