2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 int __intel_ring_space(int head
, int tail
, int size
)
39 int space
= head
- tail
;
42 return space
- I915_RING_FREE_SPACE
;
45 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
47 if (ringbuf
->last_retired_head
!= -1) {
48 ringbuf
->head
= ringbuf
->last_retired_head
;
49 ringbuf
->last_retired_head
= -1;
52 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
53 ringbuf
->tail
, ringbuf
->size
);
56 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
58 intel_ring_update_space(ringbuf
);
59 return ringbuf
->space
;
62 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
64 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
65 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
68 static void __intel_ring_advance(struct intel_engine_cs
*ring
)
70 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
71 ringbuf
->tail
&= ringbuf
->size
- 1;
72 if (intel_ring_stopped(ring
))
74 ring
->write_tail(ring
, ringbuf
->tail
);
78 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
79 u32 invalidate_domains
,
82 struct intel_engine_cs
*ring
= req
->ring
;
87 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
88 cmd
|= MI_NO_WRITE_FLUSH
;
90 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
93 ret
= intel_ring_begin(req
, 2);
97 intel_ring_emit(ring
, cmd
);
98 intel_ring_emit(ring
, MI_NOOP
);
99 intel_ring_advance(ring
);
105 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
106 u32 invalidate_domains
,
109 struct intel_engine_cs
*ring
= req
->ring
;
110 struct drm_device
*dev
= ring
->dev
;
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
126 * I915_GEM_DOMAIN_COMMAND may not exist?
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
142 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
143 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
144 cmd
&= ~MI_NO_WRITE_FLUSH
;
145 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
148 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
149 (IS_G4X(dev
) || IS_GEN5(dev
)))
150 cmd
|= MI_INVALIDATE_ISP
;
152 ret
= intel_ring_begin(req
, 2);
156 intel_ring_emit(ring
, cmd
);
157 intel_ring_emit(ring
, MI_NOOP
);
158 intel_ring_advance(ring
);
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
176 * And the workaround for these two requires this workaround first:
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
203 struct intel_engine_cs
*ring
= req
->ring
;
204 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
207 ret
= intel_ring_begin(req
, 6);
211 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
213 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
214 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
215 intel_ring_emit(ring
, 0); /* low dword */
216 intel_ring_emit(ring
, 0); /* high dword */
217 intel_ring_emit(ring
, MI_NOOP
);
218 intel_ring_advance(ring
);
220 ret
= intel_ring_begin(req
, 6);
224 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
226 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
227 intel_ring_emit(ring
, 0);
228 intel_ring_emit(ring
, 0);
229 intel_ring_emit(ring
, MI_NOOP
);
230 intel_ring_advance(ring
);
236 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
237 u32 invalidate_domains
, u32 flush_domains
)
239 struct intel_engine_cs
*ring
= req
->ring
;
241 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
244 /* Force SNB workarounds for PIPE_CONTROL flushes */
245 ret
= intel_emit_post_sync_nonzero_flush(req
);
249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
254 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
255 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
260 flags
|= PIPE_CONTROL_CS_STALL
;
262 if (invalidate_domains
) {
263 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
264 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
265 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
266 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
267 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
268 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
270 * TLB invalidate requires a post-sync write.
272 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
275 ret
= intel_ring_begin(req
, 4);
279 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(ring
, flags
);
281 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
282 intel_ring_emit(ring
, 0);
283 intel_ring_advance(ring
);
289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
291 struct intel_engine_cs
*ring
= req
->ring
;
294 ret
= intel_ring_begin(req
, 4);
298 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
300 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
301 intel_ring_emit(ring
, 0);
302 intel_ring_emit(ring
, 0);
303 intel_ring_advance(ring
);
309 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
310 u32 invalidate_domains
, u32 flush_domains
)
312 struct intel_engine_cs
*ring
= req
->ring
;
314 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
325 flags
|= PIPE_CONTROL_CS_STALL
;
327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
332 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
333 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
334 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
335 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
337 if (invalidate_domains
) {
338 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
339 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
340 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
341 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
342 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
343 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
344 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
346 * TLB invalidate requires a post-sync write.
348 flags
|= PIPE_CONTROL_QW_WRITE
;
349 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
351 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
356 gen7_render_ring_cs_stall_wa(req
);
359 ret
= intel_ring_begin(req
, 4);
363 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(ring
, flags
);
365 intel_ring_emit(ring
, scratch_addr
);
366 intel_ring_emit(ring
, 0);
367 intel_ring_advance(ring
);
373 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
374 u32 flags
, u32 scratch_addr
)
376 struct intel_engine_cs
*ring
= req
->ring
;
379 ret
= intel_ring_begin(req
, 6);
383 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(ring
, flags
);
385 intel_ring_emit(ring
, scratch_addr
);
386 intel_ring_emit(ring
, 0);
387 intel_ring_emit(ring
, 0);
388 intel_ring_emit(ring
, 0);
389 intel_ring_advance(ring
);
395 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
396 u32 invalidate_domains
, u32 flush_domains
)
399 u32 scratch_addr
= req
->ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
402 flags
|= PIPE_CONTROL_CS_STALL
;
405 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
406 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
407 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
408 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
410 if (invalidate_domains
) {
411 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
412 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
413 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
414 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
415 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
416 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
417 flags
|= PIPE_CONTROL_QW_WRITE
;
418 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
421 ret
= gen8_emit_pipe_control(req
,
422 PIPE_CONTROL_CS_STALL
|
423 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
429 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
432 static void ring_write_tail(struct intel_engine_cs
*ring
,
435 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
436 I915_WRITE_TAIL(ring
, value
);
439 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
441 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
444 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
445 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
446 RING_ACTHD_UDW(ring
->mmio_base
));
447 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
448 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
450 acthd
= I915_READ(ACTHD
);
455 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
457 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
460 addr
= dev_priv
->status_page_dmah
->busaddr
;
461 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
462 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
463 I915_WRITE(HWS_PGA
, addr
);
466 static void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
468 struct drm_device
*dev
= ring
->dev
;
469 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
478 mmio
= RENDER_HWS_PGA_GEN7
;
481 mmio
= BLT_HWS_PGA_GEN7
;
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
489 mmio
= BSD_HWS_PGA_GEN7
;
492 mmio
= VEBOX_HWS_PGA_GEN7
;
495 } else if (IS_GEN6(ring
->dev
)) {
496 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
498 /* XXX: gen8 returns to sanity */
499 mmio
= RING_HWS_PGA(ring
->mmio_base
);
502 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
506 * Flush the TLB for this page
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
512 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
513 i915_reg_t reg
= RING_INSTPM(ring
->mmio_base
);
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
521 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
528 static bool stop_ring(struct intel_engine_cs
*ring
)
530 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
532 if (!IS_GEN2(ring
->dev
)) {
533 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
534 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
536 /* Sometimes we observe that the idle flag is not
537 * set even though the ring is empty. So double
538 * check before giving up.
540 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
545 I915_WRITE_CTL(ring
, 0);
546 I915_WRITE_HEAD(ring
, 0);
547 ring
->write_tail(ring
, 0);
549 if (!IS_GEN2(ring
->dev
)) {
550 (void)I915_READ_CTL(ring
);
551 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
554 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
557 static int init_ring_common(struct intel_engine_cs
*ring
)
559 struct drm_device
*dev
= ring
->dev
;
560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
561 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
562 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
565 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
567 if (!stop_ring(ring
)) {
568 /* G45 ring initialization often fails to reset head to zero */
569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
573 I915_READ_HEAD(ring
),
574 I915_READ_TAIL(ring
),
575 I915_READ_START(ring
));
577 if (!stop_ring(ring
)) {
578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
582 I915_READ_HEAD(ring
),
583 I915_READ_TAIL(ring
),
584 I915_READ_START(ring
));
590 if (I915_NEED_GFX_HWS(dev
))
591 intel_ring_setup_status_page(ring
);
593 ring_setup_phys_status_page(ring
);
595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(ring
);
598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
602 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(ring
))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 ring
->name
, I915_READ_HEAD(ring
));
608 I915_WRITE_HEAD(ring
, 0);
609 (void)I915_READ_HEAD(ring
);
612 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
615 /* If the head is still not zero, the ring is dead */
616 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
617 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
618 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
619 DRM_ERROR("%s initialization failed "
620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
622 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
623 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
624 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
629 ringbuf
->last_retired_head
= -1;
630 ringbuf
->head
= I915_READ_HEAD(ring
);
631 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
632 intel_ring_update_space(ringbuf
);
634 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
637 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
643 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
645 struct drm_device
*dev
= ring
->dev
;
647 if (ring
->scratch
.obj
== NULL
)
650 if (INTEL_INFO(dev
)->gen
>= 5) {
651 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
652 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
655 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
656 ring
->scratch
.obj
= NULL
;
660 intel_init_pipe_control(struct intel_engine_cs
*ring
)
664 WARN_ON(ring
->scratch
.obj
);
666 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
667 if (ring
->scratch
.obj
== NULL
) {
668 DRM_ERROR("Failed to allocate seqno page\n");
673 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
677 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
681 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
682 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
683 if (ring
->scratch
.cpu_page
== NULL
) {
688 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
689 ring
->name
, ring
->scratch
.gtt_offset
);
693 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
695 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
700 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
703 struct intel_engine_cs
*ring
= req
->ring
;
704 struct drm_device
*dev
= ring
->dev
;
705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
706 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
711 ring
->gpu_caches_dirty
= true;
712 ret
= intel_ring_flush_all_caches(req
);
716 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
720 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
721 for (i
= 0; i
< w
->count
; i
++) {
722 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
723 intel_ring_emit(ring
, w
->reg
[i
].value
);
725 intel_ring_emit(ring
, MI_NOOP
);
727 intel_ring_advance(ring
);
729 ring
->gpu_caches_dirty
= true;
730 ret
= intel_ring_flush_all_caches(req
);
734 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
739 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
743 ret
= intel_ring_workarounds_emit(req
);
747 ret
= i915_gem_render_state_init(req
);
749 DRM_ERROR("init render state: %d\n", ret
);
754 static int wa_add(struct drm_i915_private
*dev_priv
,
756 const u32 mask
, const u32 val
)
758 const u32 idx
= dev_priv
->workarounds
.count
;
760 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
763 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
764 dev_priv
->workarounds
.reg
[idx
].value
= val
;
765 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
767 dev_priv
->workarounds
.count
++;
772 #define WA_REG(addr, mask, val) do { \
773 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
778 #define WA_SET_BIT_MASKED(addr, mask) \
779 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
781 #define WA_CLR_BIT_MASKED(addr, mask) \
782 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
784 #define WA_SET_FIELD_MASKED(addr, mask, value) \
785 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
787 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
788 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
790 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
792 static int wa_ring_whitelist_reg(struct intel_engine_cs
*ring
, i915_reg_t reg
)
794 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
795 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
796 const uint32_t index
= wa
->hw_whitelist_count
[ring
->id
];
798 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
801 WA_WRITE(RING_FORCE_TO_NONPRIV(ring
->mmio_base
, index
),
802 i915_mmio_reg_offset(reg
));
803 wa
->hw_whitelist_count
[ring
->id
]++;
808 static int gen8_init_workarounds(struct intel_engine_cs
*ring
)
810 struct drm_device
*dev
= ring
->dev
;
811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
815 /* WaDisableAsyncFlipPerfMode:bdw,chv */
816 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
818 /* WaDisablePartialInstShootdown:bdw,chv */
819 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
820 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
822 /* Use Force Non-Coherent whenever executing a 3D context. This is a
823 * workaround for for a possible hang in the unlikely event a TLB
824 * invalidation occurs during a PSD flush.
826 /* WaForceEnableNonCoherent:bdw,chv */
827 /* WaHdcDisableFetchWhenMasked:bdw,chv */
828 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
829 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
830 HDC_FORCE_NON_COHERENT
);
832 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
833 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
834 * polygons in the same 8x4 pixel/sample area to be processed without
835 * stalling waiting for the earlier ones to write to Hierarchical Z
838 * This optimization is off by default for BDW and CHV; turn it on.
840 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
842 /* Wa4x4STCOptimizationDisable:bdw,chv */
843 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
846 * BSpec recommends 8x4 when MSAA is used,
847 * however in practice 16x4 seems fastest.
849 * Note that PS/WM thread counts depend on the WIZ hashing
850 * disable bit, which we don't touch here, but it's good
851 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
853 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
854 GEN6_WIZ_HASHING_MASK
,
855 GEN6_WIZ_HASHING_16x4
);
860 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
863 struct drm_device
*dev
= ring
->dev
;
864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
866 ret
= gen8_init_workarounds(ring
);
870 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
871 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
873 /* WaDisableDopClockGating:bdw */
874 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
875 DOP_CLOCK_GATING_DISABLE
);
877 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
878 GEN8_SAMPLER_POWER_BYPASS_DIS
);
880 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
881 /* WaForceContextSaveRestoreNonCoherent:bdw */
882 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
883 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
884 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
889 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
892 struct drm_device
*dev
= ring
->dev
;
893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
895 ret
= gen8_init_workarounds(ring
);
899 /* WaDisableThreadStallDopClockGating:chv */
900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
908 static int gen9_init_workarounds(struct intel_engine_cs
*ring
)
910 struct drm_device
*dev
= ring
->dev
;
911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
915 /* WaEnableLbsSlaRetryTimerDecrement:skl */
916 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
917 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
919 /* WaDisableKillLogic:bxt,skl */
920 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
923 /* WaDisablePartialInstShootdown:skl,bxt */
924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
927 /* Syncing dependencies between camera and graphics:skl,bxt */
928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
931 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
932 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
933 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
935 GEN9_DG_MIRROR_FIX_ENABLE
);
937 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
938 if (IS_SKL_REVID(dev
, 0, SKL_REVID_B0
) ||
939 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
940 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
941 GEN9_RHWO_OPTIMIZATION_DISABLE
);
943 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
944 * but we do that in per ctx batchbuffer as there is an issue
945 * with this register not getting restored on ctx restore
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
950 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
) || IS_BROXTON(dev
))
951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
952 GEN9_ENABLE_YV12_BUGFIX
);
954 /* Wa4x4STCOptimizationDisable:skl,bxt */
955 /* WaDisablePartialResolveInVc:skl,bxt */
956 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
957 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
959 /* WaCcsTlbPrefetchDisable:skl,bxt */
960 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
961 GEN9_CCS_TLB_PREFETCH_ENABLE
);
963 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
964 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_C0
) ||
965 IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
966 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
967 PIXEL_MASK_CAMMING_DISABLE
);
969 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
970 tmp
= HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
;
971 if (IS_SKL_REVID(dev
, SKL_REVID_F0
, SKL_REVID_F0
) ||
972 IS_BXT_REVID(dev
, BXT_REVID_B0
, REVID_FOREVER
))
973 tmp
|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
;
974 WA_SET_BIT_MASKED(HDC_CHICKEN0
, tmp
);
976 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
977 if (IS_SKYLAKE(dev
) || IS_BXT_REVID(dev
, 0, BXT_REVID_B0
))
978 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
979 GEN8_SAMPLER_POWER_BYPASS_DIS
);
981 /* WaDisableSTUnitPowerOptimization:skl,bxt */
982 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
984 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
985 ret
= wa_ring_whitelist_reg(ring
, GEN8_CS_CHICKEN1
);
989 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
990 ret
= wa_ring_whitelist_reg(ring
, GEN8_HDC_CHICKEN1
);
997 static int skl_tune_iz_hashing(struct intel_engine_cs
*ring
)
999 struct drm_device
*dev
= ring
->dev
;
1000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1001 u8 vals
[3] = { 0, 0, 0 };
1004 for (i
= 0; i
< 3; i
++) {
1008 * Only consider slices where one, and only one, subslice has 7
1011 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
1015 * subslice_7eu[i] != 0 (because of the check above) and
1016 * ss_max == 4 (maximum number of subslices possible per slice)
1020 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1024 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1027 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1028 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1029 GEN9_IZ_HASHING_MASK(2) |
1030 GEN9_IZ_HASHING_MASK(1) |
1031 GEN9_IZ_HASHING_MASK(0),
1032 GEN9_IZ_HASHING(2, vals
[2]) |
1033 GEN9_IZ_HASHING(1, vals
[1]) |
1034 GEN9_IZ_HASHING(0, vals
[0]));
1039 static int skl_init_workarounds(struct intel_engine_cs
*ring
)
1042 struct drm_device
*dev
= ring
->dev
;
1043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 ret
= gen9_init_workarounds(ring
);
1049 if (IS_SKL_REVID(dev
, 0, SKL_REVID_D0
)) {
1050 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1051 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1052 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1055 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1056 * involving this register should also be added to WA batch as required.
1058 if (IS_SKL_REVID(dev
, 0, SKL_REVID_E0
))
1059 /* WaDisableLSQCROPERFforOCL:skl */
1060 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1061 GEN8_LQSC_RO_PERF_DIS
);
1063 /* WaEnableGapsTsvCreditFix:skl */
1064 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, REVID_FOREVER
)) {
1065 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1066 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1069 /* WaDisablePowerCompilerClockGating:skl */
1070 if (IS_SKL_REVID(dev
, SKL_REVID_B0
, SKL_REVID_B0
))
1071 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1072 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1074 if (IS_SKL_REVID(dev
, 0, SKL_REVID_F0
)) {
1076 *Use Force Non-Coherent whenever executing a 3D context. This
1077 * is a workaround for a possible hang in the unlikely event
1078 * a TLB invalidation occurs during a PSD flush.
1080 /* WaForceEnableNonCoherent:skl */
1081 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1082 HDC_FORCE_NON_COHERENT
);
1084 /* WaDisableHDCInvalidation:skl */
1085 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
1086 BDW_DISABLE_HDC_INVALIDATION
);
1089 /* WaBarrierPerformanceFixDisable:skl */
1090 if (IS_SKL_REVID(dev
, SKL_REVID_C0
, SKL_REVID_D0
))
1091 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1092 HDC_FENCE_DEST_SLM_DISABLE
|
1093 HDC_BARRIER_PERFORMANCE_DISABLE
);
1095 /* WaDisableSbeCacheDispatchPortSharing:skl */
1096 if (IS_SKL_REVID(dev
, 0, SKL_REVID_F0
))
1098 GEN7_HALF_SLICE_CHICKEN1
,
1099 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1101 return skl_tune_iz_hashing(ring
);
1104 static int bxt_init_workarounds(struct intel_engine_cs
*ring
)
1107 struct drm_device
*dev
= ring
->dev
;
1108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1110 ret
= gen9_init_workarounds(ring
);
1114 /* WaStoreMultiplePTEenable:bxt */
1115 /* This is a requirement according to Hardware specification */
1116 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
1117 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1119 /* WaSetClckGatingDisableMedia:bxt */
1120 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
)) {
1121 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1122 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1125 /* WaDisableThreadStallDopClockGating:bxt */
1126 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1127 STALL_DOP_GATING_DISABLE
);
1129 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1130 if (IS_BXT_REVID(dev
, 0, BXT_REVID_B0
)) {
1132 GEN7_HALF_SLICE_CHICKEN1
,
1133 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1139 int init_workarounds_ring(struct intel_engine_cs
*ring
)
1141 struct drm_device
*dev
= ring
->dev
;
1142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1144 WARN_ON(ring
->id
!= RCS
);
1146 dev_priv
->workarounds
.count
= 0;
1147 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1149 if (IS_BROADWELL(dev
))
1150 return bdw_init_workarounds(ring
);
1152 if (IS_CHERRYVIEW(dev
))
1153 return chv_init_workarounds(ring
);
1155 if (IS_SKYLAKE(dev
))
1156 return skl_init_workarounds(ring
);
1158 if (IS_BROXTON(dev
))
1159 return bxt_init_workarounds(ring
);
1164 static int init_render_ring(struct intel_engine_cs
*ring
)
1166 struct drm_device
*dev
= ring
->dev
;
1167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1168 int ret
= init_ring_common(ring
);
1172 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1173 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1174 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1176 /* We need to disable the AsyncFlip performance optimisations in order
1177 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1178 * programmed to '1' on all products.
1180 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1182 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1183 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1185 /* Required for the hardware to program scanline values for waiting */
1186 /* WaEnableFlushTlbInvalidationMode:snb */
1187 if (INTEL_INFO(dev
)->gen
== 6)
1188 I915_WRITE(GFX_MODE
,
1189 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1191 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1193 I915_WRITE(GFX_MODE_GEN7
,
1194 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1195 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1198 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1199 * "If this bit is set, STCunit will have LRA as replacement
1200 * policy. [...] This bit must be reset. LRA replacement
1201 * policy is not supported."
1203 I915_WRITE(CACHE_MODE_0
,
1204 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1207 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1208 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1210 if (HAS_L3_DPF(dev
))
1211 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1213 return init_workarounds_ring(ring
);
1216 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
1218 struct drm_device
*dev
= ring
->dev
;
1219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 if (dev_priv
->semaphore_obj
) {
1222 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1223 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1224 dev_priv
->semaphore_obj
= NULL
;
1227 intel_fini_pipe_control(ring
);
1230 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1231 unsigned int num_dwords
)
1233 #define MBOX_UPDATE_DWORDS 8
1234 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1235 struct drm_device
*dev
= signaller
->dev
;
1236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1237 struct intel_engine_cs
*waiter
;
1238 int i
, ret
, num_rings
;
1240 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1241 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1242 #undef MBOX_UPDATE_DWORDS
1244 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1248 for_each_ring(waiter
, dev_priv
, i
) {
1250 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1251 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1254 seqno
= i915_gem_request_get_seqno(signaller_req
);
1255 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1256 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1257 PIPE_CONTROL_QW_WRITE
|
1258 PIPE_CONTROL_FLUSH_ENABLE
);
1259 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1260 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1261 intel_ring_emit(signaller
, seqno
);
1262 intel_ring_emit(signaller
, 0);
1263 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1264 MI_SEMAPHORE_TARGET(waiter
->id
));
1265 intel_ring_emit(signaller
, 0);
1271 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1272 unsigned int num_dwords
)
1274 #define MBOX_UPDATE_DWORDS 6
1275 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1276 struct drm_device
*dev
= signaller
->dev
;
1277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1278 struct intel_engine_cs
*waiter
;
1279 int i
, ret
, num_rings
;
1281 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1282 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1283 #undef MBOX_UPDATE_DWORDS
1285 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1289 for_each_ring(waiter
, dev_priv
, i
) {
1291 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1292 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1295 seqno
= i915_gem_request_get_seqno(signaller_req
);
1296 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1297 MI_FLUSH_DW_OP_STOREDW
);
1298 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1299 MI_FLUSH_DW_USE_GTT
);
1300 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1301 intel_ring_emit(signaller
, seqno
);
1302 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1303 MI_SEMAPHORE_TARGET(waiter
->id
));
1304 intel_ring_emit(signaller
, 0);
1310 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1311 unsigned int num_dwords
)
1313 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1314 struct drm_device
*dev
= signaller
->dev
;
1315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1316 struct intel_engine_cs
*useless
;
1317 int i
, ret
, num_rings
;
1319 #define MBOX_UPDATE_DWORDS 3
1320 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1321 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1322 #undef MBOX_UPDATE_DWORDS
1324 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1328 for_each_ring(useless
, dev_priv
, i
) {
1329 i915_reg_t mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1331 if (i915_mmio_reg_valid(mbox_reg
)) {
1332 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1334 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1335 intel_ring_emit_reg(signaller
, mbox_reg
);
1336 intel_ring_emit(signaller
, seqno
);
1340 /* If num_dwords was rounded, make sure the tail pointer is correct */
1341 if (num_rings
% 2 == 0)
1342 intel_ring_emit(signaller
, MI_NOOP
);
1348 * gen6_add_request - Update the semaphore mailbox registers
1350 * @request - request to write to the ring
1352 * Update the mailbox registers in the *other* rings with the current seqno.
1353 * This acts like a signal in the canonical semaphore.
1356 gen6_add_request(struct drm_i915_gem_request
*req
)
1358 struct intel_engine_cs
*ring
= req
->ring
;
1361 if (ring
->semaphore
.signal
)
1362 ret
= ring
->semaphore
.signal(req
, 4);
1364 ret
= intel_ring_begin(req
, 4);
1369 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1370 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1371 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1372 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1373 __intel_ring_advance(ring
);
1378 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1382 return dev_priv
->last_seqno
< seqno
;
1386 * intel_ring_sync - sync the waiter to the signaller on seqno
1388 * @waiter - ring that is waiting
1389 * @signaller - ring which has, or will signal
1390 * @seqno - seqno which the waiter will block on
1394 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1395 struct intel_engine_cs
*signaller
,
1398 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1399 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1402 ret
= intel_ring_begin(waiter_req
, 4);
1406 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1407 MI_SEMAPHORE_GLOBAL_GTT
|
1409 MI_SEMAPHORE_SAD_GTE_SDD
);
1410 intel_ring_emit(waiter
, seqno
);
1411 intel_ring_emit(waiter
,
1412 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1413 intel_ring_emit(waiter
,
1414 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1415 intel_ring_advance(waiter
);
1420 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1421 struct intel_engine_cs
*signaller
,
1424 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1425 u32 dw1
= MI_SEMAPHORE_MBOX
|
1426 MI_SEMAPHORE_COMPARE
|
1427 MI_SEMAPHORE_REGISTER
;
1428 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1431 /* Throughout all of the GEM code, seqno passed implies our current
1432 * seqno is >= the last seqno executed. However for hardware the
1433 * comparison is strictly greater than.
1437 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1439 ret
= intel_ring_begin(waiter_req
, 4);
1443 /* If seqno wrap happened, omit the wait with no-ops */
1444 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1445 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1446 intel_ring_emit(waiter
, seqno
);
1447 intel_ring_emit(waiter
, 0);
1448 intel_ring_emit(waiter
, MI_NOOP
);
1450 intel_ring_emit(waiter
, MI_NOOP
);
1451 intel_ring_emit(waiter
, MI_NOOP
);
1452 intel_ring_emit(waiter
, MI_NOOP
);
1453 intel_ring_emit(waiter
, MI_NOOP
);
1455 intel_ring_advance(waiter
);
1460 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1462 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1463 PIPE_CONTROL_DEPTH_STALL); \
1464 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1465 intel_ring_emit(ring__, 0); \
1466 intel_ring_emit(ring__, 0); \
1470 pc_render_add_request(struct drm_i915_gem_request
*req
)
1472 struct intel_engine_cs
*ring
= req
->ring
;
1473 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1476 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1477 * incoherent with writes to memory, i.e. completely fubar,
1478 * so we need to use PIPE_NOTIFY instead.
1480 * However, we also need to workaround the qword write
1481 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1482 * memory before requesting an interrupt.
1484 ret
= intel_ring_begin(req
, 32);
1488 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1489 PIPE_CONTROL_WRITE_FLUSH
|
1490 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1491 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1492 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1493 intel_ring_emit(ring
, 0);
1494 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1495 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1496 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1497 scratch_addr
+= 2 * CACHELINE_BYTES
;
1498 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1499 scratch_addr
+= 2 * CACHELINE_BYTES
;
1500 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1501 scratch_addr
+= 2 * CACHELINE_BYTES
;
1502 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1503 scratch_addr
+= 2 * CACHELINE_BYTES
;
1504 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1506 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1507 PIPE_CONTROL_WRITE_FLUSH
|
1508 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1509 PIPE_CONTROL_NOTIFY
);
1510 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1511 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1512 intel_ring_emit(ring
, 0);
1513 __intel_ring_advance(ring
);
1519 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1521 /* Workaround to force correct ordering between irq and seqno writes on
1522 * ivb (and maybe also on snb) by reading from a CS register (like
1523 * ACTHD) before reading the status page. */
1524 if (!lazy_coherency
) {
1525 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1526 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1529 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1533 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1535 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1539 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1541 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1545 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1547 return ring
->scratch
.cpu_page
[0];
1551 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1553 ring
->scratch
.cpu_page
[0] = seqno
;
1557 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1559 struct drm_device
*dev
= ring
->dev
;
1560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1561 unsigned long flags
;
1563 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1566 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1567 if (ring
->irq_refcount
++ == 0)
1568 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1569 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1575 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1577 struct drm_device
*dev
= ring
->dev
;
1578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1579 unsigned long flags
;
1581 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1582 if (--ring
->irq_refcount
== 0)
1583 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1584 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1588 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1590 struct drm_device
*dev
= ring
->dev
;
1591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1592 unsigned long flags
;
1594 if (!intel_irqs_enabled(dev_priv
))
1597 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1598 if (ring
->irq_refcount
++ == 0) {
1599 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1600 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1603 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1609 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1611 struct drm_device
*dev
= ring
->dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 unsigned long flags
;
1615 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1616 if (--ring
->irq_refcount
== 0) {
1617 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1618 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1621 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1625 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1627 struct drm_device
*dev
= ring
->dev
;
1628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1629 unsigned long flags
;
1631 if (!intel_irqs_enabled(dev_priv
))
1634 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1635 if (ring
->irq_refcount
++ == 0) {
1636 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1637 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1638 POSTING_READ16(IMR
);
1640 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1646 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1648 struct drm_device
*dev
= ring
->dev
;
1649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1650 unsigned long flags
;
1652 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1653 if (--ring
->irq_refcount
== 0) {
1654 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1655 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1656 POSTING_READ16(IMR
);
1658 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1662 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1663 u32 invalidate_domains
,
1666 struct intel_engine_cs
*ring
= req
->ring
;
1669 ret
= intel_ring_begin(req
, 2);
1673 intel_ring_emit(ring
, MI_FLUSH
);
1674 intel_ring_emit(ring
, MI_NOOP
);
1675 intel_ring_advance(ring
);
1680 i9xx_add_request(struct drm_i915_gem_request
*req
)
1682 struct intel_engine_cs
*ring
= req
->ring
;
1685 ret
= intel_ring_begin(req
, 4);
1689 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1690 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1691 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1692 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1693 __intel_ring_advance(ring
);
1699 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1701 struct drm_device
*dev
= ring
->dev
;
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 unsigned long flags
;
1705 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1708 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1709 if (ring
->irq_refcount
++ == 0) {
1710 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1711 I915_WRITE_IMR(ring
,
1712 ~(ring
->irq_enable_mask
|
1713 GT_PARITY_ERROR(dev
)));
1715 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1716 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1718 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1724 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1726 struct drm_device
*dev
= ring
->dev
;
1727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1728 unsigned long flags
;
1730 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1731 if (--ring
->irq_refcount
== 0) {
1732 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1733 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1735 I915_WRITE_IMR(ring
, ~0);
1736 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1738 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1742 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1744 struct drm_device
*dev
= ring
->dev
;
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1746 unsigned long flags
;
1748 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1751 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1752 if (ring
->irq_refcount
++ == 0) {
1753 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1754 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1756 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1762 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1764 struct drm_device
*dev
= ring
->dev
;
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 unsigned long flags
;
1768 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1769 if (--ring
->irq_refcount
== 0) {
1770 I915_WRITE_IMR(ring
, ~0);
1771 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1773 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1777 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1779 struct drm_device
*dev
= ring
->dev
;
1780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1781 unsigned long flags
;
1783 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1786 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1787 if (ring
->irq_refcount
++ == 0) {
1788 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1789 I915_WRITE_IMR(ring
,
1790 ~(ring
->irq_enable_mask
|
1791 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1793 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1795 POSTING_READ(RING_IMR(ring
->mmio_base
));
1797 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1803 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1805 struct drm_device
*dev
= ring
->dev
;
1806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1807 unsigned long flags
;
1809 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1810 if (--ring
->irq_refcount
== 0) {
1811 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1812 I915_WRITE_IMR(ring
,
1813 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1815 I915_WRITE_IMR(ring
, ~0);
1817 POSTING_READ(RING_IMR(ring
->mmio_base
));
1819 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1823 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1824 u64 offset
, u32 length
,
1825 unsigned dispatch_flags
)
1827 struct intel_engine_cs
*ring
= req
->ring
;
1830 ret
= intel_ring_begin(req
, 2);
1834 intel_ring_emit(ring
,
1835 MI_BATCH_BUFFER_START
|
1837 (dispatch_flags
& I915_DISPATCH_SECURE
?
1838 0 : MI_BATCH_NON_SECURE_I965
));
1839 intel_ring_emit(ring
, offset
);
1840 intel_ring_advance(ring
);
1845 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1846 #define I830_BATCH_LIMIT (256*1024)
1847 #define I830_TLB_ENTRIES (2)
1848 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1850 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1851 u64 offset
, u32 len
,
1852 unsigned dispatch_flags
)
1854 struct intel_engine_cs
*ring
= req
->ring
;
1855 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1858 ret
= intel_ring_begin(req
, 6);
1862 /* Evict the invalid PTE TLBs */
1863 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1864 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1865 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1866 intel_ring_emit(ring
, cs_offset
);
1867 intel_ring_emit(ring
, 0xdeadbeef);
1868 intel_ring_emit(ring
, MI_NOOP
);
1869 intel_ring_advance(ring
);
1871 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1872 if (len
> I830_BATCH_LIMIT
)
1875 ret
= intel_ring_begin(req
, 6 + 2);
1879 /* Blit the batch (which has now all relocs applied) to the
1880 * stable batch scratch bo area (so that the CS never
1881 * stumbles over its tlb invalidation bug) ...
1883 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1884 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1885 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1886 intel_ring_emit(ring
, cs_offset
);
1887 intel_ring_emit(ring
, 4096);
1888 intel_ring_emit(ring
, offset
);
1890 intel_ring_emit(ring
, MI_FLUSH
);
1891 intel_ring_emit(ring
, MI_NOOP
);
1892 intel_ring_advance(ring
);
1894 /* ... and execute it. */
1898 ret
= intel_ring_begin(req
, 2);
1902 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1903 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1904 0 : MI_BATCH_NON_SECURE
));
1905 intel_ring_advance(ring
);
1911 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1912 u64 offset
, u32 len
,
1913 unsigned dispatch_flags
)
1915 struct intel_engine_cs
*ring
= req
->ring
;
1918 ret
= intel_ring_begin(req
, 2);
1922 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1923 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1924 0 : MI_BATCH_NON_SECURE
));
1925 intel_ring_advance(ring
);
1930 static void cleanup_phys_status_page(struct intel_engine_cs
*ring
)
1932 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
1934 if (!dev_priv
->status_page_dmah
)
1937 drm_pci_free(ring
->dev
, dev_priv
->status_page_dmah
);
1938 ring
->status_page
.page_addr
= NULL
;
1941 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1943 struct drm_i915_gem_object
*obj
;
1945 obj
= ring
->status_page
.obj
;
1949 kunmap(sg_page(obj
->pages
->sgl
));
1950 i915_gem_object_ggtt_unpin(obj
);
1951 drm_gem_object_unreference(&obj
->base
);
1952 ring
->status_page
.obj
= NULL
;
1955 static int init_status_page(struct intel_engine_cs
*ring
)
1957 struct drm_i915_gem_object
*obj
= ring
->status_page
.obj
;
1963 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1965 DRM_ERROR("Failed to allocate status page\n");
1969 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1974 if (!HAS_LLC(ring
->dev
))
1975 /* On g33, we cannot place HWS above 256MiB, so
1976 * restrict its pinning to the low mappable arena.
1977 * Though this restriction is not documented for
1978 * gen4, gen5, or byt, they also behave similarly
1979 * and hang if the HWS is placed at the top of the
1980 * GTT. To generalise, it appears that all !llc
1981 * platforms have issues with us placing the HWS
1982 * above the mappable region (even though we never
1985 flags
|= PIN_MAPPABLE
;
1986 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1989 drm_gem_object_unreference(&obj
->base
);
1993 ring
->status_page
.obj
= obj
;
1996 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1997 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1998 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
2000 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2001 ring
->name
, ring
->status_page
.gfx_addr
);
2006 static int init_phys_status_page(struct intel_engine_cs
*ring
)
2008 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2010 if (!dev_priv
->status_page_dmah
) {
2011 dev_priv
->status_page_dmah
=
2012 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
2013 if (!dev_priv
->status_page_dmah
)
2017 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
2018 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
2023 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2025 if (HAS_LLC(ringbuf
->obj
->base
.dev
) && !ringbuf
->obj
->stolen
)
2026 vunmap(ringbuf
->virtual_start
);
2028 iounmap(ringbuf
->virtual_start
);
2029 ringbuf
->virtual_start
= NULL
;
2030 ringbuf
->vma
= NULL
;
2031 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
2034 static u32
*vmap_obj(struct drm_i915_gem_object
*obj
)
2036 struct sg_page_iter sg_iter
;
2037 struct page
**pages
;
2041 pages
= drm_malloc_ab(obj
->base
.size
>> PAGE_SHIFT
, sizeof(*pages
));
2046 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0)
2047 pages
[i
++] = sg_page_iter_page(&sg_iter
);
2049 addr
= vmap(pages
, i
, 0, PAGE_KERNEL
);
2050 drm_free_large(pages
);
2055 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
2056 struct intel_ringbuffer
*ringbuf
)
2058 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2059 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
2062 if (HAS_LLC(dev_priv
) && !obj
->stolen
) {
2063 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, 0);
2067 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2069 i915_gem_object_ggtt_unpin(obj
);
2073 ringbuf
->virtual_start
= vmap_obj(obj
);
2074 if (ringbuf
->virtual_start
== NULL
) {
2075 i915_gem_object_ggtt_unpin(obj
);
2079 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
2083 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
2085 i915_gem_object_ggtt_unpin(obj
);
2089 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
2090 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
2091 if (ringbuf
->virtual_start
== NULL
) {
2092 i915_gem_object_ggtt_unpin(obj
);
2097 ringbuf
->vma
= i915_gem_obj_to_ggtt(obj
);
2102 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2104 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2105 ringbuf
->obj
= NULL
;
2108 static int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2109 struct intel_ringbuffer
*ringbuf
)
2111 struct drm_i915_gem_object
*obj
;
2115 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2117 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
2121 /* mark ring buffers as read-only from GPU side by default */
2129 struct intel_ringbuffer
*
2130 intel_engine_create_ringbuffer(struct intel_engine_cs
*engine
, int size
)
2132 struct intel_ringbuffer
*ring
;
2135 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2137 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2139 return ERR_PTR(-ENOMEM
);
2142 ring
->ring
= engine
;
2143 list_add(&ring
->link
, &engine
->buffers
);
2146 /* Workaround an erratum on the i830 which causes a hang if
2147 * the TAIL pointer points to within the last 2 cachelines
2150 ring
->effective_size
= size
;
2151 if (IS_I830(engine
->dev
) || IS_845G(engine
->dev
))
2152 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2154 ring
->last_retired_head
= -1;
2155 intel_ring_update_space(ring
);
2157 ret
= intel_alloc_ringbuffer_obj(engine
->dev
, ring
);
2159 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2161 list_del(&ring
->link
);
2163 return ERR_PTR(ret
);
2170 intel_ringbuffer_free(struct intel_ringbuffer
*ring
)
2172 intel_destroy_ringbuffer_obj(ring
);
2173 list_del(&ring
->link
);
2177 static int intel_init_ring_buffer(struct drm_device
*dev
,
2178 struct intel_engine_cs
*ring
)
2180 struct intel_ringbuffer
*ringbuf
;
2183 WARN_ON(ring
->buffer
);
2186 INIT_LIST_HEAD(&ring
->active_list
);
2187 INIT_LIST_HEAD(&ring
->request_list
);
2188 INIT_LIST_HEAD(&ring
->execlist_queue
);
2189 INIT_LIST_HEAD(&ring
->buffers
);
2190 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2191 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
2193 init_waitqueue_head(&ring
->irq_queue
);
2195 ringbuf
= intel_engine_create_ringbuffer(ring
, 32 * PAGE_SIZE
);
2196 if (IS_ERR(ringbuf
)) {
2197 ret
= PTR_ERR(ringbuf
);
2200 ring
->buffer
= ringbuf
;
2202 if (I915_NEED_GFX_HWS(dev
)) {
2203 ret
= init_status_page(ring
);
2207 WARN_ON(ring
->id
!= RCS
);
2208 ret
= init_phys_status_page(ring
);
2213 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2215 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2217 intel_destroy_ringbuffer_obj(ringbuf
);
2221 ret
= i915_cmd_parser_init_ring(ring
);
2228 intel_cleanup_ring_buffer(ring
);
2232 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
2234 struct drm_i915_private
*dev_priv
;
2236 if (!intel_ring_initialized(ring
))
2239 dev_priv
= to_i915(ring
->dev
);
2242 intel_stop_ring_buffer(ring
);
2243 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
2245 intel_unpin_ringbuffer_obj(ring
->buffer
);
2246 intel_ringbuffer_free(ring
->buffer
);
2247 ring
->buffer
= NULL
;
2251 ring
->cleanup(ring
);
2253 if (I915_NEED_GFX_HWS(ring
->dev
)) {
2254 cleanup_status_page(ring
);
2256 WARN_ON(ring
->id
!= RCS
);
2257 cleanup_phys_status_page(ring
);
2260 i915_cmd_parser_fini_ring(ring
);
2261 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2265 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
2267 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2268 struct drm_i915_gem_request
*request
;
2272 if (intel_ring_space(ringbuf
) >= n
)
2275 /* The whole point of reserving space is to not wait! */
2276 WARN_ON(ringbuf
->reserved_in_use
);
2278 list_for_each_entry(request
, &ring
->request_list
, list
) {
2279 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
2285 if (WARN_ON(&request
->list
== &ring
->request_list
))
2288 ret
= i915_wait_request(request
);
2292 ringbuf
->space
= space
;
2296 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
2298 uint32_t __iomem
*virt
;
2299 int rem
= ringbuf
->size
- ringbuf
->tail
;
2301 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2304 iowrite32(MI_NOOP
, virt
++);
2307 intel_ring_update_space(ringbuf
);
2310 int intel_ring_idle(struct intel_engine_cs
*ring
)
2312 struct drm_i915_gem_request
*req
;
2314 /* Wait upon the last request to be completed */
2315 if (list_empty(&ring
->request_list
))
2318 req
= list_entry(ring
->request_list
.prev
,
2319 struct drm_i915_gem_request
,
2322 /* Make sure we do not trigger any retires */
2323 return __i915_wait_request(req
,
2324 atomic_read(&to_i915(ring
->dev
)->gpu_error
.reset_counter
),
2325 to_i915(ring
->dev
)->mm
.interruptible
,
2329 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2331 request
->ringbuf
= request
->ring
->buffer
;
2335 int intel_ring_reserve_space(struct drm_i915_gem_request
*request
)
2338 * The first call merely notes the reserve request and is common for
2339 * all back ends. The subsequent localised _begin() call actually
2340 * ensures that the reservation is available. Without the begin, if
2341 * the request creator immediately submitted the request without
2342 * adding any commands to it then there might not actually be
2343 * sufficient room for the submission commands.
2345 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
2347 return intel_ring_begin(request
, 0);
2350 void intel_ring_reserved_space_reserve(struct intel_ringbuffer
*ringbuf
, int size
)
2352 WARN_ON(ringbuf
->reserved_size
);
2353 WARN_ON(ringbuf
->reserved_in_use
);
2355 ringbuf
->reserved_size
= size
;
2358 void intel_ring_reserved_space_cancel(struct intel_ringbuffer
*ringbuf
)
2360 WARN_ON(ringbuf
->reserved_in_use
);
2362 ringbuf
->reserved_size
= 0;
2363 ringbuf
->reserved_in_use
= false;
2366 void intel_ring_reserved_space_use(struct intel_ringbuffer
*ringbuf
)
2368 WARN_ON(ringbuf
->reserved_in_use
);
2370 ringbuf
->reserved_in_use
= true;
2371 ringbuf
->reserved_tail
= ringbuf
->tail
;
2374 void intel_ring_reserved_space_end(struct intel_ringbuffer
*ringbuf
)
2376 WARN_ON(!ringbuf
->reserved_in_use
);
2377 if (ringbuf
->tail
> ringbuf
->reserved_tail
) {
2378 WARN(ringbuf
->tail
> ringbuf
->reserved_tail
+ ringbuf
->reserved_size
,
2379 "request reserved size too small: %d vs %d!\n",
2380 ringbuf
->tail
- ringbuf
->reserved_tail
, ringbuf
->reserved_size
);
2383 * The ring was wrapped while the reserved space was in use.
2384 * That means that some unknown amount of the ring tail was
2385 * no-op filled and skipped. Thus simply adding the ring size
2386 * to the tail and doing the above space check will not work.
2387 * Rather than attempt to track how much tail was skipped,
2388 * it is much simpler to say that also skipping the sanity
2389 * check every once in a while is not a big issue.
2393 ringbuf
->reserved_size
= 0;
2394 ringbuf
->reserved_in_use
= false;
2397 static int __intel_ring_prepare(struct intel_engine_cs
*ring
, int bytes
)
2399 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2400 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2401 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2402 int ret
, total_bytes
, wait_bytes
= 0;
2403 bool need_wrap
= false;
2405 if (ringbuf
->reserved_in_use
)
2406 total_bytes
= bytes
;
2408 total_bytes
= bytes
+ ringbuf
->reserved_size
;
2410 if (unlikely(bytes
> remain_usable
)) {
2412 * Not enough space for the basic request. So need to flush
2413 * out the remainder and then wait for base + reserved.
2415 wait_bytes
= remain_actual
+ total_bytes
;
2418 if (unlikely(total_bytes
> remain_usable
)) {
2420 * The base request will fit but the reserved space
2421 * falls off the end. So only need to to wait for the
2422 * reserved size after flushing out the remainder.
2424 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
2426 } else if (total_bytes
> ringbuf
->space
) {
2427 /* No wrapping required, just waiting. */
2428 wait_bytes
= total_bytes
;
2433 ret
= ring_wait_for_space(ring
, wait_bytes
);
2438 __wrap_ring_buffer(ringbuf
);
2444 int intel_ring_begin(struct drm_i915_gem_request
*req
,
2447 struct intel_engine_cs
*ring
;
2448 struct drm_i915_private
*dev_priv
;
2451 WARN_ON(req
== NULL
);
2453 dev_priv
= ring
->dev
->dev_private
;
2455 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2456 dev_priv
->mm
.interruptible
);
2460 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2464 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2468 /* Align the ring tail to a cacheline boundary */
2469 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2471 struct intel_engine_cs
*ring
= req
->ring
;
2472 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2475 if (num_dwords
== 0)
2478 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2479 ret
= intel_ring_begin(req
, num_dwords
);
2483 while (num_dwords
--)
2484 intel_ring_emit(ring
, MI_NOOP
);
2486 intel_ring_advance(ring
);
2491 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2493 struct drm_device
*dev
= ring
->dev
;
2494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2496 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2497 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2498 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2500 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2503 ring
->set_seqno(ring
, seqno
);
2504 ring
->hangcheck
.seqno
= seqno
;
2507 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2510 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2512 /* Every tail move must follow the sequence below */
2514 /* Disable notification that the ring is IDLE. The GT
2515 * will then assume that it is busy and bring it out of rc6.
2517 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2518 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2520 /* Clear the context id. Here be magic! */
2521 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2523 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2524 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2525 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2527 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2529 /* Now that the ring is fully powered up, update the tail */
2530 I915_WRITE_TAIL(ring
, value
);
2531 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2533 /* Let the ring send IDLE messages to the GT again,
2534 * and so let it sleep to conserve power when idle.
2536 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2537 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2540 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2541 u32 invalidate
, u32 flush
)
2543 struct intel_engine_cs
*ring
= req
->ring
;
2547 ret
= intel_ring_begin(req
, 4);
2552 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2555 /* We always require a command barrier so that subsequent
2556 * commands, such as breadcrumb interrupts, are strictly ordered
2557 * wrt the contents of the write cache being flushed to memory
2558 * (and thus being coherent from the CPU).
2560 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2563 * Bspec vol 1c.5 - video engine command streamer:
2564 * "If ENABLED, all TLBs will be invalidated once the flush
2565 * operation is complete. This bit is only valid when the
2566 * Post-Sync Operation field is a value of 1h or 3h."
2568 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2569 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2571 intel_ring_emit(ring
, cmd
);
2572 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2573 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2574 intel_ring_emit(ring
, 0); /* upper addr */
2575 intel_ring_emit(ring
, 0); /* value */
2577 intel_ring_emit(ring
, 0);
2578 intel_ring_emit(ring
, MI_NOOP
);
2580 intel_ring_advance(ring
);
2585 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2586 u64 offset
, u32 len
,
2587 unsigned dispatch_flags
)
2589 struct intel_engine_cs
*ring
= req
->ring
;
2590 bool ppgtt
= USES_PPGTT(ring
->dev
) &&
2591 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2594 ret
= intel_ring_begin(req
, 4);
2598 /* FIXME(BDW): Address space and security selectors. */
2599 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2600 (dispatch_flags
& I915_DISPATCH_RS
?
2601 MI_BATCH_RESOURCE_STREAMER
: 0));
2602 intel_ring_emit(ring
, lower_32_bits(offset
));
2603 intel_ring_emit(ring
, upper_32_bits(offset
));
2604 intel_ring_emit(ring
, MI_NOOP
);
2605 intel_ring_advance(ring
);
2611 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2612 u64 offset
, u32 len
,
2613 unsigned dispatch_flags
)
2615 struct intel_engine_cs
*ring
= req
->ring
;
2618 ret
= intel_ring_begin(req
, 2);
2622 intel_ring_emit(ring
,
2623 MI_BATCH_BUFFER_START
|
2624 (dispatch_flags
& I915_DISPATCH_SECURE
?
2625 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2626 (dispatch_flags
& I915_DISPATCH_RS
?
2627 MI_BATCH_RESOURCE_STREAMER
: 0));
2628 /* bit0-7 is the length on GEN6+ */
2629 intel_ring_emit(ring
, offset
);
2630 intel_ring_advance(ring
);
2636 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2637 u64 offset
, u32 len
,
2638 unsigned dispatch_flags
)
2640 struct intel_engine_cs
*ring
= req
->ring
;
2643 ret
= intel_ring_begin(req
, 2);
2647 intel_ring_emit(ring
,
2648 MI_BATCH_BUFFER_START
|
2649 (dispatch_flags
& I915_DISPATCH_SECURE
?
2650 0 : MI_BATCH_NON_SECURE_I965
));
2651 /* bit0-7 is the length on GEN6+ */
2652 intel_ring_emit(ring
, offset
);
2653 intel_ring_advance(ring
);
2658 /* Blitter support (SandyBridge+) */
2660 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2661 u32 invalidate
, u32 flush
)
2663 struct intel_engine_cs
*ring
= req
->ring
;
2664 struct drm_device
*dev
= ring
->dev
;
2668 ret
= intel_ring_begin(req
, 4);
2673 if (INTEL_INFO(dev
)->gen
>= 8)
2676 /* We always require a command barrier so that subsequent
2677 * commands, such as breadcrumb interrupts, are strictly ordered
2678 * wrt the contents of the write cache being flushed to memory
2679 * (and thus being coherent from the CPU).
2681 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2684 * Bspec vol 1c.3 - blitter engine command streamer:
2685 * "If ENABLED, all TLBs will be invalidated once the flush
2686 * operation is complete. This bit is only valid when the
2687 * Post-Sync Operation field is a value of 1h or 3h."
2689 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2690 cmd
|= MI_INVALIDATE_TLB
;
2691 intel_ring_emit(ring
, cmd
);
2692 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2693 if (INTEL_INFO(dev
)->gen
>= 8) {
2694 intel_ring_emit(ring
, 0); /* upper addr */
2695 intel_ring_emit(ring
, 0); /* value */
2697 intel_ring_emit(ring
, 0);
2698 intel_ring_emit(ring
, MI_NOOP
);
2700 intel_ring_advance(ring
);
2705 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2708 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2709 struct drm_i915_gem_object
*obj
;
2712 ring
->name
= "render ring";
2714 ring
->exec_id
= I915_EXEC_RENDER
;
2715 ring
->mmio_base
= RENDER_RING_BASE
;
2717 if (INTEL_INFO(dev
)->gen
>= 8) {
2718 if (i915_semaphore_is_enabled(dev
)) {
2719 obj
= i915_gem_alloc_object(dev
, 4096);
2721 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2722 i915
.semaphores
= 0;
2724 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2725 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2727 drm_gem_object_unreference(&obj
->base
);
2728 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2729 i915
.semaphores
= 0;
2731 dev_priv
->semaphore_obj
= obj
;
2735 ring
->init_context
= intel_rcs_ctx_init
;
2736 ring
->add_request
= gen6_add_request
;
2737 ring
->flush
= gen8_render_ring_flush
;
2738 ring
->irq_get
= gen8_ring_get_irq
;
2739 ring
->irq_put
= gen8_ring_put_irq
;
2740 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2741 ring
->get_seqno
= gen6_ring_get_seqno
;
2742 ring
->set_seqno
= ring_set_seqno
;
2743 if (i915_semaphore_is_enabled(dev
)) {
2744 WARN_ON(!dev_priv
->semaphore_obj
);
2745 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2746 ring
->semaphore
.signal
= gen8_rcs_signal
;
2747 GEN8_RING_SEMAPHORE_INIT
;
2749 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2750 ring
->init_context
= intel_rcs_ctx_init
;
2751 ring
->add_request
= gen6_add_request
;
2752 ring
->flush
= gen7_render_ring_flush
;
2753 if (INTEL_INFO(dev
)->gen
== 6)
2754 ring
->flush
= gen6_render_ring_flush
;
2755 ring
->irq_get
= gen6_ring_get_irq
;
2756 ring
->irq_put
= gen6_ring_put_irq
;
2757 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2758 ring
->get_seqno
= gen6_ring_get_seqno
;
2759 ring
->set_seqno
= ring_set_seqno
;
2760 if (i915_semaphore_is_enabled(dev
)) {
2761 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2762 ring
->semaphore
.signal
= gen6_signal
;
2764 * The current semaphore is only applied on pre-gen8
2765 * platform. And there is no VCS2 ring on the pre-gen8
2766 * platform. So the semaphore between RCS and VCS2 is
2767 * initialized as INVALID. Gen8 will initialize the
2768 * sema between VCS2 and RCS later.
2770 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2771 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2772 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2773 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2774 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2775 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2776 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2777 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2778 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2779 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2781 } else if (IS_GEN5(dev
)) {
2782 ring
->add_request
= pc_render_add_request
;
2783 ring
->flush
= gen4_render_ring_flush
;
2784 ring
->get_seqno
= pc_render_get_seqno
;
2785 ring
->set_seqno
= pc_render_set_seqno
;
2786 ring
->irq_get
= gen5_ring_get_irq
;
2787 ring
->irq_put
= gen5_ring_put_irq
;
2788 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2789 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2791 ring
->add_request
= i9xx_add_request
;
2792 if (INTEL_INFO(dev
)->gen
< 4)
2793 ring
->flush
= gen2_render_ring_flush
;
2795 ring
->flush
= gen4_render_ring_flush
;
2796 ring
->get_seqno
= ring_get_seqno
;
2797 ring
->set_seqno
= ring_set_seqno
;
2799 ring
->irq_get
= i8xx_ring_get_irq
;
2800 ring
->irq_put
= i8xx_ring_put_irq
;
2802 ring
->irq_get
= i9xx_ring_get_irq
;
2803 ring
->irq_put
= i9xx_ring_put_irq
;
2805 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2807 ring
->write_tail
= ring_write_tail
;
2809 if (IS_HASWELL(dev
))
2810 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2811 else if (IS_GEN8(dev
))
2812 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2813 else if (INTEL_INFO(dev
)->gen
>= 6)
2814 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2815 else if (INTEL_INFO(dev
)->gen
>= 4)
2816 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2817 else if (IS_I830(dev
) || IS_845G(dev
))
2818 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2820 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2821 ring
->init_hw
= init_render_ring
;
2822 ring
->cleanup
= render_ring_cleanup
;
2824 /* Workaround batchbuffer to combat CS tlb bug. */
2825 if (HAS_BROKEN_CS_TLB(dev
)) {
2826 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2828 DRM_ERROR("Failed to allocate batch bo\n");
2832 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2834 drm_gem_object_unreference(&obj
->base
);
2835 DRM_ERROR("Failed to ping batch bo\n");
2839 ring
->scratch
.obj
= obj
;
2840 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2843 ret
= intel_init_ring_buffer(dev
, ring
);
2847 if (INTEL_INFO(dev
)->gen
>= 5) {
2848 ret
= intel_init_pipe_control(ring
);
2856 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2859 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2861 ring
->name
= "bsd ring";
2863 ring
->exec_id
= I915_EXEC_BSD
;
2865 ring
->write_tail
= ring_write_tail
;
2866 if (INTEL_INFO(dev
)->gen
>= 6) {
2867 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2868 /* gen6 bsd needs a special wa for tail updates */
2870 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2871 ring
->flush
= gen6_bsd_ring_flush
;
2872 ring
->add_request
= gen6_add_request
;
2873 ring
->get_seqno
= gen6_ring_get_seqno
;
2874 ring
->set_seqno
= ring_set_seqno
;
2875 if (INTEL_INFO(dev
)->gen
>= 8) {
2876 ring
->irq_enable_mask
=
2877 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2878 ring
->irq_get
= gen8_ring_get_irq
;
2879 ring
->irq_put
= gen8_ring_put_irq
;
2880 ring
->dispatch_execbuffer
=
2881 gen8_ring_dispatch_execbuffer
;
2882 if (i915_semaphore_is_enabled(dev
)) {
2883 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2884 ring
->semaphore
.signal
= gen8_xcs_signal
;
2885 GEN8_RING_SEMAPHORE_INIT
;
2888 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2889 ring
->irq_get
= gen6_ring_get_irq
;
2890 ring
->irq_put
= gen6_ring_put_irq
;
2891 ring
->dispatch_execbuffer
=
2892 gen6_ring_dispatch_execbuffer
;
2893 if (i915_semaphore_is_enabled(dev
)) {
2894 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2895 ring
->semaphore
.signal
= gen6_signal
;
2896 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2897 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2898 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2899 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2900 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2901 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2902 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2903 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2904 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2905 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2909 ring
->mmio_base
= BSD_RING_BASE
;
2910 ring
->flush
= bsd_ring_flush
;
2911 ring
->add_request
= i9xx_add_request
;
2912 ring
->get_seqno
= ring_get_seqno
;
2913 ring
->set_seqno
= ring_set_seqno
;
2915 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2916 ring
->irq_get
= gen5_ring_get_irq
;
2917 ring
->irq_put
= gen5_ring_put_irq
;
2919 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2920 ring
->irq_get
= i9xx_ring_get_irq
;
2921 ring
->irq_put
= i9xx_ring_put_irq
;
2923 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2925 ring
->init_hw
= init_ring_common
;
2927 return intel_init_ring_buffer(dev
, ring
);
2931 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2933 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2936 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2938 ring
->name
= "bsd2 ring";
2940 ring
->exec_id
= I915_EXEC_BSD
;
2942 ring
->write_tail
= ring_write_tail
;
2943 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2944 ring
->flush
= gen6_bsd_ring_flush
;
2945 ring
->add_request
= gen6_add_request
;
2946 ring
->get_seqno
= gen6_ring_get_seqno
;
2947 ring
->set_seqno
= ring_set_seqno
;
2948 ring
->irq_enable_mask
=
2949 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2950 ring
->irq_get
= gen8_ring_get_irq
;
2951 ring
->irq_put
= gen8_ring_put_irq
;
2952 ring
->dispatch_execbuffer
=
2953 gen8_ring_dispatch_execbuffer
;
2954 if (i915_semaphore_is_enabled(dev
)) {
2955 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2956 ring
->semaphore
.signal
= gen8_xcs_signal
;
2957 GEN8_RING_SEMAPHORE_INIT
;
2959 ring
->init_hw
= init_ring_common
;
2961 return intel_init_ring_buffer(dev
, ring
);
2964 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2967 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2969 ring
->name
= "blitter ring";
2971 ring
->exec_id
= I915_EXEC_BLT
;
2973 ring
->mmio_base
= BLT_RING_BASE
;
2974 ring
->write_tail
= ring_write_tail
;
2975 ring
->flush
= gen6_ring_flush
;
2976 ring
->add_request
= gen6_add_request
;
2977 ring
->get_seqno
= gen6_ring_get_seqno
;
2978 ring
->set_seqno
= ring_set_seqno
;
2979 if (INTEL_INFO(dev
)->gen
>= 8) {
2980 ring
->irq_enable_mask
=
2981 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2982 ring
->irq_get
= gen8_ring_get_irq
;
2983 ring
->irq_put
= gen8_ring_put_irq
;
2984 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2985 if (i915_semaphore_is_enabled(dev
)) {
2986 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2987 ring
->semaphore
.signal
= gen8_xcs_signal
;
2988 GEN8_RING_SEMAPHORE_INIT
;
2991 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2992 ring
->irq_get
= gen6_ring_get_irq
;
2993 ring
->irq_put
= gen6_ring_put_irq
;
2994 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2995 if (i915_semaphore_is_enabled(dev
)) {
2996 ring
->semaphore
.signal
= gen6_signal
;
2997 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2999 * The current semaphore is only applied on pre-gen8
3000 * platform. And there is no VCS2 ring on the pre-gen8
3001 * platform. So the semaphore between BCS and VCS2 is
3002 * initialized as INVALID. Gen8 will initialize the
3003 * sema between BCS and VCS2 later.
3005 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
3006 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
3007 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
3008 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
3009 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3010 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
3011 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
3012 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
3013 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
3014 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3017 ring
->init_hw
= init_ring_common
;
3019 return intel_init_ring_buffer(dev
, ring
);
3022 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
3024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3025 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
3027 ring
->name
= "video enhancement ring";
3029 ring
->exec_id
= I915_EXEC_VEBOX
;
3031 ring
->mmio_base
= VEBOX_RING_BASE
;
3032 ring
->write_tail
= ring_write_tail
;
3033 ring
->flush
= gen6_ring_flush
;
3034 ring
->add_request
= gen6_add_request
;
3035 ring
->get_seqno
= gen6_ring_get_seqno
;
3036 ring
->set_seqno
= ring_set_seqno
;
3038 if (INTEL_INFO(dev
)->gen
>= 8) {
3039 ring
->irq_enable_mask
=
3040 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
3041 ring
->irq_get
= gen8_ring_get_irq
;
3042 ring
->irq_put
= gen8_ring_put_irq
;
3043 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
3044 if (i915_semaphore_is_enabled(dev
)) {
3045 ring
->semaphore
.sync_to
= gen8_ring_sync
;
3046 ring
->semaphore
.signal
= gen8_xcs_signal
;
3047 GEN8_RING_SEMAPHORE_INIT
;
3050 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
3051 ring
->irq_get
= hsw_vebox_get_irq
;
3052 ring
->irq_put
= hsw_vebox_put_irq
;
3053 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
3054 if (i915_semaphore_is_enabled(dev
)) {
3055 ring
->semaphore
.sync_to
= gen6_ring_sync
;
3056 ring
->semaphore
.signal
= gen6_signal
;
3057 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
3058 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
3059 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
3060 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
3061 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
3062 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
3063 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
3064 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
3065 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
3066 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
3069 ring
->init_hw
= init_ring_common
;
3071 return intel_init_ring_buffer(dev
, ring
);
3075 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
3077 struct intel_engine_cs
*ring
= req
->ring
;
3080 if (!ring
->gpu_caches_dirty
)
3083 ret
= ring
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3087 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
3089 ring
->gpu_caches_dirty
= false;
3094 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
3096 struct intel_engine_cs
*ring
= req
->ring
;
3097 uint32_t flush_domains
;
3101 if (ring
->gpu_caches_dirty
)
3102 flush_domains
= I915_GEM_GPU_DOMAINS
;
3104 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3108 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
3110 ring
->gpu_caches_dirty
= false;
3115 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
3119 if (!intel_ring_initialized(ring
))
3122 ret
= intel_ring_idle(ring
);
3123 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
3124 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",