2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
36 static u32
i915_gem_get_seqno(struct drm_device
*dev
)
38 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
41 seqno
= dev_priv
->next_seqno
;
43 /* reserve 0 for non-seqno */
44 if (++dev_priv
->next_seqno
== 0)
45 dev_priv
->next_seqno
= 1;
51 render_ring_flush(struct drm_device
*dev
,
52 struct intel_ring_buffer
*ring
,
53 u32 invalidate_domains
,
56 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
60 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
61 invalidate_domains
, flush_domains
);
64 trace_i915_gem_request_flush(dev
, dev_priv
->next_seqno
,
65 invalidate_domains
, flush_domains
);
67 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
80 * I915_GEM_DOMAIN_COMMAND may not exist?
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
96 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
97 if ((invalidate_domains
|flush_domains
) &
98 I915_GEM_DOMAIN_RENDER
)
99 cmd
&= ~MI_NO_WRITE_FLUSH
;
100 if (INTEL_INFO(dev
)->gen
< 4) {
102 * On the 965, the sampler cache always gets flushed
103 * and this bit is reserved.
105 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
106 cmd
|= MI_READ_FLUSH
;
108 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
112 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
114 intel_ring_begin(dev
, ring
, 2);
115 intel_ring_emit(dev
, ring
, cmd
);
116 intel_ring_emit(dev
, ring
, MI_NOOP
);
117 intel_ring_advance(dev
, ring
);
120 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
123 static unsigned int render_ring_get_head(struct drm_device
*dev
,
124 struct intel_ring_buffer
*ring
)
126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
127 return I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
130 static unsigned int render_ring_get_tail(struct drm_device
*dev
,
131 struct intel_ring_buffer
*ring
)
133 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
134 return I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
137 static unsigned int render_ring_get_active_head(struct drm_device
*dev
,
138 struct intel_ring_buffer
*ring
)
140 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
141 u32 acthd_reg
= INTEL_INFO(dev
)->gen
? ACTHD_I965
: ACTHD
;
143 return I915_READ(acthd_reg
);
146 static void render_ring_advance_ring(struct drm_device
*dev
,
147 struct intel_ring_buffer
*ring
)
149 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
150 I915_WRITE(PRB0_TAIL
, ring
->tail
);
153 static int init_ring_common(struct drm_device
*dev
,
154 struct intel_ring_buffer
*ring
)
157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
158 struct drm_i915_gem_object
*obj_priv
;
159 obj_priv
= to_intel_bo(ring
->gem_object
);
161 /* Stop the ring if it's running. */
162 I915_WRITE(ring
->regs
.ctl
, 0);
163 I915_WRITE(ring
->regs
.head
, 0);
164 I915_WRITE(ring
->regs
.tail
, 0);
166 /* Initialize the ring. */
167 I915_WRITE(ring
->regs
.start
, obj_priv
->gtt_offset
);
168 head
= ring
->get_head(dev
, ring
);
170 /* G45 ring initialization fails to reset head to zero */
172 DRM_ERROR("%s head not reset to zero "
173 "ctl %08x head %08x tail %08x start %08x\n",
175 I915_READ(ring
->regs
.ctl
),
176 I915_READ(ring
->regs
.head
),
177 I915_READ(ring
->regs
.tail
),
178 I915_READ(ring
->regs
.start
));
180 I915_WRITE(ring
->regs
.head
, 0);
182 DRM_ERROR("%s head forced to zero "
183 "ctl %08x head %08x tail %08x start %08x\n",
185 I915_READ(ring
->regs
.ctl
),
186 I915_READ(ring
->regs
.head
),
187 I915_READ(ring
->regs
.tail
),
188 I915_READ(ring
->regs
.start
));
191 I915_WRITE(ring
->regs
.ctl
,
192 ((ring
->gem_object
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
193 | RING_NO_REPORT
| RING_VALID
);
195 head
= I915_READ(ring
->regs
.head
) & HEAD_ADDR
;
196 /* If the head is still not zero, the ring is dead */
198 DRM_ERROR("%s initialization failed "
199 "ctl %08x head %08x tail %08x start %08x\n",
201 I915_READ(ring
->regs
.ctl
),
202 I915_READ(ring
->regs
.head
),
203 I915_READ(ring
->regs
.tail
),
204 I915_READ(ring
->regs
.start
));
208 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
209 i915_kernel_lost_context(dev
);
211 ring
->head
= ring
->get_head(dev
, ring
);
212 ring
->tail
= ring
->get_tail(dev
, ring
);
213 ring
->space
= ring
->head
- (ring
->tail
+ 8);
215 ring
->space
+= ring
->size
;
220 static int init_render_ring(struct drm_device
*dev
,
221 struct intel_ring_buffer
*ring
)
223 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
224 int ret
= init_ring_common(dev
, ring
);
227 if (INTEL_INFO(dev
)->gen
> 3) {
228 mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
230 mode
|= MI_FLUSH_ENABLE
<< 16 | MI_FLUSH_ENABLE
;
231 I915_WRITE(MI_MODE
, mode
);
236 #define PIPE_CONTROL_FLUSH(addr) \
238 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
239 PIPE_CONTROL_DEPTH_STALL | 2); \
240 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
246 * Creates a new sequence number, emitting a write of it to the status page
247 * plus an interrupt, which will trigger i915_user_interrupt_handler.
249 * Must be called with struct_lock held.
251 * Returned sequence numbers are nonzero on success.
254 render_ring_add_request(struct drm_device
*dev
,
255 struct intel_ring_buffer
*ring
,
256 struct drm_file
*file_priv
,
259 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
262 seqno
= i915_gem_get_seqno(dev
);
266 OUT_RING(GFX_OP_PIPE_CONTROL
| 3);
267 OUT_RING(PIPE_CONTROL_QW_WRITE
|
268 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_IS_FLUSH
|
269 PIPE_CONTROL_NOTIFY
);
270 OUT_RING(dev_priv
->seqno_gfx_addr
| PIPE_CONTROL_GLOBAL_GTT
);
275 } else if (HAS_PIPE_CONTROL(dev
)) {
276 u32 scratch_addr
= dev_priv
->seqno_gfx_addr
+ 128;
279 * Workaround qword write incoherence by flushing the
280 * PIPE_NOTIFY buffers out to memory before requesting
284 OUT_RING(GFX_OP_PIPE_CONTROL
| PIPE_CONTROL_QW_WRITE
|
285 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_TC_FLUSH
);
286 OUT_RING(dev_priv
->seqno_gfx_addr
| PIPE_CONTROL_GLOBAL_GTT
);
289 PIPE_CONTROL_FLUSH(scratch_addr
);
290 scratch_addr
+= 128; /* write to separate cachelines */
291 PIPE_CONTROL_FLUSH(scratch_addr
);
293 PIPE_CONTROL_FLUSH(scratch_addr
);
295 PIPE_CONTROL_FLUSH(scratch_addr
);
297 PIPE_CONTROL_FLUSH(scratch_addr
);
299 PIPE_CONTROL_FLUSH(scratch_addr
);
300 OUT_RING(GFX_OP_PIPE_CONTROL
| PIPE_CONTROL_QW_WRITE
|
301 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_TC_FLUSH
|
302 PIPE_CONTROL_NOTIFY
);
303 OUT_RING(dev_priv
->seqno_gfx_addr
| PIPE_CONTROL_GLOBAL_GTT
);
309 OUT_RING(MI_STORE_DWORD_INDEX
);
310 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
313 OUT_RING(MI_USER_INTERRUPT
);
320 render_ring_get_gem_seqno(struct drm_device
*dev
,
321 struct intel_ring_buffer
*ring
)
323 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
324 if (HAS_PIPE_CONTROL(dev
))
325 return ((volatile u32
*)(dev_priv
->seqno_page
))[0];
327 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
331 render_ring_get_user_irq(struct drm_device
*dev
,
332 struct intel_ring_buffer
*ring
)
334 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
335 unsigned long irqflags
;
337 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
338 if (dev
->irq_enabled
&& (++ring
->user_irq_refcount
== 1)) {
339 if (HAS_PCH_SPLIT(dev
))
340 ironlake_enable_graphics_irq(dev_priv
, GT_PIPE_NOTIFY
);
342 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
344 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
348 render_ring_put_user_irq(struct drm_device
*dev
,
349 struct intel_ring_buffer
*ring
)
351 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
352 unsigned long irqflags
;
354 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
355 BUG_ON(dev
->irq_enabled
&& ring
->user_irq_refcount
<= 0);
356 if (dev
->irq_enabled
&& (--ring
->user_irq_refcount
== 0)) {
357 if (HAS_PCH_SPLIT(dev
))
358 ironlake_disable_graphics_irq(dev_priv
, GT_PIPE_NOTIFY
);
360 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
362 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
365 static void render_setup_status_page(struct drm_device
*dev
,
366 struct intel_ring_buffer
*ring
)
368 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
370 I915_WRITE(HWS_PGA_GEN6
, ring
->status_page
.gfx_addr
);
371 I915_READ(HWS_PGA_GEN6
); /* posting read */
373 I915_WRITE(HWS_PGA
, ring
->status_page
.gfx_addr
);
374 I915_READ(HWS_PGA
); /* posting read */
380 bsd_ring_flush(struct drm_device
*dev
,
381 struct intel_ring_buffer
*ring
,
382 u32 invalidate_domains
,
385 intel_ring_begin(dev
, ring
, 2);
386 intel_ring_emit(dev
, ring
, MI_FLUSH
);
387 intel_ring_emit(dev
, ring
, MI_NOOP
);
388 intel_ring_advance(dev
, ring
);
390 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
393 static inline unsigned int bsd_ring_get_head(struct drm_device
*dev
,
394 struct intel_ring_buffer
*ring
)
396 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
397 return I915_READ(BSD_RING_HEAD
) & HEAD_ADDR
;
400 static inline unsigned int bsd_ring_get_tail(struct drm_device
*dev
,
401 struct intel_ring_buffer
*ring
)
403 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
404 return I915_READ(BSD_RING_TAIL
) & TAIL_ADDR
;
407 static inline unsigned int bsd_ring_get_active_head(struct drm_device
*dev
,
408 struct intel_ring_buffer
*ring
)
410 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
411 return I915_READ(BSD_RING_ACTHD
);
414 static inline void bsd_ring_advance_ring(struct drm_device
*dev
,
415 struct intel_ring_buffer
*ring
)
417 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
418 I915_WRITE(BSD_RING_TAIL
, ring
->tail
);
421 static int init_bsd_ring(struct drm_device
*dev
,
422 struct intel_ring_buffer
*ring
)
424 return init_ring_common(dev
, ring
);
428 bsd_ring_add_request(struct drm_device
*dev
,
429 struct intel_ring_buffer
*ring
,
430 struct drm_file
*file_priv
,
435 seqno
= i915_gem_get_seqno(dev
);
437 intel_ring_begin(dev
, ring
, 4);
438 intel_ring_emit(dev
, ring
, MI_STORE_DWORD_INDEX
);
439 intel_ring_emit(dev
, ring
,
440 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
441 intel_ring_emit(dev
, ring
, seqno
);
442 intel_ring_emit(dev
, ring
, MI_USER_INTERRUPT
);
443 intel_ring_advance(dev
, ring
);
445 DRM_DEBUG_DRIVER("%s %d\n", ring
->name
, seqno
);
450 static void bsd_setup_status_page(struct drm_device
*dev
,
451 struct intel_ring_buffer
*ring
)
453 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
454 I915_WRITE(BSD_HWS_PGA
, ring
->status_page
.gfx_addr
);
455 I915_READ(BSD_HWS_PGA
);
459 bsd_ring_get_user_irq(struct drm_device
*dev
,
460 struct intel_ring_buffer
*ring
)
465 bsd_ring_put_user_irq(struct drm_device
*dev
,
466 struct intel_ring_buffer
*ring
)
472 bsd_ring_get_gem_seqno(struct drm_device
*dev
,
473 struct intel_ring_buffer
*ring
)
475 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
479 bsd_ring_dispatch_gem_execbuffer(struct drm_device
*dev
,
480 struct intel_ring_buffer
*ring
,
481 struct drm_i915_gem_execbuffer2
*exec
,
482 struct drm_clip_rect
*cliprects
,
483 uint64_t exec_offset
)
486 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
487 intel_ring_begin(dev
, ring
, 2);
488 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER_START
|
489 (2 << 6) | MI_BATCH_NON_SECURE_I965
);
490 intel_ring_emit(dev
, ring
, exec_start
);
491 intel_ring_advance(dev
, ring
);
497 render_ring_dispatch_gem_execbuffer(struct drm_device
*dev
,
498 struct intel_ring_buffer
*ring
,
499 struct drm_i915_gem_execbuffer2
*exec
,
500 struct drm_clip_rect
*cliprects
,
501 uint64_t exec_offset
)
503 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
504 int nbox
= exec
->num_cliprects
;
506 uint32_t exec_start
, exec_len
;
507 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
508 exec_len
= (uint32_t) exec
->batch_len
;
510 trace_i915_gem_request_submit(dev
, dev_priv
->next_seqno
+ 1);
512 count
= nbox
? nbox
: 1;
514 for (i
= 0; i
< count
; i
++) {
516 int ret
= i915_emit_box(dev
, cliprects
, i
,
517 exec
->DR1
, exec
->DR4
);
522 if (IS_I830(dev
) || IS_845G(dev
)) {
523 intel_ring_begin(dev
, ring
, 4);
524 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER
);
525 intel_ring_emit(dev
, ring
,
526 exec_start
| MI_BATCH_NON_SECURE
);
527 intel_ring_emit(dev
, ring
, exec_start
+ exec_len
- 4);
528 intel_ring_emit(dev
, ring
, 0);
530 intel_ring_begin(dev
, ring
, 4);
531 if (INTEL_INFO(dev
)->gen
>= 4) {
532 intel_ring_emit(dev
, ring
,
533 MI_BATCH_BUFFER_START
| (2 << 6)
534 | MI_BATCH_NON_SECURE_I965
);
535 intel_ring_emit(dev
, ring
, exec_start
);
537 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER_START
539 intel_ring_emit(dev
, ring
, exec_start
|
540 MI_BATCH_NON_SECURE
);
543 intel_ring_advance(dev
, ring
);
546 if (IS_G4X(dev
) || IS_IRONLAKE(dev
)) {
547 intel_ring_begin(dev
, ring
, 2);
548 intel_ring_emit(dev
, ring
, MI_FLUSH
|
551 intel_ring_emit(dev
, ring
, MI_NOOP
);
552 intel_ring_advance(dev
, ring
);
559 static void cleanup_status_page(struct drm_device
*dev
,
560 struct intel_ring_buffer
*ring
)
562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
563 struct drm_gem_object
*obj
;
564 struct drm_i915_gem_object
*obj_priv
;
566 obj
= ring
->status_page
.obj
;
569 obj_priv
= to_intel_bo(obj
);
571 kunmap(obj_priv
->pages
[0]);
572 i915_gem_object_unpin(obj
);
573 drm_gem_object_unreference(obj
);
574 ring
->status_page
.obj
= NULL
;
576 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
579 static int init_status_page(struct drm_device
*dev
,
580 struct intel_ring_buffer
*ring
)
582 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
583 struct drm_gem_object
*obj
;
584 struct drm_i915_gem_object
*obj_priv
;
587 obj
= i915_gem_alloc_object(dev
, 4096);
589 DRM_ERROR("Failed to allocate status page\n");
593 obj_priv
= to_intel_bo(obj
);
594 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
596 ret
= i915_gem_object_pin(obj
, 4096);
601 ring
->status_page
.gfx_addr
= obj_priv
->gtt_offset
;
602 ring
->status_page
.page_addr
= kmap(obj_priv
->pages
[0]);
603 if (ring
->status_page
.page_addr
== NULL
) {
604 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
607 ring
->status_page
.obj
= obj
;
608 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
610 ring
->setup_status_page(dev
, ring
);
611 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
612 ring
->name
, ring
->status_page
.gfx_addr
);
617 i915_gem_object_unpin(obj
);
619 drm_gem_object_unreference(obj
);
625 int intel_init_ring_buffer(struct drm_device
*dev
,
626 struct intel_ring_buffer
*ring
)
628 struct drm_i915_gem_object
*obj_priv
;
629 struct drm_gem_object
*obj
;
634 if (I915_NEED_GFX_HWS(dev
)) {
635 ret
= init_status_page(dev
, ring
);
640 obj
= i915_gem_alloc_object(dev
, ring
->size
);
642 DRM_ERROR("Failed to allocate ringbuffer\n");
647 ring
->gem_object
= obj
;
649 ret
= i915_gem_object_pin(obj
, ring
->alignment
);
653 obj_priv
= to_intel_bo(obj
);
654 ring
->map
.size
= ring
->size
;
655 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
660 drm_core_ioremap_wc(&ring
->map
, dev
);
661 if (ring
->map
.handle
== NULL
) {
662 DRM_ERROR("Failed to map ringbuffer.\n");
667 ring
->virtual_start
= ring
->map
.handle
;
668 ret
= ring
->init(dev
, ring
);
672 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
673 i915_kernel_lost_context(dev
);
675 ring
->head
= ring
->get_head(dev
, ring
);
676 ring
->tail
= ring
->get_tail(dev
, ring
);
677 ring
->space
= ring
->head
- (ring
->tail
+ 8);
679 ring
->space
+= ring
->size
;
681 INIT_LIST_HEAD(&ring
->active_list
);
682 INIT_LIST_HEAD(&ring
->request_list
);
686 drm_core_ioremapfree(&ring
->map
, dev
);
688 i915_gem_object_unpin(obj
);
690 drm_gem_object_unreference(obj
);
691 ring
->gem_object
= NULL
;
693 cleanup_status_page(dev
, ring
);
697 void intel_cleanup_ring_buffer(struct drm_device
*dev
,
698 struct intel_ring_buffer
*ring
)
700 if (ring
->gem_object
== NULL
)
703 drm_core_ioremapfree(&ring
->map
, dev
);
705 i915_gem_object_unpin(ring
->gem_object
);
706 drm_gem_object_unreference(ring
->gem_object
);
707 ring
->gem_object
= NULL
;
708 cleanup_status_page(dev
, ring
);
711 int intel_wrap_ring_buffer(struct drm_device
*dev
,
712 struct intel_ring_buffer
*ring
)
716 rem
= ring
->size
- ring
->tail
;
718 if (ring
->space
< rem
) {
719 int ret
= intel_wait_ring_buffer(dev
, ring
, rem
);
724 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
732 ring
->space
= ring
->head
- 8;
737 int intel_wait_ring_buffer(struct drm_device
*dev
,
738 struct intel_ring_buffer
*ring
, int n
)
742 trace_i915_ring_wait_begin (dev
);
743 end
= jiffies
+ 3 * HZ
;
745 ring
->head
= ring
->get_head(dev
, ring
);
746 ring
->space
= ring
->head
- (ring
->tail
+ 8);
748 ring
->space
+= ring
->size
;
749 if (ring
->space
>= n
) {
750 trace_i915_ring_wait_end (dev
);
754 if (dev
->primary
->master
) {
755 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
756 if (master_priv
->sarea_priv
)
757 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
761 } while (!time_after(jiffies
, end
));
762 trace_i915_ring_wait_end (dev
);
766 void intel_ring_begin(struct drm_device
*dev
,
767 struct intel_ring_buffer
*ring
, int num_dwords
)
769 int n
= 4*num_dwords
;
770 if (unlikely(ring
->tail
+ n
> ring
->size
))
771 intel_wrap_ring_buffer(dev
, ring
);
772 if (unlikely(ring
->space
< n
))
773 intel_wait_ring_buffer(dev
, ring
, n
);
778 void intel_ring_advance(struct drm_device
*dev
,
779 struct intel_ring_buffer
*ring
)
781 ring
->tail
&= ring
->size
- 1;
782 ring
->advance_ring(dev
, ring
);
785 void intel_fill_struct(struct drm_device
*dev
,
786 struct intel_ring_buffer
*ring
,
790 unsigned int *virt
= ring
->virtual_start
+ ring
->tail
;
791 BUG_ON((len
&~(4-1)) != 0);
792 intel_ring_begin(dev
, ring
, len
/4);
793 memcpy(virt
, data
, len
);
795 ring
->tail
&= ring
->size
- 1;
797 intel_ring_advance(dev
, ring
);
800 struct intel_ring_buffer render_ring
= {
801 .name
= "render ring",
808 .size
= 32 * PAGE_SIZE
,
809 .alignment
= PAGE_SIZE
,
810 .virtual_start
= NULL
,
816 .user_irq_refcount
= 0,
818 .waiting_gem_seqno
= 0,
819 .setup_status_page
= render_setup_status_page
,
820 .init
= init_render_ring
,
821 .get_head
= render_ring_get_head
,
822 .get_tail
= render_ring_get_tail
,
823 .get_active_head
= render_ring_get_active_head
,
824 .advance_ring
= render_ring_advance_ring
,
825 .flush
= render_ring_flush
,
826 .add_request
= render_ring_add_request
,
827 .get_gem_seqno
= render_ring_get_gem_seqno
,
828 .user_irq_get
= render_ring_get_user_irq
,
829 .user_irq_put
= render_ring_put_user_irq
,
830 .dispatch_gem_execbuffer
= render_ring_dispatch_gem_execbuffer
,
831 .status_page
= {NULL
, 0, NULL
},
835 /* ring buffer for bit-stream decoder */
837 struct intel_ring_buffer bsd_ring
= {
841 .head
= BSD_RING_HEAD
,
842 .tail
= BSD_RING_TAIL
,
843 .start
= BSD_RING_START
845 .size
= 32 * PAGE_SIZE
,
846 .alignment
= PAGE_SIZE
,
847 .virtual_start
= NULL
,
853 .user_irq_refcount
= 0,
855 .waiting_gem_seqno
= 0,
856 .setup_status_page
= bsd_setup_status_page
,
857 .init
= init_bsd_ring
,
858 .get_head
= bsd_ring_get_head
,
859 .get_tail
= bsd_ring_get_tail
,
860 .get_active_head
= bsd_ring_get_active_head
,
861 .advance_ring
= bsd_ring_advance_ring
,
862 .flush
= bsd_ring_flush
,
863 .add_request
= bsd_ring_add_request
,
864 .get_gem_seqno
= bsd_ring_get_gem_seqno
,
865 .user_irq_get
= bsd_ring_get_user_irq
,
866 .user_irq_put
= bsd_ring_put_user_irq
,
867 .dispatch_gem_execbuffer
= bsd_ring_dispatch_gem_execbuffer
,
868 .status_page
= {NULL
, 0, NULL
},