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drm/i915: add helpers for platform specific revision id range checks
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - tail;
56 if (space <= 0)
57 space += size;
58 return space - I915_RING_FREE_SPACE;
59 }
60
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62 {
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70 }
71
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
73 {
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
76 }
77
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
79 {
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82 }
83
84 static void __intel_ring_advance(struct intel_engine_cs *ring)
85 {
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
89 return;
90 ring->write_tail(ring, ringbuf->tail);
91 }
92
93 static int
94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
95 u32 invalidate_domains,
96 u32 flush_domains)
97 {
98 struct intel_engine_cs *ring = req->ring;
99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
109 ret = intel_ring_begin(req, 2);
110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118 }
119
120 static int
121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
122 u32 invalidate_domains,
123 u32 flush_domains)
124 {
125 struct intel_engine_cs *ring = req->ring;
126 struct drm_device *dev = ring->dev;
127 u32 cmd;
128 int ret;
129
130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
160 cmd &= ~MI_NO_WRITE_FLUSH;
161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
163
164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
167
168 ret = intel_ring_begin(req, 2);
169 if (ret)
170 return ret;
171
172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
175
176 return 0;
177 }
178
179 /**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216 static int
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
218 {
219 struct intel_engine_cs *ring = req->ring;
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
221 int ret;
222
223 ret = intel_ring_begin(req, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
236 ret = intel_ring_begin(req, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static int
252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
254 {
255 struct intel_engine_cs *ring = req->ring;
256 u32 flags = 0;
257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
258 int ret;
259
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret = intel_emit_post_sync_nonzero_flush(req);
262 if (ret)
263 return ret;
264
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
276 flags |= PIPE_CONTROL_CS_STALL;
277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
289 }
290
291 ret = intel_ring_begin(req, 4);
292 if (ret)
293 return ret;
294
295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
298 intel_ring_emit(ring, 0);
299 intel_ring_advance(ring);
300
301 return 0;
302 }
303
304 static int
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
306 {
307 struct intel_engine_cs *ring = req->ring;
308 int ret;
309
310 ret = intel_ring_begin(req, 4);
311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322 }
323
324 static int
325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
326 u32 invalidate_domains, u32 flush_domains)
327 {
328 struct intel_engine_cs *ring = req->ring;
329 u32 flags = 0;
330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
331 int ret;
332
333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
364
365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req);
371 }
372
373 ret = intel_ring_begin(req, 4);
374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
379 intel_ring_emit(ring, scratch_addr);
380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384 }
385
386 static int
387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
388 u32 flags, u32 scratch_addr)
389 {
390 struct intel_engine_cs *ring = req->ring;
391 int ret;
392
393 ret = intel_ring_begin(req, 6);
394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406 }
407
408 static int
409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
410 u32 invalidate_domains, u32 flush_domains)
411 {
412 u32 flags = 0;
413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
414 int ret;
415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret = gen8_emit_pipe_control(req,
434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
439 }
440
441 return gen8_emit_pipe_control(req, flags, scratch_addr);
442 }
443
444 static void ring_write_tail(struct intel_engine_cs *ring,
445 u32 value)
446 {
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
448 I915_WRITE_TAIL(ring, value);
449 }
450
451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
452 {
453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
454 u64 acthd;
455
456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
465 }
466
467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
468 {
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476 }
477
478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479 {
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538 }
539
540 static bool stop_ring(struct intel_engine_cs *ring)
541 {
542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
543
544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
554 }
555 }
556
557 I915_WRITE_CTL(ring, 0);
558 I915_WRITE_HEAD(ring, 0);
559 ring->write_tail(ring, 0);
560
561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
565
566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567 }
568
569 static int init_ring_common(struct intel_engine_cs *ring)
570 {
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
575 int ret = 0;
576
577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
588
589 if (!stop_ring(ring)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
597 ret = -EIO;
598 goto out;
599 }
600 }
601
602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
623 I915_WRITE_CTL(ring,
624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
625 | RING_VALID);
626
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
637 ret = -EIO;
638 goto out;
639 }
640
641 ringbuf->last_retired_head = -1;
642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
644 intel_ring_update_space(ringbuf);
645
646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
648 out:
649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
650
651 return ret;
652 }
653
654 void
655 intel_fini_pipe_control(struct intel_engine_cs *ring)
656 {
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669 }
670
671 int
672 intel_init_pipe_control(struct intel_engine_cs *ring)
673 {
674 int ret;
675
676 WARN_ON(ring->scratch.obj);
677
678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
684
685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
688
689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
690 if (ret)
691 goto err_unref;
692
693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
696 ret = -ENOMEM;
697 goto err_unpin;
698 }
699
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring->name, ring->scratch.gtt_offset);
702 return 0;
703
704 err_unpin:
705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
706 err_unref:
707 drm_gem_object_unreference(&ring->scratch.obj->base);
708 err:
709 return ret;
710 }
711
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
713 {
714 int ret, i;
715 struct intel_engine_cs *ring = req->ring;
716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718 struct i915_workarounds *w = &dev_priv->workarounds;
719
720 if (w->count == 0)
721 return 0;
722
723 ring->gpu_caches_dirty = true;
724 ret = intel_ring_flush_all_caches(req);
725 if (ret)
726 return ret;
727
728 ret = intel_ring_begin(req, (w->count * 2 + 2));
729 if (ret)
730 return ret;
731
732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
733 for (i = 0; i < w->count; i++) {
734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
737 intel_ring_emit(ring, MI_NOOP);
738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
742 ret = intel_ring_flush_all_caches(req);
743 if (ret)
744 return ret;
745
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
747
748 return 0;
749 }
750
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
752 {
753 int ret;
754
755 ret = intel_ring_workarounds_emit(req);
756 if (ret != 0)
757 return ret;
758
759 ret = i915_gem_render_state_init(req);
760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764 }
765
766 static int wa_add(struct drm_i915_private *dev_priv,
767 const u32 addr, const u32 mask, const u32 val)
768 {
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
781 }
782
783 #define WA_REG(addr, mask, val) do { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
785 if (r) \
786 return r; \
787 } while (0)
788
789 #define WA_SET_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
791
792 #define WA_CLR_BIT_MASKED(addr, mask) \
793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
794
795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
797
798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
800
801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
802
803 static int gen8_init_workarounds(struct intel_engine_cs *ring)
804 {
805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807
808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
809
810 /* WaDisableAsyncFlipPerfMode:bdw,chv */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
813 /* WaDisablePartialInstShootdown:bdw,chv */
814 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
815 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
816
817 /* Use Force Non-Coherent whenever executing a 3D context. This is a
818 * workaround for for a possible hang in the unlikely event a TLB
819 * invalidation occurs during a PSD flush.
820 */
821 /* WaForceEnableNonCoherent:bdw,chv */
822 /* WaHdcDisableFetchWhenMasked:bdw,chv */
823 WA_SET_BIT_MASKED(HDC_CHICKEN0,
824 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
825 HDC_FORCE_NON_COHERENT);
826
827 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
828 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
829 * polygons in the same 8x4 pixel/sample area to be processed without
830 * stalling waiting for the earlier ones to write to Hierarchical Z
831 * buffer."
832 *
833 * This optimization is off by default for BDW and CHV; turn it on.
834 */
835 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
836
837 /* Wa4x4STCOptimizationDisable:bdw,chv */
838 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
839
840 /*
841 * BSpec recommends 8x4 when MSAA is used,
842 * however in practice 16x4 seems fastest.
843 *
844 * Note that PS/WM thread counts depend on the WIZ hashing
845 * disable bit, which we don't touch here, but it's good
846 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
847 */
848 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
849 GEN6_WIZ_HASHING_MASK,
850 GEN6_WIZ_HASHING_16x4);
851
852 return 0;
853 }
854
855 static int bdw_init_workarounds(struct intel_engine_cs *ring)
856 {
857 int ret;
858 struct drm_device *dev = ring->dev;
859 struct drm_i915_private *dev_priv = dev->dev_private;
860
861 ret = gen8_init_workarounds(ring);
862 if (ret)
863 return ret;
864
865 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
866 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
867
868 /* WaDisableDopClockGating:bdw */
869 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
870 DOP_CLOCK_GATING_DISABLE);
871
872 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
873 GEN8_SAMPLER_POWER_BYPASS_DIS);
874
875 WA_SET_BIT_MASKED(HDC_CHICKEN0,
876 /* WaForceContextSaveRestoreNonCoherent:bdw */
877 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
878 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
879 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
880
881 return 0;
882 }
883
884 static int chv_init_workarounds(struct intel_engine_cs *ring)
885 {
886 int ret;
887 struct drm_device *dev = ring->dev;
888 struct drm_i915_private *dev_priv = dev->dev_private;
889
890 ret = gen8_init_workarounds(ring);
891 if (ret)
892 return ret;
893
894 /* WaDisableThreadStallDopClockGating:chv */
895 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
896
897 /* Improve HiZ throughput on CHV. */
898 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
899
900 return 0;
901 }
902
903 static int gen9_init_workarounds(struct intel_engine_cs *ring)
904 {
905 struct drm_device *dev = ring->dev;
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 uint32_t tmp;
908
909 /* WaEnableLbsSlaRetryTimerDecrement:skl */
910 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
911 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
912
913 /* WaDisableKillLogic:bxt,skl */
914 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
915 ECOCHK_DIS_TLB);
916
917 /* WaDisablePartialInstShootdown:skl,bxt */
918 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
919 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
920
921 /* Syncing dependencies between camera and graphics:skl,bxt */
922 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
923 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
924
925 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
926 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
927 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
928 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
929 GEN9_DG_MIRROR_FIX_ENABLE);
930
931 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
932 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
933 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
934 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
935 GEN9_RHWO_OPTIMIZATION_DISABLE);
936 /*
937 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
938 * but we do that in per ctx batchbuffer as there is an issue
939 * with this register not getting restored on ctx restore
940 */
941 }
942
943 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
944 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
945 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
946 GEN9_ENABLE_YV12_BUGFIX);
947
948 /* Wa4x4STCOptimizationDisable:skl,bxt */
949 /* WaDisablePartialResolveInVc:skl,bxt */
950 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
951 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
952
953 /* WaCcsTlbPrefetchDisable:skl,bxt */
954 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
955 GEN9_CCS_TLB_PREFETCH_ENABLE);
956
957 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
958 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
959 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
960 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
961 PIXEL_MASK_CAMMING_DISABLE);
962
963 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
964 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
965 if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
966 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
967 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
968 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
969
970 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
971 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
972 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
973 GEN8_SAMPLER_POWER_BYPASS_DIS);
974
975 /* WaDisableSTUnitPowerOptimization:skl,bxt */
976 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
977
978 return 0;
979 }
980
981 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
982 {
983 struct drm_device *dev = ring->dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u8 vals[3] = { 0, 0, 0 };
986 unsigned int i;
987
988 for (i = 0; i < 3; i++) {
989 u8 ss;
990
991 /*
992 * Only consider slices where one, and only one, subslice has 7
993 * EUs
994 */
995 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
996 continue;
997
998 /*
999 * subslice_7eu[i] != 0 (because of the check above) and
1000 * ss_max == 4 (maximum number of subslices possible per slice)
1001 *
1002 * -> 0 <= ss <= 3;
1003 */
1004 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1005 vals[i] = 3 - ss;
1006 }
1007
1008 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1009 return 0;
1010
1011 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1013 GEN9_IZ_HASHING_MASK(2) |
1014 GEN9_IZ_HASHING_MASK(1) |
1015 GEN9_IZ_HASHING_MASK(0),
1016 GEN9_IZ_HASHING(2, vals[2]) |
1017 GEN9_IZ_HASHING(1, vals[1]) |
1018 GEN9_IZ_HASHING(0, vals[0]));
1019
1020 return 0;
1021 }
1022
1023 static int skl_init_workarounds(struct intel_engine_cs *ring)
1024 {
1025 int ret;
1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028
1029 ret = gen9_init_workarounds(ring);
1030 if (ret)
1031 return ret;
1032
1033 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1034 /* WaDisableHDCInvalidation:skl */
1035 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1036 BDW_DISABLE_HDC_INVALIDATION);
1037
1038 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1039 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1040 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1041 }
1042
1043 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1044 * involving this register should also be added to WA batch as required.
1045 */
1046 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1047 /* WaDisableLSQCROPERFforOCL:skl */
1048 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1049 GEN8_LQSC_RO_PERF_DIS);
1050
1051 /* WaEnableGapsTsvCreditFix:skl */
1052 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1053 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1054 GEN9_GAPS_TSV_CREDIT_DISABLE));
1055 }
1056
1057 /* WaDisablePowerCompilerClockGating:skl */
1058 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1059 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1060 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1061
1062 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1063 /*
1064 *Use Force Non-Coherent whenever executing a 3D context. This
1065 * is a workaround for a possible hang in the unlikely event
1066 * a TLB invalidation occurs during a PSD flush.
1067 */
1068 /* WaForceEnableNonCoherent:skl */
1069 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1070 HDC_FORCE_NON_COHERENT);
1071 }
1072
1073 /* WaBarrierPerformanceFixDisable:skl */
1074 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1075 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1076 HDC_FENCE_DEST_SLM_DISABLE |
1077 HDC_BARRIER_PERFORMANCE_DISABLE);
1078
1079 /* WaDisableSbeCacheDispatchPortSharing:skl */
1080 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1081 WA_SET_BIT_MASKED(
1082 GEN7_HALF_SLICE_CHICKEN1,
1083 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1084
1085 return skl_tune_iz_hashing(ring);
1086 }
1087
1088 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1089 {
1090 int ret;
1091 struct drm_device *dev = ring->dev;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093
1094 ret = gen9_init_workarounds(ring);
1095 if (ret)
1096 return ret;
1097
1098 /* WaStoreMultiplePTEenable:bxt */
1099 /* This is a requirement according to Hardware specification */
1100 if (IS_BXT_REVID(dev, 0, BXT_REVID_A0))
1101 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1102
1103 /* WaSetClckGatingDisableMedia:bxt */
1104 if (IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
1105 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1106 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1107 }
1108
1109 /* WaDisableThreadStallDopClockGating:bxt */
1110 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1111 STALL_DOP_GATING_DISABLE);
1112
1113 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1114 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1115 WA_SET_BIT_MASKED(
1116 GEN7_HALF_SLICE_CHICKEN1,
1117 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1118 }
1119
1120 return 0;
1121 }
1122
1123 int init_workarounds_ring(struct intel_engine_cs *ring)
1124 {
1125 struct drm_device *dev = ring->dev;
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127
1128 WARN_ON(ring->id != RCS);
1129
1130 dev_priv->workarounds.count = 0;
1131
1132 if (IS_BROADWELL(dev))
1133 return bdw_init_workarounds(ring);
1134
1135 if (IS_CHERRYVIEW(dev))
1136 return chv_init_workarounds(ring);
1137
1138 if (IS_SKYLAKE(dev))
1139 return skl_init_workarounds(ring);
1140
1141 if (IS_BROXTON(dev))
1142 return bxt_init_workarounds(ring);
1143
1144 return 0;
1145 }
1146
1147 static int init_render_ring(struct intel_engine_cs *ring)
1148 {
1149 struct drm_device *dev = ring->dev;
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 int ret = init_ring_common(ring);
1152 if (ret)
1153 return ret;
1154
1155 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1156 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1157 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1158
1159 /* We need to disable the AsyncFlip performance optimisations in order
1160 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1161 * programmed to '1' on all products.
1162 *
1163 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1164 */
1165 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1166 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1167
1168 /* Required for the hardware to program scanline values for waiting */
1169 /* WaEnableFlushTlbInvalidationMode:snb */
1170 if (INTEL_INFO(dev)->gen == 6)
1171 I915_WRITE(GFX_MODE,
1172 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1173
1174 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1175 if (IS_GEN7(dev))
1176 I915_WRITE(GFX_MODE_GEN7,
1177 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1178 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1179
1180 if (IS_GEN6(dev)) {
1181 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1182 * "If this bit is set, STCunit will have LRA as replacement
1183 * policy. [...] This bit must be reset. LRA replacement
1184 * policy is not supported."
1185 */
1186 I915_WRITE(CACHE_MODE_0,
1187 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1188 }
1189
1190 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1191 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1192
1193 if (HAS_L3_DPF(dev))
1194 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1195
1196 return init_workarounds_ring(ring);
1197 }
1198
1199 static void render_ring_cleanup(struct intel_engine_cs *ring)
1200 {
1201 struct drm_device *dev = ring->dev;
1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203
1204 if (dev_priv->semaphore_obj) {
1205 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1206 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1207 dev_priv->semaphore_obj = NULL;
1208 }
1209
1210 intel_fini_pipe_control(ring);
1211 }
1212
1213 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1214 unsigned int num_dwords)
1215 {
1216 #define MBOX_UPDATE_DWORDS 8
1217 struct intel_engine_cs *signaller = signaller_req->ring;
1218 struct drm_device *dev = signaller->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 struct intel_engine_cs *waiter;
1221 int i, ret, num_rings;
1222
1223 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1224 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1225 #undef MBOX_UPDATE_DWORDS
1226
1227 ret = intel_ring_begin(signaller_req, num_dwords);
1228 if (ret)
1229 return ret;
1230
1231 for_each_ring(waiter, dev_priv, i) {
1232 u32 seqno;
1233 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1234 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1235 continue;
1236
1237 seqno = i915_gem_request_get_seqno(signaller_req);
1238 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1239 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1240 PIPE_CONTROL_QW_WRITE |
1241 PIPE_CONTROL_FLUSH_ENABLE);
1242 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1243 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1244 intel_ring_emit(signaller, seqno);
1245 intel_ring_emit(signaller, 0);
1246 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1247 MI_SEMAPHORE_TARGET(waiter->id));
1248 intel_ring_emit(signaller, 0);
1249 }
1250
1251 return 0;
1252 }
1253
1254 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1255 unsigned int num_dwords)
1256 {
1257 #define MBOX_UPDATE_DWORDS 6
1258 struct intel_engine_cs *signaller = signaller_req->ring;
1259 struct drm_device *dev = signaller->dev;
1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 struct intel_engine_cs *waiter;
1262 int i, ret, num_rings;
1263
1264 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1265 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1266 #undef MBOX_UPDATE_DWORDS
1267
1268 ret = intel_ring_begin(signaller_req, num_dwords);
1269 if (ret)
1270 return ret;
1271
1272 for_each_ring(waiter, dev_priv, i) {
1273 u32 seqno;
1274 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1275 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1276 continue;
1277
1278 seqno = i915_gem_request_get_seqno(signaller_req);
1279 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1280 MI_FLUSH_DW_OP_STOREDW);
1281 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1282 MI_FLUSH_DW_USE_GTT);
1283 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1284 intel_ring_emit(signaller, seqno);
1285 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1286 MI_SEMAPHORE_TARGET(waiter->id));
1287 intel_ring_emit(signaller, 0);
1288 }
1289
1290 return 0;
1291 }
1292
1293 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1294 unsigned int num_dwords)
1295 {
1296 struct intel_engine_cs *signaller = signaller_req->ring;
1297 struct drm_device *dev = signaller->dev;
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299 struct intel_engine_cs *useless;
1300 int i, ret, num_rings;
1301
1302 #define MBOX_UPDATE_DWORDS 3
1303 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1304 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1305 #undef MBOX_UPDATE_DWORDS
1306
1307 ret = intel_ring_begin(signaller_req, num_dwords);
1308 if (ret)
1309 return ret;
1310
1311 for_each_ring(useless, dev_priv, i) {
1312 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1313 if (mbox_reg != GEN6_NOSYNC) {
1314 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1315 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1316 intel_ring_emit(signaller, mbox_reg);
1317 intel_ring_emit(signaller, seqno);
1318 }
1319 }
1320
1321 /* If num_dwords was rounded, make sure the tail pointer is correct */
1322 if (num_rings % 2 == 0)
1323 intel_ring_emit(signaller, MI_NOOP);
1324
1325 return 0;
1326 }
1327
1328 /**
1329 * gen6_add_request - Update the semaphore mailbox registers
1330 *
1331 * @request - request to write to the ring
1332 *
1333 * Update the mailbox registers in the *other* rings with the current seqno.
1334 * This acts like a signal in the canonical semaphore.
1335 */
1336 static int
1337 gen6_add_request(struct drm_i915_gem_request *req)
1338 {
1339 struct intel_engine_cs *ring = req->ring;
1340 int ret;
1341
1342 if (ring->semaphore.signal)
1343 ret = ring->semaphore.signal(req, 4);
1344 else
1345 ret = intel_ring_begin(req, 4);
1346
1347 if (ret)
1348 return ret;
1349
1350 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1351 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1352 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1353 intel_ring_emit(ring, MI_USER_INTERRUPT);
1354 __intel_ring_advance(ring);
1355
1356 return 0;
1357 }
1358
1359 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1360 u32 seqno)
1361 {
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 return dev_priv->last_seqno < seqno;
1364 }
1365
1366 /**
1367 * intel_ring_sync - sync the waiter to the signaller on seqno
1368 *
1369 * @waiter - ring that is waiting
1370 * @signaller - ring which has, or will signal
1371 * @seqno - seqno which the waiter will block on
1372 */
1373
1374 static int
1375 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1376 struct intel_engine_cs *signaller,
1377 u32 seqno)
1378 {
1379 struct intel_engine_cs *waiter = waiter_req->ring;
1380 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1381 int ret;
1382
1383 ret = intel_ring_begin(waiter_req, 4);
1384 if (ret)
1385 return ret;
1386
1387 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1388 MI_SEMAPHORE_GLOBAL_GTT |
1389 MI_SEMAPHORE_POLL |
1390 MI_SEMAPHORE_SAD_GTE_SDD);
1391 intel_ring_emit(waiter, seqno);
1392 intel_ring_emit(waiter,
1393 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1394 intel_ring_emit(waiter,
1395 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1396 intel_ring_advance(waiter);
1397 return 0;
1398 }
1399
1400 static int
1401 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1402 struct intel_engine_cs *signaller,
1403 u32 seqno)
1404 {
1405 struct intel_engine_cs *waiter = waiter_req->ring;
1406 u32 dw1 = MI_SEMAPHORE_MBOX |
1407 MI_SEMAPHORE_COMPARE |
1408 MI_SEMAPHORE_REGISTER;
1409 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1410 int ret;
1411
1412 /* Throughout all of the GEM code, seqno passed implies our current
1413 * seqno is >= the last seqno executed. However for hardware the
1414 * comparison is strictly greater than.
1415 */
1416 seqno -= 1;
1417
1418 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1419
1420 ret = intel_ring_begin(waiter_req, 4);
1421 if (ret)
1422 return ret;
1423
1424 /* If seqno wrap happened, omit the wait with no-ops */
1425 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1426 intel_ring_emit(waiter, dw1 | wait_mbox);
1427 intel_ring_emit(waiter, seqno);
1428 intel_ring_emit(waiter, 0);
1429 intel_ring_emit(waiter, MI_NOOP);
1430 } else {
1431 intel_ring_emit(waiter, MI_NOOP);
1432 intel_ring_emit(waiter, MI_NOOP);
1433 intel_ring_emit(waiter, MI_NOOP);
1434 intel_ring_emit(waiter, MI_NOOP);
1435 }
1436 intel_ring_advance(waiter);
1437
1438 return 0;
1439 }
1440
1441 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1442 do { \
1443 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1444 PIPE_CONTROL_DEPTH_STALL); \
1445 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1446 intel_ring_emit(ring__, 0); \
1447 intel_ring_emit(ring__, 0); \
1448 } while (0)
1449
1450 static int
1451 pc_render_add_request(struct drm_i915_gem_request *req)
1452 {
1453 struct intel_engine_cs *ring = req->ring;
1454 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1455 int ret;
1456
1457 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1458 * incoherent with writes to memory, i.e. completely fubar,
1459 * so we need to use PIPE_NOTIFY instead.
1460 *
1461 * However, we also need to workaround the qword write
1462 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1463 * memory before requesting an interrupt.
1464 */
1465 ret = intel_ring_begin(req, 32);
1466 if (ret)
1467 return ret;
1468
1469 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1470 PIPE_CONTROL_WRITE_FLUSH |
1471 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1472 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1473 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1474 intel_ring_emit(ring, 0);
1475 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1476 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1477 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1478 scratch_addr += 2 * CACHELINE_BYTES;
1479 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1480 scratch_addr += 2 * CACHELINE_BYTES;
1481 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1482 scratch_addr += 2 * CACHELINE_BYTES;
1483 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1484 scratch_addr += 2 * CACHELINE_BYTES;
1485 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1486
1487 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1488 PIPE_CONTROL_WRITE_FLUSH |
1489 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1490 PIPE_CONTROL_NOTIFY);
1491 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1492 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1493 intel_ring_emit(ring, 0);
1494 __intel_ring_advance(ring);
1495
1496 return 0;
1497 }
1498
1499 static u32
1500 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1501 {
1502 /* Workaround to force correct ordering between irq and seqno writes on
1503 * ivb (and maybe also on snb) by reading from a CS register (like
1504 * ACTHD) before reading the status page. */
1505 if (!lazy_coherency) {
1506 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1507 POSTING_READ(RING_ACTHD(ring->mmio_base));
1508 }
1509
1510 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1511 }
1512
1513 static u32
1514 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1515 {
1516 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1517 }
1518
1519 static void
1520 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1521 {
1522 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1523 }
1524
1525 static u32
1526 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1527 {
1528 return ring->scratch.cpu_page[0];
1529 }
1530
1531 static void
1532 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1533 {
1534 ring->scratch.cpu_page[0] = seqno;
1535 }
1536
1537 static bool
1538 gen5_ring_get_irq(struct intel_engine_cs *ring)
1539 {
1540 struct drm_device *dev = ring->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 unsigned long flags;
1543
1544 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1545 return false;
1546
1547 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1548 if (ring->irq_refcount++ == 0)
1549 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1550 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1551
1552 return true;
1553 }
1554
1555 static void
1556 gen5_ring_put_irq(struct intel_engine_cs *ring)
1557 {
1558 struct drm_device *dev = ring->dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 unsigned long flags;
1561
1562 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1563 if (--ring->irq_refcount == 0)
1564 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1565 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1566 }
1567
1568 static bool
1569 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1570 {
1571 struct drm_device *dev = ring->dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 unsigned long flags;
1574
1575 if (!intel_irqs_enabled(dev_priv))
1576 return false;
1577
1578 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1579 if (ring->irq_refcount++ == 0) {
1580 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1581 I915_WRITE(IMR, dev_priv->irq_mask);
1582 POSTING_READ(IMR);
1583 }
1584 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1585
1586 return true;
1587 }
1588
1589 static void
1590 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1591 {
1592 struct drm_device *dev = ring->dev;
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1597 if (--ring->irq_refcount == 0) {
1598 dev_priv->irq_mask |= ring->irq_enable_mask;
1599 I915_WRITE(IMR, dev_priv->irq_mask);
1600 POSTING_READ(IMR);
1601 }
1602 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1603 }
1604
1605 static bool
1606 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1607 {
1608 struct drm_device *dev = ring->dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 unsigned long flags;
1611
1612 if (!intel_irqs_enabled(dev_priv))
1613 return false;
1614
1615 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1616 if (ring->irq_refcount++ == 0) {
1617 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1618 I915_WRITE16(IMR, dev_priv->irq_mask);
1619 POSTING_READ16(IMR);
1620 }
1621 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1622
1623 return true;
1624 }
1625
1626 static void
1627 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1628 {
1629 struct drm_device *dev = ring->dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 unsigned long flags;
1632
1633 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1634 if (--ring->irq_refcount == 0) {
1635 dev_priv->irq_mask |= ring->irq_enable_mask;
1636 I915_WRITE16(IMR, dev_priv->irq_mask);
1637 POSTING_READ16(IMR);
1638 }
1639 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1640 }
1641
1642 static int
1643 bsd_ring_flush(struct drm_i915_gem_request *req,
1644 u32 invalidate_domains,
1645 u32 flush_domains)
1646 {
1647 struct intel_engine_cs *ring = req->ring;
1648 int ret;
1649
1650 ret = intel_ring_begin(req, 2);
1651 if (ret)
1652 return ret;
1653
1654 intel_ring_emit(ring, MI_FLUSH);
1655 intel_ring_emit(ring, MI_NOOP);
1656 intel_ring_advance(ring);
1657 return 0;
1658 }
1659
1660 static int
1661 i9xx_add_request(struct drm_i915_gem_request *req)
1662 {
1663 struct intel_engine_cs *ring = req->ring;
1664 int ret;
1665
1666 ret = intel_ring_begin(req, 4);
1667 if (ret)
1668 return ret;
1669
1670 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1671 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1672 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1673 intel_ring_emit(ring, MI_USER_INTERRUPT);
1674 __intel_ring_advance(ring);
1675
1676 return 0;
1677 }
1678
1679 static bool
1680 gen6_ring_get_irq(struct intel_engine_cs *ring)
1681 {
1682 struct drm_device *dev = ring->dev;
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684 unsigned long flags;
1685
1686 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1687 return false;
1688
1689 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1690 if (ring->irq_refcount++ == 0) {
1691 if (HAS_L3_DPF(dev) && ring->id == RCS)
1692 I915_WRITE_IMR(ring,
1693 ~(ring->irq_enable_mask |
1694 GT_PARITY_ERROR(dev)));
1695 else
1696 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1697 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1698 }
1699 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1700
1701 return true;
1702 }
1703
1704 static void
1705 gen6_ring_put_irq(struct intel_engine_cs *ring)
1706 {
1707 struct drm_device *dev = ring->dev;
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 unsigned long flags;
1710
1711 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1712 if (--ring->irq_refcount == 0) {
1713 if (HAS_L3_DPF(dev) && ring->id == RCS)
1714 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1715 else
1716 I915_WRITE_IMR(ring, ~0);
1717 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1718 }
1719 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1720 }
1721
1722 static bool
1723 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1724 {
1725 struct drm_device *dev = ring->dev;
1726 struct drm_i915_private *dev_priv = dev->dev_private;
1727 unsigned long flags;
1728
1729 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1730 return false;
1731
1732 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1733 if (ring->irq_refcount++ == 0) {
1734 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1735 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1736 }
1737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1738
1739 return true;
1740 }
1741
1742 static void
1743 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1744 {
1745 struct drm_device *dev = ring->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747 unsigned long flags;
1748
1749 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1750 if (--ring->irq_refcount == 0) {
1751 I915_WRITE_IMR(ring, ~0);
1752 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1753 }
1754 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1755 }
1756
1757 static bool
1758 gen8_ring_get_irq(struct intel_engine_cs *ring)
1759 {
1760 struct drm_device *dev = ring->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 unsigned long flags;
1763
1764 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1765 return false;
1766
1767 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1768 if (ring->irq_refcount++ == 0) {
1769 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1770 I915_WRITE_IMR(ring,
1771 ~(ring->irq_enable_mask |
1772 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1773 } else {
1774 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1775 }
1776 POSTING_READ(RING_IMR(ring->mmio_base));
1777 }
1778 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1779
1780 return true;
1781 }
1782
1783 static void
1784 gen8_ring_put_irq(struct intel_engine_cs *ring)
1785 {
1786 struct drm_device *dev = ring->dev;
1787 struct drm_i915_private *dev_priv = dev->dev_private;
1788 unsigned long flags;
1789
1790 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1791 if (--ring->irq_refcount == 0) {
1792 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1793 I915_WRITE_IMR(ring,
1794 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1795 } else {
1796 I915_WRITE_IMR(ring, ~0);
1797 }
1798 POSTING_READ(RING_IMR(ring->mmio_base));
1799 }
1800 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1801 }
1802
1803 static int
1804 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1805 u64 offset, u32 length,
1806 unsigned dispatch_flags)
1807 {
1808 struct intel_engine_cs *ring = req->ring;
1809 int ret;
1810
1811 ret = intel_ring_begin(req, 2);
1812 if (ret)
1813 return ret;
1814
1815 intel_ring_emit(ring,
1816 MI_BATCH_BUFFER_START |
1817 MI_BATCH_GTT |
1818 (dispatch_flags & I915_DISPATCH_SECURE ?
1819 0 : MI_BATCH_NON_SECURE_I965));
1820 intel_ring_emit(ring, offset);
1821 intel_ring_advance(ring);
1822
1823 return 0;
1824 }
1825
1826 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1827 #define I830_BATCH_LIMIT (256*1024)
1828 #define I830_TLB_ENTRIES (2)
1829 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1830 static int
1831 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1832 u64 offset, u32 len,
1833 unsigned dispatch_flags)
1834 {
1835 struct intel_engine_cs *ring = req->ring;
1836 u32 cs_offset = ring->scratch.gtt_offset;
1837 int ret;
1838
1839 ret = intel_ring_begin(req, 6);
1840 if (ret)
1841 return ret;
1842
1843 /* Evict the invalid PTE TLBs */
1844 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1845 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1846 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1847 intel_ring_emit(ring, cs_offset);
1848 intel_ring_emit(ring, 0xdeadbeef);
1849 intel_ring_emit(ring, MI_NOOP);
1850 intel_ring_advance(ring);
1851
1852 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1853 if (len > I830_BATCH_LIMIT)
1854 return -ENOSPC;
1855
1856 ret = intel_ring_begin(req, 6 + 2);
1857 if (ret)
1858 return ret;
1859
1860 /* Blit the batch (which has now all relocs applied) to the
1861 * stable batch scratch bo area (so that the CS never
1862 * stumbles over its tlb invalidation bug) ...
1863 */
1864 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1865 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1866 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1867 intel_ring_emit(ring, cs_offset);
1868 intel_ring_emit(ring, 4096);
1869 intel_ring_emit(ring, offset);
1870
1871 intel_ring_emit(ring, MI_FLUSH);
1872 intel_ring_emit(ring, MI_NOOP);
1873 intel_ring_advance(ring);
1874
1875 /* ... and execute it. */
1876 offset = cs_offset;
1877 }
1878
1879 ret = intel_ring_begin(req, 4);
1880 if (ret)
1881 return ret;
1882
1883 intel_ring_emit(ring, MI_BATCH_BUFFER);
1884 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1885 0 : MI_BATCH_NON_SECURE));
1886 intel_ring_emit(ring, offset + len - 8);
1887 intel_ring_emit(ring, MI_NOOP);
1888 intel_ring_advance(ring);
1889
1890 return 0;
1891 }
1892
1893 static int
1894 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1895 u64 offset, u32 len,
1896 unsigned dispatch_flags)
1897 {
1898 struct intel_engine_cs *ring = req->ring;
1899 int ret;
1900
1901 ret = intel_ring_begin(req, 2);
1902 if (ret)
1903 return ret;
1904
1905 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1906 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1907 0 : MI_BATCH_NON_SECURE));
1908 intel_ring_advance(ring);
1909
1910 return 0;
1911 }
1912
1913 static void cleanup_status_page(struct intel_engine_cs *ring)
1914 {
1915 struct drm_i915_gem_object *obj;
1916
1917 obj = ring->status_page.obj;
1918 if (obj == NULL)
1919 return;
1920
1921 kunmap(sg_page(obj->pages->sgl));
1922 i915_gem_object_ggtt_unpin(obj);
1923 drm_gem_object_unreference(&obj->base);
1924 ring->status_page.obj = NULL;
1925 }
1926
1927 static int init_status_page(struct intel_engine_cs *ring)
1928 {
1929 struct drm_i915_gem_object *obj;
1930
1931 if ((obj = ring->status_page.obj) == NULL) {
1932 unsigned flags;
1933 int ret;
1934
1935 obj = i915_gem_alloc_object(ring->dev, 4096);
1936 if (obj == NULL) {
1937 DRM_ERROR("Failed to allocate status page\n");
1938 return -ENOMEM;
1939 }
1940
1941 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1942 if (ret)
1943 goto err_unref;
1944
1945 flags = 0;
1946 if (!HAS_LLC(ring->dev))
1947 /* On g33, we cannot place HWS above 256MiB, so
1948 * restrict its pinning to the low mappable arena.
1949 * Though this restriction is not documented for
1950 * gen4, gen5, or byt, they also behave similarly
1951 * and hang if the HWS is placed at the top of the
1952 * GTT. To generalise, it appears that all !llc
1953 * platforms have issues with us placing the HWS
1954 * above the mappable region (even though we never
1955 * actualy map it).
1956 */
1957 flags |= PIN_MAPPABLE;
1958 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1959 if (ret) {
1960 err_unref:
1961 drm_gem_object_unreference(&obj->base);
1962 return ret;
1963 }
1964
1965 ring->status_page.obj = obj;
1966 }
1967
1968 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1969 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1970 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1971
1972 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1973 ring->name, ring->status_page.gfx_addr);
1974
1975 return 0;
1976 }
1977
1978 static int init_phys_status_page(struct intel_engine_cs *ring)
1979 {
1980 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1981
1982 if (!dev_priv->status_page_dmah) {
1983 dev_priv->status_page_dmah =
1984 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1985 if (!dev_priv->status_page_dmah)
1986 return -ENOMEM;
1987 }
1988
1989 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1990 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1991
1992 return 0;
1993 }
1994
1995 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1996 {
1997 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
1998 vunmap(ringbuf->virtual_start);
1999 else
2000 iounmap(ringbuf->virtual_start);
2001 ringbuf->virtual_start = NULL;
2002 i915_gem_object_ggtt_unpin(ringbuf->obj);
2003 }
2004
2005 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2006 {
2007 struct sg_page_iter sg_iter;
2008 struct page **pages;
2009 void *addr;
2010 int i;
2011
2012 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2013 if (pages == NULL)
2014 return NULL;
2015
2016 i = 0;
2017 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2018 pages[i++] = sg_page_iter_page(&sg_iter);
2019
2020 addr = vmap(pages, i, 0, PAGE_KERNEL);
2021 drm_free_large(pages);
2022
2023 return addr;
2024 }
2025
2026 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2027 struct intel_ringbuffer *ringbuf)
2028 {
2029 struct drm_i915_private *dev_priv = to_i915(dev);
2030 struct drm_i915_gem_object *obj = ringbuf->obj;
2031 int ret;
2032
2033 if (HAS_LLC(dev_priv) && !obj->stolen) {
2034 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2035 if (ret)
2036 return ret;
2037
2038 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2039 if (ret) {
2040 i915_gem_object_ggtt_unpin(obj);
2041 return ret;
2042 }
2043
2044 ringbuf->virtual_start = vmap_obj(obj);
2045 if (ringbuf->virtual_start == NULL) {
2046 i915_gem_object_ggtt_unpin(obj);
2047 return -ENOMEM;
2048 }
2049 } else {
2050 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2051 if (ret)
2052 return ret;
2053
2054 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2055 if (ret) {
2056 i915_gem_object_ggtt_unpin(obj);
2057 return ret;
2058 }
2059
2060 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2061 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2062 if (ringbuf->virtual_start == NULL) {
2063 i915_gem_object_ggtt_unpin(obj);
2064 return -EINVAL;
2065 }
2066 }
2067
2068 return 0;
2069 }
2070
2071 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2072 {
2073 drm_gem_object_unreference(&ringbuf->obj->base);
2074 ringbuf->obj = NULL;
2075 }
2076
2077 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2078 struct intel_ringbuffer *ringbuf)
2079 {
2080 struct drm_i915_gem_object *obj;
2081
2082 obj = NULL;
2083 if (!HAS_LLC(dev))
2084 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2085 if (obj == NULL)
2086 obj = i915_gem_alloc_object(dev, ringbuf->size);
2087 if (obj == NULL)
2088 return -ENOMEM;
2089
2090 /* mark ring buffers as read-only from GPU side by default */
2091 obj->gt_ro = 1;
2092
2093 ringbuf->obj = obj;
2094
2095 return 0;
2096 }
2097
2098 struct intel_ringbuffer *
2099 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2100 {
2101 struct intel_ringbuffer *ring;
2102 int ret;
2103
2104 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2105 if (ring == NULL)
2106 return ERR_PTR(-ENOMEM);
2107
2108 ring->ring = engine;
2109
2110 ring->size = size;
2111 /* Workaround an erratum on the i830 which causes a hang if
2112 * the TAIL pointer points to within the last 2 cachelines
2113 * of the buffer.
2114 */
2115 ring->effective_size = size;
2116 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2117 ring->effective_size -= 2 * CACHELINE_BYTES;
2118
2119 ring->last_retired_head = -1;
2120 intel_ring_update_space(ring);
2121
2122 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2123 if (ret) {
2124 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2125 engine->name, ret);
2126 kfree(ring);
2127 return ERR_PTR(ret);
2128 }
2129
2130 return ring;
2131 }
2132
2133 void
2134 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2135 {
2136 intel_destroy_ringbuffer_obj(ring);
2137 kfree(ring);
2138 }
2139
2140 static int intel_init_ring_buffer(struct drm_device *dev,
2141 struct intel_engine_cs *ring)
2142 {
2143 struct intel_ringbuffer *ringbuf;
2144 int ret;
2145
2146 WARN_ON(ring->buffer);
2147
2148 ring->dev = dev;
2149 INIT_LIST_HEAD(&ring->active_list);
2150 INIT_LIST_HEAD(&ring->request_list);
2151 INIT_LIST_HEAD(&ring->execlist_queue);
2152 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2153 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2154
2155 init_waitqueue_head(&ring->irq_queue);
2156
2157 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2158 if (IS_ERR(ringbuf))
2159 return PTR_ERR(ringbuf);
2160 ring->buffer = ringbuf;
2161
2162 if (I915_NEED_GFX_HWS(dev)) {
2163 ret = init_status_page(ring);
2164 if (ret)
2165 goto error;
2166 } else {
2167 BUG_ON(ring->id != RCS);
2168 ret = init_phys_status_page(ring);
2169 if (ret)
2170 goto error;
2171 }
2172
2173 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2174 if (ret) {
2175 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2176 ring->name, ret);
2177 intel_destroy_ringbuffer_obj(ringbuf);
2178 goto error;
2179 }
2180
2181 ret = i915_cmd_parser_init_ring(ring);
2182 if (ret)
2183 goto error;
2184
2185 return 0;
2186
2187 error:
2188 intel_ringbuffer_free(ringbuf);
2189 ring->buffer = NULL;
2190 return ret;
2191 }
2192
2193 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2194 {
2195 struct drm_i915_private *dev_priv;
2196
2197 if (!intel_ring_initialized(ring))
2198 return;
2199
2200 dev_priv = to_i915(ring->dev);
2201
2202 intel_stop_ring_buffer(ring);
2203 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2204
2205 intel_unpin_ringbuffer_obj(ring->buffer);
2206 intel_ringbuffer_free(ring->buffer);
2207 ring->buffer = NULL;
2208
2209 if (ring->cleanup)
2210 ring->cleanup(ring);
2211
2212 cleanup_status_page(ring);
2213
2214 i915_cmd_parser_fini_ring(ring);
2215 i915_gem_batch_pool_fini(&ring->batch_pool);
2216 }
2217
2218 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2219 {
2220 struct intel_ringbuffer *ringbuf = ring->buffer;
2221 struct drm_i915_gem_request *request;
2222 unsigned space;
2223 int ret;
2224
2225 if (intel_ring_space(ringbuf) >= n)
2226 return 0;
2227
2228 /* The whole point of reserving space is to not wait! */
2229 WARN_ON(ringbuf->reserved_in_use);
2230
2231 list_for_each_entry(request, &ring->request_list, list) {
2232 space = __intel_ring_space(request->postfix, ringbuf->tail,
2233 ringbuf->size);
2234 if (space >= n)
2235 break;
2236 }
2237
2238 if (WARN_ON(&request->list == &ring->request_list))
2239 return -ENOSPC;
2240
2241 ret = i915_wait_request(request);
2242 if (ret)
2243 return ret;
2244
2245 ringbuf->space = space;
2246 return 0;
2247 }
2248
2249 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2250 {
2251 uint32_t __iomem *virt;
2252 int rem = ringbuf->size - ringbuf->tail;
2253
2254 virt = ringbuf->virtual_start + ringbuf->tail;
2255 rem /= 4;
2256 while (rem--)
2257 iowrite32(MI_NOOP, virt++);
2258
2259 ringbuf->tail = 0;
2260 intel_ring_update_space(ringbuf);
2261 }
2262
2263 int intel_ring_idle(struct intel_engine_cs *ring)
2264 {
2265 struct drm_i915_gem_request *req;
2266
2267 /* Wait upon the last request to be completed */
2268 if (list_empty(&ring->request_list))
2269 return 0;
2270
2271 req = list_entry(ring->request_list.prev,
2272 struct drm_i915_gem_request,
2273 list);
2274
2275 /* Make sure we do not trigger any retires */
2276 return __i915_wait_request(req,
2277 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2278 to_i915(ring->dev)->mm.interruptible,
2279 NULL, NULL);
2280 }
2281
2282 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2283 {
2284 request->ringbuf = request->ring->buffer;
2285 return 0;
2286 }
2287
2288 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2289 {
2290 /*
2291 * The first call merely notes the reserve request and is common for
2292 * all back ends. The subsequent localised _begin() call actually
2293 * ensures that the reservation is available. Without the begin, if
2294 * the request creator immediately submitted the request without
2295 * adding any commands to it then there might not actually be
2296 * sufficient room for the submission commands.
2297 */
2298 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2299
2300 return intel_ring_begin(request, 0);
2301 }
2302
2303 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2304 {
2305 WARN_ON(ringbuf->reserved_size);
2306 WARN_ON(ringbuf->reserved_in_use);
2307
2308 ringbuf->reserved_size = size;
2309 }
2310
2311 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2312 {
2313 WARN_ON(ringbuf->reserved_in_use);
2314
2315 ringbuf->reserved_size = 0;
2316 ringbuf->reserved_in_use = false;
2317 }
2318
2319 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2320 {
2321 WARN_ON(ringbuf->reserved_in_use);
2322
2323 ringbuf->reserved_in_use = true;
2324 ringbuf->reserved_tail = ringbuf->tail;
2325 }
2326
2327 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2328 {
2329 WARN_ON(!ringbuf->reserved_in_use);
2330 if (ringbuf->tail > ringbuf->reserved_tail) {
2331 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2332 "request reserved size too small: %d vs %d!\n",
2333 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2334 } else {
2335 /*
2336 * The ring was wrapped while the reserved space was in use.
2337 * That means that some unknown amount of the ring tail was
2338 * no-op filled and skipped. Thus simply adding the ring size
2339 * to the tail and doing the above space check will not work.
2340 * Rather than attempt to track how much tail was skipped,
2341 * it is much simpler to say that also skipping the sanity
2342 * check every once in a while is not a big issue.
2343 */
2344 }
2345
2346 ringbuf->reserved_size = 0;
2347 ringbuf->reserved_in_use = false;
2348 }
2349
2350 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2351 {
2352 struct intel_ringbuffer *ringbuf = ring->buffer;
2353 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2354 int remain_actual = ringbuf->size - ringbuf->tail;
2355 int ret, total_bytes, wait_bytes = 0;
2356 bool need_wrap = false;
2357
2358 if (ringbuf->reserved_in_use)
2359 total_bytes = bytes;
2360 else
2361 total_bytes = bytes + ringbuf->reserved_size;
2362
2363 if (unlikely(bytes > remain_usable)) {
2364 /*
2365 * Not enough space for the basic request. So need to flush
2366 * out the remainder and then wait for base + reserved.
2367 */
2368 wait_bytes = remain_actual + total_bytes;
2369 need_wrap = true;
2370 } else {
2371 if (unlikely(total_bytes > remain_usable)) {
2372 /*
2373 * The base request will fit but the reserved space
2374 * falls off the end. So only need to to wait for the
2375 * reserved size after flushing out the remainder.
2376 */
2377 wait_bytes = remain_actual + ringbuf->reserved_size;
2378 need_wrap = true;
2379 } else if (total_bytes > ringbuf->space) {
2380 /* No wrapping required, just waiting. */
2381 wait_bytes = total_bytes;
2382 }
2383 }
2384
2385 if (wait_bytes) {
2386 ret = ring_wait_for_space(ring, wait_bytes);
2387 if (unlikely(ret))
2388 return ret;
2389
2390 if (need_wrap)
2391 __wrap_ring_buffer(ringbuf);
2392 }
2393
2394 return 0;
2395 }
2396
2397 int intel_ring_begin(struct drm_i915_gem_request *req,
2398 int num_dwords)
2399 {
2400 struct intel_engine_cs *ring;
2401 struct drm_i915_private *dev_priv;
2402 int ret;
2403
2404 WARN_ON(req == NULL);
2405 ring = req->ring;
2406 dev_priv = ring->dev->dev_private;
2407
2408 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2409 dev_priv->mm.interruptible);
2410 if (ret)
2411 return ret;
2412
2413 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2414 if (ret)
2415 return ret;
2416
2417 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2418 return 0;
2419 }
2420
2421 /* Align the ring tail to a cacheline boundary */
2422 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2423 {
2424 struct intel_engine_cs *ring = req->ring;
2425 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2426 int ret;
2427
2428 if (num_dwords == 0)
2429 return 0;
2430
2431 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2432 ret = intel_ring_begin(req, num_dwords);
2433 if (ret)
2434 return ret;
2435
2436 while (num_dwords--)
2437 intel_ring_emit(ring, MI_NOOP);
2438
2439 intel_ring_advance(ring);
2440
2441 return 0;
2442 }
2443
2444 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2445 {
2446 struct drm_device *dev = ring->dev;
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448
2449 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2450 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2451 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2452 if (HAS_VEBOX(dev))
2453 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2454 }
2455
2456 ring->set_seqno(ring, seqno);
2457 ring->hangcheck.seqno = seqno;
2458 }
2459
2460 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2461 u32 value)
2462 {
2463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2464
2465 /* Every tail move must follow the sequence below */
2466
2467 /* Disable notification that the ring is IDLE. The GT
2468 * will then assume that it is busy and bring it out of rc6.
2469 */
2470 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2471 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2472
2473 /* Clear the context id. Here be magic! */
2474 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2475
2476 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2477 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2478 GEN6_BSD_SLEEP_INDICATOR) == 0,
2479 50))
2480 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2481
2482 /* Now that the ring is fully powered up, update the tail */
2483 I915_WRITE_TAIL(ring, value);
2484 POSTING_READ(RING_TAIL(ring->mmio_base));
2485
2486 /* Let the ring send IDLE messages to the GT again,
2487 * and so let it sleep to conserve power when idle.
2488 */
2489 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2490 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2491 }
2492
2493 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2494 u32 invalidate, u32 flush)
2495 {
2496 struct intel_engine_cs *ring = req->ring;
2497 uint32_t cmd;
2498 int ret;
2499
2500 ret = intel_ring_begin(req, 4);
2501 if (ret)
2502 return ret;
2503
2504 cmd = MI_FLUSH_DW;
2505 if (INTEL_INFO(ring->dev)->gen >= 8)
2506 cmd += 1;
2507
2508 /* We always require a command barrier so that subsequent
2509 * commands, such as breadcrumb interrupts, are strictly ordered
2510 * wrt the contents of the write cache being flushed to memory
2511 * (and thus being coherent from the CPU).
2512 */
2513 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2514
2515 /*
2516 * Bspec vol 1c.5 - video engine command streamer:
2517 * "If ENABLED, all TLBs will be invalidated once the flush
2518 * operation is complete. This bit is only valid when the
2519 * Post-Sync Operation field is a value of 1h or 3h."
2520 */
2521 if (invalidate & I915_GEM_GPU_DOMAINS)
2522 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2523
2524 intel_ring_emit(ring, cmd);
2525 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2526 if (INTEL_INFO(ring->dev)->gen >= 8) {
2527 intel_ring_emit(ring, 0); /* upper addr */
2528 intel_ring_emit(ring, 0); /* value */
2529 } else {
2530 intel_ring_emit(ring, 0);
2531 intel_ring_emit(ring, MI_NOOP);
2532 }
2533 intel_ring_advance(ring);
2534 return 0;
2535 }
2536
2537 static int
2538 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2539 u64 offset, u32 len,
2540 unsigned dispatch_flags)
2541 {
2542 struct intel_engine_cs *ring = req->ring;
2543 bool ppgtt = USES_PPGTT(ring->dev) &&
2544 !(dispatch_flags & I915_DISPATCH_SECURE);
2545 int ret;
2546
2547 ret = intel_ring_begin(req, 4);
2548 if (ret)
2549 return ret;
2550
2551 /* FIXME(BDW): Address space and security selectors. */
2552 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2553 (dispatch_flags & I915_DISPATCH_RS ?
2554 MI_BATCH_RESOURCE_STREAMER : 0));
2555 intel_ring_emit(ring, lower_32_bits(offset));
2556 intel_ring_emit(ring, upper_32_bits(offset));
2557 intel_ring_emit(ring, MI_NOOP);
2558 intel_ring_advance(ring);
2559
2560 return 0;
2561 }
2562
2563 static int
2564 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2565 u64 offset, u32 len,
2566 unsigned dispatch_flags)
2567 {
2568 struct intel_engine_cs *ring = req->ring;
2569 int ret;
2570
2571 ret = intel_ring_begin(req, 2);
2572 if (ret)
2573 return ret;
2574
2575 intel_ring_emit(ring,
2576 MI_BATCH_BUFFER_START |
2577 (dispatch_flags & I915_DISPATCH_SECURE ?
2578 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2579 (dispatch_flags & I915_DISPATCH_RS ?
2580 MI_BATCH_RESOURCE_STREAMER : 0));
2581 /* bit0-7 is the length on GEN6+ */
2582 intel_ring_emit(ring, offset);
2583 intel_ring_advance(ring);
2584
2585 return 0;
2586 }
2587
2588 static int
2589 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2590 u64 offset, u32 len,
2591 unsigned dispatch_flags)
2592 {
2593 struct intel_engine_cs *ring = req->ring;
2594 int ret;
2595
2596 ret = intel_ring_begin(req, 2);
2597 if (ret)
2598 return ret;
2599
2600 intel_ring_emit(ring,
2601 MI_BATCH_BUFFER_START |
2602 (dispatch_flags & I915_DISPATCH_SECURE ?
2603 0 : MI_BATCH_NON_SECURE_I965));
2604 /* bit0-7 is the length on GEN6+ */
2605 intel_ring_emit(ring, offset);
2606 intel_ring_advance(ring);
2607
2608 return 0;
2609 }
2610
2611 /* Blitter support (SandyBridge+) */
2612
2613 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2614 u32 invalidate, u32 flush)
2615 {
2616 struct intel_engine_cs *ring = req->ring;
2617 struct drm_device *dev = ring->dev;
2618 uint32_t cmd;
2619 int ret;
2620
2621 ret = intel_ring_begin(req, 4);
2622 if (ret)
2623 return ret;
2624
2625 cmd = MI_FLUSH_DW;
2626 if (INTEL_INFO(dev)->gen >= 8)
2627 cmd += 1;
2628
2629 /* We always require a command barrier so that subsequent
2630 * commands, such as breadcrumb interrupts, are strictly ordered
2631 * wrt the contents of the write cache being flushed to memory
2632 * (and thus being coherent from the CPU).
2633 */
2634 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2635
2636 /*
2637 * Bspec vol 1c.3 - blitter engine command streamer:
2638 * "If ENABLED, all TLBs will be invalidated once the flush
2639 * operation is complete. This bit is only valid when the
2640 * Post-Sync Operation field is a value of 1h or 3h."
2641 */
2642 if (invalidate & I915_GEM_DOMAIN_RENDER)
2643 cmd |= MI_INVALIDATE_TLB;
2644 intel_ring_emit(ring, cmd);
2645 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2646 if (INTEL_INFO(dev)->gen >= 8) {
2647 intel_ring_emit(ring, 0); /* upper addr */
2648 intel_ring_emit(ring, 0); /* value */
2649 } else {
2650 intel_ring_emit(ring, 0);
2651 intel_ring_emit(ring, MI_NOOP);
2652 }
2653 intel_ring_advance(ring);
2654
2655 return 0;
2656 }
2657
2658 int intel_init_render_ring_buffer(struct drm_device *dev)
2659 {
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2662 struct drm_i915_gem_object *obj;
2663 int ret;
2664
2665 ring->name = "render ring";
2666 ring->id = RCS;
2667 ring->mmio_base = RENDER_RING_BASE;
2668
2669 if (INTEL_INFO(dev)->gen >= 8) {
2670 if (i915_semaphore_is_enabled(dev)) {
2671 obj = i915_gem_alloc_object(dev, 4096);
2672 if (obj == NULL) {
2673 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2674 i915.semaphores = 0;
2675 } else {
2676 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2677 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2678 if (ret != 0) {
2679 drm_gem_object_unreference(&obj->base);
2680 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2681 i915.semaphores = 0;
2682 } else
2683 dev_priv->semaphore_obj = obj;
2684 }
2685 }
2686
2687 ring->init_context = intel_rcs_ctx_init;
2688 ring->add_request = gen6_add_request;
2689 ring->flush = gen8_render_ring_flush;
2690 ring->irq_get = gen8_ring_get_irq;
2691 ring->irq_put = gen8_ring_put_irq;
2692 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2693 ring->get_seqno = gen6_ring_get_seqno;
2694 ring->set_seqno = ring_set_seqno;
2695 if (i915_semaphore_is_enabled(dev)) {
2696 WARN_ON(!dev_priv->semaphore_obj);
2697 ring->semaphore.sync_to = gen8_ring_sync;
2698 ring->semaphore.signal = gen8_rcs_signal;
2699 GEN8_RING_SEMAPHORE_INIT;
2700 }
2701 } else if (INTEL_INFO(dev)->gen >= 6) {
2702 ring->init_context = intel_rcs_ctx_init;
2703 ring->add_request = gen6_add_request;
2704 ring->flush = gen7_render_ring_flush;
2705 if (INTEL_INFO(dev)->gen == 6)
2706 ring->flush = gen6_render_ring_flush;
2707 ring->irq_get = gen6_ring_get_irq;
2708 ring->irq_put = gen6_ring_put_irq;
2709 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2710 ring->get_seqno = gen6_ring_get_seqno;
2711 ring->set_seqno = ring_set_seqno;
2712 if (i915_semaphore_is_enabled(dev)) {
2713 ring->semaphore.sync_to = gen6_ring_sync;
2714 ring->semaphore.signal = gen6_signal;
2715 /*
2716 * The current semaphore is only applied on pre-gen8
2717 * platform. And there is no VCS2 ring on the pre-gen8
2718 * platform. So the semaphore between RCS and VCS2 is
2719 * initialized as INVALID. Gen8 will initialize the
2720 * sema between VCS2 and RCS later.
2721 */
2722 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2723 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2724 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2725 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2726 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2727 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2728 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2729 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2730 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2731 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2732 }
2733 } else if (IS_GEN5(dev)) {
2734 ring->add_request = pc_render_add_request;
2735 ring->flush = gen4_render_ring_flush;
2736 ring->get_seqno = pc_render_get_seqno;
2737 ring->set_seqno = pc_render_set_seqno;
2738 ring->irq_get = gen5_ring_get_irq;
2739 ring->irq_put = gen5_ring_put_irq;
2740 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2741 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2742 } else {
2743 ring->add_request = i9xx_add_request;
2744 if (INTEL_INFO(dev)->gen < 4)
2745 ring->flush = gen2_render_ring_flush;
2746 else
2747 ring->flush = gen4_render_ring_flush;
2748 ring->get_seqno = ring_get_seqno;
2749 ring->set_seqno = ring_set_seqno;
2750 if (IS_GEN2(dev)) {
2751 ring->irq_get = i8xx_ring_get_irq;
2752 ring->irq_put = i8xx_ring_put_irq;
2753 } else {
2754 ring->irq_get = i9xx_ring_get_irq;
2755 ring->irq_put = i9xx_ring_put_irq;
2756 }
2757 ring->irq_enable_mask = I915_USER_INTERRUPT;
2758 }
2759 ring->write_tail = ring_write_tail;
2760
2761 if (IS_HASWELL(dev))
2762 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2763 else if (IS_GEN8(dev))
2764 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2765 else if (INTEL_INFO(dev)->gen >= 6)
2766 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2767 else if (INTEL_INFO(dev)->gen >= 4)
2768 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2769 else if (IS_I830(dev) || IS_845G(dev))
2770 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2771 else
2772 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2773 ring->init_hw = init_render_ring;
2774 ring->cleanup = render_ring_cleanup;
2775
2776 /* Workaround batchbuffer to combat CS tlb bug. */
2777 if (HAS_BROKEN_CS_TLB(dev)) {
2778 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2779 if (obj == NULL) {
2780 DRM_ERROR("Failed to allocate batch bo\n");
2781 return -ENOMEM;
2782 }
2783
2784 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2785 if (ret != 0) {
2786 drm_gem_object_unreference(&obj->base);
2787 DRM_ERROR("Failed to ping batch bo\n");
2788 return ret;
2789 }
2790
2791 ring->scratch.obj = obj;
2792 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2793 }
2794
2795 ret = intel_init_ring_buffer(dev, ring);
2796 if (ret)
2797 return ret;
2798
2799 if (INTEL_INFO(dev)->gen >= 5) {
2800 ret = intel_init_pipe_control(ring);
2801 if (ret)
2802 return ret;
2803 }
2804
2805 return 0;
2806 }
2807
2808 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2809 {
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2812
2813 ring->name = "bsd ring";
2814 ring->id = VCS;
2815
2816 ring->write_tail = ring_write_tail;
2817 if (INTEL_INFO(dev)->gen >= 6) {
2818 ring->mmio_base = GEN6_BSD_RING_BASE;
2819 /* gen6 bsd needs a special wa for tail updates */
2820 if (IS_GEN6(dev))
2821 ring->write_tail = gen6_bsd_ring_write_tail;
2822 ring->flush = gen6_bsd_ring_flush;
2823 ring->add_request = gen6_add_request;
2824 ring->get_seqno = gen6_ring_get_seqno;
2825 ring->set_seqno = ring_set_seqno;
2826 if (INTEL_INFO(dev)->gen >= 8) {
2827 ring->irq_enable_mask =
2828 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2829 ring->irq_get = gen8_ring_get_irq;
2830 ring->irq_put = gen8_ring_put_irq;
2831 ring->dispatch_execbuffer =
2832 gen8_ring_dispatch_execbuffer;
2833 if (i915_semaphore_is_enabled(dev)) {
2834 ring->semaphore.sync_to = gen8_ring_sync;
2835 ring->semaphore.signal = gen8_xcs_signal;
2836 GEN8_RING_SEMAPHORE_INIT;
2837 }
2838 } else {
2839 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2840 ring->irq_get = gen6_ring_get_irq;
2841 ring->irq_put = gen6_ring_put_irq;
2842 ring->dispatch_execbuffer =
2843 gen6_ring_dispatch_execbuffer;
2844 if (i915_semaphore_is_enabled(dev)) {
2845 ring->semaphore.sync_to = gen6_ring_sync;
2846 ring->semaphore.signal = gen6_signal;
2847 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2848 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2849 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2850 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2851 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2852 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2853 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2854 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2855 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2856 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2857 }
2858 }
2859 } else {
2860 ring->mmio_base = BSD_RING_BASE;
2861 ring->flush = bsd_ring_flush;
2862 ring->add_request = i9xx_add_request;
2863 ring->get_seqno = ring_get_seqno;
2864 ring->set_seqno = ring_set_seqno;
2865 if (IS_GEN5(dev)) {
2866 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2867 ring->irq_get = gen5_ring_get_irq;
2868 ring->irq_put = gen5_ring_put_irq;
2869 } else {
2870 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2871 ring->irq_get = i9xx_ring_get_irq;
2872 ring->irq_put = i9xx_ring_put_irq;
2873 }
2874 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2875 }
2876 ring->init_hw = init_ring_common;
2877
2878 return intel_init_ring_buffer(dev, ring);
2879 }
2880
2881 /**
2882 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2883 */
2884 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2885 {
2886 struct drm_i915_private *dev_priv = dev->dev_private;
2887 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2888
2889 ring->name = "bsd2 ring";
2890 ring->id = VCS2;
2891
2892 ring->write_tail = ring_write_tail;
2893 ring->mmio_base = GEN8_BSD2_RING_BASE;
2894 ring->flush = gen6_bsd_ring_flush;
2895 ring->add_request = gen6_add_request;
2896 ring->get_seqno = gen6_ring_get_seqno;
2897 ring->set_seqno = ring_set_seqno;
2898 ring->irq_enable_mask =
2899 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2900 ring->irq_get = gen8_ring_get_irq;
2901 ring->irq_put = gen8_ring_put_irq;
2902 ring->dispatch_execbuffer =
2903 gen8_ring_dispatch_execbuffer;
2904 if (i915_semaphore_is_enabled(dev)) {
2905 ring->semaphore.sync_to = gen8_ring_sync;
2906 ring->semaphore.signal = gen8_xcs_signal;
2907 GEN8_RING_SEMAPHORE_INIT;
2908 }
2909 ring->init_hw = init_ring_common;
2910
2911 return intel_init_ring_buffer(dev, ring);
2912 }
2913
2914 int intel_init_blt_ring_buffer(struct drm_device *dev)
2915 {
2916 struct drm_i915_private *dev_priv = dev->dev_private;
2917 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2918
2919 ring->name = "blitter ring";
2920 ring->id = BCS;
2921
2922 ring->mmio_base = BLT_RING_BASE;
2923 ring->write_tail = ring_write_tail;
2924 ring->flush = gen6_ring_flush;
2925 ring->add_request = gen6_add_request;
2926 ring->get_seqno = gen6_ring_get_seqno;
2927 ring->set_seqno = ring_set_seqno;
2928 if (INTEL_INFO(dev)->gen >= 8) {
2929 ring->irq_enable_mask =
2930 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2931 ring->irq_get = gen8_ring_get_irq;
2932 ring->irq_put = gen8_ring_put_irq;
2933 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2934 if (i915_semaphore_is_enabled(dev)) {
2935 ring->semaphore.sync_to = gen8_ring_sync;
2936 ring->semaphore.signal = gen8_xcs_signal;
2937 GEN8_RING_SEMAPHORE_INIT;
2938 }
2939 } else {
2940 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2941 ring->irq_get = gen6_ring_get_irq;
2942 ring->irq_put = gen6_ring_put_irq;
2943 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2944 if (i915_semaphore_is_enabled(dev)) {
2945 ring->semaphore.signal = gen6_signal;
2946 ring->semaphore.sync_to = gen6_ring_sync;
2947 /*
2948 * The current semaphore is only applied on pre-gen8
2949 * platform. And there is no VCS2 ring on the pre-gen8
2950 * platform. So the semaphore between BCS and VCS2 is
2951 * initialized as INVALID. Gen8 will initialize the
2952 * sema between BCS and VCS2 later.
2953 */
2954 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2955 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2956 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2957 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2958 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2959 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2960 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2961 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2962 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2963 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2964 }
2965 }
2966 ring->init_hw = init_ring_common;
2967
2968 return intel_init_ring_buffer(dev, ring);
2969 }
2970
2971 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2972 {
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2974 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2975
2976 ring->name = "video enhancement ring";
2977 ring->id = VECS;
2978
2979 ring->mmio_base = VEBOX_RING_BASE;
2980 ring->write_tail = ring_write_tail;
2981 ring->flush = gen6_ring_flush;
2982 ring->add_request = gen6_add_request;
2983 ring->get_seqno = gen6_ring_get_seqno;
2984 ring->set_seqno = ring_set_seqno;
2985
2986 if (INTEL_INFO(dev)->gen >= 8) {
2987 ring->irq_enable_mask =
2988 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2989 ring->irq_get = gen8_ring_get_irq;
2990 ring->irq_put = gen8_ring_put_irq;
2991 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2992 if (i915_semaphore_is_enabled(dev)) {
2993 ring->semaphore.sync_to = gen8_ring_sync;
2994 ring->semaphore.signal = gen8_xcs_signal;
2995 GEN8_RING_SEMAPHORE_INIT;
2996 }
2997 } else {
2998 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2999 ring->irq_get = hsw_vebox_get_irq;
3000 ring->irq_put = hsw_vebox_put_irq;
3001 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3002 if (i915_semaphore_is_enabled(dev)) {
3003 ring->semaphore.sync_to = gen6_ring_sync;
3004 ring->semaphore.signal = gen6_signal;
3005 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3006 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3007 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3008 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3009 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3010 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3011 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3012 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3013 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3014 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3015 }
3016 }
3017 ring->init_hw = init_ring_common;
3018
3019 return intel_init_ring_buffer(dev, ring);
3020 }
3021
3022 int
3023 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3024 {
3025 struct intel_engine_cs *ring = req->ring;
3026 int ret;
3027
3028 if (!ring->gpu_caches_dirty)
3029 return 0;
3030
3031 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3032 if (ret)
3033 return ret;
3034
3035 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3036
3037 ring->gpu_caches_dirty = false;
3038 return 0;
3039 }
3040
3041 int
3042 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3043 {
3044 struct intel_engine_cs *ring = req->ring;
3045 uint32_t flush_domains;
3046 int ret;
3047
3048 flush_domains = 0;
3049 if (ring->gpu_caches_dirty)
3050 flush_domains = I915_GEM_GPU_DOMAINS;
3051
3052 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3053 if (ret)
3054 return ret;
3055
3056 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3057
3058 ring->gpu_caches_dirty = false;
3059 return 0;
3060 }
3061
3062 void
3063 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3064 {
3065 int ret;
3066
3067 if (!intel_ring_initialized(ring))
3068 return;
3069
3070 ret = intel_ring_idle(ring);
3071 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3072 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3073 ring->name, ret);
3074
3075 stop_ring(ring);
3076 }
Linux kernel - Deliverables
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