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Merge branch 'topic/drm-vblank-rework' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
37 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
38 * to give some inclination as to some of the magic values used in the various
39 * workarounds!
40 */
41 #define CACHELINE_BYTES 64
42
43 static inline int __ring_space(int head, int tail, int size)
44 {
45 int space = head - (tail + I915_RING_FREE_SPACE);
46 if (space < 0)
47 space += size;
48 return space;
49 }
50
51 static inline int ring_space(struct intel_ring_buffer *ring)
52 {
53 return __ring_space(ring->head & HEAD_ADDR, ring->tail, ring->size);
54 }
55
56 static bool intel_ring_stopped(struct intel_ring_buffer *ring)
57 {
58 struct drm_i915_private *dev_priv = ring->dev->dev_private;
59 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
60 }
61
62 void __intel_ring_advance(struct intel_ring_buffer *ring)
63 {
64 ring->tail &= ring->size - 1;
65 if (intel_ring_stopped(ring))
66 return;
67 ring->write_tail(ring, ring->tail);
68 }
69
70 static int
71 gen2_render_ring_flush(struct intel_ring_buffer *ring,
72 u32 invalidate_domains,
73 u32 flush_domains)
74 {
75 u32 cmd;
76 int ret;
77
78 cmd = MI_FLUSH;
79 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
80 cmd |= MI_NO_WRITE_FLUSH;
81
82 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
83 cmd |= MI_READ_FLUSH;
84
85 ret = intel_ring_begin(ring, 2);
86 if (ret)
87 return ret;
88
89 intel_ring_emit(ring, cmd);
90 intel_ring_emit(ring, MI_NOOP);
91 intel_ring_advance(ring);
92
93 return 0;
94 }
95
96 static int
97 gen4_render_ring_flush(struct intel_ring_buffer *ring,
98 u32 invalidate_domains,
99 u32 flush_domains)
100 {
101 struct drm_device *dev = ring->dev;
102 u32 cmd;
103 int ret;
104
105 /*
106 * read/write caches:
107 *
108 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
109 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
110 * also flushed at 2d versus 3d pipeline switches.
111 *
112 * read-only caches:
113 *
114 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
115 * MI_READ_FLUSH is set, and is always flushed on 965.
116 *
117 * I915_GEM_DOMAIN_COMMAND may not exist?
118 *
119 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
120 * invalidated when MI_EXE_FLUSH is set.
121 *
122 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
123 * invalidated with every MI_FLUSH.
124 *
125 * TLBs:
126 *
127 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
128 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
129 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
130 * are flushed at any MI_FLUSH.
131 */
132
133 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
134 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
135 cmd &= ~MI_NO_WRITE_FLUSH;
136 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
137 cmd |= MI_EXE_FLUSH;
138
139 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
140 (IS_G4X(dev) || IS_GEN5(dev)))
141 cmd |= MI_INVALIDATE_ISP;
142
143 ret = intel_ring_begin(ring, 2);
144 if (ret)
145 return ret;
146
147 intel_ring_emit(ring, cmd);
148 intel_ring_emit(ring, MI_NOOP);
149 intel_ring_advance(ring);
150
151 return 0;
152 }
153
154 /**
155 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
156 * implementing two workarounds on gen6. From section 1.4.7.1
157 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
158 *
159 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
160 * produced by non-pipelined state commands), software needs to first
161 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
162 * 0.
163 *
164 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
165 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
166 *
167 * And the workaround for these two requires this workaround first:
168 *
169 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
170 * BEFORE the pipe-control with a post-sync op and no write-cache
171 * flushes.
172 *
173 * And this last workaround is tricky because of the requirements on
174 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
175 * volume 2 part 1:
176 *
177 * "1 of the following must also be set:
178 * - Render Target Cache Flush Enable ([12] of DW1)
179 * - Depth Cache Flush Enable ([0] of DW1)
180 * - Stall at Pixel Scoreboard ([1] of DW1)
181 * - Depth Stall ([13] of DW1)
182 * - Post-Sync Operation ([13] of DW1)
183 * - Notify Enable ([8] of DW1)"
184 *
185 * The cache flushes require the workaround flush that triggered this
186 * one, so we can't use it. Depth stall would trigger the same.
187 * Post-sync nonzero is what triggered this second workaround, so we
188 * can't use that one either. Notify enable is IRQs, which aren't
189 * really our business. That leaves only stall at scoreboard.
190 */
191 static int
192 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
193 {
194 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
195 int ret;
196
197
198 ret = intel_ring_begin(ring, 6);
199 if (ret)
200 return ret;
201
202 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
203 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
204 PIPE_CONTROL_STALL_AT_SCOREBOARD);
205 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
206 intel_ring_emit(ring, 0); /* low dword */
207 intel_ring_emit(ring, 0); /* high dword */
208 intel_ring_emit(ring, MI_NOOP);
209 intel_ring_advance(ring);
210
211 ret = intel_ring_begin(ring, 6);
212 if (ret)
213 return ret;
214
215 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
216 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0);
219 intel_ring_emit(ring, 0);
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 return 0;
224 }
225
226 static int
227 gen6_render_ring_flush(struct intel_ring_buffer *ring,
228 u32 invalidate_domains, u32 flush_domains)
229 {
230 u32 flags = 0;
231 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
232 int ret;
233
234 /* Force SNB workarounds for PIPE_CONTROL flushes */
235 ret = intel_emit_post_sync_nonzero_flush(ring);
236 if (ret)
237 return ret;
238
239 /* Just flush everything. Experiments have shown that reducing the
240 * number of bits based on the write domains has little performance
241 * impact.
242 */
243 if (flush_domains) {
244 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
245 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
246 /*
247 * Ensure that any following seqno writes only happen
248 * when the render cache is indeed flushed.
249 */
250 flags |= PIPE_CONTROL_CS_STALL;
251 }
252 if (invalidate_domains) {
253 flags |= PIPE_CONTROL_TLB_INVALIDATE;
254 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
255 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
256 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
257 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
258 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
259 /*
260 * TLB invalidate requires a post-sync write.
261 */
262 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
263 }
264
265 ret = intel_ring_begin(ring, 4);
266 if (ret)
267 return ret;
268
269 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
270 intel_ring_emit(ring, flags);
271 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
272 intel_ring_emit(ring, 0);
273 intel_ring_advance(ring);
274
275 return 0;
276 }
277
278 static int
279 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
280 {
281 int ret;
282
283 ret = intel_ring_begin(ring, 4);
284 if (ret)
285 return ret;
286
287 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
288 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
289 PIPE_CONTROL_STALL_AT_SCOREBOARD);
290 intel_ring_emit(ring, 0);
291 intel_ring_emit(ring, 0);
292 intel_ring_advance(ring);
293
294 return 0;
295 }
296
297 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
298 {
299 int ret;
300
301 if (!ring->fbc_dirty)
302 return 0;
303
304 ret = intel_ring_begin(ring, 6);
305 if (ret)
306 return ret;
307 /* WaFbcNukeOn3DBlt:ivb/hsw */
308 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
309 intel_ring_emit(ring, MSG_FBC_REND_STATE);
310 intel_ring_emit(ring, value);
311 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
312 intel_ring_emit(ring, MSG_FBC_REND_STATE);
313 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
314 intel_ring_advance(ring);
315
316 ring->fbc_dirty = false;
317 return 0;
318 }
319
320 static int
321 gen7_render_ring_flush(struct intel_ring_buffer *ring,
322 u32 invalidate_domains, u32 flush_domains)
323 {
324 u32 flags = 0;
325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
326 int ret;
327
328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
345 }
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
353 /*
354 * TLB invalidate requires a post-sync write.
355 */
356 flags |= PIPE_CONTROL_QW_WRITE;
357 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
358
359 /* Workaround: we must issue a pipe_control with CS-stall bit
360 * set before a pipe_control command that has the state cache
361 * invalidate bit set. */
362 gen7_render_ring_cs_stall_wa(ring);
363 }
364
365 ret = intel_ring_begin(ring, 4);
366 if (ret)
367 return ret;
368
369 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
370 intel_ring_emit(ring, flags);
371 intel_ring_emit(ring, scratch_addr);
372 intel_ring_emit(ring, 0);
373 intel_ring_advance(ring);
374
375 if (!invalidate_domains && flush_domains)
376 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
377
378 return 0;
379 }
380
381 static int
382 gen8_render_ring_flush(struct intel_ring_buffer *ring,
383 u32 invalidate_domains, u32 flush_domains)
384 {
385 u32 flags = 0;
386 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
387 int ret;
388
389 flags |= PIPE_CONTROL_CS_STALL;
390
391 if (flush_domains) {
392 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
393 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
394 }
395 if (invalidate_domains) {
396 flags |= PIPE_CONTROL_TLB_INVALIDATE;
397 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
398 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
399 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
400 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
401 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
402 flags |= PIPE_CONTROL_QW_WRITE;
403 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
404 }
405
406 ret = intel_ring_begin(ring, 6);
407 if (ret)
408 return ret;
409
410 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
411 intel_ring_emit(ring, flags);
412 intel_ring_emit(ring, scratch_addr);
413 intel_ring_emit(ring, 0);
414 intel_ring_emit(ring, 0);
415 intel_ring_emit(ring, 0);
416 intel_ring_advance(ring);
417
418 return 0;
419
420 }
421
422 static void ring_write_tail(struct intel_ring_buffer *ring,
423 u32 value)
424 {
425 struct drm_i915_private *dev_priv = ring->dev->dev_private;
426 I915_WRITE_TAIL(ring, value);
427 }
428
429 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
430 {
431 struct drm_i915_private *dev_priv = ring->dev->dev_private;
432 u64 acthd;
433
434 if (INTEL_INFO(ring->dev)->gen >= 8)
435 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
436 RING_ACTHD_UDW(ring->mmio_base));
437 else if (INTEL_INFO(ring->dev)->gen >= 4)
438 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
439 else
440 acthd = I915_READ(ACTHD);
441
442 return acthd;
443 }
444
445 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
446 {
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
448 u32 addr;
449
450 addr = dev_priv->status_page_dmah->busaddr;
451 if (INTEL_INFO(ring->dev)->gen >= 4)
452 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
453 I915_WRITE(HWS_PGA, addr);
454 }
455
456 static bool stop_ring(struct intel_ring_buffer *ring)
457 {
458 struct drm_i915_private *dev_priv = to_i915(ring->dev);
459
460 if (!IS_GEN2(ring->dev)) {
461 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
462 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
463 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
464 return false;
465 }
466 }
467
468 I915_WRITE_CTL(ring, 0);
469 I915_WRITE_HEAD(ring, 0);
470 ring->write_tail(ring, 0);
471
472 if (!IS_GEN2(ring->dev)) {
473 (void)I915_READ_CTL(ring);
474 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
475 }
476
477 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
478 }
479
480 static int init_ring_common(struct intel_ring_buffer *ring)
481 {
482 struct drm_device *dev = ring->dev;
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_i915_gem_object *obj = ring->obj;
485 int ret = 0;
486
487 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
488
489 if (!stop_ring(ring)) {
490 /* G45 ring initialization often fails to reset head to zero */
491 DRM_DEBUG_KMS("%s head not reset to zero "
492 "ctl %08x head %08x tail %08x start %08x\n",
493 ring->name,
494 I915_READ_CTL(ring),
495 I915_READ_HEAD(ring),
496 I915_READ_TAIL(ring),
497 I915_READ_START(ring));
498
499 if (!stop_ring(ring)) {
500 DRM_ERROR("failed to set %s head to zero "
501 "ctl %08x head %08x tail %08x start %08x\n",
502 ring->name,
503 I915_READ_CTL(ring),
504 I915_READ_HEAD(ring),
505 I915_READ_TAIL(ring),
506 I915_READ_START(ring));
507 ret = -EIO;
508 goto out;
509 }
510 }
511
512 if (I915_NEED_GFX_HWS(dev))
513 intel_ring_setup_status_page(ring);
514 else
515 ring_setup_phys_status_page(ring);
516
517 /* Initialize the ring. This must happen _after_ we've cleared the ring
518 * registers with the above sequence (the readback of the HEAD registers
519 * also enforces ordering), otherwise the hw might lose the new ring
520 * register values. */
521 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
522 I915_WRITE_CTL(ring,
523 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
524 | RING_VALID);
525
526 /* If the head is still not zero, the ring is dead */
527 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
528 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
529 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
530 DRM_ERROR("%s initialization failed "
531 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
532 ring->name,
533 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
534 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
535 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
536 ret = -EIO;
537 goto out;
538 }
539
540 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
541 i915_kernel_lost_context(ring->dev);
542 else {
543 ring->head = I915_READ_HEAD(ring);
544 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
545 ring->space = ring_space(ring);
546 ring->last_retired_head = -1;
547 }
548
549 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
550
551 out:
552 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
553
554 return ret;
555 }
556
557 static int
558 init_pipe_control(struct intel_ring_buffer *ring)
559 {
560 int ret;
561
562 if (ring->scratch.obj)
563 return 0;
564
565 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
566 if (ring->scratch.obj == NULL) {
567 DRM_ERROR("Failed to allocate seqno page\n");
568 ret = -ENOMEM;
569 goto err;
570 }
571
572 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
573 if (ret)
574 goto err_unref;
575
576 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
577 if (ret)
578 goto err_unref;
579
580 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
581 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
582 if (ring->scratch.cpu_page == NULL) {
583 ret = -ENOMEM;
584 goto err_unpin;
585 }
586
587 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
588 ring->name, ring->scratch.gtt_offset);
589 return 0;
590
591 err_unpin:
592 i915_gem_object_ggtt_unpin(ring->scratch.obj);
593 err_unref:
594 drm_gem_object_unreference(&ring->scratch.obj->base);
595 err:
596 return ret;
597 }
598
599 static int init_render_ring(struct intel_ring_buffer *ring)
600 {
601 struct drm_device *dev = ring->dev;
602 struct drm_i915_private *dev_priv = dev->dev_private;
603 int ret = init_ring_common(ring);
604
605 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
606 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
607 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
608
609 /* We need to disable the AsyncFlip performance optimisations in order
610 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
611 * programmed to '1' on all products.
612 *
613 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
614 */
615 if (INTEL_INFO(dev)->gen >= 6)
616 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
617
618 /* Required for the hardware to program scanline values for waiting */
619 /* WaEnableFlushTlbInvalidationMode:snb */
620 if (INTEL_INFO(dev)->gen == 6)
621 I915_WRITE(GFX_MODE,
622 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
623
624 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
625 if (IS_GEN7(dev))
626 I915_WRITE(GFX_MODE_GEN7,
627 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
628 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
629
630 if (INTEL_INFO(dev)->gen >= 5) {
631 ret = init_pipe_control(ring);
632 if (ret)
633 return ret;
634 }
635
636 if (IS_GEN6(dev)) {
637 /* From the Sandybridge PRM, volume 1 part 3, page 24:
638 * "If this bit is set, STCunit will have LRA as replacement
639 * policy. [...] This bit must be reset. LRA replacement
640 * policy is not supported."
641 */
642 I915_WRITE(CACHE_MODE_0,
643 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
644 }
645
646 if (INTEL_INFO(dev)->gen >= 6)
647 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
648
649 if (HAS_L3_DPF(dev))
650 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
651
652 return ret;
653 }
654
655 static void render_ring_cleanup(struct intel_ring_buffer *ring)
656 {
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669 }
670
671 static int gen6_signal(struct intel_ring_buffer *signaller,
672 unsigned int num_dwords)
673 {
674 struct drm_device *dev = signaller->dev;
675 struct drm_i915_private *dev_priv = dev->dev_private;
676 struct intel_ring_buffer *useless;
677 int i, ret;
678
679 /* NB: In order to be able to do semaphore MBOX updates for varying
680 * number of rings, it's easiest if we round up each individual update
681 * to a multiple of 2 (since ring updates must always be a multiple of
682 * 2) even though the actual update only requires 3 dwords.
683 */
684 #define MBOX_UPDATE_DWORDS 4
685 if (i915_semaphore_is_enabled(dev))
686 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
687 else
688 return intel_ring_begin(signaller, num_dwords);
689
690 ret = intel_ring_begin(signaller, num_dwords);
691 if (ret)
692 return ret;
693 #undef MBOX_UPDATE_DWORDS
694
695 for_each_ring(useless, dev_priv, i) {
696 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
697 if (mbox_reg != GEN6_NOSYNC) {
698 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
699 intel_ring_emit(signaller, mbox_reg);
700 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
701 intel_ring_emit(signaller, MI_NOOP);
702 } else {
703 intel_ring_emit(signaller, MI_NOOP);
704 intel_ring_emit(signaller, MI_NOOP);
705 intel_ring_emit(signaller, MI_NOOP);
706 intel_ring_emit(signaller, MI_NOOP);
707 }
708 }
709
710 return 0;
711 }
712
713 /**
714 * gen6_add_request - Update the semaphore mailbox registers
715 *
716 * @ring - ring that is adding a request
717 * @seqno - return seqno stuck into the ring
718 *
719 * Update the mailbox registers in the *other* rings with the current seqno.
720 * This acts like a signal in the canonical semaphore.
721 */
722 static int
723 gen6_add_request(struct intel_ring_buffer *ring)
724 {
725 int ret;
726
727 ret = ring->semaphore.signal(ring, 4);
728 if (ret)
729 return ret;
730
731 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
732 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
733 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
734 intel_ring_emit(ring, MI_USER_INTERRUPT);
735 __intel_ring_advance(ring);
736
737 return 0;
738 }
739
740 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
741 u32 seqno)
742 {
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 return dev_priv->last_seqno < seqno;
745 }
746
747 /**
748 * intel_ring_sync - sync the waiter to the signaller on seqno
749 *
750 * @waiter - ring that is waiting
751 * @signaller - ring which has, or will signal
752 * @seqno - seqno which the waiter will block on
753 */
754 static int
755 gen6_ring_sync(struct intel_ring_buffer *waiter,
756 struct intel_ring_buffer *signaller,
757 u32 seqno)
758 {
759 u32 dw1 = MI_SEMAPHORE_MBOX |
760 MI_SEMAPHORE_COMPARE |
761 MI_SEMAPHORE_REGISTER;
762 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
763 int ret;
764
765 /* Throughout all of the GEM code, seqno passed implies our current
766 * seqno is >= the last seqno executed. However for hardware the
767 * comparison is strictly greater than.
768 */
769 seqno -= 1;
770
771 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
772
773 ret = intel_ring_begin(waiter, 4);
774 if (ret)
775 return ret;
776
777 /* If seqno wrap happened, omit the wait with no-ops */
778 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
779 intel_ring_emit(waiter, dw1 | wait_mbox);
780 intel_ring_emit(waiter, seqno);
781 intel_ring_emit(waiter, 0);
782 intel_ring_emit(waiter, MI_NOOP);
783 } else {
784 intel_ring_emit(waiter, MI_NOOP);
785 intel_ring_emit(waiter, MI_NOOP);
786 intel_ring_emit(waiter, MI_NOOP);
787 intel_ring_emit(waiter, MI_NOOP);
788 }
789 intel_ring_advance(waiter);
790
791 return 0;
792 }
793
794 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
795 do { \
796 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
797 PIPE_CONTROL_DEPTH_STALL); \
798 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
799 intel_ring_emit(ring__, 0); \
800 intel_ring_emit(ring__, 0); \
801 } while (0)
802
803 static int
804 pc_render_add_request(struct intel_ring_buffer *ring)
805 {
806 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
807 int ret;
808
809 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
810 * incoherent with writes to memory, i.e. completely fubar,
811 * so we need to use PIPE_NOTIFY instead.
812 *
813 * However, we also need to workaround the qword write
814 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
815 * memory before requesting an interrupt.
816 */
817 ret = intel_ring_begin(ring, 32);
818 if (ret)
819 return ret;
820
821 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
822 PIPE_CONTROL_WRITE_FLUSH |
823 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
824 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
825 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
826 intel_ring_emit(ring, 0);
827 PIPE_CONTROL_FLUSH(ring, scratch_addr);
828 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
829 PIPE_CONTROL_FLUSH(ring, scratch_addr);
830 scratch_addr += 2 * CACHELINE_BYTES;
831 PIPE_CONTROL_FLUSH(ring, scratch_addr);
832 scratch_addr += 2 * CACHELINE_BYTES;
833 PIPE_CONTROL_FLUSH(ring, scratch_addr);
834 scratch_addr += 2 * CACHELINE_BYTES;
835 PIPE_CONTROL_FLUSH(ring, scratch_addr);
836 scratch_addr += 2 * CACHELINE_BYTES;
837 PIPE_CONTROL_FLUSH(ring, scratch_addr);
838
839 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
840 PIPE_CONTROL_WRITE_FLUSH |
841 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
842 PIPE_CONTROL_NOTIFY);
843 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
844 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
845 intel_ring_emit(ring, 0);
846 __intel_ring_advance(ring);
847
848 return 0;
849 }
850
851 static u32
852 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
853 {
854 /* Workaround to force correct ordering between irq and seqno writes on
855 * ivb (and maybe also on snb) by reading from a CS register (like
856 * ACTHD) before reading the status page. */
857 if (!lazy_coherency) {
858 struct drm_i915_private *dev_priv = ring->dev->dev_private;
859 POSTING_READ(RING_ACTHD(ring->mmio_base));
860 }
861
862 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
863 }
864
865 static u32
866 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
867 {
868 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
869 }
870
871 static void
872 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
873 {
874 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
875 }
876
877 static u32
878 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
879 {
880 return ring->scratch.cpu_page[0];
881 }
882
883 static void
884 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
885 {
886 ring->scratch.cpu_page[0] = seqno;
887 }
888
889 static bool
890 gen5_ring_get_irq(struct intel_ring_buffer *ring)
891 {
892 struct drm_device *dev = ring->dev;
893 struct drm_i915_private *dev_priv = dev->dev_private;
894 unsigned long flags;
895
896 if (!dev->irq_enabled)
897 return false;
898
899 spin_lock_irqsave(&dev_priv->irq_lock, flags);
900 if (ring->irq_refcount++ == 0)
901 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
902 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
903
904 return true;
905 }
906
907 static void
908 gen5_ring_put_irq(struct intel_ring_buffer *ring)
909 {
910 struct drm_device *dev = ring->dev;
911 struct drm_i915_private *dev_priv = dev->dev_private;
912 unsigned long flags;
913
914 spin_lock_irqsave(&dev_priv->irq_lock, flags);
915 if (--ring->irq_refcount == 0)
916 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
917 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
918 }
919
920 static bool
921 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
922 {
923 struct drm_device *dev = ring->dev;
924 struct drm_i915_private *dev_priv = dev->dev_private;
925 unsigned long flags;
926
927 if (!dev->irq_enabled)
928 return false;
929
930 spin_lock_irqsave(&dev_priv->irq_lock, flags);
931 if (ring->irq_refcount++ == 0) {
932 dev_priv->irq_mask &= ~ring->irq_enable_mask;
933 I915_WRITE(IMR, dev_priv->irq_mask);
934 POSTING_READ(IMR);
935 }
936 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
937
938 return true;
939 }
940
941 static void
942 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
943 {
944 struct drm_device *dev = ring->dev;
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 unsigned long flags;
947
948 spin_lock_irqsave(&dev_priv->irq_lock, flags);
949 if (--ring->irq_refcount == 0) {
950 dev_priv->irq_mask |= ring->irq_enable_mask;
951 I915_WRITE(IMR, dev_priv->irq_mask);
952 POSTING_READ(IMR);
953 }
954 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
955 }
956
957 static bool
958 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
959 {
960 struct drm_device *dev = ring->dev;
961 struct drm_i915_private *dev_priv = dev->dev_private;
962 unsigned long flags;
963
964 if (!dev->irq_enabled)
965 return false;
966
967 spin_lock_irqsave(&dev_priv->irq_lock, flags);
968 if (ring->irq_refcount++ == 0) {
969 dev_priv->irq_mask &= ~ring->irq_enable_mask;
970 I915_WRITE16(IMR, dev_priv->irq_mask);
971 POSTING_READ16(IMR);
972 }
973 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
974
975 return true;
976 }
977
978 static void
979 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
980 {
981 struct drm_device *dev = ring->dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 unsigned long flags;
984
985 spin_lock_irqsave(&dev_priv->irq_lock, flags);
986 if (--ring->irq_refcount == 0) {
987 dev_priv->irq_mask |= ring->irq_enable_mask;
988 I915_WRITE16(IMR, dev_priv->irq_mask);
989 POSTING_READ16(IMR);
990 }
991 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
992 }
993
994 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
995 {
996 struct drm_device *dev = ring->dev;
997 struct drm_i915_private *dev_priv = ring->dev->dev_private;
998 u32 mmio = 0;
999
1000 /* The ring status page addresses are no longer next to the rest of
1001 * the ring registers as of gen7.
1002 */
1003 if (IS_GEN7(dev)) {
1004 switch (ring->id) {
1005 case RCS:
1006 mmio = RENDER_HWS_PGA_GEN7;
1007 break;
1008 case BCS:
1009 mmio = BLT_HWS_PGA_GEN7;
1010 break;
1011 /*
1012 * VCS2 actually doesn't exist on Gen7. Only shut up
1013 * gcc switch check warning
1014 */
1015 case VCS2:
1016 case VCS:
1017 mmio = BSD_HWS_PGA_GEN7;
1018 break;
1019 case VECS:
1020 mmio = VEBOX_HWS_PGA_GEN7;
1021 break;
1022 }
1023 } else if (IS_GEN6(ring->dev)) {
1024 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1025 } else {
1026 /* XXX: gen8 returns to sanity */
1027 mmio = RING_HWS_PGA(ring->mmio_base);
1028 }
1029
1030 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1031 POSTING_READ(mmio);
1032
1033 /*
1034 * Flush the TLB for this page
1035 *
1036 * FIXME: These two bits have disappeared on gen8, so a question
1037 * arises: do we still need this and if so how should we go about
1038 * invalidating the TLB?
1039 */
1040 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1041 u32 reg = RING_INSTPM(ring->mmio_base);
1042
1043 /* ring should be idle before issuing a sync flush*/
1044 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1045
1046 I915_WRITE(reg,
1047 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1048 INSTPM_SYNC_FLUSH));
1049 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1050 1000))
1051 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1052 ring->name);
1053 }
1054 }
1055
1056 static int
1057 bsd_ring_flush(struct intel_ring_buffer *ring,
1058 u32 invalidate_domains,
1059 u32 flush_domains)
1060 {
1061 int ret;
1062
1063 ret = intel_ring_begin(ring, 2);
1064 if (ret)
1065 return ret;
1066
1067 intel_ring_emit(ring, MI_FLUSH);
1068 intel_ring_emit(ring, MI_NOOP);
1069 intel_ring_advance(ring);
1070 return 0;
1071 }
1072
1073 static int
1074 i9xx_add_request(struct intel_ring_buffer *ring)
1075 {
1076 int ret;
1077
1078 ret = intel_ring_begin(ring, 4);
1079 if (ret)
1080 return ret;
1081
1082 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1083 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1084 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1085 intel_ring_emit(ring, MI_USER_INTERRUPT);
1086 __intel_ring_advance(ring);
1087
1088 return 0;
1089 }
1090
1091 static bool
1092 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1093 {
1094 struct drm_device *dev = ring->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 unsigned long flags;
1097
1098 if (!dev->irq_enabled)
1099 return false;
1100
1101 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1102 if (ring->irq_refcount++ == 0) {
1103 if (HAS_L3_DPF(dev) && ring->id == RCS)
1104 I915_WRITE_IMR(ring,
1105 ~(ring->irq_enable_mask |
1106 GT_PARITY_ERROR(dev)));
1107 else
1108 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1109 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1110 }
1111 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1112
1113 return true;
1114 }
1115
1116 static void
1117 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1118 {
1119 struct drm_device *dev = ring->dev;
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 unsigned long flags;
1122
1123 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1124 if (--ring->irq_refcount == 0) {
1125 if (HAS_L3_DPF(dev) && ring->id == RCS)
1126 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1127 else
1128 I915_WRITE_IMR(ring, ~0);
1129 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1130 }
1131 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1132 }
1133
1134 static bool
1135 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1136 {
1137 struct drm_device *dev = ring->dev;
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139 unsigned long flags;
1140
1141 if (!dev->irq_enabled)
1142 return false;
1143
1144 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1145 if (ring->irq_refcount++ == 0) {
1146 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1147 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1148 }
1149 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1150
1151 return true;
1152 }
1153
1154 static void
1155 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1156 {
1157 struct drm_device *dev = ring->dev;
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1159 unsigned long flags;
1160
1161 if (!dev->irq_enabled)
1162 return;
1163
1164 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1165 if (--ring->irq_refcount == 0) {
1166 I915_WRITE_IMR(ring, ~0);
1167 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1168 }
1169 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1170 }
1171
1172 static bool
1173 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1174 {
1175 struct drm_device *dev = ring->dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 unsigned long flags;
1178
1179 if (!dev->irq_enabled)
1180 return false;
1181
1182 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1183 if (ring->irq_refcount++ == 0) {
1184 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1185 I915_WRITE_IMR(ring,
1186 ~(ring->irq_enable_mask |
1187 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1188 } else {
1189 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1190 }
1191 POSTING_READ(RING_IMR(ring->mmio_base));
1192 }
1193 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1194
1195 return true;
1196 }
1197
1198 static void
1199 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1200 {
1201 struct drm_device *dev = ring->dev;
1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1206 if (--ring->irq_refcount == 0) {
1207 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1208 I915_WRITE_IMR(ring,
1209 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1210 } else {
1211 I915_WRITE_IMR(ring, ~0);
1212 }
1213 POSTING_READ(RING_IMR(ring->mmio_base));
1214 }
1215 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1216 }
1217
1218 static int
1219 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1220 u64 offset, u32 length,
1221 unsigned flags)
1222 {
1223 int ret;
1224
1225 ret = intel_ring_begin(ring, 2);
1226 if (ret)
1227 return ret;
1228
1229 intel_ring_emit(ring,
1230 MI_BATCH_BUFFER_START |
1231 MI_BATCH_GTT |
1232 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1233 intel_ring_emit(ring, offset);
1234 intel_ring_advance(ring);
1235
1236 return 0;
1237 }
1238
1239 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1240 #define I830_BATCH_LIMIT (256*1024)
1241 static int
1242 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1243 u64 offset, u32 len,
1244 unsigned flags)
1245 {
1246 int ret;
1247
1248 if (flags & I915_DISPATCH_PINNED) {
1249 ret = intel_ring_begin(ring, 4);
1250 if (ret)
1251 return ret;
1252
1253 intel_ring_emit(ring, MI_BATCH_BUFFER);
1254 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1255 intel_ring_emit(ring, offset + len - 8);
1256 intel_ring_emit(ring, MI_NOOP);
1257 intel_ring_advance(ring);
1258 } else {
1259 u32 cs_offset = ring->scratch.gtt_offset;
1260
1261 if (len > I830_BATCH_LIMIT)
1262 return -ENOSPC;
1263
1264 ret = intel_ring_begin(ring, 9+3);
1265 if (ret)
1266 return ret;
1267 /* Blit the batch (which has now all relocs applied) to the stable batch
1268 * scratch bo area (so that the CS never stumbles over its tlb
1269 * invalidation bug) ... */
1270 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1271 XY_SRC_COPY_BLT_WRITE_ALPHA |
1272 XY_SRC_COPY_BLT_WRITE_RGB);
1273 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1274 intel_ring_emit(ring, 0);
1275 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1276 intel_ring_emit(ring, cs_offset);
1277 intel_ring_emit(ring, 0);
1278 intel_ring_emit(ring, 4096);
1279 intel_ring_emit(ring, offset);
1280 intel_ring_emit(ring, MI_FLUSH);
1281
1282 /* ... and execute it. */
1283 intel_ring_emit(ring, MI_BATCH_BUFFER);
1284 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1285 intel_ring_emit(ring, cs_offset + len - 8);
1286 intel_ring_advance(ring);
1287 }
1288
1289 return 0;
1290 }
1291
1292 static int
1293 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1294 u64 offset, u32 len,
1295 unsigned flags)
1296 {
1297 int ret;
1298
1299 ret = intel_ring_begin(ring, 2);
1300 if (ret)
1301 return ret;
1302
1303 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1304 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1305 intel_ring_advance(ring);
1306
1307 return 0;
1308 }
1309
1310 static void cleanup_status_page(struct intel_ring_buffer *ring)
1311 {
1312 struct drm_i915_gem_object *obj;
1313
1314 obj = ring->status_page.obj;
1315 if (obj == NULL)
1316 return;
1317
1318 kunmap(sg_page(obj->pages->sgl));
1319 i915_gem_object_ggtt_unpin(obj);
1320 drm_gem_object_unreference(&obj->base);
1321 ring->status_page.obj = NULL;
1322 }
1323
1324 static int init_status_page(struct intel_ring_buffer *ring)
1325 {
1326 struct drm_i915_gem_object *obj;
1327
1328 if ((obj = ring->status_page.obj) == NULL) {
1329 int ret;
1330
1331 obj = i915_gem_alloc_object(ring->dev, 4096);
1332 if (obj == NULL) {
1333 DRM_ERROR("Failed to allocate status page\n");
1334 return -ENOMEM;
1335 }
1336
1337 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1338 if (ret)
1339 goto err_unref;
1340
1341 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1342 if (ret) {
1343 err_unref:
1344 drm_gem_object_unreference(&obj->base);
1345 return ret;
1346 }
1347
1348 ring->status_page.obj = obj;
1349 }
1350
1351 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1352 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1353 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1354
1355 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1356 ring->name, ring->status_page.gfx_addr);
1357
1358 return 0;
1359 }
1360
1361 static int init_phys_status_page(struct intel_ring_buffer *ring)
1362 {
1363 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1364
1365 if (!dev_priv->status_page_dmah) {
1366 dev_priv->status_page_dmah =
1367 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1368 if (!dev_priv->status_page_dmah)
1369 return -ENOMEM;
1370 }
1371
1372 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1373 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1374
1375 return 0;
1376 }
1377
1378 static int allocate_ring_buffer(struct intel_ring_buffer *ring)
1379 {
1380 struct drm_device *dev = ring->dev;
1381 struct drm_i915_private *dev_priv = to_i915(dev);
1382 struct drm_i915_gem_object *obj;
1383 int ret;
1384
1385 if (ring->obj)
1386 return 0;
1387
1388 obj = NULL;
1389 if (!HAS_LLC(dev))
1390 obj = i915_gem_object_create_stolen(dev, ring->size);
1391 if (obj == NULL)
1392 obj = i915_gem_alloc_object(dev, ring->size);
1393 if (obj == NULL)
1394 return -ENOMEM;
1395
1396 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1397 if (ret)
1398 goto err_unref;
1399
1400 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1401 if (ret)
1402 goto err_unpin;
1403
1404 ring->virtual_start =
1405 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1406 ring->size);
1407 if (ring->virtual_start == NULL) {
1408 ret = -EINVAL;
1409 goto err_unpin;
1410 }
1411
1412 ring->obj = obj;
1413 return 0;
1414
1415 err_unpin:
1416 i915_gem_object_ggtt_unpin(obj);
1417 err_unref:
1418 drm_gem_object_unreference(&obj->base);
1419 return ret;
1420 }
1421
1422 static int intel_init_ring_buffer(struct drm_device *dev,
1423 struct intel_ring_buffer *ring)
1424 {
1425 int ret;
1426
1427 ring->dev = dev;
1428 INIT_LIST_HEAD(&ring->active_list);
1429 INIT_LIST_HEAD(&ring->request_list);
1430 ring->size = 32 * PAGE_SIZE;
1431 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1432
1433 init_waitqueue_head(&ring->irq_queue);
1434
1435 if (I915_NEED_GFX_HWS(dev)) {
1436 ret = init_status_page(ring);
1437 if (ret)
1438 return ret;
1439 } else {
1440 BUG_ON(ring->id != RCS);
1441 ret = init_phys_status_page(ring);
1442 if (ret)
1443 return ret;
1444 }
1445
1446 ret = allocate_ring_buffer(ring);
1447 if (ret) {
1448 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1449 return ret;
1450 }
1451
1452 /* Workaround an erratum on the i830 which causes a hang if
1453 * the TAIL pointer points to within the last 2 cachelines
1454 * of the buffer.
1455 */
1456 ring->effective_size = ring->size;
1457 if (IS_I830(dev) || IS_845G(dev))
1458 ring->effective_size -= 2 * CACHELINE_BYTES;
1459
1460 ret = i915_cmd_parser_init_ring(ring);
1461 if (ret)
1462 return ret;
1463
1464 return ring->init(ring);
1465 }
1466
1467 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1468 {
1469 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1470
1471 if (ring->obj == NULL)
1472 return;
1473
1474 intel_stop_ring_buffer(ring);
1475 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1476
1477 iounmap(ring->virtual_start);
1478
1479 i915_gem_object_ggtt_unpin(ring->obj);
1480 drm_gem_object_unreference(&ring->obj->base);
1481 ring->obj = NULL;
1482 ring->preallocated_lazy_request = NULL;
1483 ring->outstanding_lazy_seqno = 0;
1484
1485 if (ring->cleanup)
1486 ring->cleanup(ring);
1487
1488 cleanup_status_page(ring);
1489
1490 i915_cmd_parser_fini_ring(ring);
1491 }
1492
1493 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1494 {
1495 struct drm_i915_gem_request *request;
1496 u32 seqno = 0;
1497 int ret;
1498
1499 if (ring->last_retired_head != -1) {
1500 ring->head = ring->last_retired_head;
1501 ring->last_retired_head = -1;
1502
1503 ring->space = ring_space(ring);
1504 if (ring->space >= n)
1505 return 0;
1506 }
1507
1508 list_for_each_entry(request, &ring->request_list, list) {
1509 if (__ring_space(request->tail, ring->tail, ring->size) >= n) {
1510 seqno = request->seqno;
1511 break;
1512 }
1513 }
1514
1515 if (seqno == 0)
1516 return -ENOSPC;
1517
1518 ret = i915_wait_seqno(ring, seqno);
1519 if (ret)
1520 return ret;
1521
1522 i915_gem_retire_requests_ring(ring);
1523 ring->head = ring->last_retired_head;
1524 ring->last_retired_head = -1;
1525
1526 ring->space = ring_space(ring);
1527 return 0;
1528 }
1529
1530 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1531 {
1532 struct drm_device *dev = ring->dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 unsigned long end;
1535 int ret;
1536
1537 ret = intel_ring_wait_request(ring, n);
1538 if (ret != -ENOSPC)
1539 return ret;
1540
1541 /* force the tail write in case we have been skipping them */
1542 __intel_ring_advance(ring);
1543
1544 /* With GEM the hangcheck timer should kick us out of the loop,
1545 * leaving it early runs the risk of corrupting GEM state (due
1546 * to running on almost untested codepaths). But on resume
1547 * timers don't work yet, so prevent a complete hang in that
1548 * case by choosing an insanely large timeout. */
1549 end = jiffies + 60 * HZ;
1550
1551 trace_i915_ring_wait_begin(ring);
1552 do {
1553 ring->head = I915_READ_HEAD(ring);
1554 ring->space = ring_space(ring);
1555 if (ring->space >= n) {
1556 ret = 0;
1557 break;
1558 }
1559
1560 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1561 dev->primary->master) {
1562 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1563 if (master_priv->sarea_priv)
1564 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1565 }
1566
1567 msleep(1);
1568
1569 if (dev_priv->mm.interruptible && signal_pending(current)) {
1570 ret = -ERESTARTSYS;
1571 break;
1572 }
1573
1574 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1575 dev_priv->mm.interruptible);
1576 if (ret)
1577 break;
1578
1579 if (time_after(jiffies, end)) {
1580 ret = -EBUSY;
1581 break;
1582 }
1583 } while (1);
1584 trace_i915_ring_wait_end(ring);
1585 return ret;
1586 }
1587
1588 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1589 {
1590 uint32_t __iomem *virt;
1591 int rem = ring->size - ring->tail;
1592
1593 if (ring->space < rem) {
1594 int ret = ring_wait_for_space(ring, rem);
1595 if (ret)
1596 return ret;
1597 }
1598
1599 virt = ring->virtual_start + ring->tail;
1600 rem /= 4;
1601 while (rem--)
1602 iowrite32(MI_NOOP, virt++);
1603
1604 ring->tail = 0;
1605 ring->space = ring_space(ring);
1606
1607 return 0;
1608 }
1609
1610 int intel_ring_idle(struct intel_ring_buffer *ring)
1611 {
1612 u32 seqno;
1613 int ret;
1614
1615 /* We need to add any requests required to flush the objects and ring */
1616 if (ring->outstanding_lazy_seqno) {
1617 ret = i915_add_request(ring, NULL);
1618 if (ret)
1619 return ret;
1620 }
1621
1622 /* Wait upon the last request to be completed */
1623 if (list_empty(&ring->request_list))
1624 return 0;
1625
1626 seqno = list_entry(ring->request_list.prev,
1627 struct drm_i915_gem_request,
1628 list)->seqno;
1629
1630 return i915_wait_seqno(ring, seqno);
1631 }
1632
1633 static int
1634 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1635 {
1636 if (ring->outstanding_lazy_seqno)
1637 return 0;
1638
1639 if (ring->preallocated_lazy_request == NULL) {
1640 struct drm_i915_gem_request *request;
1641
1642 request = kmalloc(sizeof(*request), GFP_KERNEL);
1643 if (request == NULL)
1644 return -ENOMEM;
1645
1646 ring->preallocated_lazy_request = request;
1647 }
1648
1649 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1650 }
1651
1652 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1653 int bytes)
1654 {
1655 int ret;
1656
1657 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1658 ret = intel_wrap_ring_buffer(ring);
1659 if (unlikely(ret))
1660 return ret;
1661 }
1662
1663 if (unlikely(ring->space < bytes)) {
1664 ret = ring_wait_for_space(ring, bytes);
1665 if (unlikely(ret))
1666 return ret;
1667 }
1668
1669 return 0;
1670 }
1671
1672 int intel_ring_begin(struct intel_ring_buffer *ring,
1673 int num_dwords)
1674 {
1675 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1676 int ret;
1677
1678 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1679 dev_priv->mm.interruptible);
1680 if (ret)
1681 return ret;
1682
1683 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1684 if (ret)
1685 return ret;
1686
1687 /* Preallocate the olr before touching the ring */
1688 ret = intel_ring_alloc_seqno(ring);
1689 if (ret)
1690 return ret;
1691
1692 ring->space -= num_dwords * sizeof(uint32_t);
1693 return 0;
1694 }
1695
1696 /* Align the ring tail to a cacheline boundary */
1697 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1698 {
1699 int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1700 int ret;
1701
1702 if (num_dwords == 0)
1703 return 0;
1704
1705 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1706 ret = intel_ring_begin(ring, num_dwords);
1707 if (ret)
1708 return ret;
1709
1710 while (num_dwords--)
1711 intel_ring_emit(ring, MI_NOOP);
1712
1713 intel_ring_advance(ring);
1714
1715 return 0;
1716 }
1717
1718 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1719 {
1720 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1721
1722 BUG_ON(ring->outstanding_lazy_seqno);
1723
1724 if (INTEL_INFO(ring->dev)->gen >= 6) {
1725 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1726 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1727 if (HAS_VEBOX(ring->dev))
1728 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1729 }
1730
1731 ring->set_seqno(ring, seqno);
1732 ring->hangcheck.seqno = seqno;
1733 }
1734
1735 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1736 u32 value)
1737 {
1738 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1739
1740 /* Every tail move must follow the sequence below */
1741
1742 /* Disable notification that the ring is IDLE. The GT
1743 * will then assume that it is busy and bring it out of rc6.
1744 */
1745 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1746 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1747
1748 /* Clear the context id. Here be magic! */
1749 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1750
1751 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1752 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1753 GEN6_BSD_SLEEP_INDICATOR) == 0,
1754 50))
1755 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1756
1757 /* Now that the ring is fully powered up, update the tail */
1758 I915_WRITE_TAIL(ring, value);
1759 POSTING_READ(RING_TAIL(ring->mmio_base));
1760
1761 /* Let the ring send IDLE messages to the GT again,
1762 * and so let it sleep to conserve power when idle.
1763 */
1764 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1765 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1766 }
1767
1768 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1769 u32 invalidate, u32 flush)
1770 {
1771 uint32_t cmd;
1772 int ret;
1773
1774 ret = intel_ring_begin(ring, 4);
1775 if (ret)
1776 return ret;
1777
1778 cmd = MI_FLUSH_DW;
1779 if (INTEL_INFO(ring->dev)->gen >= 8)
1780 cmd += 1;
1781 /*
1782 * Bspec vol 1c.5 - video engine command streamer:
1783 * "If ENABLED, all TLBs will be invalidated once the flush
1784 * operation is complete. This bit is only valid when the
1785 * Post-Sync Operation field is a value of 1h or 3h."
1786 */
1787 if (invalidate & I915_GEM_GPU_DOMAINS)
1788 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1789 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1790 intel_ring_emit(ring, cmd);
1791 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1792 if (INTEL_INFO(ring->dev)->gen >= 8) {
1793 intel_ring_emit(ring, 0); /* upper addr */
1794 intel_ring_emit(ring, 0); /* value */
1795 } else {
1796 intel_ring_emit(ring, 0);
1797 intel_ring_emit(ring, MI_NOOP);
1798 }
1799 intel_ring_advance(ring);
1800 return 0;
1801 }
1802
1803 static int
1804 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1805 u64 offset, u32 len,
1806 unsigned flags)
1807 {
1808 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1809 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1810 !(flags & I915_DISPATCH_SECURE);
1811 int ret;
1812
1813 ret = intel_ring_begin(ring, 4);
1814 if (ret)
1815 return ret;
1816
1817 /* FIXME(BDW): Address space and security selectors. */
1818 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1819 intel_ring_emit(ring, lower_32_bits(offset));
1820 intel_ring_emit(ring, upper_32_bits(offset));
1821 intel_ring_emit(ring, MI_NOOP);
1822 intel_ring_advance(ring);
1823
1824 return 0;
1825 }
1826
1827 static int
1828 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1829 u64 offset, u32 len,
1830 unsigned flags)
1831 {
1832 int ret;
1833
1834 ret = intel_ring_begin(ring, 2);
1835 if (ret)
1836 return ret;
1837
1838 intel_ring_emit(ring,
1839 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1840 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1841 /* bit0-7 is the length on GEN6+ */
1842 intel_ring_emit(ring, offset);
1843 intel_ring_advance(ring);
1844
1845 return 0;
1846 }
1847
1848 static int
1849 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1850 u64 offset, u32 len,
1851 unsigned flags)
1852 {
1853 int ret;
1854
1855 ret = intel_ring_begin(ring, 2);
1856 if (ret)
1857 return ret;
1858
1859 intel_ring_emit(ring,
1860 MI_BATCH_BUFFER_START |
1861 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1862 /* bit0-7 is the length on GEN6+ */
1863 intel_ring_emit(ring, offset);
1864 intel_ring_advance(ring);
1865
1866 return 0;
1867 }
1868
1869 /* Blitter support (SandyBridge+) */
1870
1871 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1872 u32 invalidate, u32 flush)
1873 {
1874 struct drm_device *dev = ring->dev;
1875 uint32_t cmd;
1876 int ret;
1877
1878 ret = intel_ring_begin(ring, 4);
1879 if (ret)
1880 return ret;
1881
1882 cmd = MI_FLUSH_DW;
1883 if (INTEL_INFO(ring->dev)->gen >= 8)
1884 cmd += 1;
1885 /*
1886 * Bspec vol 1c.3 - blitter engine command streamer:
1887 * "If ENABLED, all TLBs will be invalidated once the flush
1888 * operation is complete. This bit is only valid when the
1889 * Post-Sync Operation field is a value of 1h or 3h."
1890 */
1891 if (invalidate & I915_GEM_DOMAIN_RENDER)
1892 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1893 MI_FLUSH_DW_OP_STOREDW;
1894 intel_ring_emit(ring, cmd);
1895 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1896 if (INTEL_INFO(ring->dev)->gen >= 8) {
1897 intel_ring_emit(ring, 0); /* upper addr */
1898 intel_ring_emit(ring, 0); /* value */
1899 } else {
1900 intel_ring_emit(ring, 0);
1901 intel_ring_emit(ring, MI_NOOP);
1902 }
1903 intel_ring_advance(ring);
1904
1905 if (IS_GEN7(dev) && !invalidate && flush)
1906 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1907
1908 return 0;
1909 }
1910
1911 int intel_init_render_ring_buffer(struct drm_device *dev)
1912 {
1913 struct drm_i915_private *dev_priv = dev->dev_private;
1914 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1915
1916 ring->name = "render ring";
1917 ring->id = RCS;
1918 ring->mmio_base = RENDER_RING_BASE;
1919
1920 if (INTEL_INFO(dev)->gen >= 6) {
1921 ring->add_request = gen6_add_request;
1922 ring->flush = gen7_render_ring_flush;
1923 if (INTEL_INFO(dev)->gen == 6)
1924 ring->flush = gen6_render_ring_flush;
1925 if (INTEL_INFO(dev)->gen >= 8) {
1926 ring->flush = gen8_render_ring_flush;
1927 ring->irq_get = gen8_ring_get_irq;
1928 ring->irq_put = gen8_ring_put_irq;
1929 } else {
1930 ring->irq_get = gen6_ring_get_irq;
1931 ring->irq_put = gen6_ring_put_irq;
1932 }
1933 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1934 ring->get_seqno = gen6_ring_get_seqno;
1935 ring->set_seqno = ring_set_seqno;
1936 ring->semaphore.sync_to = gen6_ring_sync;
1937 ring->semaphore.signal = gen6_signal;
1938 /*
1939 * The current semaphore is only applied on pre-gen8 platform.
1940 * And there is no VCS2 ring on the pre-gen8 platform. So the
1941 * semaphore between RCS and VCS2 is initialized as INVALID.
1942 * Gen8 will initialize the sema between VCS2 and RCS later.
1943 */
1944 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1945 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
1946 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
1947 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
1948 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
1949 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
1950 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
1951 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
1952 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
1953 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
1954 } else if (IS_GEN5(dev)) {
1955 ring->add_request = pc_render_add_request;
1956 ring->flush = gen4_render_ring_flush;
1957 ring->get_seqno = pc_render_get_seqno;
1958 ring->set_seqno = pc_render_set_seqno;
1959 ring->irq_get = gen5_ring_get_irq;
1960 ring->irq_put = gen5_ring_put_irq;
1961 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1962 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1963 } else {
1964 ring->add_request = i9xx_add_request;
1965 if (INTEL_INFO(dev)->gen < 4)
1966 ring->flush = gen2_render_ring_flush;
1967 else
1968 ring->flush = gen4_render_ring_flush;
1969 ring->get_seqno = ring_get_seqno;
1970 ring->set_seqno = ring_set_seqno;
1971 if (IS_GEN2(dev)) {
1972 ring->irq_get = i8xx_ring_get_irq;
1973 ring->irq_put = i8xx_ring_put_irq;
1974 } else {
1975 ring->irq_get = i9xx_ring_get_irq;
1976 ring->irq_put = i9xx_ring_put_irq;
1977 }
1978 ring->irq_enable_mask = I915_USER_INTERRUPT;
1979 }
1980 ring->write_tail = ring_write_tail;
1981 if (IS_HASWELL(dev))
1982 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1983 else if (IS_GEN8(dev))
1984 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1985 else if (INTEL_INFO(dev)->gen >= 6)
1986 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1987 else if (INTEL_INFO(dev)->gen >= 4)
1988 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1989 else if (IS_I830(dev) || IS_845G(dev))
1990 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1991 else
1992 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1993 ring->init = init_render_ring;
1994 ring->cleanup = render_ring_cleanup;
1995
1996 /* Workaround batchbuffer to combat CS tlb bug. */
1997 if (HAS_BROKEN_CS_TLB(dev)) {
1998 struct drm_i915_gem_object *obj;
1999 int ret;
2000
2001 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
2002 if (obj == NULL) {
2003 DRM_ERROR("Failed to allocate batch bo\n");
2004 return -ENOMEM;
2005 }
2006
2007 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2008 if (ret != 0) {
2009 drm_gem_object_unreference(&obj->base);
2010 DRM_ERROR("Failed to ping batch bo\n");
2011 return ret;
2012 }
2013
2014 ring->scratch.obj = obj;
2015 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2016 }
2017
2018 return intel_init_ring_buffer(dev, ring);
2019 }
2020
2021 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2022 {
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2025 int ret;
2026
2027 ring->name = "render ring";
2028 ring->id = RCS;
2029 ring->mmio_base = RENDER_RING_BASE;
2030
2031 if (INTEL_INFO(dev)->gen >= 6) {
2032 /* non-kms not supported on gen6+ */
2033 return -ENODEV;
2034 }
2035
2036 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2037 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2038 * the special gen5 functions. */
2039 ring->add_request = i9xx_add_request;
2040 if (INTEL_INFO(dev)->gen < 4)
2041 ring->flush = gen2_render_ring_flush;
2042 else
2043 ring->flush = gen4_render_ring_flush;
2044 ring->get_seqno = ring_get_seqno;
2045 ring->set_seqno = ring_set_seqno;
2046 if (IS_GEN2(dev)) {
2047 ring->irq_get = i8xx_ring_get_irq;
2048 ring->irq_put = i8xx_ring_put_irq;
2049 } else {
2050 ring->irq_get = i9xx_ring_get_irq;
2051 ring->irq_put = i9xx_ring_put_irq;
2052 }
2053 ring->irq_enable_mask = I915_USER_INTERRUPT;
2054 ring->write_tail = ring_write_tail;
2055 if (INTEL_INFO(dev)->gen >= 4)
2056 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2057 else if (IS_I830(dev) || IS_845G(dev))
2058 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2059 else
2060 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2061 ring->init = init_render_ring;
2062 ring->cleanup = render_ring_cleanup;
2063
2064 ring->dev = dev;
2065 INIT_LIST_HEAD(&ring->active_list);
2066 INIT_LIST_HEAD(&ring->request_list);
2067
2068 ring->size = size;
2069 ring->effective_size = ring->size;
2070 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2071 ring->effective_size -= 2 * CACHELINE_BYTES;
2072
2073 ring->virtual_start = ioremap_wc(start, size);
2074 if (ring->virtual_start == NULL) {
2075 DRM_ERROR("can not ioremap virtual address for"
2076 " ring buffer\n");
2077 return -ENOMEM;
2078 }
2079
2080 if (!I915_NEED_GFX_HWS(dev)) {
2081 ret = init_phys_status_page(ring);
2082 if (ret)
2083 return ret;
2084 }
2085
2086 return 0;
2087 }
2088
2089 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2090 {
2091 struct drm_i915_private *dev_priv = dev->dev_private;
2092 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2093
2094 ring->name = "bsd ring";
2095 ring->id = VCS;
2096
2097 ring->write_tail = ring_write_tail;
2098 if (INTEL_INFO(dev)->gen >= 6) {
2099 ring->mmio_base = GEN6_BSD_RING_BASE;
2100 /* gen6 bsd needs a special wa for tail updates */
2101 if (IS_GEN6(dev))
2102 ring->write_tail = gen6_bsd_ring_write_tail;
2103 ring->flush = gen6_bsd_ring_flush;
2104 ring->add_request = gen6_add_request;
2105 ring->get_seqno = gen6_ring_get_seqno;
2106 ring->set_seqno = ring_set_seqno;
2107 if (INTEL_INFO(dev)->gen >= 8) {
2108 ring->irq_enable_mask =
2109 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2110 ring->irq_get = gen8_ring_get_irq;
2111 ring->irq_put = gen8_ring_put_irq;
2112 ring->dispatch_execbuffer =
2113 gen8_ring_dispatch_execbuffer;
2114 } else {
2115 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2116 ring->irq_get = gen6_ring_get_irq;
2117 ring->irq_put = gen6_ring_put_irq;
2118 ring->dispatch_execbuffer =
2119 gen6_ring_dispatch_execbuffer;
2120 }
2121 ring->semaphore.sync_to = gen6_ring_sync;
2122 ring->semaphore.signal = gen6_signal;
2123 /*
2124 * The current semaphore is only applied on pre-gen8 platform.
2125 * And there is no VCS2 ring on the pre-gen8 platform. So the
2126 * semaphore between VCS and VCS2 is initialized as INVALID.
2127 * Gen8 will initialize the sema between VCS2 and VCS later.
2128 */
2129 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2130 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2131 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2132 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2133 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2134 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2135 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2136 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2137 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2138 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2139 } else {
2140 ring->mmio_base = BSD_RING_BASE;
2141 ring->flush = bsd_ring_flush;
2142 ring->add_request = i9xx_add_request;
2143 ring->get_seqno = ring_get_seqno;
2144 ring->set_seqno = ring_set_seqno;
2145 if (IS_GEN5(dev)) {
2146 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2147 ring->irq_get = gen5_ring_get_irq;
2148 ring->irq_put = gen5_ring_put_irq;
2149 } else {
2150 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2151 ring->irq_get = i9xx_ring_get_irq;
2152 ring->irq_put = i9xx_ring_put_irq;
2153 }
2154 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2155 }
2156 ring->init = init_ring_common;
2157
2158 return intel_init_ring_buffer(dev, ring);
2159 }
2160
2161 /**
2162 * Initialize the second BSD ring for Broadwell GT3.
2163 * It is noted that this only exists on Broadwell GT3.
2164 */
2165 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2166 {
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct intel_ring_buffer *ring = &dev_priv->ring[VCS2];
2169
2170 if ((INTEL_INFO(dev)->gen != 8)) {
2171 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2172 return -EINVAL;
2173 }
2174
2175 ring->name = "bds2_ring";
2176 ring->id = VCS2;
2177
2178 ring->write_tail = ring_write_tail;
2179 ring->mmio_base = GEN8_BSD2_RING_BASE;
2180 ring->flush = gen6_bsd_ring_flush;
2181 ring->add_request = gen6_add_request;
2182 ring->get_seqno = gen6_ring_get_seqno;
2183 ring->set_seqno = ring_set_seqno;
2184 ring->irq_enable_mask =
2185 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2186 ring->irq_get = gen8_ring_get_irq;
2187 ring->irq_put = gen8_ring_put_irq;
2188 ring->dispatch_execbuffer =
2189 gen8_ring_dispatch_execbuffer;
2190 ring->semaphore.sync_to = gen6_ring_sync;
2191 ring->semaphore.signal = gen6_signal;
2192 /*
2193 * The current semaphore is only applied on the pre-gen8. And there
2194 * is no bsd2 ring on the pre-gen8. So now the semaphore_register
2195 * between VCS2 and other ring is initialized as invalid.
2196 * Gen8 will initialize the sema between VCS2 and other ring later.
2197 */
2198 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2199 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2200 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2201 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2202 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2203 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2204 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2205 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2206 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2207 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2208
2209 ring->init = init_ring_common;
2210
2211 return intel_init_ring_buffer(dev, ring);
2212 }
2213
2214 int intel_init_blt_ring_buffer(struct drm_device *dev)
2215 {
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2218
2219 ring->name = "blitter ring";
2220 ring->id = BCS;
2221
2222 ring->mmio_base = BLT_RING_BASE;
2223 ring->write_tail = ring_write_tail;
2224 ring->flush = gen6_ring_flush;
2225 ring->add_request = gen6_add_request;
2226 ring->get_seqno = gen6_ring_get_seqno;
2227 ring->set_seqno = ring_set_seqno;
2228 if (INTEL_INFO(dev)->gen >= 8) {
2229 ring->irq_enable_mask =
2230 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2231 ring->irq_get = gen8_ring_get_irq;
2232 ring->irq_put = gen8_ring_put_irq;
2233 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2234 } else {
2235 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2236 ring->irq_get = gen6_ring_get_irq;
2237 ring->irq_put = gen6_ring_put_irq;
2238 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2239 }
2240 ring->semaphore.sync_to = gen6_ring_sync;
2241 ring->semaphore.signal = gen6_signal;
2242 /*
2243 * The current semaphore is only applied on pre-gen8 platform. And
2244 * there is no VCS2 ring on the pre-gen8 platform. So the semaphore
2245 * between BCS and VCS2 is initialized as INVALID.
2246 * Gen8 will initialize the sema between BCS and VCS2 later.
2247 */
2248 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2249 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2250 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2251 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2252 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2253 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2254 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2255 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2256 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2257 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2258 ring->init = init_ring_common;
2259
2260 return intel_init_ring_buffer(dev, ring);
2261 }
2262
2263 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2264 {
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2267
2268 ring->name = "video enhancement ring";
2269 ring->id = VECS;
2270
2271 ring->mmio_base = VEBOX_RING_BASE;
2272 ring->write_tail = ring_write_tail;
2273 ring->flush = gen6_ring_flush;
2274 ring->add_request = gen6_add_request;
2275 ring->get_seqno = gen6_ring_get_seqno;
2276 ring->set_seqno = ring_set_seqno;
2277
2278 if (INTEL_INFO(dev)->gen >= 8) {
2279 ring->irq_enable_mask =
2280 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2281 ring->irq_get = gen8_ring_get_irq;
2282 ring->irq_put = gen8_ring_put_irq;
2283 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2284 } else {
2285 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2286 ring->irq_get = hsw_vebox_get_irq;
2287 ring->irq_put = hsw_vebox_put_irq;
2288 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2289 }
2290 ring->semaphore.sync_to = gen6_ring_sync;
2291 ring->semaphore.signal = gen6_signal;
2292 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2293 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2294 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2295 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2296 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2297 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2298 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2299 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2300 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2301 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2302 ring->init = init_ring_common;
2303
2304 return intel_init_ring_buffer(dev, ring);
2305 }
2306
2307 int
2308 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2309 {
2310 int ret;
2311
2312 if (!ring->gpu_caches_dirty)
2313 return 0;
2314
2315 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2316 if (ret)
2317 return ret;
2318
2319 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2320
2321 ring->gpu_caches_dirty = false;
2322 return 0;
2323 }
2324
2325 int
2326 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2327 {
2328 uint32_t flush_domains;
2329 int ret;
2330
2331 flush_domains = 0;
2332 if (ring->gpu_caches_dirty)
2333 flush_domains = I915_GEM_GPU_DOMAINS;
2334
2335 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2336 if (ret)
2337 return ret;
2338
2339 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2340
2341 ring->gpu_caches_dirty = false;
2342 return 0;
2343 }
2344
2345 void
2346 intel_stop_ring_buffer(struct intel_ring_buffer *ring)
2347 {
2348 int ret;
2349
2350 if (!intel_ring_initialized(ring))
2351 return;
2352
2353 ret = intel_ring_idle(ring);
2354 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2355 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2356 ring->name, ret);
2357
2358 stop_ring(ring);
2359 }
Linux kernel - Deliverables
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