2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- tail
;
58 return space
- I915_RING_FREE_SPACE
;
61 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
63 if (ringbuf
->last_retired_head
!= -1) {
64 ringbuf
->head
= ringbuf
->last_retired_head
;
65 ringbuf
->last_retired_head
= -1;
68 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
69 ringbuf
->tail
, ringbuf
->size
);
72 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
74 intel_ring_update_space(ringbuf
);
75 return ringbuf
->space
;
78 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
80 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
81 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
84 void __intel_ring_advance(struct intel_engine_cs
*ring
)
86 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
87 ringbuf
->tail
&= ringbuf
->size
- 1;
88 if (intel_ring_stopped(ring
))
90 ring
->write_tail(ring
, ringbuf
->tail
);
94 gen2_render_ring_flush(struct intel_engine_cs
*ring
,
95 u32 invalidate_domains
,
102 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
103 cmd
|= MI_NO_WRITE_FLUSH
;
105 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
106 cmd
|= MI_READ_FLUSH
;
108 ret
= intel_ring_begin(ring
, 2);
112 intel_ring_emit(ring
, cmd
);
113 intel_ring_emit(ring
, MI_NOOP
);
114 intel_ring_advance(ring
);
120 gen4_render_ring_flush(struct intel_engine_cs
*ring
,
121 u32 invalidate_domains
,
124 struct drm_device
*dev
= ring
->dev
;
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
140 * I915_GEM_DOMAIN_COMMAND may not exist?
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
156 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
157 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
158 cmd
&= ~MI_NO_WRITE_FLUSH
;
159 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
162 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
163 (IS_G4X(dev
) || IS_GEN5(dev
)))
164 cmd
|= MI_INVALIDATE_ISP
;
166 ret
= intel_ring_begin(ring
, 2);
170 intel_ring_emit(ring
, cmd
);
171 intel_ring_emit(ring
, MI_NOOP
);
172 intel_ring_advance(ring
);
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 * And the workaround for these two requires this workaround first:
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
215 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs
*ring
)
217 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
221 ret
= intel_ring_begin(ring
, 6);
225 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
227 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
228 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
229 intel_ring_emit(ring
, 0); /* low dword */
230 intel_ring_emit(ring
, 0); /* high dword */
231 intel_ring_emit(ring
, MI_NOOP
);
232 intel_ring_advance(ring
);
234 ret
= intel_ring_begin(ring
, 6);
238 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
240 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
241 intel_ring_emit(ring
, 0);
242 intel_ring_emit(ring
, 0);
243 intel_ring_emit(ring
, MI_NOOP
);
244 intel_ring_advance(ring
);
250 gen6_render_ring_flush(struct intel_engine_cs
*ring
,
251 u32 invalidate_domains
, u32 flush_domains
)
254 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret
= intel_emit_post_sync_nonzero_flush(ring
);
262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
267 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
268 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
273 flags
|= PIPE_CONTROL_CS_STALL
;
275 if (invalidate_domains
) {
276 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
277 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
278 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
279 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
280 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
281 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
283 * TLB invalidate requires a post-sync write.
285 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
288 ret
= intel_ring_begin(ring
, 4);
292 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(ring
, flags
);
294 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
295 intel_ring_emit(ring
, 0);
296 intel_ring_advance(ring
);
302 gen7_render_ring_cs_stall_wa(struct intel_engine_cs
*ring
)
306 ret
= intel_ring_begin(ring
, 4);
310 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
312 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
313 intel_ring_emit(ring
, 0);
314 intel_ring_emit(ring
, 0);
315 intel_ring_advance(ring
);
320 static int gen7_ring_fbc_flush(struct intel_engine_cs
*ring
, u32 value
)
324 if (!ring
->fbc_dirty
)
327 ret
= intel_ring_begin(ring
, 6);
330 /* WaFbcNukeOn3DBlt:ivb/hsw */
331 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
332 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
333 intel_ring_emit(ring
, value
);
334 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
335 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
336 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
337 intel_ring_advance(ring
);
339 ring
->fbc_dirty
= false;
344 gen7_render_ring_flush(struct intel_engine_cs
*ring
,
345 u32 invalidate_domains
, u32 flush_domains
)
348 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
352 * Ensure that any following seqno writes only happen when the render
353 * cache is indeed flushed.
355 * Workaround: 4th PIPE_CONTROL command (except the ones with only
356 * read-cache invalidate bits set) must have the CS_STALL bit set. We
357 * don't try to be clever and just set it unconditionally.
359 flags
|= PIPE_CONTROL_CS_STALL
;
361 /* Just flush everything. Experiments have shown that reducing the
362 * number of bits based on the write domains has little performance
366 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
367 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
369 if (invalidate_domains
) {
370 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
371 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
372 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
373 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
374 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
375 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
377 * TLB invalidate requires a post-sync write.
379 flags
|= PIPE_CONTROL_QW_WRITE
;
380 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
382 /* Workaround: we must issue a pipe_control with CS-stall bit
383 * set before a pipe_control command that has the state cache
384 * invalidate bit set. */
385 gen7_render_ring_cs_stall_wa(ring
);
388 ret
= intel_ring_begin(ring
, 4);
392 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
393 intel_ring_emit(ring
, flags
);
394 intel_ring_emit(ring
, scratch_addr
);
395 intel_ring_emit(ring
, 0);
396 intel_ring_advance(ring
);
398 if (!invalidate_domains
&& flush_domains
)
399 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
405 gen8_emit_pipe_control(struct intel_engine_cs
*ring
,
406 u32 flags
, u32 scratch_addr
)
410 ret
= intel_ring_begin(ring
, 6);
414 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
415 intel_ring_emit(ring
, flags
);
416 intel_ring_emit(ring
, scratch_addr
);
417 intel_ring_emit(ring
, 0);
418 intel_ring_emit(ring
, 0);
419 intel_ring_emit(ring
, 0);
420 intel_ring_advance(ring
);
426 gen8_render_ring_flush(struct intel_engine_cs
*ring
,
427 u32 invalidate_domains
, u32 flush_domains
)
430 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
433 flags
|= PIPE_CONTROL_CS_STALL
;
436 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
437 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
439 if (invalidate_domains
) {
440 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
441 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
442 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
443 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
444 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
445 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
446 flags
|= PIPE_CONTROL_QW_WRITE
;
447 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
449 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
450 ret
= gen8_emit_pipe_control(ring
,
451 PIPE_CONTROL_CS_STALL
|
452 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
458 ret
= gen8_emit_pipe_control(ring
, flags
, scratch_addr
);
462 if (!invalidate_domains
&& flush_domains
)
463 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
468 static void ring_write_tail(struct intel_engine_cs
*ring
,
471 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 I915_WRITE_TAIL(ring
, value
);
475 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
477 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
480 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
481 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
482 RING_ACTHD_UDW(ring
->mmio_base
));
483 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
484 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
486 acthd
= I915_READ(ACTHD
);
491 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
493 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
496 addr
= dev_priv
->status_page_dmah
->busaddr
;
497 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
498 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
499 I915_WRITE(HWS_PGA
, addr
);
502 static bool stop_ring(struct intel_engine_cs
*ring
)
504 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
506 if (!IS_GEN2(ring
->dev
)) {
507 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
508 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
509 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
510 /* Sometimes we observe that the idle flag is not
511 * set even though the ring is empty. So double
512 * check before giving up.
514 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
519 I915_WRITE_CTL(ring
, 0);
520 I915_WRITE_HEAD(ring
, 0);
521 ring
->write_tail(ring
, 0);
523 if (!IS_GEN2(ring
->dev
)) {
524 (void)I915_READ_CTL(ring
);
525 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
528 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
531 static int init_ring_common(struct intel_engine_cs
*ring
)
533 struct drm_device
*dev
= ring
->dev
;
534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
535 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
536 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
539 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
541 if (!stop_ring(ring
)) {
542 /* G45 ring initialization often fails to reset head to zero */
543 DRM_DEBUG_KMS("%s head not reset to zero "
544 "ctl %08x head %08x tail %08x start %08x\n",
547 I915_READ_HEAD(ring
),
548 I915_READ_TAIL(ring
),
549 I915_READ_START(ring
));
551 if (!stop_ring(ring
)) {
552 DRM_ERROR("failed to set %s head to zero "
553 "ctl %08x head %08x tail %08x start %08x\n",
556 I915_READ_HEAD(ring
),
557 I915_READ_TAIL(ring
),
558 I915_READ_START(ring
));
564 if (I915_NEED_GFX_HWS(dev
))
565 intel_ring_setup_status_page(ring
);
567 ring_setup_phys_status_page(ring
);
569 /* Enforce ordering by reading HEAD register back */
570 I915_READ_HEAD(ring
);
572 /* Initialize the ring. This must happen _after_ we've cleared the ring
573 * registers with the above sequence (the readback of the HEAD registers
574 * also enforces ordering), otherwise the hw might lose the new ring
575 * register values. */
576 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
578 /* WaClearRingBufHeadRegAtInit:ctg,elk */
579 if (I915_READ_HEAD(ring
))
580 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
581 ring
->name
, I915_READ_HEAD(ring
));
582 I915_WRITE_HEAD(ring
, 0);
583 (void)I915_READ_HEAD(ring
);
586 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
589 /* If the head is still not zero, the ring is dead */
590 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
591 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
592 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
593 DRM_ERROR("%s initialization failed "
594 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
596 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
597 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
598 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
603 ringbuf
->last_retired_head
= -1;
604 ringbuf
->head
= I915_READ_HEAD(ring
);
605 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
606 intel_ring_update_space(ringbuf
);
608 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
611 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
617 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
619 struct drm_device
*dev
= ring
->dev
;
621 if (ring
->scratch
.obj
== NULL
)
624 if (INTEL_INFO(dev
)->gen
>= 5) {
625 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
626 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
629 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
630 ring
->scratch
.obj
= NULL
;
634 intel_init_pipe_control(struct intel_engine_cs
*ring
)
638 WARN_ON(ring
->scratch
.obj
);
640 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
641 if (ring
->scratch
.obj
== NULL
) {
642 DRM_ERROR("Failed to allocate seqno page\n");
647 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
651 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
655 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
656 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
657 if (ring
->scratch
.cpu_page
== NULL
) {
662 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
663 ring
->name
, ring
->scratch
.gtt_offset
);
667 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
669 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
674 static int intel_ring_workarounds_emit(struct intel_engine_cs
*ring
,
675 struct intel_context
*ctx
)
678 struct drm_device
*dev
= ring
->dev
;
679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
680 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
682 if (WARN_ON(w
->count
== 0))
685 ring
->gpu_caches_dirty
= true;
686 ret
= intel_ring_flush_all_caches(ring
);
690 ret
= intel_ring_begin(ring
, (w
->count
* 2 + 2));
694 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
695 for (i
= 0; i
< w
->count
; i
++) {
696 intel_ring_emit(ring
, w
->reg
[i
].addr
);
697 intel_ring_emit(ring
, w
->reg
[i
].value
);
699 intel_ring_emit(ring
, MI_NOOP
);
701 intel_ring_advance(ring
);
703 ring
->gpu_caches_dirty
= true;
704 ret
= intel_ring_flush_all_caches(ring
);
708 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
713 static int wa_add(struct drm_i915_private
*dev_priv
,
714 const u32 addr
, const u32 val
, const u32 mask
)
716 const u32 idx
= dev_priv
->workarounds
.count
;
718 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
721 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
722 dev_priv
->workarounds
.reg
[idx
].value
= val
;
723 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
725 dev_priv
->workarounds
.count
++;
730 #define WA_REG(addr, val, mask) { \
731 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
736 #define WA_SET_BIT_MASKED(addr, mask) \
737 WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
739 #define WA_CLR_BIT_MASKED(addr, mask) \
740 WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
742 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
743 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
745 #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
747 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
749 struct drm_device
*dev
= ring
->dev
;
750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
752 /* WaDisablePartialInstShootdown:bdw */
753 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
754 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
755 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
756 STALL_DOP_GATING_DISABLE
);
758 /* WaDisableDopClockGating:bdw */
759 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
760 DOP_CLOCK_GATING_DISABLE
);
762 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
763 GEN8_SAMPLER_POWER_BYPASS_DIS
);
765 /* Use Force Non-Coherent whenever executing a 3D context. This is a
766 * workaround for for a possible hang in the unlikely event a TLB
767 * invalidation occurs during a PSD flush.
769 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
770 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
771 HDC_FORCE_NON_COHERENT
|
772 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
774 /* Wa4x4STCOptimizationDisable:bdw */
775 WA_SET_BIT_MASKED(CACHE_MODE_1
,
776 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
779 * BSpec recommends 8x4 when MSAA is used,
780 * however in practice 16x4 seems fastest.
782 * Note that PS/WM thread counts depend on the WIZ hashing
783 * disable bit, which we don't touch here, but it's good
784 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
786 WA_SET_BIT_MASKED(GEN7_GT_MODE
,
787 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
792 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
794 struct drm_device
*dev
= ring
->dev
;
795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 /* WaDisablePartialInstShootdown:chv */
798 /* WaDisableThreadStallDopClockGating:chv */
799 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
800 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
801 STALL_DOP_GATING_DISABLE
);
803 /* Use Force Non-Coherent whenever executing a 3D context. This is a
804 * workaround for a possible hang in the unlikely event a TLB
805 * invalidation occurs during a PSD flush.
807 /* WaForceEnableNonCoherent:chv */
808 /* WaHdcDisableFetchWhenMasked:chv */
809 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
810 HDC_FORCE_NON_COHERENT
|
811 HDC_DONOT_FETCH_MEM_WHEN_MASKED
);
816 int init_workarounds_ring(struct intel_engine_cs
*ring
)
818 struct drm_device
*dev
= ring
->dev
;
819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
821 WARN_ON(ring
->id
!= RCS
);
823 dev_priv
->workarounds
.count
= 0;
825 if (IS_BROADWELL(dev
))
826 return bdw_init_workarounds(ring
);
828 if (IS_CHERRYVIEW(dev
))
829 return chv_init_workarounds(ring
);
834 static int init_render_ring(struct intel_engine_cs
*ring
)
836 struct drm_device
*dev
= ring
->dev
;
837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
838 int ret
= init_ring_common(ring
);
842 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
843 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
844 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
846 /* We need to disable the AsyncFlip performance optimisations in order
847 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
848 * programmed to '1' on all products.
850 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
852 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 9)
853 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
855 /* Required for the hardware to program scanline values for waiting */
856 /* WaEnableFlushTlbInvalidationMode:snb */
857 if (INTEL_INFO(dev
)->gen
== 6)
859 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
861 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
863 I915_WRITE(GFX_MODE_GEN7
,
864 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
865 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
868 /* From the Sandybridge PRM, volume 1 part 3, page 24:
869 * "If this bit is set, STCunit will have LRA as replacement
870 * policy. [...] This bit must be reset. LRA replacement
871 * policy is not supported."
873 I915_WRITE(CACHE_MODE_0
,
874 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
877 if (INTEL_INFO(dev
)->gen
>= 6)
878 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
881 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
883 return init_workarounds_ring(ring
);
886 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
888 struct drm_device
*dev
= ring
->dev
;
889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
891 if (dev_priv
->semaphore_obj
) {
892 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
893 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
894 dev_priv
->semaphore_obj
= NULL
;
897 intel_fini_pipe_control(ring
);
900 static int gen8_rcs_signal(struct intel_engine_cs
*signaller
,
901 unsigned int num_dwords
)
903 #define MBOX_UPDATE_DWORDS 8
904 struct drm_device
*dev
= signaller
->dev
;
905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
906 struct intel_engine_cs
*waiter
;
907 int i
, ret
, num_rings
;
909 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
910 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
911 #undef MBOX_UPDATE_DWORDS
913 ret
= intel_ring_begin(signaller
, num_dwords
);
917 for_each_ring(waiter
, dev_priv
, i
) {
919 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
920 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
923 seqno
= i915_gem_request_get_seqno(
924 signaller
->outstanding_lazy_request
);
925 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
926 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
927 PIPE_CONTROL_QW_WRITE
|
928 PIPE_CONTROL_FLUSH_ENABLE
);
929 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
930 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
931 intel_ring_emit(signaller
, seqno
);
932 intel_ring_emit(signaller
, 0);
933 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
934 MI_SEMAPHORE_TARGET(waiter
->id
));
935 intel_ring_emit(signaller
, 0);
941 static int gen8_xcs_signal(struct intel_engine_cs
*signaller
,
942 unsigned int num_dwords
)
944 #define MBOX_UPDATE_DWORDS 6
945 struct drm_device
*dev
= signaller
->dev
;
946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
947 struct intel_engine_cs
*waiter
;
948 int i
, ret
, num_rings
;
950 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
951 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
952 #undef MBOX_UPDATE_DWORDS
954 ret
= intel_ring_begin(signaller
, num_dwords
);
958 for_each_ring(waiter
, dev_priv
, i
) {
960 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
961 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
964 seqno
= i915_gem_request_get_seqno(
965 signaller
->outstanding_lazy_request
);
966 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
967 MI_FLUSH_DW_OP_STOREDW
);
968 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
969 MI_FLUSH_DW_USE_GTT
);
970 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
971 intel_ring_emit(signaller
, seqno
);
972 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
973 MI_SEMAPHORE_TARGET(waiter
->id
));
974 intel_ring_emit(signaller
, 0);
980 static int gen6_signal(struct intel_engine_cs
*signaller
,
981 unsigned int num_dwords
)
983 struct drm_device
*dev
= signaller
->dev
;
984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
985 struct intel_engine_cs
*useless
;
986 int i
, ret
, num_rings
;
988 #define MBOX_UPDATE_DWORDS 3
989 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
990 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
991 #undef MBOX_UPDATE_DWORDS
993 ret
= intel_ring_begin(signaller
, num_dwords
);
997 for_each_ring(useless
, dev_priv
, i
) {
998 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
999 if (mbox_reg
!= GEN6_NOSYNC
) {
1000 u32 seqno
= i915_gem_request_get_seqno(
1001 signaller
->outstanding_lazy_request
);
1002 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1003 intel_ring_emit(signaller
, mbox_reg
);
1004 intel_ring_emit(signaller
, seqno
);
1008 /* If num_dwords was rounded, make sure the tail pointer is correct */
1009 if (num_rings
% 2 == 0)
1010 intel_ring_emit(signaller
, MI_NOOP
);
1016 * gen6_add_request - Update the semaphore mailbox registers
1018 * @ring - ring that is adding a request
1019 * @seqno - return seqno stuck into the ring
1021 * Update the mailbox registers in the *other* rings with the current seqno.
1022 * This acts like a signal in the canonical semaphore.
1025 gen6_add_request(struct intel_engine_cs
*ring
)
1029 if (ring
->semaphore
.signal
)
1030 ret
= ring
->semaphore
.signal(ring
, 4);
1032 ret
= intel_ring_begin(ring
, 4);
1037 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1038 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1039 intel_ring_emit(ring
,
1040 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1041 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1042 __intel_ring_advance(ring
);
1047 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1051 return dev_priv
->last_seqno
< seqno
;
1055 * intel_ring_sync - sync the waiter to the signaller on seqno
1057 * @waiter - ring that is waiting
1058 * @signaller - ring which has, or will signal
1059 * @seqno - seqno which the waiter will block on
1063 gen8_ring_sync(struct intel_engine_cs
*waiter
,
1064 struct intel_engine_cs
*signaller
,
1067 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1070 ret
= intel_ring_begin(waiter
, 4);
1074 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1075 MI_SEMAPHORE_GLOBAL_GTT
|
1077 MI_SEMAPHORE_SAD_GTE_SDD
);
1078 intel_ring_emit(waiter
, seqno
);
1079 intel_ring_emit(waiter
,
1080 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1081 intel_ring_emit(waiter
,
1082 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1083 intel_ring_advance(waiter
);
1088 gen6_ring_sync(struct intel_engine_cs
*waiter
,
1089 struct intel_engine_cs
*signaller
,
1092 u32 dw1
= MI_SEMAPHORE_MBOX
|
1093 MI_SEMAPHORE_COMPARE
|
1094 MI_SEMAPHORE_REGISTER
;
1095 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1098 /* Throughout all of the GEM code, seqno passed implies our current
1099 * seqno is >= the last seqno executed. However for hardware the
1100 * comparison is strictly greater than.
1104 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1106 ret
= intel_ring_begin(waiter
, 4);
1110 /* If seqno wrap happened, omit the wait with no-ops */
1111 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1112 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1113 intel_ring_emit(waiter
, seqno
);
1114 intel_ring_emit(waiter
, 0);
1115 intel_ring_emit(waiter
, MI_NOOP
);
1117 intel_ring_emit(waiter
, MI_NOOP
);
1118 intel_ring_emit(waiter
, MI_NOOP
);
1119 intel_ring_emit(waiter
, MI_NOOP
);
1120 intel_ring_emit(waiter
, MI_NOOP
);
1122 intel_ring_advance(waiter
);
1127 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1129 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1130 PIPE_CONTROL_DEPTH_STALL); \
1131 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1132 intel_ring_emit(ring__, 0); \
1133 intel_ring_emit(ring__, 0); \
1137 pc_render_add_request(struct intel_engine_cs
*ring
)
1139 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1142 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1143 * incoherent with writes to memory, i.e. completely fubar,
1144 * so we need to use PIPE_NOTIFY instead.
1146 * However, we also need to workaround the qword write
1147 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1148 * memory before requesting an interrupt.
1150 ret
= intel_ring_begin(ring
, 32);
1154 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1155 PIPE_CONTROL_WRITE_FLUSH
|
1156 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1157 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1158 intel_ring_emit(ring
,
1159 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1160 intel_ring_emit(ring
, 0);
1161 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1162 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1163 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1164 scratch_addr
+= 2 * CACHELINE_BYTES
;
1165 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1166 scratch_addr
+= 2 * CACHELINE_BYTES
;
1167 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1168 scratch_addr
+= 2 * CACHELINE_BYTES
;
1169 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1170 scratch_addr
+= 2 * CACHELINE_BYTES
;
1171 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1173 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1174 PIPE_CONTROL_WRITE_FLUSH
|
1175 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1176 PIPE_CONTROL_NOTIFY
);
1177 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1178 intel_ring_emit(ring
,
1179 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1180 intel_ring_emit(ring
, 0);
1181 __intel_ring_advance(ring
);
1187 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1189 /* Workaround to force correct ordering between irq and seqno writes on
1190 * ivb (and maybe also on snb) by reading from a CS register (like
1191 * ACTHD) before reading the status page. */
1192 if (!lazy_coherency
) {
1193 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1194 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1197 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1201 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1203 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1207 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1209 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1213 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1215 return ring
->scratch
.cpu_page
[0];
1219 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1221 ring
->scratch
.cpu_page
[0] = seqno
;
1225 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1227 struct drm_device
*dev
= ring
->dev
;
1228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1229 unsigned long flags
;
1231 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1234 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1235 if (ring
->irq_refcount
++ == 0)
1236 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1237 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1243 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1245 struct drm_device
*dev
= ring
->dev
;
1246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1247 unsigned long flags
;
1249 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1250 if (--ring
->irq_refcount
== 0)
1251 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1252 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1256 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1258 struct drm_device
*dev
= ring
->dev
;
1259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1260 unsigned long flags
;
1262 if (!intel_irqs_enabled(dev_priv
))
1265 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1266 if (ring
->irq_refcount
++ == 0) {
1267 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1268 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1271 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1277 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1279 struct drm_device
*dev
= ring
->dev
;
1280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1281 unsigned long flags
;
1283 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1284 if (--ring
->irq_refcount
== 0) {
1285 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1286 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1289 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1293 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1295 struct drm_device
*dev
= ring
->dev
;
1296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1297 unsigned long flags
;
1299 if (!intel_irqs_enabled(dev_priv
))
1302 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1303 if (ring
->irq_refcount
++ == 0) {
1304 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1305 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1306 POSTING_READ16(IMR
);
1308 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1314 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1316 struct drm_device
*dev
= ring
->dev
;
1317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1318 unsigned long flags
;
1320 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1321 if (--ring
->irq_refcount
== 0) {
1322 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1323 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1324 POSTING_READ16(IMR
);
1326 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1329 void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
1331 struct drm_device
*dev
= ring
->dev
;
1332 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1335 /* The ring status page addresses are no longer next to the rest of
1336 * the ring registers as of gen7.
1341 mmio
= RENDER_HWS_PGA_GEN7
;
1344 mmio
= BLT_HWS_PGA_GEN7
;
1347 * VCS2 actually doesn't exist on Gen7. Only shut up
1348 * gcc switch check warning
1352 mmio
= BSD_HWS_PGA_GEN7
;
1355 mmio
= VEBOX_HWS_PGA_GEN7
;
1358 } else if (IS_GEN6(ring
->dev
)) {
1359 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
1361 /* XXX: gen8 returns to sanity */
1362 mmio
= RING_HWS_PGA(ring
->mmio_base
);
1365 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
1369 * Flush the TLB for this page
1371 * FIXME: These two bits have disappeared on gen8, so a question
1372 * arises: do we still need this and if so how should we go about
1373 * invalidating the TLB?
1375 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
1376 u32 reg
= RING_INSTPM(ring
->mmio_base
);
1378 /* ring should be idle before issuing a sync flush*/
1379 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1382 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
1383 INSTPM_SYNC_FLUSH
));
1384 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
1386 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1392 bsd_ring_flush(struct intel_engine_cs
*ring
,
1393 u32 invalidate_domains
,
1398 ret
= intel_ring_begin(ring
, 2);
1402 intel_ring_emit(ring
, MI_FLUSH
);
1403 intel_ring_emit(ring
, MI_NOOP
);
1404 intel_ring_advance(ring
);
1409 i9xx_add_request(struct intel_engine_cs
*ring
)
1413 ret
= intel_ring_begin(ring
, 4);
1417 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1418 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1419 intel_ring_emit(ring
,
1420 i915_gem_request_get_seqno(ring
->outstanding_lazy_request
));
1421 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1422 __intel_ring_advance(ring
);
1428 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1430 struct drm_device
*dev
= ring
->dev
;
1431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1432 unsigned long flags
;
1434 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1437 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1438 if (ring
->irq_refcount
++ == 0) {
1439 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1440 I915_WRITE_IMR(ring
,
1441 ~(ring
->irq_enable_mask
|
1442 GT_PARITY_ERROR(dev
)));
1444 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1445 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1447 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1453 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1455 struct drm_device
*dev
= ring
->dev
;
1456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1457 unsigned long flags
;
1459 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1460 if (--ring
->irq_refcount
== 0) {
1461 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1462 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1464 I915_WRITE_IMR(ring
, ~0);
1465 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1467 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1471 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1473 struct drm_device
*dev
= ring
->dev
;
1474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1475 unsigned long flags
;
1477 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1480 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1481 if (ring
->irq_refcount
++ == 0) {
1482 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1483 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1485 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1491 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1493 struct drm_device
*dev
= ring
->dev
;
1494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1495 unsigned long flags
;
1497 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1498 if (--ring
->irq_refcount
== 0) {
1499 I915_WRITE_IMR(ring
, ~0);
1500 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1502 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1506 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1508 struct drm_device
*dev
= ring
->dev
;
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 unsigned long flags
;
1512 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1515 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1516 if (ring
->irq_refcount
++ == 0) {
1517 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1518 I915_WRITE_IMR(ring
,
1519 ~(ring
->irq_enable_mask
|
1520 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1522 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1524 POSTING_READ(RING_IMR(ring
->mmio_base
));
1526 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1532 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1534 struct drm_device
*dev
= ring
->dev
;
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 unsigned long flags
;
1538 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1539 if (--ring
->irq_refcount
== 0) {
1540 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1541 I915_WRITE_IMR(ring
,
1542 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1544 I915_WRITE_IMR(ring
, ~0);
1546 POSTING_READ(RING_IMR(ring
->mmio_base
));
1548 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1552 i965_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1553 u64 offset
, u32 length
,
1558 ret
= intel_ring_begin(ring
, 2);
1562 intel_ring_emit(ring
,
1563 MI_BATCH_BUFFER_START
|
1565 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1566 intel_ring_emit(ring
, offset
);
1567 intel_ring_advance(ring
);
1572 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1573 #define I830_BATCH_LIMIT (256*1024)
1574 #define I830_TLB_ENTRIES (2)
1575 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1577 i830_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1578 u64 offset
, u32 len
,
1581 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1584 ret
= intel_ring_begin(ring
, 6);
1588 /* Evict the invalid PTE TLBs */
1589 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1590 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1591 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1592 intel_ring_emit(ring
, cs_offset
);
1593 intel_ring_emit(ring
, 0xdeadbeef);
1594 intel_ring_emit(ring
, MI_NOOP
);
1595 intel_ring_advance(ring
);
1597 if ((flags
& I915_DISPATCH_PINNED
) == 0) {
1598 if (len
> I830_BATCH_LIMIT
)
1601 ret
= intel_ring_begin(ring
, 6 + 2);
1605 /* Blit the batch (which has now all relocs applied) to the
1606 * stable batch scratch bo area (so that the CS never
1607 * stumbles over its tlb invalidation bug) ...
1609 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1610 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1611 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1612 intel_ring_emit(ring
, cs_offset
);
1613 intel_ring_emit(ring
, 4096);
1614 intel_ring_emit(ring
, offset
);
1616 intel_ring_emit(ring
, MI_FLUSH
);
1617 intel_ring_emit(ring
, MI_NOOP
);
1618 intel_ring_advance(ring
);
1620 /* ... and execute it. */
1624 ret
= intel_ring_begin(ring
, 4);
1628 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1629 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1630 intel_ring_emit(ring
, offset
+ len
- 8);
1631 intel_ring_emit(ring
, MI_NOOP
);
1632 intel_ring_advance(ring
);
1638 i915_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1639 u64 offset
, u32 len
,
1644 ret
= intel_ring_begin(ring
, 2);
1648 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1649 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1650 intel_ring_advance(ring
);
1655 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1657 struct drm_i915_gem_object
*obj
;
1659 obj
= ring
->status_page
.obj
;
1663 kunmap(sg_page(obj
->pages
->sgl
));
1664 i915_gem_object_ggtt_unpin(obj
);
1665 drm_gem_object_unreference(&obj
->base
);
1666 ring
->status_page
.obj
= NULL
;
1669 static int init_status_page(struct intel_engine_cs
*ring
)
1671 struct drm_i915_gem_object
*obj
;
1673 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1677 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1679 DRM_ERROR("Failed to allocate status page\n");
1683 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1688 if (!HAS_LLC(ring
->dev
))
1689 /* On g33, we cannot place HWS above 256MiB, so
1690 * restrict its pinning to the low mappable arena.
1691 * Though this restriction is not documented for
1692 * gen4, gen5, or byt, they also behave similarly
1693 * and hang if the HWS is placed at the top of the
1694 * GTT. To generalise, it appears that all !llc
1695 * platforms have issues with us placing the HWS
1696 * above the mappable region (even though we never
1699 flags
|= PIN_MAPPABLE
;
1700 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1703 drm_gem_object_unreference(&obj
->base
);
1707 ring
->status_page
.obj
= obj
;
1710 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1711 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1712 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1714 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1715 ring
->name
, ring
->status_page
.gfx_addr
);
1720 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1722 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1724 if (!dev_priv
->status_page_dmah
) {
1725 dev_priv
->status_page_dmah
=
1726 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1727 if (!dev_priv
->status_page_dmah
)
1731 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1732 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1737 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1739 iounmap(ringbuf
->virtual_start
);
1740 ringbuf
->virtual_start
= NULL
;
1741 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1744 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
1745 struct intel_ringbuffer
*ringbuf
)
1747 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1748 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
1751 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1755 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1757 i915_gem_object_ggtt_unpin(obj
);
1761 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
1762 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
1763 if (ringbuf
->virtual_start
== NULL
) {
1764 i915_gem_object_ggtt_unpin(obj
);
1771 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1773 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1774 ringbuf
->obj
= NULL
;
1777 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1778 struct intel_ringbuffer
*ringbuf
)
1780 struct drm_i915_gem_object
*obj
;
1784 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
1786 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
1790 /* mark ring buffers as read-only from GPU side by default */
1798 static int intel_init_ring_buffer(struct drm_device
*dev
,
1799 struct intel_engine_cs
*ring
)
1801 struct intel_ringbuffer
*ringbuf
;
1804 WARN_ON(ring
->buffer
);
1806 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1809 ring
->buffer
= ringbuf
;
1812 INIT_LIST_HEAD(&ring
->active_list
);
1813 INIT_LIST_HEAD(&ring
->request_list
);
1814 INIT_LIST_HEAD(&ring
->execlist_queue
);
1815 ringbuf
->size
= 32 * PAGE_SIZE
;
1816 ringbuf
->ring
= ring
;
1817 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
1819 init_waitqueue_head(&ring
->irq_queue
);
1821 if (I915_NEED_GFX_HWS(dev
)) {
1822 ret
= init_status_page(ring
);
1826 BUG_ON(ring
->id
!= RCS
);
1827 ret
= init_phys_status_page(ring
);
1832 WARN_ON(ringbuf
->obj
);
1834 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1836 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1841 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
1843 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1845 intel_destroy_ringbuffer_obj(ringbuf
);
1849 /* Workaround an erratum on the i830 which causes a hang if
1850 * the TAIL pointer points to within the last 2 cachelines
1853 ringbuf
->effective_size
= ringbuf
->size
;
1854 if (IS_I830(dev
) || IS_845G(dev
))
1855 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
1857 ret
= i915_cmd_parser_init_ring(ring
);
1865 ring
->buffer
= NULL
;
1869 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
1871 struct drm_i915_private
*dev_priv
;
1872 struct intel_ringbuffer
*ringbuf
;
1874 if (!intel_ring_initialized(ring
))
1877 dev_priv
= to_i915(ring
->dev
);
1878 ringbuf
= ring
->buffer
;
1880 intel_stop_ring_buffer(ring
);
1881 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1883 intel_unpin_ringbuffer_obj(ringbuf
);
1884 intel_destroy_ringbuffer_obj(ringbuf
);
1885 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
1888 ring
->cleanup(ring
);
1890 cleanup_status_page(ring
);
1892 i915_cmd_parser_fini_ring(ring
);
1895 ring
->buffer
= NULL
;
1898 static int intel_ring_wait_request(struct intel_engine_cs
*ring
, int n
)
1900 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1901 struct drm_i915_gem_request
*request
;
1904 if (intel_ring_space(ringbuf
) >= n
)
1907 list_for_each_entry(request
, &ring
->request_list
, list
) {
1908 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
1909 ringbuf
->size
) >= n
) {
1914 if (&request
->list
== &ring
->request_list
)
1917 ret
= i915_wait_request(request
);
1921 i915_gem_retire_requests_ring(ring
);
1926 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
1928 struct drm_device
*dev
= ring
->dev
;
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1930 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1934 ret
= intel_ring_wait_request(ring
, n
);
1938 /* force the tail write in case we have been skipping them */
1939 __intel_ring_advance(ring
);
1941 /* With GEM the hangcheck timer should kick us out of the loop,
1942 * leaving it early runs the risk of corrupting GEM state (due
1943 * to running on almost untested codepaths). But on resume
1944 * timers don't work yet, so prevent a complete hang in that
1945 * case by choosing an insanely large timeout. */
1946 end
= jiffies
+ 60 * HZ
;
1949 trace_i915_ring_wait_begin(ring
);
1951 if (intel_ring_space(ringbuf
) >= n
)
1953 ringbuf
->head
= I915_READ_HEAD(ring
);
1954 if (intel_ring_space(ringbuf
) >= n
)
1959 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
1964 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1965 dev_priv
->mm
.interruptible
);
1969 if (time_after(jiffies
, end
)) {
1974 trace_i915_ring_wait_end(ring
);
1978 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
1980 uint32_t __iomem
*virt
;
1981 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1982 int rem
= ringbuf
->size
- ringbuf
->tail
;
1984 if (ringbuf
->space
< rem
) {
1985 int ret
= ring_wait_for_space(ring
, rem
);
1990 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
1993 iowrite32(MI_NOOP
, virt
++);
1996 intel_ring_update_space(ringbuf
);
2001 int intel_ring_idle(struct intel_engine_cs
*ring
)
2003 struct drm_i915_gem_request
*req
;
2006 /* We need to add any requests required to flush the objects and ring */
2007 if (ring
->outstanding_lazy_request
) {
2008 ret
= i915_add_request(ring
);
2013 /* Wait upon the last request to be completed */
2014 if (list_empty(&ring
->request_list
))
2017 req
= list_entry(ring
->request_list
.prev
,
2018 struct drm_i915_gem_request
,
2021 return i915_wait_request(req
);
2025 intel_ring_alloc_request(struct intel_engine_cs
*ring
)
2028 struct drm_i915_gem_request
*request
;
2030 if (ring
->outstanding_lazy_request
)
2033 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2034 if (request
== NULL
)
2037 kref_init(&request
->ref
);
2038 request
->ring
= ring
;
2040 ret
= i915_gem_get_seqno(ring
->dev
, &request
->seqno
);
2046 ring
->outstanding_lazy_request
= request
;
2050 static int __intel_ring_prepare(struct intel_engine_cs
*ring
,
2053 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2056 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2057 ret
= intel_wrap_ring_buffer(ring
);
2062 if (unlikely(ringbuf
->space
< bytes
)) {
2063 ret
= ring_wait_for_space(ring
, bytes
);
2071 int intel_ring_begin(struct intel_engine_cs
*ring
,
2074 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2077 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2078 dev_priv
->mm
.interruptible
);
2082 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2086 /* Preallocate the olr before touching the ring */
2087 ret
= intel_ring_alloc_request(ring
);
2091 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2095 /* Align the ring tail to a cacheline boundary */
2096 int intel_ring_cacheline_align(struct intel_engine_cs
*ring
)
2098 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2101 if (num_dwords
== 0)
2104 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2105 ret
= intel_ring_begin(ring
, num_dwords
);
2109 while (num_dwords
--)
2110 intel_ring_emit(ring
, MI_NOOP
);
2112 intel_ring_advance(ring
);
2117 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2119 struct drm_device
*dev
= ring
->dev
;
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2122 BUG_ON(ring
->outstanding_lazy_request
);
2124 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2125 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2126 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2128 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2131 ring
->set_seqno(ring
, seqno
);
2132 ring
->hangcheck
.seqno
= seqno
;
2135 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2138 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2140 /* Every tail move must follow the sequence below */
2142 /* Disable notification that the ring is IDLE. The GT
2143 * will then assume that it is busy and bring it out of rc6.
2145 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2146 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2148 /* Clear the context id. Here be magic! */
2149 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2151 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2152 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2153 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2155 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2157 /* Now that the ring is fully powered up, update the tail */
2158 I915_WRITE_TAIL(ring
, value
);
2159 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2161 /* Let the ring send IDLE messages to the GT again,
2162 * and so let it sleep to conserve power when idle.
2164 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2165 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2168 static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring
,
2169 u32 invalidate
, u32 flush
)
2174 ret
= intel_ring_begin(ring
, 4);
2179 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2182 * Bspec vol 1c.5 - video engine command streamer:
2183 * "If ENABLED, all TLBs will be invalidated once the flush
2184 * operation is complete. This bit is only valid when the
2185 * Post-Sync Operation field is a value of 1h or 3h."
2187 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2188 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
2189 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2190 intel_ring_emit(ring
, cmd
);
2191 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2192 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2193 intel_ring_emit(ring
, 0); /* upper addr */
2194 intel_ring_emit(ring
, 0); /* value */
2196 intel_ring_emit(ring
, 0);
2197 intel_ring_emit(ring
, MI_NOOP
);
2199 intel_ring_advance(ring
);
2204 gen8_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2205 u64 offset
, u32 len
,
2208 bool ppgtt
= USES_PPGTT(ring
->dev
) && !(flags
& I915_DISPATCH_SECURE
);
2211 ret
= intel_ring_begin(ring
, 4);
2215 /* FIXME(BDW): Address space and security selectors. */
2216 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2217 intel_ring_emit(ring
, lower_32_bits(offset
));
2218 intel_ring_emit(ring
, upper_32_bits(offset
));
2219 intel_ring_emit(ring
, MI_NOOP
);
2220 intel_ring_advance(ring
);
2226 hsw_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2227 u64 offset
, u32 len
,
2232 ret
= intel_ring_begin(ring
, 2);
2236 intel_ring_emit(ring
,
2237 MI_BATCH_BUFFER_START
|
2238 (flags
& I915_DISPATCH_SECURE
?
2239 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
));
2240 /* bit0-7 is the length on GEN6+ */
2241 intel_ring_emit(ring
, offset
);
2242 intel_ring_advance(ring
);
2248 gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2249 u64 offset
, u32 len
,
2254 ret
= intel_ring_begin(ring
, 2);
2258 intel_ring_emit(ring
,
2259 MI_BATCH_BUFFER_START
|
2260 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
2261 /* bit0-7 is the length on GEN6+ */
2262 intel_ring_emit(ring
, offset
);
2263 intel_ring_advance(ring
);
2268 /* Blitter support (SandyBridge+) */
2270 static int gen6_ring_flush(struct intel_engine_cs
*ring
,
2271 u32 invalidate
, u32 flush
)
2273 struct drm_device
*dev
= ring
->dev
;
2274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2278 ret
= intel_ring_begin(ring
, 4);
2283 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2286 * Bspec vol 1c.3 - blitter engine command streamer:
2287 * "If ENABLED, all TLBs will be invalidated once the flush
2288 * operation is complete. This bit is only valid when the
2289 * Post-Sync Operation field is a value of 1h or 3h."
2291 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2292 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
2293 MI_FLUSH_DW_OP_STOREDW
;
2294 intel_ring_emit(ring
, cmd
);
2295 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2296 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2297 intel_ring_emit(ring
, 0); /* upper addr */
2298 intel_ring_emit(ring
, 0); /* value */
2300 intel_ring_emit(ring
, 0);
2301 intel_ring_emit(ring
, MI_NOOP
);
2303 intel_ring_advance(ring
);
2305 if (!invalidate
&& flush
) {
2307 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
2308 else if (IS_BROADWELL(dev
))
2309 dev_priv
->fbc
.need_sw_cache_clean
= true;
2315 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2318 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2319 struct drm_i915_gem_object
*obj
;
2322 ring
->name
= "render ring";
2324 ring
->mmio_base
= RENDER_RING_BASE
;
2326 if (INTEL_INFO(dev
)->gen
>= 8) {
2327 if (i915_semaphore_is_enabled(dev
)) {
2328 obj
= i915_gem_alloc_object(dev
, 4096);
2330 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2331 i915
.semaphores
= 0;
2333 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2334 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2336 drm_gem_object_unreference(&obj
->base
);
2337 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2338 i915
.semaphores
= 0;
2340 dev_priv
->semaphore_obj
= obj
;
2344 ring
->init_context
= intel_ring_workarounds_emit
;
2345 ring
->add_request
= gen6_add_request
;
2346 ring
->flush
= gen8_render_ring_flush
;
2347 ring
->irq_get
= gen8_ring_get_irq
;
2348 ring
->irq_put
= gen8_ring_put_irq
;
2349 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2350 ring
->get_seqno
= gen6_ring_get_seqno
;
2351 ring
->set_seqno
= ring_set_seqno
;
2352 if (i915_semaphore_is_enabled(dev
)) {
2353 WARN_ON(!dev_priv
->semaphore_obj
);
2354 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2355 ring
->semaphore
.signal
= gen8_rcs_signal
;
2356 GEN8_RING_SEMAPHORE_INIT
;
2358 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2359 ring
->add_request
= gen6_add_request
;
2360 ring
->flush
= gen7_render_ring_flush
;
2361 if (INTEL_INFO(dev
)->gen
== 6)
2362 ring
->flush
= gen6_render_ring_flush
;
2363 ring
->irq_get
= gen6_ring_get_irq
;
2364 ring
->irq_put
= gen6_ring_put_irq
;
2365 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2366 ring
->get_seqno
= gen6_ring_get_seqno
;
2367 ring
->set_seqno
= ring_set_seqno
;
2368 if (i915_semaphore_is_enabled(dev
)) {
2369 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2370 ring
->semaphore
.signal
= gen6_signal
;
2372 * The current semaphore is only applied on pre-gen8
2373 * platform. And there is no VCS2 ring on the pre-gen8
2374 * platform. So the semaphore between RCS and VCS2 is
2375 * initialized as INVALID. Gen8 will initialize the
2376 * sema between VCS2 and RCS later.
2378 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2379 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2380 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2381 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2382 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2383 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2384 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2385 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2386 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2387 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2389 } else if (IS_GEN5(dev
)) {
2390 ring
->add_request
= pc_render_add_request
;
2391 ring
->flush
= gen4_render_ring_flush
;
2392 ring
->get_seqno
= pc_render_get_seqno
;
2393 ring
->set_seqno
= pc_render_set_seqno
;
2394 ring
->irq_get
= gen5_ring_get_irq
;
2395 ring
->irq_put
= gen5_ring_put_irq
;
2396 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2397 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2399 ring
->add_request
= i9xx_add_request
;
2400 if (INTEL_INFO(dev
)->gen
< 4)
2401 ring
->flush
= gen2_render_ring_flush
;
2403 ring
->flush
= gen4_render_ring_flush
;
2404 ring
->get_seqno
= ring_get_seqno
;
2405 ring
->set_seqno
= ring_set_seqno
;
2407 ring
->irq_get
= i8xx_ring_get_irq
;
2408 ring
->irq_put
= i8xx_ring_put_irq
;
2410 ring
->irq_get
= i9xx_ring_get_irq
;
2411 ring
->irq_put
= i9xx_ring_put_irq
;
2413 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2415 ring
->write_tail
= ring_write_tail
;
2417 if (IS_HASWELL(dev
))
2418 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2419 else if (IS_GEN8(dev
))
2420 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2421 else if (INTEL_INFO(dev
)->gen
>= 6)
2422 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2423 else if (INTEL_INFO(dev
)->gen
>= 4)
2424 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2425 else if (IS_I830(dev
) || IS_845G(dev
))
2426 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2428 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2429 ring
->init_hw
= init_render_ring
;
2430 ring
->cleanup
= render_ring_cleanup
;
2432 /* Workaround batchbuffer to combat CS tlb bug. */
2433 if (HAS_BROKEN_CS_TLB(dev
)) {
2434 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2436 DRM_ERROR("Failed to allocate batch bo\n");
2440 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2442 drm_gem_object_unreference(&obj
->base
);
2443 DRM_ERROR("Failed to ping batch bo\n");
2447 ring
->scratch
.obj
= obj
;
2448 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2451 ret
= intel_init_ring_buffer(dev
, ring
);
2455 if (INTEL_INFO(dev
)->gen
>= 5) {
2456 ret
= intel_init_pipe_control(ring
);
2464 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2467 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2469 ring
->name
= "bsd ring";
2472 ring
->write_tail
= ring_write_tail
;
2473 if (INTEL_INFO(dev
)->gen
>= 6) {
2474 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2475 /* gen6 bsd needs a special wa for tail updates */
2477 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2478 ring
->flush
= gen6_bsd_ring_flush
;
2479 ring
->add_request
= gen6_add_request
;
2480 ring
->get_seqno
= gen6_ring_get_seqno
;
2481 ring
->set_seqno
= ring_set_seqno
;
2482 if (INTEL_INFO(dev
)->gen
>= 8) {
2483 ring
->irq_enable_mask
=
2484 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2485 ring
->irq_get
= gen8_ring_get_irq
;
2486 ring
->irq_put
= gen8_ring_put_irq
;
2487 ring
->dispatch_execbuffer
=
2488 gen8_ring_dispatch_execbuffer
;
2489 if (i915_semaphore_is_enabled(dev
)) {
2490 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2491 ring
->semaphore
.signal
= gen8_xcs_signal
;
2492 GEN8_RING_SEMAPHORE_INIT
;
2495 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2496 ring
->irq_get
= gen6_ring_get_irq
;
2497 ring
->irq_put
= gen6_ring_put_irq
;
2498 ring
->dispatch_execbuffer
=
2499 gen6_ring_dispatch_execbuffer
;
2500 if (i915_semaphore_is_enabled(dev
)) {
2501 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2502 ring
->semaphore
.signal
= gen6_signal
;
2503 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2504 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2505 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2506 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2507 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2508 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2509 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2510 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2511 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2512 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2516 ring
->mmio_base
= BSD_RING_BASE
;
2517 ring
->flush
= bsd_ring_flush
;
2518 ring
->add_request
= i9xx_add_request
;
2519 ring
->get_seqno
= ring_get_seqno
;
2520 ring
->set_seqno
= ring_set_seqno
;
2522 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2523 ring
->irq_get
= gen5_ring_get_irq
;
2524 ring
->irq_put
= gen5_ring_put_irq
;
2526 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2527 ring
->irq_get
= i9xx_ring_get_irq
;
2528 ring
->irq_put
= i9xx_ring_put_irq
;
2530 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2532 ring
->init_hw
= init_ring_common
;
2534 return intel_init_ring_buffer(dev
, ring
);
2538 * Initialize the second BSD ring for Broadwell GT3.
2539 * It is noted that this only exists on Broadwell GT3.
2541 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2544 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2546 if ((INTEL_INFO(dev
)->gen
!= 8)) {
2547 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2551 ring
->name
= "bsd2 ring";
2554 ring
->write_tail
= ring_write_tail
;
2555 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2556 ring
->flush
= gen6_bsd_ring_flush
;
2557 ring
->add_request
= gen6_add_request
;
2558 ring
->get_seqno
= gen6_ring_get_seqno
;
2559 ring
->set_seqno
= ring_set_seqno
;
2560 ring
->irq_enable_mask
=
2561 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2562 ring
->irq_get
= gen8_ring_get_irq
;
2563 ring
->irq_put
= gen8_ring_put_irq
;
2564 ring
->dispatch_execbuffer
=
2565 gen8_ring_dispatch_execbuffer
;
2566 if (i915_semaphore_is_enabled(dev
)) {
2567 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2568 ring
->semaphore
.signal
= gen8_xcs_signal
;
2569 GEN8_RING_SEMAPHORE_INIT
;
2571 ring
->init_hw
= init_ring_common
;
2573 return intel_init_ring_buffer(dev
, ring
);
2576 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2579 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2581 ring
->name
= "blitter ring";
2584 ring
->mmio_base
= BLT_RING_BASE
;
2585 ring
->write_tail
= ring_write_tail
;
2586 ring
->flush
= gen6_ring_flush
;
2587 ring
->add_request
= gen6_add_request
;
2588 ring
->get_seqno
= gen6_ring_get_seqno
;
2589 ring
->set_seqno
= ring_set_seqno
;
2590 if (INTEL_INFO(dev
)->gen
>= 8) {
2591 ring
->irq_enable_mask
=
2592 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2593 ring
->irq_get
= gen8_ring_get_irq
;
2594 ring
->irq_put
= gen8_ring_put_irq
;
2595 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2596 if (i915_semaphore_is_enabled(dev
)) {
2597 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2598 ring
->semaphore
.signal
= gen8_xcs_signal
;
2599 GEN8_RING_SEMAPHORE_INIT
;
2602 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2603 ring
->irq_get
= gen6_ring_get_irq
;
2604 ring
->irq_put
= gen6_ring_put_irq
;
2605 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2606 if (i915_semaphore_is_enabled(dev
)) {
2607 ring
->semaphore
.signal
= gen6_signal
;
2608 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2610 * The current semaphore is only applied on pre-gen8
2611 * platform. And there is no VCS2 ring on the pre-gen8
2612 * platform. So the semaphore between BCS and VCS2 is
2613 * initialized as INVALID. Gen8 will initialize the
2614 * sema between BCS and VCS2 later.
2616 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2617 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2618 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2619 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2620 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2621 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2622 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2623 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2624 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2625 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2628 ring
->init_hw
= init_ring_common
;
2630 return intel_init_ring_buffer(dev
, ring
);
2633 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2636 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2638 ring
->name
= "video enhancement ring";
2641 ring
->mmio_base
= VEBOX_RING_BASE
;
2642 ring
->write_tail
= ring_write_tail
;
2643 ring
->flush
= gen6_ring_flush
;
2644 ring
->add_request
= gen6_add_request
;
2645 ring
->get_seqno
= gen6_ring_get_seqno
;
2646 ring
->set_seqno
= ring_set_seqno
;
2648 if (INTEL_INFO(dev
)->gen
>= 8) {
2649 ring
->irq_enable_mask
=
2650 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2651 ring
->irq_get
= gen8_ring_get_irq
;
2652 ring
->irq_put
= gen8_ring_put_irq
;
2653 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2654 if (i915_semaphore_is_enabled(dev
)) {
2655 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2656 ring
->semaphore
.signal
= gen8_xcs_signal
;
2657 GEN8_RING_SEMAPHORE_INIT
;
2660 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2661 ring
->irq_get
= hsw_vebox_get_irq
;
2662 ring
->irq_put
= hsw_vebox_put_irq
;
2663 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2664 if (i915_semaphore_is_enabled(dev
)) {
2665 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2666 ring
->semaphore
.signal
= gen6_signal
;
2667 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2668 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2669 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2670 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2671 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2672 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2673 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2674 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2675 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2676 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2679 ring
->init_hw
= init_ring_common
;
2681 return intel_init_ring_buffer(dev
, ring
);
2685 intel_ring_flush_all_caches(struct intel_engine_cs
*ring
)
2689 if (!ring
->gpu_caches_dirty
)
2692 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2696 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2698 ring
->gpu_caches_dirty
= false;
2703 intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
)
2705 uint32_t flush_domains
;
2709 if (ring
->gpu_caches_dirty
)
2710 flush_domains
= I915_GEM_GPU_DOMAINS
;
2712 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2716 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2718 ring
->gpu_caches_dirty
= false;
2723 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2727 if (!intel_ring_initialized(ring
))
2730 ret
= intel_ring_idle(ring
);
2731 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2732 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",