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drm/i915: Replace the array of pages with a scatterlist
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 ret = intel_emit_post_sync_nonzero_flush(ring);
223 if (ret)
224 return ret;
225
226 /* Just flush everything. Experiments have shown that reducing the
227 * number of bits based on the write domains has little performance
228 * impact.
229 */
230 if (flush_domains) {
231 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
233 /*
234 * Ensure that any following seqno writes only happen
235 * when the render cache is indeed flushed.
236 */
237 flags |= PIPE_CONTROL_CS_STALL;
238 }
239 if (invalidate_domains) {
240 flags |= PIPE_CONTROL_TLB_INVALIDATE;
241 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
245 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
246 /*
247 * TLB invalidate requires a post-sync write.
248 */
249 flags |= PIPE_CONTROL_QW_WRITE;
250 }
251
252 ret = intel_ring_begin(ring, 4);
253 if (ret)
254 return ret;
255
256 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
257 intel_ring_emit(ring, flags);
258 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
259 intel_ring_emit(ring, 0);
260 intel_ring_advance(ring);
261
262 return 0;
263 }
264
265 static int
266 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
267 {
268 int ret;
269
270 ret = intel_ring_begin(ring, 4);
271 if (ret)
272 return ret;
273
274 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
275 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
276 PIPE_CONTROL_STALL_AT_SCOREBOARD);
277 intel_ring_emit(ring, 0);
278 intel_ring_emit(ring, 0);
279 intel_ring_advance(ring);
280
281 return 0;
282 }
283
284 static int
285 gen7_render_ring_flush(struct intel_ring_buffer *ring,
286 u32 invalidate_domains, u32 flush_domains)
287 {
288 u32 flags = 0;
289 struct pipe_control *pc = ring->private;
290 u32 scratch_addr = pc->gtt_offset + 128;
291 int ret;
292
293 /*
294 * Ensure that any following seqno writes only happen when the render
295 * cache is indeed flushed.
296 *
297 * Workaround: 4th PIPE_CONTROL command (except the ones with only
298 * read-cache invalidate bits set) must have the CS_STALL bit set. We
299 * don't try to be clever and just set it unconditionally.
300 */
301 flags |= PIPE_CONTROL_CS_STALL;
302
303 /* Just flush everything. Experiments have shown that reducing the
304 * number of bits based on the write domains has little performance
305 * impact.
306 */
307 if (flush_domains) {
308 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
309 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
310 }
311 if (invalidate_domains) {
312 flags |= PIPE_CONTROL_TLB_INVALIDATE;
313 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
317 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
318 /*
319 * TLB invalidate requires a post-sync write.
320 */
321 flags |= PIPE_CONTROL_QW_WRITE;
322
323 /* Workaround: we must issue a pipe_control with CS-stall bit
324 * set before a pipe_control command that has the state cache
325 * invalidate bit set. */
326 gen7_render_ring_cs_stall_wa(ring);
327 }
328
329 ret = intel_ring_begin(ring, 4);
330 if (ret)
331 return ret;
332
333 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
334 intel_ring_emit(ring, flags);
335 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
336 intel_ring_emit(ring, 0);
337 intel_ring_advance(ring);
338
339 return 0;
340 }
341
342 static void ring_write_tail(struct intel_ring_buffer *ring,
343 u32 value)
344 {
345 drm_i915_private_t *dev_priv = ring->dev->dev_private;
346 I915_WRITE_TAIL(ring, value);
347 }
348
349 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
350 {
351 drm_i915_private_t *dev_priv = ring->dev->dev_private;
352 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
353 RING_ACTHD(ring->mmio_base) : ACTHD;
354
355 return I915_READ(acthd_reg);
356 }
357
358 static int init_ring_common(struct intel_ring_buffer *ring)
359 {
360 struct drm_device *dev = ring->dev;
361 drm_i915_private_t *dev_priv = dev->dev_private;
362 struct drm_i915_gem_object *obj = ring->obj;
363 int ret = 0;
364 u32 head;
365
366 if (HAS_FORCE_WAKE(dev))
367 gen6_gt_force_wake_get(dev_priv);
368
369 /* Stop the ring if it's running. */
370 I915_WRITE_CTL(ring, 0);
371 I915_WRITE_HEAD(ring, 0);
372 ring->write_tail(ring, 0);
373
374 head = I915_READ_HEAD(ring) & HEAD_ADDR;
375
376 /* G45 ring initialization fails to reset head to zero */
377 if (head != 0) {
378 DRM_DEBUG_KMS("%s head not reset to zero "
379 "ctl %08x head %08x tail %08x start %08x\n",
380 ring->name,
381 I915_READ_CTL(ring),
382 I915_READ_HEAD(ring),
383 I915_READ_TAIL(ring),
384 I915_READ_START(ring));
385
386 I915_WRITE_HEAD(ring, 0);
387
388 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
389 DRM_ERROR("failed to set %s head to zero "
390 "ctl %08x head %08x tail %08x start %08x\n",
391 ring->name,
392 I915_READ_CTL(ring),
393 I915_READ_HEAD(ring),
394 I915_READ_TAIL(ring),
395 I915_READ_START(ring));
396 }
397 }
398
399 /* Initialize the ring. This must happen _after_ we've cleared the ring
400 * registers with the above sequence (the readback of the HEAD registers
401 * also enforces ordering), otherwise the hw might lose the new ring
402 * register values. */
403 I915_WRITE_START(ring, obj->gtt_offset);
404 I915_WRITE_CTL(ring,
405 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
406 | RING_VALID);
407
408 /* If the head is still not zero, the ring is dead */
409 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
410 I915_READ_START(ring) == obj->gtt_offset &&
411 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
412 DRM_ERROR("%s initialization failed "
413 "ctl %08x head %08x tail %08x start %08x\n",
414 ring->name,
415 I915_READ_CTL(ring),
416 I915_READ_HEAD(ring),
417 I915_READ_TAIL(ring),
418 I915_READ_START(ring));
419 ret = -EIO;
420 goto out;
421 }
422
423 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
424 i915_kernel_lost_context(ring->dev);
425 else {
426 ring->head = I915_READ_HEAD(ring);
427 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
428 ring->space = ring_space(ring);
429 ring->last_retired_head = -1;
430 }
431
432 out:
433 if (HAS_FORCE_WAKE(dev))
434 gen6_gt_force_wake_put(dev_priv);
435
436 return ret;
437 }
438
439 static int
440 init_pipe_control(struct intel_ring_buffer *ring)
441 {
442 struct pipe_control *pc;
443 struct drm_i915_gem_object *obj;
444 int ret;
445
446 if (ring->private)
447 return 0;
448
449 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
450 if (!pc)
451 return -ENOMEM;
452
453 obj = i915_gem_alloc_object(ring->dev, 4096);
454 if (obj == NULL) {
455 DRM_ERROR("Failed to allocate seqno page\n");
456 ret = -ENOMEM;
457 goto err;
458 }
459
460 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
461
462 ret = i915_gem_object_pin(obj, 4096, true, false);
463 if (ret)
464 goto err_unref;
465
466 pc->gtt_offset = obj->gtt_offset;
467 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
468 if (pc->cpu_page == NULL)
469 goto err_unpin;
470
471 pc->obj = obj;
472 ring->private = pc;
473 return 0;
474
475 err_unpin:
476 i915_gem_object_unpin(obj);
477 err_unref:
478 drm_gem_object_unreference(&obj->base);
479 err:
480 kfree(pc);
481 return ret;
482 }
483
484 static void
485 cleanup_pipe_control(struct intel_ring_buffer *ring)
486 {
487 struct pipe_control *pc = ring->private;
488 struct drm_i915_gem_object *obj;
489
490 if (!ring->private)
491 return;
492
493 obj = pc->obj;
494
495 kunmap(sg_page(obj->pages->sgl));
496 i915_gem_object_unpin(obj);
497 drm_gem_object_unreference(&obj->base);
498
499 kfree(pc);
500 ring->private = NULL;
501 }
502
503 static int init_render_ring(struct intel_ring_buffer *ring)
504 {
505 struct drm_device *dev = ring->dev;
506 struct drm_i915_private *dev_priv = dev->dev_private;
507 int ret = init_ring_common(ring);
508
509 if (INTEL_INFO(dev)->gen > 3) {
510 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
511 if (IS_GEN7(dev))
512 I915_WRITE(GFX_MODE_GEN7,
513 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
514 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
515 }
516
517 if (INTEL_INFO(dev)->gen >= 5) {
518 ret = init_pipe_control(ring);
519 if (ret)
520 return ret;
521 }
522
523 if (IS_GEN6(dev)) {
524 /* From the Sandybridge PRM, volume 1 part 3, page 24:
525 * "If this bit is set, STCunit will have LRA as replacement
526 * policy. [...] This bit must be reset. LRA replacement
527 * policy is not supported."
528 */
529 I915_WRITE(CACHE_MODE_0,
530 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
531
532 /* This is not explicitly set for GEN6, so read the register.
533 * see intel_ring_mi_set_context() for why we care.
534 * TODO: consider explicitly setting the bit for GEN5
535 */
536 ring->itlb_before_ctx_switch =
537 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
538 }
539
540 if (INTEL_INFO(dev)->gen >= 6)
541 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
542
543 if (HAS_L3_GPU_CACHE(dev))
544 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
545
546 return ret;
547 }
548
549 static void render_ring_cleanup(struct intel_ring_buffer *ring)
550 {
551 if (!ring->private)
552 return;
553
554 cleanup_pipe_control(ring);
555 }
556
557 static void
558 update_mboxes(struct intel_ring_buffer *ring,
559 u32 seqno,
560 u32 mmio_offset)
561 {
562 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
563 MI_SEMAPHORE_GLOBAL_GTT |
564 MI_SEMAPHORE_REGISTER |
565 MI_SEMAPHORE_UPDATE);
566 intel_ring_emit(ring, seqno);
567 intel_ring_emit(ring, mmio_offset);
568 }
569
570 /**
571 * gen6_add_request - Update the semaphore mailbox registers
572 *
573 * @ring - ring that is adding a request
574 * @seqno - return seqno stuck into the ring
575 *
576 * Update the mailbox registers in the *other* rings with the current seqno.
577 * This acts like a signal in the canonical semaphore.
578 */
579 static int
580 gen6_add_request(struct intel_ring_buffer *ring,
581 u32 *seqno)
582 {
583 u32 mbox1_reg;
584 u32 mbox2_reg;
585 int ret;
586
587 ret = intel_ring_begin(ring, 10);
588 if (ret)
589 return ret;
590
591 mbox1_reg = ring->signal_mbox[0];
592 mbox2_reg = ring->signal_mbox[1];
593
594 *seqno = i915_gem_next_request_seqno(ring);
595
596 update_mboxes(ring, *seqno, mbox1_reg);
597 update_mboxes(ring, *seqno, mbox2_reg);
598 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
599 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
600 intel_ring_emit(ring, *seqno);
601 intel_ring_emit(ring, MI_USER_INTERRUPT);
602 intel_ring_advance(ring);
603
604 return 0;
605 }
606
607 /**
608 * intel_ring_sync - sync the waiter to the signaller on seqno
609 *
610 * @waiter - ring that is waiting
611 * @signaller - ring which has, or will signal
612 * @seqno - seqno which the waiter will block on
613 */
614 static int
615 gen6_ring_sync(struct intel_ring_buffer *waiter,
616 struct intel_ring_buffer *signaller,
617 u32 seqno)
618 {
619 int ret;
620 u32 dw1 = MI_SEMAPHORE_MBOX |
621 MI_SEMAPHORE_COMPARE |
622 MI_SEMAPHORE_REGISTER;
623
624 /* Throughout all of the GEM code, seqno passed implies our current
625 * seqno is >= the last seqno executed. However for hardware the
626 * comparison is strictly greater than.
627 */
628 seqno -= 1;
629
630 WARN_ON(signaller->semaphore_register[waiter->id] ==
631 MI_SEMAPHORE_SYNC_INVALID);
632
633 ret = intel_ring_begin(waiter, 4);
634 if (ret)
635 return ret;
636
637 intel_ring_emit(waiter,
638 dw1 | signaller->semaphore_register[waiter->id]);
639 intel_ring_emit(waiter, seqno);
640 intel_ring_emit(waiter, 0);
641 intel_ring_emit(waiter, MI_NOOP);
642 intel_ring_advance(waiter);
643
644 return 0;
645 }
646
647 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
648 do { \
649 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
650 PIPE_CONTROL_DEPTH_STALL); \
651 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
652 intel_ring_emit(ring__, 0); \
653 intel_ring_emit(ring__, 0); \
654 } while (0)
655
656 static int
657 pc_render_add_request(struct intel_ring_buffer *ring,
658 u32 *result)
659 {
660 u32 seqno = i915_gem_next_request_seqno(ring);
661 struct pipe_control *pc = ring->private;
662 u32 scratch_addr = pc->gtt_offset + 128;
663 int ret;
664
665 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
666 * incoherent with writes to memory, i.e. completely fubar,
667 * so we need to use PIPE_NOTIFY instead.
668 *
669 * However, we also need to workaround the qword write
670 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
671 * memory before requesting an interrupt.
672 */
673 ret = intel_ring_begin(ring, 32);
674 if (ret)
675 return ret;
676
677 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
678 PIPE_CONTROL_WRITE_FLUSH |
679 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
680 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
681 intel_ring_emit(ring, seqno);
682 intel_ring_emit(ring, 0);
683 PIPE_CONTROL_FLUSH(ring, scratch_addr);
684 scratch_addr += 128; /* write to separate cachelines */
685 PIPE_CONTROL_FLUSH(ring, scratch_addr);
686 scratch_addr += 128;
687 PIPE_CONTROL_FLUSH(ring, scratch_addr);
688 scratch_addr += 128;
689 PIPE_CONTROL_FLUSH(ring, scratch_addr);
690 scratch_addr += 128;
691 PIPE_CONTROL_FLUSH(ring, scratch_addr);
692 scratch_addr += 128;
693 PIPE_CONTROL_FLUSH(ring, scratch_addr);
694
695 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
696 PIPE_CONTROL_WRITE_FLUSH |
697 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
698 PIPE_CONTROL_NOTIFY);
699 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
700 intel_ring_emit(ring, seqno);
701 intel_ring_emit(ring, 0);
702 intel_ring_advance(ring);
703
704 *result = seqno;
705 return 0;
706 }
707
708 static u32
709 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
710 {
711 /* Workaround to force correct ordering between irq and seqno writes on
712 * ivb (and maybe also on snb) by reading from a CS register (like
713 * ACTHD) before reading the status page. */
714 if (!lazy_coherency)
715 intel_ring_get_active_head(ring);
716 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
717 }
718
719 static u32
720 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
721 {
722 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
723 }
724
725 static u32
726 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
727 {
728 struct pipe_control *pc = ring->private;
729 return pc->cpu_page[0];
730 }
731
732 static bool
733 gen5_ring_get_irq(struct intel_ring_buffer *ring)
734 {
735 struct drm_device *dev = ring->dev;
736 drm_i915_private_t *dev_priv = dev->dev_private;
737 unsigned long flags;
738
739 if (!dev->irq_enabled)
740 return false;
741
742 spin_lock_irqsave(&dev_priv->irq_lock, flags);
743 if (ring->irq_refcount++ == 0) {
744 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
745 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
746 POSTING_READ(GTIMR);
747 }
748 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
749
750 return true;
751 }
752
753 static void
754 gen5_ring_put_irq(struct intel_ring_buffer *ring)
755 {
756 struct drm_device *dev = ring->dev;
757 drm_i915_private_t *dev_priv = dev->dev_private;
758 unsigned long flags;
759
760 spin_lock_irqsave(&dev_priv->irq_lock, flags);
761 if (--ring->irq_refcount == 0) {
762 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
763 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
764 POSTING_READ(GTIMR);
765 }
766 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
767 }
768
769 static bool
770 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
771 {
772 struct drm_device *dev = ring->dev;
773 drm_i915_private_t *dev_priv = dev->dev_private;
774 unsigned long flags;
775
776 if (!dev->irq_enabled)
777 return false;
778
779 spin_lock_irqsave(&dev_priv->irq_lock, flags);
780 if (ring->irq_refcount++ == 0) {
781 dev_priv->irq_mask &= ~ring->irq_enable_mask;
782 I915_WRITE(IMR, dev_priv->irq_mask);
783 POSTING_READ(IMR);
784 }
785 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
786
787 return true;
788 }
789
790 static void
791 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
792 {
793 struct drm_device *dev = ring->dev;
794 drm_i915_private_t *dev_priv = dev->dev_private;
795 unsigned long flags;
796
797 spin_lock_irqsave(&dev_priv->irq_lock, flags);
798 if (--ring->irq_refcount == 0) {
799 dev_priv->irq_mask |= ring->irq_enable_mask;
800 I915_WRITE(IMR, dev_priv->irq_mask);
801 POSTING_READ(IMR);
802 }
803 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
804 }
805
806 static bool
807 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
808 {
809 struct drm_device *dev = ring->dev;
810 drm_i915_private_t *dev_priv = dev->dev_private;
811 unsigned long flags;
812
813 if (!dev->irq_enabled)
814 return false;
815
816 spin_lock_irqsave(&dev_priv->irq_lock, flags);
817 if (ring->irq_refcount++ == 0) {
818 dev_priv->irq_mask &= ~ring->irq_enable_mask;
819 I915_WRITE16(IMR, dev_priv->irq_mask);
820 POSTING_READ16(IMR);
821 }
822 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
823
824 return true;
825 }
826
827 static void
828 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
829 {
830 struct drm_device *dev = ring->dev;
831 drm_i915_private_t *dev_priv = dev->dev_private;
832 unsigned long flags;
833
834 spin_lock_irqsave(&dev_priv->irq_lock, flags);
835 if (--ring->irq_refcount == 0) {
836 dev_priv->irq_mask |= ring->irq_enable_mask;
837 I915_WRITE16(IMR, dev_priv->irq_mask);
838 POSTING_READ16(IMR);
839 }
840 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
841 }
842
843 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
844 {
845 struct drm_device *dev = ring->dev;
846 drm_i915_private_t *dev_priv = ring->dev->dev_private;
847 u32 mmio = 0;
848
849 /* The ring status page addresses are no longer next to the rest of
850 * the ring registers as of gen7.
851 */
852 if (IS_GEN7(dev)) {
853 switch (ring->id) {
854 case RCS:
855 mmio = RENDER_HWS_PGA_GEN7;
856 break;
857 case BCS:
858 mmio = BLT_HWS_PGA_GEN7;
859 break;
860 case VCS:
861 mmio = BSD_HWS_PGA_GEN7;
862 break;
863 }
864 } else if (IS_GEN6(ring->dev)) {
865 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
866 } else {
867 mmio = RING_HWS_PGA(ring->mmio_base);
868 }
869
870 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
871 POSTING_READ(mmio);
872 }
873
874 static int
875 bsd_ring_flush(struct intel_ring_buffer *ring,
876 u32 invalidate_domains,
877 u32 flush_domains)
878 {
879 int ret;
880
881 ret = intel_ring_begin(ring, 2);
882 if (ret)
883 return ret;
884
885 intel_ring_emit(ring, MI_FLUSH);
886 intel_ring_emit(ring, MI_NOOP);
887 intel_ring_advance(ring);
888 return 0;
889 }
890
891 static int
892 i9xx_add_request(struct intel_ring_buffer *ring,
893 u32 *result)
894 {
895 u32 seqno;
896 int ret;
897
898 ret = intel_ring_begin(ring, 4);
899 if (ret)
900 return ret;
901
902 seqno = i915_gem_next_request_seqno(ring);
903
904 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
905 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
906 intel_ring_emit(ring, seqno);
907 intel_ring_emit(ring, MI_USER_INTERRUPT);
908 intel_ring_advance(ring);
909
910 *result = seqno;
911 return 0;
912 }
913
914 static bool
915 gen6_ring_get_irq(struct intel_ring_buffer *ring)
916 {
917 struct drm_device *dev = ring->dev;
918 drm_i915_private_t *dev_priv = dev->dev_private;
919 unsigned long flags;
920
921 if (!dev->irq_enabled)
922 return false;
923
924 /* It looks like we need to prevent the gt from suspending while waiting
925 * for an notifiy irq, otherwise irqs seem to get lost on at least the
926 * blt/bsd rings on ivb. */
927 gen6_gt_force_wake_get(dev_priv);
928
929 spin_lock_irqsave(&dev_priv->irq_lock, flags);
930 if (ring->irq_refcount++ == 0) {
931 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
932 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
933 GEN6_RENDER_L3_PARITY_ERROR));
934 else
935 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
936 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
937 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
938 POSTING_READ(GTIMR);
939 }
940 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
941
942 return true;
943 }
944
945 static void
946 gen6_ring_put_irq(struct intel_ring_buffer *ring)
947 {
948 struct drm_device *dev = ring->dev;
949 drm_i915_private_t *dev_priv = dev->dev_private;
950 unsigned long flags;
951
952 spin_lock_irqsave(&dev_priv->irq_lock, flags);
953 if (--ring->irq_refcount == 0) {
954 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
955 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
956 else
957 I915_WRITE_IMR(ring, ~0);
958 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
959 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
960 POSTING_READ(GTIMR);
961 }
962 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
963
964 gen6_gt_force_wake_put(dev_priv);
965 }
966
967 static int
968 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
969 {
970 int ret;
971
972 ret = intel_ring_begin(ring, 2);
973 if (ret)
974 return ret;
975
976 intel_ring_emit(ring,
977 MI_BATCH_BUFFER_START |
978 MI_BATCH_GTT |
979 MI_BATCH_NON_SECURE_I965);
980 intel_ring_emit(ring, offset);
981 intel_ring_advance(ring);
982
983 return 0;
984 }
985
986 static int
987 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
988 u32 offset, u32 len)
989 {
990 int ret;
991
992 ret = intel_ring_begin(ring, 4);
993 if (ret)
994 return ret;
995
996 intel_ring_emit(ring, MI_BATCH_BUFFER);
997 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
998 intel_ring_emit(ring, offset + len - 8);
999 intel_ring_emit(ring, 0);
1000 intel_ring_advance(ring);
1001
1002 return 0;
1003 }
1004
1005 static int
1006 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1007 u32 offset, u32 len)
1008 {
1009 int ret;
1010
1011 ret = intel_ring_begin(ring, 2);
1012 if (ret)
1013 return ret;
1014
1015 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1016 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
1017 intel_ring_advance(ring);
1018
1019 return 0;
1020 }
1021
1022 static void cleanup_status_page(struct intel_ring_buffer *ring)
1023 {
1024 struct drm_i915_gem_object *obj;
1025
1026 obj = ring->status_page.obj;
1027 if (obj == NULL)
1028 return;
1029
1030 kunmap(sg_page(obj->pages->sgl));
1031 i915_gem_object_unpin(obj);
1032 drm_gem_object_unreference(&obj->base);
1033 ring->status_page.obj = NULL;
1034 }
1035
1036 static int init_status_page(struct intel_ring_buffer *ring)
1037 {
1038 struct drm_device *dev = ring->dev;
1039 struct drm_i915_gem_object *obj;
1040 int ret;
1041
1042 obj = i915_gem_alloc_object(dev, 4096);
1043 if (obj == NULL) {
1044 DRM_ERROR("Failed to allocate status page\n");
1045 ret = -ENOMEM;
1046 goto err;
1047 }
1048
1049 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1050
1051 ret = i915_gem_object_pin(obj, 4096, true, false);
1052 if (ret != 0) {
1053 goto err_unref;
1054 }
1055
1056 ring->status_page.gfx_addr = obj->gtt_offset;
1057 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1058 if (ring->status_page.page_addr == NULL) {
1059 ret = -ENOMEM;
1060 goto err_unpin;
1061 }
1062 ring->status_page.obj = obj;
1063 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1064
1065 intel_ring_setup_status_page(ring);
1066 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1067 ring->name, ring->status_page.gfx_addr);
1068
1069 return 0;
1070
1071 err_unpin:
1072 i915_gem_object_unpin(obj);
1073 err_unref:
1074 drm_gem_object_unreference(&obj->base);
1075 err:
1076 return ret;
1077 }
1078
1079 static int intel_init_ring_buffer(struct drm_device *dev,
1080 struct intel_ring_buffer *ring)
1081 {
1082 struct drm_i915_gem_object *obj;
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 int ret;
1085
1086 ring->dev = dev;
1087 INIT_LIST_HEAD(&ring->active_list);
1088 INIT_LIST_HEAD(&ring->request_list);
1089 ring->size = 32 * PAGE_SIZE;
1090
1091 init_waitqueue_head(&ring->irq_queue);
1092
1093 if (I915_NEED_GFX_HWS(dev)) {
1094 ret = init_status_page(ring);
1095 if (ret)
1096 return ret;
1097 }
1098
1099 obj = i915_gem_alloc_object(dev, ring->size);
1100 if (obj == NULL) {
1101 DRM_ERROR("Failed to allocate ringbuffer\n");
1102 ret = -ENOMEM;
1103 goto err_hws;
1104 }
1105
1106 ring->obj = obj;
1107
1108 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1109 if (ret)
1110 goto err_unref;
1111
1112 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1113 if (ret)
1114 goto err_unpin;
1115
1116 ring->virtual_start =
1117 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1118 ring->size);
1119 if (ring->virtual_start == NULL) {
1120 DRM_ERROR("Failed to map ringbuffer.\n");
1121 ret = -EINVAL;
1122 goto err_unpin;
1123 }
1124
1125 ret = ring->init(ring);
1126 if (ret)
1127 goto err_unmap;
1128
1129 /* Workaround an erratum on the i830 which causes a hang if
1130 * the TAIL pointer points to within the last 2 cachelines
1131 * of the buffer.
1132 */
1133 ring->effective_size = ring->size;
1134 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1135 ring->effective_size -= 128;
1136
1137 return 0;
1138
1139 err_unmap:
1140 iounmap(ring->virtual_start);
1141 err_unpin:
1142 i915_gem_object_unpin(obj);
1143 err_unref:
1144 drm_gem_object_unreference(&obj->base);
1145 ring->obj = NULL;
1146 err_hws:
1147 cleanup_status_page(ring);
1148 return ret;
1149 }
1150
1151 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1152 {
1153 struct drm_i915_private *dev_priv;
1154 int ret;
1155
1156 if (ring->obj == NULL)
1157 return;
1158
1159 /* Disable the ring buffer. The ring must be idle at this point */
1160 dev_priv = ring->dev->dev_private;
1161 ret = intel_wait_ring_idle(ring);
1162 if (ret)
1163 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1164 ring->name, ret);
1165
1166 I915_WRITE_CTL(ring, 0);
1167
1168 iounmap(ring->virtual_start);
1169
1170 i915_gem_object_unpin(ring->obj);
1171 drm_gem_object_unreference(&ring->obj->base);
1172 ring->obj = NULL;
1173
1174 if (ring->cleanup)
1175 ring->cleanup(ring);
1176
1177 cleanup_status_page(ring);
1178 }
1179
1180 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1181 {
1182 uint32_t __iomem *virt;
1183 int rem = ring->size - ring->tail;
1184
1185 if (ring->space < rem) {
1186 int ret = intel_wait_ring_buffer(ring, rem);
1187 if (ret)
1188 return ret;
1189 }
1190
1191 virt = ring->virtual_start + ring->tail;
1192 rem /= 4;
1193 while (rem--)
1194 iowrite32(MI_NOOP, virt++);
1195
1196 ring->tail = 0;
1197 ring->space = ring_space(ring);
1198
1199 return 0;
1200 }
1201
1202 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1203 {
1204 int ret;
1205
1206 ret = i915_wait_seqno(ring, seqno);
1207 if (!ret)
1208 i915_gem_retire_requests_ring(ring);
1209
1210 return ret;
1211 }
1212
1213 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1214 {
1215 struct drm_i915_gem_request *request;
1216 u32 seqno = 0;
1217 int ret;
1218
1219 i915_gem_retire_requests_ring(ring);
1220
1221 if (ring->last_retired_head != -1) {
1222 ring->head = ring->last_retired_head;
1223 ring->last_retired_head = -1;
1224 ring->space = ring_space(ring);
1225 if (ring->space >= n)
1226 return 0;
1227 }
1228
1229 list_for_each_entry(request, &ring->request_list, list) {
1230 int space;
1231
1232 if (request->tail == -1)
1233 continue;
1234
1235 space = request->tail - (ring->tail + 8);
1236 if (space < 0)
1237 space += ring->size;
1238 if (space >= n) {
1239 seqno = request->seqno;
1240 break;
1241 }
1242
1243 /* Consume this request in case we need more space than
1244 * is available and so need to prevent a race between
1245 * updating last_retired_head and direct reads of
1246 * I915_RING_HEAD. It also provides a nice sanity check.
1247 */
1248 request->tail = -1;
1249 }
1250
1251 if (seqno == 0)
1252 return -ENOSPC;
1253
1254 ret = intel_ring_wait_seqno(ring, seqno);
1255 if (ret)
1256 return ret;
1257
1258 if (WARN_ON(ring->last_retired_head == -1))
1259 return -ENOSPC;
1260
1261 ring->head = ring->last_retired_head;
1262 ring->last_retired_head = -1;
1263 ring->space = ring_space(ring);
1264 if (WARN_ON(ring->space < n))
1265 return -ENOSPC;
1266
1267 return 0;
1268 }
1269
1270 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1271 {
1272 struct drm_device *dev = ring->dev;
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 unsigned long end;
1275 int ret;
1276
1277 ret = intel_ring_wait_request(ring, n);
1278 if (ret != -ENOSPC)
1279 return ret;
1280
1281 trace_i915_ring_wait_begin(ring);
1282 /* With GEM the hangcheck timer should kick us out of the loop,
1283 * leaving it early runs the risk of corrupting GEM state (due
1284 * to running on almost untested codepaths). But on resume
1285 * timers don't work yet, so prevent a complete hang in that
1286 * case by choosing an insanely large timeout. */
1287 end = jiffies + 60 * HZ;
1288
1289 do {
1290 ring->head = I915_READ_HEAD(ring);
1291 ring->space = ring_space(ring);
1292 if (ring->space >= n) {
1293 trace_i915_ring_wait_end(ring);
1294 return 0;
1295 }
1296
1297 if (dev->primary->master) {
1298 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1299 if (master_priv->sarea_priv)
1300 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1301 }
1302
1303 msleep(1);
1304
1305 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1306 if (ret)
1307 return ret;
1308 } while (!time_after(jiffies, end));
1309 trace_i915_ring_wait_end(ring);
1310 return -EBUSY;
1311 }
1312
1313 int intel_ring_begin(struct intel_ring_buffer *ring,
1314 int num_dwords)
1315 {
1316 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1317 int n = 4*num_dwords;
1318 int ret;
1319
1320 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1321 if (ret)
1322 return ret;
1323
1324 if (unlikely(ring->tail + n > ring->effective_size)) {
1325 ret = intel_wrap_ring_buffer(ring);
1326 if (unlikely(ret))
1327 return ret;
1328 }
1329
1330 if (unlikely(ring->space < n)) {
1331 ret = intel_wait_ring_buffer(ring, n);
1332 if (unlikely(ret))
1333 return ret;
1334 }
1335
1336 ring->space -= n;
1337 return 0;
1338 }
1339
1340 void intel_ring_advance(struct intel_ring_buffer *ring)
1341 {
1342 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1343
1344 ring->tail &= ring->size - 1;
1345 if (dev_priv->stop_rings & intel_ring_flag(ring))
1346 return;
1347 ring->write_tail(ring, ring->tail);
1348 }
1349
1350
1351 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1352 u32 value)
1353 {
1354 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1355
1356 /* Every tail move must follow the sequence below */
1357
1358 /* Disable notification that the ring is IDLE. The GT
1359 * will then assume that it is busy and bring it out of rc6.
1360 */
1361 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1362 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1363
1364 /* Clear the context id. Here be magic! */
1365 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1366
1367 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1368 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1369 GEN6_BSD_SLEEP_INDICATOR) == 0,
1370 50))
1371 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1372
1373 /* Now that the ring is fully powered up, update the tail */
1374 I915_WRITE_TAIL(ring, value);
1375 POSTING_READ(RING_TAIL(ring->mmio_base));
1376
1377 /* Let the ring send IDLE messages to the GT again,
1378 * and so let it sleep to conserve power when idle.
1379 */
1380 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1381 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1382 }
1383
1384 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1385 u32 invalidate, u32 flush)
1386 {
1387 uint32_t cmd;
1388 int ret;
1389
1390 ret = intel_ring_begin(ring, 4);
1391 if (ret)
1392 return ret;
1393
1394 cmd = MI_FLUSH_DW;
1395 if (invalidate & I915_GEM_GPU_DOMAINS)
1396 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1397 intel_ring_emit(ring, cmd);
1398 intel_ring_emit(ring, 0);
1399 intel_ring_emit(ring, 0);
1400 intel_ring_emit(ring, MI_NOOP);
1401 intel_ring_advance(ring);
1402 return 0;
1403 }
1404
1405 static int
1406 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1407 u32 offset, u32 len)
1408 {
1409 int ret;
1410
1411 ret = intel_ring_begin(ring, 2);
1412 if (ret)
1413 return ret;
1414
1415 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1416 /* bit0-7 is the length on GEN6+ */
1417 intel_ring_emit(ring, offset);
1418 intel_ring_advance(ring);
1419
1420 return 0;
1421 }
1422
1423 /* Blitter support (SandyBridge+) */
1424
1425 static int blt_ring_flush(struct intel_ring_buffer *ring,
1426 u32 invalidate, u32 flush)
1427 {
1428 uint32_t cmd;
1429 int ret;
1430
1431 ret = intel_ring_begin(ring, 4);
1432 if (ret)
1433 return ret;
1434
1435 cmd = MI_FLUSH_DW;
1436 if (invalidate & I915_GEM_DOMAIN_RENDER)
1437 cmd |= MI_INVALIDATE_TLB;
1438 intel_ring_emit(ring, cmd);
1439 intel_ring_emit(ring, 0);
1440 intel_ring_emit(ring, 0);
1441 intel_ring_emit(ring, MI_NOOP);
1442 intel_ring_advance(ring);
1443 return 0;
1444 }
1445
1446 int intel_init_render_ring_buffer(struct drm_device *dev)
1447 {
1448 drm_i915_private_t *dev_priv = dev->dev_private;
1449 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1450
1451 ring->name = "render ring";
1452 ring->id = RCS;
1453 ring->mmio_base = RENDER_RING_BASE;
1454
1455 if (INTEL_INFO(dev)->gen >= 6) {
1456 ring->add_request = gen6_add_request;
1457 ring->flush = gen7_render_ring_flush;
1458 if (INTEL_INFO(dev)->gen == 6)
1459 ring->flush = gen6_render_ring_flush;
1460 ring->irq_get = gen6_ring_get_irq;
1461 ring->irq_put = gen6_ring_put_irq;
1462 ring->irq_enable_mask = GT_USER_INTERRUPT;
1463 ring->get_seqno = gen6_ring_get_seqno;
1464 ring->sync_to = gen6_ring_sync;
1465 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1466 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1467 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1468 ring->signal_mbox[0] = GEN6_VRSYNC;
1469 ring->signal_mbox[1] = GEN6_BRSYNC;
1470 } else if (IS_GEN5(dev)) {
1471 ring->add_request = pc_render_add_request;
1472 ring->flush = gen4_render_ring_flush;
1473 ring->get_seqno = pc_render_get_seqno;
1474 ring->irq_get = gen5_ring_get_irq;
1475 ring->irq_put = gen5_ring_put_irq;
1476 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1477 } else {
1478 ring->add_request = i9xx_add_request;
1479 if (INTEL_INFO(dev)->gen < 4)
1480 ring->flush = gen2_render_ring_flush;
1481 else
1482 ring->flush = gen4_render_ring_flush;
1483 ring->get_seqno = ring_get_seqno;
1484 if (IS_GEN2(dev)) {
1485 ring->irq_get = i8xx_ring_get_irq;
1486 ring->irq_put = i8xx_ring_put_irq;
1487 } else {
1488 ring->irq_get = i9xx_ring_get_irq;
1489 ring->irq_put = i9xx_ring_put_irq;
1490 }
1491 ring->irq_enable_mask = I915_USER_INTERRUPT;
1492 }
1493 ring->write_tail = ring_write_tail;
1494 if (INTEL_INFO(dev)->gen >= 6)
1495 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1496 else if (INTEL_INFO(dev)->gen >= 4)
1497 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1498 else if (IS_I830(dev) || IS_845G(dev))
1499 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1500 else
1501 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1502 ring->init = init_render_ring;
1503 ring->cleanup = render_ring_cleanup;
1504
1505
1506 if (!I915_NEED_GFX_HWS(dev)) {
1507 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1508 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1509 }
1510
1511 return intel_init_ring_buffer(dev, ring);
1512 }
1513
1514 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1515 {
1516 drm_i915_private_t *dev_priv = dev->dev_private;
1517 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1518
1519 ring->name = "render ring";
1520 ring->id = RCS;
1521 ring->mmio_base = RENDER_RING_BASE;
1522
1523 if (INTEL_INFO(dev)->gen >= 6) {
1524 /* non-kms not supported on gen6+ */
1525 return -ENODEV;
1526 }
1527
1528 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1529 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1530 * the special gen5 functions. */
1531 ring->add_request = i9xx_add_request;
1532 if (INTEL_INFO(dev)->gen < 4)
1533 ring->flush = gen2_render_ring_flush;
1534 else
1535 ring->flush = gen4_render_ring_flush;
1536 ring->get_seqno = ring_get_seqno;
1537 if (IS_GEN2(dev)) {
1538 ring->irq_get = i8xx_ring_get_irq;
1539 ring->irq_put = i8xx_ring_put_irq;
1540 } else {
1541 ring->irq_get = i9xx_ring_get_irq;
1542 ring->irq_put = i9xx_ring_put_irq;
1543 }
1544 ring->irq_enable_mask = I915_USER_INTERRUPT;
1545 ring->write_tail = ring_write_tail;
1546 if (INTEL_INFO(dev)->gen >= 4)
1547 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1548 else if (IS_I830(dev) || IS_845G(dev))
1549 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1550 else
1551 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1552 ring->init = init_render_ring;
1553 ring->cleanup = render_ring_cleanup;
1554
1555 if (!I915_NEED_GFX_HWS(dev))
1556 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1557
1558 ring->dev = dev;
1559 INIT_LIST_HEAD(&ring->active_list);
1560 INIT_LIST_HEAD(&ring->request_list);
1561
1562 ring->size = size;
1563 ring->effective_size = ring->size;
1564 if (IS_I830(ring->dev))
1565 ring->effective_size -= 128;
1566
1567 ring->virtual_start = ioremap_wc(start, size);
1568 if (ring->virtual_start == NULL) {
1569 DRM_ERROR("can not ioremap virtual address for"
1570 " ring buffer\n");
1571 return -ENOMEM;
1572 }
1573
1574 return 0;
1575 }
1576
1577 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1578 {
1579 drm_i915_private_t *dev_priv = dev->dev_private;
1580 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1581
1582 ring->name = "bsd ring";
1583 ring->id = VCS;
1584
1585 ring->write_tail = ring_write_tail;
1586 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1587 ring->mmio_base = GEN6_BSD_RING_BASE;
1588 /* gen6 bsd needs a special wa for tail updates */
1589 if (IS_GEN6(dev))
1590 ring->write_tail = gen6_bsd_ring_write_tail;
1591 ring->flush = gen6_ring_flush;
1592 ring->add_request = gen6_add_request;
1593 ring->get_seqno = gen6_ring_get_seqno;
1594 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1595 ring->irq_get = gen6_ring_get_irq;
1596 ring->irq_put = gen6_ring_put_irq;
1597 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1598 ring->sync_to = gen6_ring_sync;
1599 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1600 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1601 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1602 ring->signal_mbox[0] = GEN6_RVSYNC;
1603 ring->signal_mbox[1] = GEN6_BVSYNC;
1604 } else {
1605 ring->mmio_base = BSD_RING_BASE;
1606 ring->flush = bsd_ring_flush;
1607 ring->add_request = i9xx_add_request;
1608 ring->get_seqno = ring_get_seqno;
1609 if (IS_GEN5(dev)) {
1610 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1611 ring->irq_get = gen5_ring_get_irq;
1612 ring->irq_put = gen5_ring_put_irq;
1613 } else {
1614 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1615 ring->irq_get = i9xx_ring_get_irq;
1616 ring->irq_put = i9xx_ring_put_irq;
1617 }
1618 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1619 }
1620 ring->init = init_ring_common;
1621
1622
1623 return intel_init_ring_buffer(dev, ring);
1624 }
1625
1626 int intel_init_blt_ring_buffer(struct drm_device *dev)
1627 {
1628 drm_i915_private_t *dev_priv = dev->dev_private;
1629 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1630
1631 ring->name = "blitter ring";
1632 ring->id = BCS;
1633
1634 ring->mmio_base = BLT_RING_BASE;
1635 ring->write_tail = ring_write_tail;
1636 ring->flush = blt_ring_flush;
1637 ring->add_request = gen6_add_request;
1638 ring->get_seqno = gen6_ring_get_seqno;
1639 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1640 ring->irq_get = gen6_ring_get_irq;
1641 ring->irq_put = gen6_ring_put_irq;
1642 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1643 ring->sync_to = gen6_ring_sync;
1644 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1645 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1646 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1647 ring->signal_mbox[0] = GEN6_RBSYNC;
1648 ring->signal_mbox[1] = GEN6_VBSYNC;
1649 ring->init = init_ring_common;
1650
1651 return intel_init_ring_buffer(dev, ring);
1652 }
1653
1654 int
1655 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1656 {
1657 int ret;
1658
1659 if (!ring->gpu_caches_dirty)
1660 return 0;
1661
1662 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1663 if (ret)
1664 return ret;
1665
1666 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1667
1668 ring->gpu_caches_dirty = false;
1669 return 0;
1670 }
1671
1672 int
1673 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1674 {
1675 uint32_t flush_domains;
1676 int ret;
1677
1678 flush_domains = 0;
1679 if (ring->gpu_caches_dirty)
1680 flush_domains = I915_GEM_GPU_DOMAINS;
1681
1682 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1683 if (ret)
1684 return ret;
1685
1686 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1687
1688 ring->gpu_caches_dirty = false;
1689 return 0;
1690 }
Linux kernel - Deliverables
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