2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- tail
;
58 return space
- I915_RING_FREE_SPACE
;
61 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
63 if (ringbuf
->last_retired_head
!= -1) {
64 ringbuf
->head
= ringbuf
->last_retired_head
;
65 ringbuf
->last_retired_head
= -1;
68 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
69 ringbuf
->tail
, ringbuf
->size
);
72 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
74 intel_ring_update_space(ringbuf
);
75 return ringbuf
->space
;
78 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
80 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
81 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
84 static void __intel_ring_advance(struct intel_engine_cs
*ring
)
86 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
87 ringbuf
->tail
&= ringbuf
->size
- 1;
88 if (intel_ring_stopped(ring
))
90 ring
->write_tail(ring
, ringbuf
->tail
);
94 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
95 u32 invalidate_domains
,
98 struct intel_engine_cs
*ring
= req
->ring
;
103 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
104 cmd
|= MI_NO_WRITE_FLUSH
;
106 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
107 cmd
|= MI_READ_FLUSH
;
109 ret
= intel_ring_begin(req
, 2);
113 intel_ring_emit(ring
, cmd
);
114 intel_ring_emit(ring
, MI_NOOP
);
115 intel_ring_advance(ring
);
121 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
122 u32 invalidate_domains
,
125 struct intel_engine_cs
*ring
= req
->ring
;
126 struct drm_device
*dev
= ring
->dev
;
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
142 * I915_GEM_DOMAIN_COMMAND may not exist?
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
158 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
159 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
160 cmd
&= ~MI_NO_WRITE_FLUSH
;
161 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
164 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
165 (IS_G4X(dev
) || IS_GEN5(dev
)))
166 cmd
|= MI_INVALIDATE_ISP
;
168 ret
= intel_ring_begin(req
, 2);
172 intel_ring_emit(ring
, cmd
);
173 intel_ring_emit(ring
, MI_NOOP
);
174 intel_ring_advance(ring
);
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
192 * And the workaround for these two requires this workaround first:
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
219 struct intel_engine_cs
*ring
= req
->ring
;
220 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
223 ret
= intel_ring_begin(req
, 6);
227 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
229 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
230 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
231 intel_ring_emit(ring
, 0); /* low dword */
232 intel_ring_emit(ring
, 0); /* high dword */
233 intel_ring_emit(ring
, MI_NOOP
);
234 intel_ring_advance(ring
);
236 ret
= intel_ring_begin(req
, 6);
240 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
242 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
243 intel_ring_emit(ring
, 0);
244 intel_ring_emit(ring
, 0);
245 intel_ring_emit(ring
, MI_NOOP
);
246 intel_ring_advance(ring
);
252 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
253 u32 invalidate_domains
, u32 flush_domains
)
255 struct intel_engine_cs
*ring
= req
->ring
;
257 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret
= intel_emit_post_sync_nonzero_flush(req
);
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
270 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
271 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
276 flags
|= PIPE_CONTROL_CS_STALL
;
278 if (invalidate_domains
) {
279 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
280 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
281 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
282 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
283 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
284 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
286 * TLB invalidate requires a post-sync write.
288 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
291 ret
= intel_ring_begin(req
, 4);
295 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring
, flags
);
297 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
298 intel_ring_emit(ring
, 0);
299 intel_ring_advance(ring
);
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
307 struct intel_engine_cs
*ring
= req
->ring
;
310 ret
= intel_ring_begin(req
, 4);
314 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
316 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
317 intel_ring_emit(ring
, 0);
318 intel_ring_emit(ring
, 0);
319 intel_ring_advance(ring
);
325 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
326 u32 invalidate_domains
, u32 flush_domains
)
328 struct intel_engine_cs
*ring
= req
->ring
;
330 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
341 flags
|= PIPE_CONTROL_CS_STALL
;
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
348 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
349 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
351 if (invalidate_domains
) {
352 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
353 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
354 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
355 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
356 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
357 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
358 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
360 * TLB invalidate requires a post-sync write.
362 flags
|= PIPE_CONTROL_QW_WRITE
;
363 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
365 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req
);
373 ret
= intel_ring_begin(req
, 4);
377 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring
, flags
);
379 intel_ring_emit(ring
, scratch_addr
);
380 intel_ring_emit(ring
, 0);
381 intel_ring_advance(ring
);
387 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
388 u32 flags
, u32 scratch_addr
)
390 struct intel_engine_cs
*ring
= req
->ring
;
393 ret
= intel_ring_begin(req
, 6);
397 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring
, flags
);
399 intel_ring_emit(ring
, scratch_addr
);
400 intel_ring_emit(ring
, 0);
401 intel_ring_emit(ring
, 0);
402 intel_ring_emit(ring
, 0);
403 intel_ring_advance(ring
);
409 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
410 u32 invalidate_domains
, u32 flush_domains
)
413 u32 scratch_addr
= req
->ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
416 flags
|= PIPE_CONTROL_CS_STALL
;
419 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
420 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
422 if (invalidate_domains
) {
423 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
424 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
425 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
426 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
427 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
428 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
429 flags
|= PIPE_CONTROL_QW_WRITE
;
430 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret
= gen8_emit_pipe_control(req
,
434 PIPE_CONTROL_CS_STALL
|
435 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
441 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
444 static void ring_write_tail(struct intel_engine_cs
*ring
,
447 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
448 I915_WRITE_TAIL(ring
, value
);
451 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
453 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
456 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
457 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
458 RING_ACTHD_UDW(ring
->mmio_base
));
459 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
460 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
462 acthd
= I915_READ(ACTHD
);
467 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
469 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 addr
= dev_priv
->status_page_dmah
->busaddr
;
473 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
474 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
475 I915_WRITE(HWS_PGA
, addr
);
478 static void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
480 struct drm_device
*dev
= ring
->dev
;
481 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
490 mmio
= RENDER_HWS_PGA_GEN7
;
493 mmio
= BLT_HWS_PGA_GEN7
;
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
501 mmio
= BSD_HWS_PGA_GEN7
;
504 mmio
= VEBOX_HWS_PGA_GEN7
;
507 } else if (IS_GEN6(ring
->dev
)) {
508 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
510 /* XXX: gen8 returns to sanity */
511 mmio
= RING_HWS_PGA(ring
->mmio_base
);
514 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
518 * Flush the TLB for this page
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
524 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
525 u32 reg
= RING_INSTPM(ring
->mmio_base
);
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
533 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
540 static bool stop_ring(struct intel_engine_cs
*ring
)
542 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
544 if (!IS_GEN2(ring
->dev
)) {
545 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
546 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
552 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
557 I915_WRITE_CTL(ring
, 0);
558 I915_WRITE_HEAD(ring
, 0);
559 ring
->write_tail(ring
, 0);
561 if (!IS_GEN2(ring
->dev
)) {
562 (void)I915_READ_CTL(ring
);
563 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
566 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
569 static int init_ring_common(struct intel_engine_cs
*ring
)
571 struct drm_device
*dev
= ring
->dev
;
572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
573 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
574 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
577 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
579 if (!stop_ring(ring
)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
585 I915_READ_HEAD(ring
),
586 I915_READ_TAIL(ring
),
587 I915_READ_START(ring
));
589 if (!stop_ring(ring
)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
594 I915_READ_HEAD(ring
),
595 I915_READ_TAIL(ring
),
596 I915_READ_START(ring
));
602 if (I915_NEED_GFX_HWS(dev
))
603 intel_ring_setup_status_page(ring
);
605 ring_setup_phys_status_page(ring
);
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring
);
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring
))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring
->name
, I915_READ_HEAD(ring
));
620 I915_WRITE_HEAD(ring
, 0);
621 (void)I915_READ_HEAD(ring
);
624 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
629 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
630 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
634 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
635 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
636 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
641 ringbuf
->last_retired_head
= -1;
642 ringbuf
->head
= I915_READ_HEAD(ring
);
643 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
644 intel_ring_update_space(ringbuf
);
646 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
649 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
655 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
657 struct drm_device
*dev
= ring
->dev
;
659 if (ring
->scratch
.obj
== NULL
)
662 if (INTEL_INFO(dev
)->gen
>= 5) {
663 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
664 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
667 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
668 ring
->scratch
.obj
= NULL
;
672 intel_init_pipe_control(struct intel_engine_cs
*ring
)
676 WARN_ON(ring
->scratch
.obj
);
678 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
679 if (ring
->scratch
.obj
== NULL
) {
680 DRM_ERROR("Failed to allocate seqno page\n");
685 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
689 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
693 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
694 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
695 if (ring
->scratch
.cpu_page
== NULL
) {
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring
->name
, ring
->scratch
.gtt_offset
);
705 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
707 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
715 struct intel_engine_cs
*ring
= req
->ring
;
716 struct drm_device
*dev
= ring
->dev
;
717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
718 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
720 if (WARN_ON_ONCE(w
->count
== 0))
723 ring
->gpu_caches_dirty
= true;
724 ret
= intel_ring_flush_all_caches(req
);
728 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
732 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
733 for (i
= 0; i
< w
->count
; i
++) {
734 intel_ring_emit(ring
, w
->reg
[i
].addr
);
735 intel_ring_emit(ring
, w
->reg
[i
].value
);
737 intel_ring_emit(ring
, MI_NOOP
);
739 intel_ring_advance(ring
);
741 ring
->gpu_caches_dirty
= true;
742 ret
= intel_ring_flush_all_caches(req
);
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
755 ret
= intel_ring_workarounds_emit(req
);
759 ret
= i915_gem_render_state_init(req
);
761 DRM_ERROR("init render state: %d\n", ret
);
766 static int wa_add(struct drm_i915_private
*dev_priv
,
767 const u32 addr
, const u32 mask
, const u32 val
)
769 const u32 idx
= dev_priv
->workarounds
.count
;
771 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
774 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
775 dev_priv
->workarounds
.reg
[idx
].value
= val
;
776 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
778 dev_priv
->workarounds
.count
++;
783 #define WA_REG(addr, mask, val) { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
789 #define WA_SET_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
792 #define WA_CLR_BIT_MASKED(addr, mask) \
793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
803 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
805 struct drm_device
*dev
= ring
->dev
;
806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
808 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
810 /* WaDisableAsyncFlipPerfMode:bdw */
811 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
813 /* WaDisablePartialInstShootdown:bdw */
814 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
817 STALL_DOP_GATING_DISABLE
);
819 /* WaDisableDopClockGating:bdw */
820 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
821 DOP_CLOCK_GATING_DISABLE
);
823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
824 GEN8_SAMPLER_POWER_BYPASS_DIS
);
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
830 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
831 /* WaForceEnableNonCoherent:bdw */
832 HDC_FORCE_NON_COHERENT
|
833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
835 /* WaHdcDisableFetchWhenMasked:bdw */
836 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
837 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
838 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
840 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
841 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
842 * polygons in the same 8x4 pixel/sample area to be processed without
843 * stalling waiting for the earlier ones to write to Hierarchical Z
846 * This optimization is off by default for Broadwell; turn it on.
848 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
850 /* Wa4x4STCOptimizationDisable:bdw */
851 WA_SET_BIT_MASKED(CACHE_MODE_1
,
852 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
855 * BSpec recommends 8x4 when MSAA is used,
856 * however in practice 16x4 seems fastest.
858 * Note that PS/WM thread counts depend on the WIZ hashing
859 * disable bit, which we don't touch here, but it's good
860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
862 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
863 GEN6_WIZ_HASHING_MASK
,
864 GEN6_WIZ_HASHING_16x4
);
869 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
871 struct drm_device
*dev
= ring
->dev
;
872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
874 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
876 /* WaDisableAsyncFlipPerfMode:chv */
877 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
879 /* WaDisablePartialInstShootdown:chv */
880 /* WaDisableThreadStallDopClockGating:chv */
881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
882 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
883 STALL_DOP_GATING_DISABLE
);
885 /* Use Force Non-Coherent whenever executing a 3D context. This is a
886 * workaround for a possible hang in the unlikely event a TLB
887 * invalidation occurs during a PSD flush.
889 /* WaForceEnableNonCoherent:chv */
890 /* WaHdcDisableFetchWhenMasked:chv */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
892 HDC_FORCE_NON_COHERENT
|
893 HDC_DONOT_FETCH_MEM_WHEN_MASKED
);
895 /* According to the CACHE_MODE_0 default value documentation, some
896 * CHV platforms disable this optimization by default. Turn it on.
898 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
900 /* Wa4x4STCOptimizationDisable:chv */
901 WA_SET_BIT_MASKED(CACHE_MODE_1
,
902 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
904 /* Improve HiZ throughput on CHV. */
905 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
908 * BSpec recommends 8x4 when MSAA is used,
909 * however in practice 16x4 seems fastest.
911 * Note that PS/WM thread counts depend on the WIZ hashing
912 * disable bit, which we don't touch here, but it's good
913 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
915 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
916 GEN6_WIZ_HASHING_MASK
,
917 GEN6_WIZ_HASHING_16x4
);
922 static int gen9_init_workarounds(struct intel_engine_cs
*ring
)
924 struct drm_device
*dev
= ring
->dev
;
925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 /* WaDisablePartialInstShootdown:skl,bxt */
929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
932 /* Syncing dependencies between camera and graphics:skl,bxt */
933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
936 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) == SKL_REVID_A0
||
937 INTEL_REVID(dev
) == SKL_REVID_B0
)) ||
938 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
)) {
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
940 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
941 GEN9_DG_MIRROR_FIX_ENABLE
);
944 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
) ||
945 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
)) {
946 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
948 GEN9_RHWO_OPTIMIZATION_DISABLE
);
949 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0
,
950 DISABLE_PIXEL_MASK_CAMMING
);
953 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) >= SKL_REVID_C0
) ||
955 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
956 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
957 GEN9_ENABLE_YV12_BUGFIX
);
960 /* Wa4x4STCOptimizationDisable:skl,bxt */
961 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
963 /* WaDisablePartialResolveInVc:skl,bxt */
964 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
);
966 /* WaCcsTlbPrefetchDisable:skl,bxt */
967 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
968 GEN9_CCS_TLB_PREFETCH_ENABLE
);
970 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
971 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) == SKL_REVID_C0
) ||
972 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
))
973 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
974 PIXEL_MASK_CAMMING_DISABLE
);
976 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
977 tmp
= HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
;
978 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) == SKL_REVID_F0
) ||
979 (IS_BROXTON(dev
) && INTEL_REVID(dev
) >= BXT_REVID_B0
))
980 tmp
|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
;
981 WA_SET_BIT_MASKED(HDC_CHICKEN0
, tmp
);
986 static int skl_tune_iz_hashing(struct intel_engine_cs
*ring
)
988 struct drm_device
*dev
= ring
->dev
;
989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
990 u8 vals
[3] = { 0, 0, 0 };
993 for (i
= 0; i
< 3; i
++) {
997 * Only consider slices where one, and only one, subslice has 7
1000 if (hweight8(dev_priv
->info
.subslice_7eu
[i
]) != 1)
1004 * subslice_7eu[i] != 0 (because of the check above) and
1005 * ss_max == 4 (maximum number of subslices possible per slice)
1009 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1013 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1016 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1017 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1018 GEN9_IZ_HASHING_MASK(2) |
1019 GEN9_IZ_HASHING_MASK(1) |
1020 GEN9_IZ_HASHING_MASK(0),
1021 GEN9_IZ_HASHING(2, vals
[2]) |
1022 GEN9_IZ_HASHING(1, vals
[1]) |
1023 GEN9_IZ_HASHING(0, vals
[0]));
1029 static int skl_init_workarounds(struct intel_engine_cs
*ring
)
1031 struct drm_device
*dev
= ring
->dev
;
1032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1034 gen9_init_workarounds(ring
);
1036 /* WaDisablePowerCompilerClockGating:skl */
1037 if (INTEL_REVID(dev
) == SKL_REVID_B0
)
1038 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1039 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1041 if (INTEL_REVID(dev
) <= SKL_REVID_D0
) {
1043 *Use Force Non-Coherent whenever executing a 3D context. This
1044 * is a workaround for a possible hang in the unlikely event
1045 * a TLB invalidation occurs during a PSD flush.
1047 /* WaForceEnableNonCoherent:skl */
1048 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1049 HDC_FORCE_NON_COHERENT
);
1052 if (INTEL_REVID(dev
) == SKL_REVID_C0
||
1053 INTEL_REVID(dev
) == SKL_REVID_D0
)
1054 /* WaBarrierPerformanceFixDisable:skl */
1055 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1056 HDC_FENCE_DEST_SLM_DISABLE
|
1057 HDC_BARRIER_PERFORMANCE_DISABLE
);
1059 return skl_tune_iz_hashing(ring
);
1062 static int bxt_init_workarounds(struct intel_engine_cs
*ring
)
1064 struct drm_device
*dev
= ring
->dev
;
1065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1067 gen9_init_workarounds(ring
);
1069 /* WaDisableThreadStallDopClockGating:bxt */
1070 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1071 STALL_DOP_GATING_DISABLE
);
1073 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1074 if (INTEL_REVID(dev
) <= BXT_REVID_B0
) {
1076 GEN7_HALF_SLICE_CHICKEN1
,
1077 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1083 int init_workarounds_ring(struct intel_engine_cs
*ring
)
1085 struct drm_device
*dev
= ring
->dev
;
1086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1088 WARN_ON(ring
->id
!= RCS
);
1090 dev_priv
->workarounds
.count
= 0;
1092 if (IS_BROADWELL(dev
))
1093 return bdw_init_workarounds(ring
);
1095 if (IS_CHERRYVIEW(dev
))
1096 return chv_init_workarounds(ring
);
1098 if (IS_SKYLAKE(dev
))
1099 return skl_init_workarounds(ring
);
1101 if (IS_BROXTON(dev
))
1102 return bxt_init_workarounds(ring
);
1107 static int init_render_ring(struct intel_engine_cs
*ring
)
1109 struct drm_device
*dev
= ring
->dev
;
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1111 int ret
= init_ring_common(ring
);
1115 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1116 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1117 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1119 /* We need to disable the AsyncFlip performance optimisations in order
1120 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1121 * programmed to '1' on all products.
1123 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1125 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1126 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1128 /* Required for the hardware to program scanline values for waiting */
1129 /* WaEnableFlushTlbInvalidationMode:snb */
1130 if (INTEL_INFO(dev
)->gen
== 6)
1131 I915_WRITE(GFX_MODE
,
1132 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1134 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1136 I915_WRITE(GFX_MODE_GEN7
,
1137 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1138 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1141 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1142 * "If this bit is set, STCunit will have LRA as replacement
1143 * policy. [...] This bit must be reset. LRA replacement
1144 * policy is not supported."
1146 I915_WRITE(CACHE_MODE_0
,
1147 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1150 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1151 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1153 if (HAS_L3_DPF(dev
))
1154 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1156 return init_workarounds_ring(ring
);
1159 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
1161 struct drm_device
*dev
= ring
->dev
;
1162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1164 if (dev_priv
->semaphore_obj
) {
1165 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1166 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1167 dev_priv
->semaphore_obj
= NULL
;
1170 intel_fini_pipe_control(ring
);
1173 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1174 unsigned int num_dwords
)
1176 #define MBOX_UPDATE_DWORDS 8
1177 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1178 struct drm_device
*dev
= signaller
->dev
;
1179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1180 struct intel_engine_cs
*waiter
;
1181 int i
, ret
, num_rings
;
1183 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1184 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1185 #undef MBOX_UPDATE_DWORDS
1187 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1191 for_each_ring(waiter
, dev_priv
, i
) {
1193 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1194 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1197 seqno
= i915_gem_request_get_seqno(signaller_req
);
1198 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1199 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1200 PIPE_CONTROL_QW_WRITE
|
1201 PIPE_CONTROL_FLUSH_ENABLE
);
1202 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1203 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1204 intel_ring_emit(signaller
, seqno
);
1205 intel_ring_emit(signaller
, 0);
1206 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1207 MI_SEMAPHORE_TARGET(waiter
->id
));
1208 intel_ring_emit(signaller
, 0);
1214 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1215 unsigned int num_dwords
)
1217 #define MBOX_UPDATE_DWORDS 6
1218 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1219 struct drm_device
*dev
= signaller
->dev
;
1220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 struct intel_engine_cs
*waiter
;
1222 int i
, ret
, num_rings
;
1224 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1225 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1226 #undef MBOX_UPDATE_DWORDS
1228 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1232 for_each_ring(waiter
, dev_priv
, i
) {
1234 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1235 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1238 seqno
= i915_gem_request_get_seqno(signaller_req
);
1239 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1240 MI_FLUSH_DW_OP_STOREDW
);
1241 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1242 MI_FLUSH_DW_USE_GTT
);
1243 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1244 intel_ring_emit(signaller
, seqno
);
1245 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1246 MI_SEMAPHORE_TARGET(waiter
->id
));
1247 intel_ring_emit(signaller
, 0);
1253 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1254 unsigned int num_dwords
)
1256 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1257 struct drm_device
*dev
= signaller
->dev
;
1258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1259 struct intel_engine_cs
*useless
;
1260 int i
, ret
, num_rings
;
1262 #define MBOX_UPDATE_DWORDS 3
1263 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1264 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1265 #undef MBOX_UPDATE_DWORDS
1267 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1271 for_each_ring(useless
, dev_priv
, i
) {
1272 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1273 if (mbox_reg
!= GEN6_NOSYNC
) {
1274 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1275 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1276 intel_ring_emit(signaller
, mbox_reg
);
1277 intel_ring_emit(signaller
, seqno
);
1281 /* If num_dwords was rounded, make sure the tail pointer is correct */
1282 if (num_rings
% 2 == 0)
1283 intel_ring_emit(signaller
, MI_NOOP
);
1289 * gen6_add_request - Update the semaphore mailbox registers
1291 * @request - request to write to the ring
1293 * Update the mailbox registers in the *other* rings with the current seqno.
1294 * This acts like a signal in the canonical semaphore.
1297 gen6_add_request(struct drm_i915_gem_request
*req
)
1299 struct intel_engine_cs
*ring
= req
->ring
;
1302 if (ring
->semaphore
.signal
)
1303 ret
= ring
->semaphore
.signal(req
, 4);
1305 ret
= intel_ring_begin(req
, 4);
1310 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1311 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1312 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1313 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1314 __intel_ring_advance(ring
);
1319 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1323 return dev_priv
->last_seqno
< seqno
;
1327 * intel_ring_sync - sync the waiter to the signaller on seqno
1329 * @waiter - ring that is waiting
1330 * @signaller - ring which has, or will signal
1331 * @seqno - seqno which the waiter will block on
1335 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1336 struct intel_engine_cs
*signaller
,
1339 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1340 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1343 ret
= intel_ring_begin(waiter_req
, 4);
1347 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1348 MI_SEMAPHORE_GLOBAL_GTT
|
1350 MI_SEMAPHORE_SAD_GTE_SDD
);
1351 intel_ring_emit(waiter
, seqno
);
1352 intel_ring_emit(waiter
,
1353 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1354 intel_ring_emit(waiter
,
1355 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1356 intel_ring_advance(waiter
);
1361 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1362 struct intel_engine_cs
*signaller
,
1365 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1366 u32 dw1
= MI_SEMAPHORE_MBOX
|
1367 MI_SEMAPHORE_COMPARE
|
1368 MI_SEMAPHORE_REGISTER
;
1369 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1372 /* Throughout all of the GEM code, seqno passed implies our current
1373 * seqno is >= the last seqno executed. However for hardware the
1374 * comparison is strictly greater than.
1378 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1380 ret
= intel_ring_begin(waiter_req
, 4);
1384 /* If seqno wrap happened, omit the wait with no-ops */
1385 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1386 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1387 intel_ring_emit(waiter
, seqno
);
1388 intel_ring_emit(waiter
, 0);
1389 intel_ring_emit(waiter
, MI_NOOP
);
1391 intel_ring_emit(waiter
, MI_NOOP
);
1392 intel_ring_emit(waiter
, MI_NOOP
);
1393 intel_ring_emit(waiter
, MI_NOOP
);
1394 intel_ring_emit(waiter
, MI_NOOP
);
1396 intel_ring_advance(waiter
);
1401 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1403 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1404 PIPE_CONTROL_DEPTH_STALL); \
1405 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1406 intel_ring_emit(ring__, 0); \
1407 intel_ring_emit(ring__, 0); \
1411 pc_render_add_request(struct drm_i915_gem_request
*req
)
1413 struct intel_engine_cs
*ring
= req
->ring
;
1414 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1417 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1418 * incoherent with writes to memory, i.e. completely fubar,
1419 * so we need to use PIPE_NOTIFY instead.
1421 * However, we also need to workaround the qword write
1422 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1423 * memory before requesting an interrupt.
1425 ret
= intel_ring_begin(req
, 32);
1429 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1430 PIPE_CONTROL_WRITE_FLUSH
|
1431 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1432 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1433 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1434 intel_ring_emit(ring
, 0);
1435 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1436 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1437 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1438 scratch_addr
+= 2 * CACHELINE_BYTES
;
1439 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1440 scratch_addr
+= 2 * CACHELINE_BYTES
;
1441 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1442 scratch_addr
+= 2 * CACHELINE_BYTES
;
1443 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1444 scratch_addr
+= 2 * CACHELINE_BYTES
;
1445 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1447 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1448 PIPE_CONTROL_WRITE_FLUSH
|
1449 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1450 PIPE_CONTROL_NOTIFY
);
1451 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1452 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1453 intel_ring_emit(ring
, 0);
1454 __intel_ring_advance(ring
);
1460 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1462 /* Workaround to force correct ordering between irq and seqno writes on
1463 * ivb (and maybe also on snb) by reading from a CS register (like
1464 * ACTHD) before reading the status page. */
1465 if (!lazy_coherency
) {
1466 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1467 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1470 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1474 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1476 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1480 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1482 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1486 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1488 return ring
->scratch
.cpu_page
[0];
1492 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1494 ring
->scratch
.cpu_page
[0] = seqno
;
1498 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1500 struct drm_device
*dev
= ring
->dev
;
1501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 unsigned long flags
;
1504 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1507 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1508 if (ring
->irq_refcount
++ == 0)
1509 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1510 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1516 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1518 struct drm_device
*dev
= ring
->dev
;
1519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1520 unsigned long flags
;
1522 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1523 if (--ring
->irq_refcount
== 0)
1524 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1525 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1529 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1531 struct drm_device
*dev
= ring
->dev
;
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 unsigned long flags
;
1535 if (!intel_irqs_enabled(dev_priv
))
1538 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1539 if (ring
->irq_refcount
++ == 0) {
1540 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1541 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1544 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1550 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1552 struct drm_device
*dev
= ring
->dev
;
1553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1554 unsigned long flags
;
1556 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1557 if (--ring
->irq_refcount
== 0) {
1558 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1559 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1562 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1566 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1568 struct drm_device
*dev
= ring
->dev
;
1569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1570 unsigned long flags
;
1572 if (!intel_irqs_enabled(dev_priv
))
1575 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1576 if (ring
->irq_refcount
++ == 0) {
1577 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1578 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1579 POSTING_READ16(IMR
);
1581 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1587 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1589 struct drm_device
*dev
= ring
->dev
;
1590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1591 unsigned long flags
;
1593 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1594 if (--ring
->irq_refcount
== 0) {
1595 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1596 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1597 POSTING_READ16(IMR
);
1599 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1603 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1604 u32 invalidate_domains
,
1607 struct intel_engine_cs
*ring
= req
->ring
;
1610 ret
= intel_ring_begin(req
, 2);
1614 intel_ring_emit(ring
, MI_FLUSH
);
1615 intel_ring_emit(ring
, MI_NOOP
);
1616 intel_ring_advance(ring
);
1621 i9xx_add_request(struct drm_i915_gem_request
*req
)
1623 struct intel_engine_cs
*ring
= req
->ring
;
1626 ret
= intel_ring_begin(req
, 4);
1630 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1631 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1632 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1633 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1634 __intel_ring_advance(ring
);
1640 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1642 struct drm_device
*dev
= ring
->dev
;
1643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1644 unsigned long flags
;
1646 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1649 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1650 if (ring
->irq_refcount
++ == 0) {
1651 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1652 I915_WRITE_IMR(ring
,
1653 ~(ring
->irq_enable_mask
|
1654 GT_PARITY_ERROR(dev
)));
1656 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1657 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1659 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1665 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1667 struct drm_device
*dev
= ring
->dev
;
1668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1669 unsigned long flags
;
1671 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1672 if (--ring
->irq_refcount
== 0) {
1673 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1674 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1676 I915_WRITE_IMR(ring
, ~0);
1677 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1679 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1683 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1685 struct drm_device
*dev
= ring
->dev
;
1686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1687 unsigned long flags
;
1689 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1692 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1693 if (ring
->irq_refcount
++ == 0) {
1694 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1695 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1697 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1703 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1705 struct drm_device
*dev
= ring
->dev
;
1706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1707 unsigned long flags
;
1709 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1710 if (--ring
->irq_refcount
== 0) {
1711 I915_WRITE_IMR(ring
, ~0);
1712 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1714 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1718 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1720 struct drm_device
*dev
= ring
->dev
;
1721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1722 unsigned long flags
;
1724 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1727 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1728 if (ring
->irq_refcount
++ == 0) {
1729 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1730 I915_WRITE_IMR(ring
,
1731 ~(ring
->irq_enable_mask
|
1732 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1734 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1736 POSTING_READ(RING_IMR(ring
->mmio_base
));
1738 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1744 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1746 struct drm_device
*dev
= ring
->dev
;
1747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1748 unsigned long flags
;
1750 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1751 if (--ring
->irq_refcount
== 0) {
1752 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1753 I915_WRITE_IMR(ring
,
1754 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1756 I915_WRITE_IMR(ring
, ~0);
1758 POSTING_READ(RING_IMR(ring
->mmio_base
));
1760 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1764 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1765 u64 offset
, u32 length
,
1766 unsigned dispatch_flags
)
1768 struct intel_engine_cs
*ring
= req
->ring
;
1771 ret
= intel_ring_begin(req
, 2);
1775 intel_ring_emit(ring
,
1776 MI_BATCH_BUFFER_START
|
1778 (dispatch_flags
& I915_DISPATCH_SECURE
?
1779 0 : MI_BATCH_NON_SECURE_I965
));
1780 intel_ring_emit(ring
, offset
);
1781 intel_ring_advance(ring
);
1786 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1787 #define I830_BATCH_LIMIT (256*1024)
1788 #define I830_TLB_ENTRIES (2)
1789 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1791 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1792 u64 offset
, u32 len
,
1793 unsigned dispatch_flags
)
1795 struct intel_engine_cs
*ring
= req
->ring
;
1796 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1799 ret
= intel_ring_begin(req
, 6);
1803 /* Evict the invalid PTE TLBs */
1804 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1805 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1806 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1807 intel_ring_emit(ring
, cs_offset
);
1808 intel_ring_emit(ring
, 0xdeadbeef);
1809 intel_ring_emit(ring
, MI_NOOP
);
1810 intel_ring_advance(ring
);
1812 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1813 if (len
> I830_BATCH_LIMIT
)
1816 ret
= intel_ring_begin(req
, 6 + 2);
1820 /* Blit the batch (which has now all relocs applied) to the
1821 * stable batch scratch bo area (so that the CS never
1822 * stumbles over its tlb invalidation bug) ...
1824 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1825 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1826 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1827 intel_ring_emit(ring
, cs_offset
);
1828 intel_ring_emit(ring
, 4096);
1829 intel_ring_emit(ring
, offset
);
1831 intel_ring_emit(ring
, MI_FLUSH
);
1832 intel_ring_emit(ring
, MI_NOOP
);
1833 intel_ring_advance(ring
);
1835 /* ... and execute it. */
1839 ret
= intel_ring_begin(req
, 4);
1843 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1844 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1845 0 : MI_BATCH_NON_SECURE
));
1846 intel_ring_emit(ring
, offset
+ len
- 8);
1847 intel_ring_emit(ring
, MI_NOOP
);
1848 intel_ring_advance(ring
);
1854 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1855 u64 offset
, u32 len
,
1856 unsigned dispatch_flags
)
1858 struct intel_engine_cs
*ring
= req
->ring
;
1861 ret
= intel_ring_begin(req
, 2);
1865 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1866 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1867 0 : MI_BATCH_NON_SECURE
));
1868 intel_ring_advance(ring
);
1873 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1875 struct drm_i915_gem_object
*obj
;
1877 obj
= ring
->status_page
.obj
;
1881 kunmap(sg_page(obj
->pages
->sgl
));
1882 i915_gem_object_ggtt_unpin(obj
);
1883 drm_gem_object_unreference(&obj
->base
);
1884 ring
->status_page
.obj
= NULL
;
1887 static int init_status_page(struct intel_engine_cs
*ring
)
1889 struct drm_i915_gem_object
*obj
;
1891 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1895 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1897 DRM_ERROR("Failed to allocate status page\n");
1901 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1906 if (!HAS_LLC(ring
->dev
))
1907 /* On g33, we cannot place HWS above 256MiB, so
1908 * restrict its pinning to the low mappable arena.
1909 * Though this restriction is not documented for
1910 * gen4, gen5, or byt, they also behave similarly
1911 * and hang if the HWS is placed at the top of the
1912 * GTT. To generalise, it appears that all !llc
1913 * platforms have issues with us placing the HWS
1914 * above the mappable region (even though we never
1917 flags
|= PIN_MAPPABLE
;
1918 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1921 drm_gem_object_unreference(&obj
->base
);
1925 ring
->status_page
.obj
= obj
;
1928 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1929 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1930 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1932 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1933 ring
->name
, ring
->status_page
.gfx_addr
);
1938 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1940 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1942 if (!dev_priv
->status_page_dmah
) {
1943 dev_priv
->status_page_dmah
=
1944 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1945 if (!dev_priv
->status_page_dmah
)
1949 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1950 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1955 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1957 iounmap(ringbuf
->virtual_start
);
1958 ringbuf
->virtual_start
= NULL
;
1959 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1962 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
1963 struct intel_ringbuffer
*ringbuf
)
1965 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1966 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
1969 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1973 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1975 i915_gem_object_ggtt_unpin(obj
);
1979 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
1980 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
1981 if (ringbuf
->virtual_start
== NULL
) {
1982 i915_gem_object_ggtt_unpin(obj
);
1989 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1991 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1992 ringbuf
->obj
= NULL
;
1995 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1996 struct intel_ringbuffer
*ringbuf
)
1998 struct drm_i915_gem_object
*obj
;
2002 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2004 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
2008 /* mark ring buffers as read-only from GPU side by default */
2016 static int intel_init_ring_buffer(struct drm_device
*dev
,
2017 struct intel_engine_cs
*ring
)
2019 struct intel_ringbuffer
*ringbuf
;
2022 WARN_ON(ring
->buffer
);
2024 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2027 ring
->buffer
= ringbuf
;
2030 INIT_LIST_HEAD(&ring
->active_list
);
2031 INIT_LIST_HEAD(&ring
->request_list
);
2032 INIT_LIST_HEAD(&ring
->execlist_queue
);
2033 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2034 ringbuf
->size
= 32 * PAGE_SIZE
;
2035 ringbuf
->ring
= ring
;
2036 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
2038 init_waitqueue_head(&ring
->irq_queue
);
2040 if (I915_NEED_GFX_HWS(dev
)) {
2041 ret
= init_status_page(ring
);
2045 BUG_ON(ring
->id
!= RCS
);
2046 ret
= init_phys_status_page(ring
);
2051 WARN_ON(ringbuf
->obj
);
2053 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2055 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2060 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2062 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2064 intel_destroy_ringbuffer_obj(ringbuf
);
2068 /* Workaround an erratum on the i830 which causes a hang if
2069 * the TAIL pointer points to within the last 2 cachelines
2072 ringbuf
->effective_size
= ringbuf
->size
;
2073 if (IS_I830(dev
) || IS_845G(dev
))
2074 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
2076 ret
= i915_cmd_parser_init_ring(ring
);
2084 ring
->buffer
= NULL
;
2088 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
2090 struct drm_i915_private
*dev_priv
;
2091 struct intel_ringbuffer
*ringbuf
;
2093 if (!intel_ring_initialized(ring
))
2096 dev_priv
= to_i915(ring
->dev
);
2097 ringbuf
= ring
->buffer
;
2099 intel_stop_ring_buffer(ring
);
2100 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
2102 intel_unpin_ringbuffer_obj(ringbuf
);
2103 intel_destroy_ringbuffer_obj(ringbuf
);
2104 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2107 ring
->cleanup(ring
);
2109 cleanup_status_page(ring
);
2111 i915_cmd_parser_fini_ring(ring
);
2112 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2115 ring
->buffer
= NULL
;
2118 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
2120 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2121 struct drm_i915_gem_request
*request
;
2125 /* The whole point of reserving space is to not wait! */
2126 WARN_ON(ringbuf
->reserved_in_use
);
2128 if (intel_ring_space(ringbuf
) >= n
)
2131 list_for_each_entry(request
, &ring
->request_list
, list
) {
2132 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
2138 if (WARN_ON(&request
->list
== &ring
->request_list
))
2141 ret
= i915_wait_request(request
);
2145 ringbuf
->space
= space
;
2149 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
2151 uint32_t __iomem
*virt
;
2152 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2153 int rem
= ringbuf
->size
- ringbuf
->tail
;
2155 /* Can't wrap if space has already been reserved! */
2156 WARN_ON(ringbuf
->reserved_in_use
);
2158 if (ringbuf
->space
< rem
) {
2159 int ret
= ring_wait_for_space(ring
, rem
);
2164 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2167 iowrite32(MI_NOOP
, virt
++);
2170 intel_ring_update_space(ringbuf
);
2175 int intel_ring_idle(struct intel_engine_cs
*ring
)
2177 struct drm_i915_gem_request
*req
;
2179 /* We need to add any requests required to flush the objects and ring */
2180 WARN_ON(ring
->outstanding_lazy_request
);
2181 if (ring
->outstanding_lazy_request
)
2182 i915_add_request(ring
->outstanding_lazy_request
);
2184 /* Wait upon the last request to be completed */
2185 if (list_empty(&ring
->request_list
))
2188 req
= list_entry(ring
->request_list
.prev
,
2189 struct drm_i915_gem_request
,
2192 /* Make sure we do not trigger any retires */
2193 return __i915_wait_request(req
,
2194 atomic_read(&to_i915(ring
->dev
)->gpu_error
.reset_counter
),
2195 to_i915(ring
->dev
)->mm
.interruptible
,
2199 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2201 request
->ringbuf
= request
->ring
->buffer
;
2205 int intel_ring_reserve_space(struct drm_i915_gem_request
*request
)
2208 * The first call merely notes the reserve request and is common for
2209 * all back ends. The subsequent localised _begin() call actually
2210 * ensures that the reservation is available. Without the begin, if
2211 * the request creator immediately submitted the request without
2212 * adding any commands to it then there might not actually be
2213 * sufficient room for the submission commands.
2215 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
2217 return intel_ring_begin(request
, 0);
2220 void intel_ring_reserved_space_reserve(struct intel_ringbuffer
*ringbuf
, int size
)
2222 WARN_ON(ringbuf
->reserved_size
);
2223 WARN_ON(ringbuf
->reserved_in_use
);
2225 ringbuf
->reserved_size
= size
;
2228 void intel_ring_reserved_space_cancel(struct intel_ringbuffer
*ringbuf
)
2230 WARN_ON(ringbuf
->reserved_in_use
);
2232 ringbuf
->reserved_size
= 0;
2233 ringbuf
->reserved_in_use
= false;
2236 void intel_ring_reserved_space_use(struct intel_ringbuffer
*ringbuf
)
2238 WARN_ON(ringbuf
->reserved_in_use
);
2240 ringbuf
->reserved_in_use
= true;
2241 ringbuf
->reserved_tail
= ringbuf
->tail
;
2244 void intel_ring_reserved_space_end(struct intel_ringbuffer
*ringbuf
)
2246 WARN_ON(!ringbuf
->reserved_in_use
);
2247 WARN(ringbuf
->tail
> ringbuf
->reserved_tail
+ ringbuf
->reserved_size
,
2248 "request reserved size too small: %d vs %d!\n",
2249 ringbuf
->tail
- ringbuf
->reserved_tail
, ringbuf
->reserved_size
);
2251 ringbuf
->reserved_size
= 0;
2252 ringbuf
->reserved_in_use
= false;
2255 static int __intel_ring_prepare(struct intel_engine_cs
*ring
, int bytes
)
2257 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2261 * Add on the reserved size to the request to make sure that after
2262 * the intended commands have been emitted, there is guaranteed to
2263 * still be enough free space to send them to the hardware.
2265 if (!ringbuf
->reserved_in_use
)
2266 bytes
+= ringbuf
->reserved_size
;
2268 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2269 ret
= intel_wrap_ring_buffer(ring
);
2273 if(ringbuf
->reserved_size
) {
2274 uint32_t size
= ringbuf
->reserved_size
;
2276 intel_ring_reserved_space_cancel(ringbuf
);
2277 intel_ring_reserved_space_reserve(ringbuf
, size
);
2281 if (unlikely(ringbuf
->space
< bytes
)) {
2282 ret
= ring_wait_for_space(ring
, bytes
);
2290 int intel_ring_begin(struct drm_i915_gem_request
*req
,
2293 struct intel_engine_cs
*ring
;
2294 struct drm_i915_private
*dev_priv
;
2297 WARN_ON(req
== NULL
);
2299 dev_priv
= ring
->dev
->dev_private
;
2301 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2302 dev_priv
->mm
.interruptible
);
2306 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2310 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2314 /* Align the ring tail to a cacheline boundary */
2315 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2317 struct intel_engine_cs
*ring
= req
->ring
;
2318 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2321 if (num_dwords
== 0)
2324 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2325 ret
= intel_ring_begin(req
, num_dwords
);
2329 while (num_dwords
--)
2330 intel_ring_emit(ring
, MI_NOOP
);
2332 intel_ring_advance(ring
);
2337 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2339 struct drm_device
*dev
= ring
->dev
;
2340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 BUG_ON(ring
->outstanding_lazy_request
);
2344 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2345 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2346 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2348 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2351 ring
->set_seqno(ring
, seqno
);
2352 ring
->hangcheck
.seqno
= seqno
;
2355 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2358 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2360 /* Every tail move must follow the sequence below */
2362 /* Disable notification that the ring is IDLE. The GT
2363 * will then assume that it is busy and bring it out of rc6.
2365 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2366 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2368 /* Clear the context id. Here be magic! */
2369 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2371 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2372 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2373 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2375 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2377 /* Now that the ring is fully powered up, update the tail */
2378 I915_WRITE_TAIL(ring
, value
);
2379 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2381 /* Let the ring send IDLE messages to the GT again,
2382 * and so let it sleep to conserve power when idle.
2384 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2385 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2388 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2389 u32 invalidate
, u32 flush
)
2391 struct intel_engine_cs
*ring
= req
->ring
;
2395 ret
= intel_ring_begin(req
, 4);
2400 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2403 /* We always require a command barrier so that subsequent
2404 * commands, such as breadcrumb interrupts, are strictly ordered
2405 * wrt the contents of the write cache being flushed to memory
2406 * (and thus being coherent from the CPU).
2408 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2411 * Bspec vol 1c.5 - video engine command streamer:
2412 * "If ENABLED, all TLBs will be invalidated once the flush
2413 * operation is complete. This bit is only valid when the
2414 * Post-Sync Operation field is a value of 1h or 3h."
2416 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2417 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2419 intel_ring_emit(ring
, cmd
);
2420 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2421 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2422 intel_ring_emit(ring
, 0); /* upper addr */
2423 intel_ring_emit(ring
, 0); /* value */
2425 intel_ring_emit(ring
, 0);
2426 intel_ring_emit(ring
, MI_NOOP
);
2428 intel_ring_advance(ring
);
2433 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2434 u64 offset
, u32 len
,
2435 unsigned dispatch_flags
)
2437 struct intel_engine_cs
*ring
= req
->ring
;
2438 bool ppgtt
= USES_PPGTT(ring
->dev
) &&
2439 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2442 ret
= intel_ring_begin(req
, 4);
2446 /* FIXME(BDW): Address space and security selectors. */
2447 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2448 intel_ring_emit(ring
, lower_32_bits(offset
));
2449 intel_ring_emit(ring
, upper_32_bits(offset
));
2450 intel_ring_emit(ring
, MI_NOOP
);
2451 intel_ring_advance(ring
);
2457 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2458 u64 offset
, u32 len
,
2459 unsigned dispatch_flags
)
2461 struct intel_engine_cs
*ring
= req
->ring
;
2464 ret
= intel_ring_begin(req
, 2);
2468 intel_ring_emit(ring
,
2469 MI_BATCH_BUFFER_START
|
2470 (dispatch_flags
& I915_DISPATCH_SECURE
?
2471 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
));
2472 /* bit0-7 is the length on GEN6+ */
2473 intel_ring_emit(ring
, offset
);
2474 intel_ring_advance(ring
);
2480 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2481 u64 offset
, u32 len
,
2482 unsigned dispatch_flags
)
2484 struct intel_engine_cs
*ring
= req
->ring
;
2487 ret
= intel_ring_begin(req
, 2);
2491 intel_ring_emit(ring
,
2492 MI_BATCH_BUFFER_START
|
2493 (dispatch_flags
& I915_DISPATCH_SECURE
?
2494 0 : MI_BATCH_NON_SECURE_I965
));
2495 /* bit0-7 is the length on GEN6+ */
2496 intel_ring_emit(ring
, offset
);
2497 intel_ring_advance(ring
);
2502 /* Blitter support (SandyBridge+) */
2504 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2505 u32 invalidate
, u32 flush
)
2507 struct intel_engine_cs
*ring
= req
->ring
;
2508 struct drm_device
*dev
= ring
->dev
;
2512 ret
= intel_ring_begin(req
, 4);
2517 if (INTEL_INFO(dev
)->gen
>= 8)
2520 /* We always require a command barrier so that subsequent
2521 * commands, such as breadcrumb interrupts, are strictly ordered
2522 * wrt the contents of the write cache being flushed to memory
2523 * (and thus being coherent from the CPU).
2525 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2528 * Bspec vol 1c.3 - blitter engine command streamer:
2529 * "If ENABLED, all TLBs will be invalidated once the flush
2530 * operation is complete. This bit is only valid when the
2531 * Post-Sync Operation field is a value of 1h or 3h."
2533 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2534 cmd
|= MI_INVALIDATE_TLB
;
2535 intel_ring_emit(ring
, cmd
);
2536 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2537 if (INTEL_INFO(dev
)->gen
>= 8) {
2538 intel_ring_emit(ring
, 0); /* upper addr */
2539 intel_ring_emit(ring
, 0); /* value */
2541 intel_ring_emit(ring
, 0);
2542 intel_ring_emit(ring
, MI_NOOP
);
2544 intel_ring_advance(ring
);
2549 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2552 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2553 struct drm_i915_gem_object
*obj
;
2556 ring
->name
= "render ring";
2558 ring
->mmio_base
= RENDER_RING_BASE
;
2560 if (INTEL_INFO(dev
)->gen
>= 8) {
2561 if (i915_semaphore_is_enabled(dev
)) {
2562 obj
= i915_gem_alloc_object(dev
, 4096);
2564 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2565 i915
.semaphores
= 0;
2567 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2568 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2570 drm_gem_object_unreference(&obj
->base
);
2571 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2572 i915
.semaphores
= 0;
2574 dev_priv
->semaphore_obj
= obj
;
2578 ring
->init_context
= intel_rcs_ctx_init
;
2579 ring
->add_request
= gen6_add_request
;
2580 ring
->flush
= gen8_render_ring_flush
;
2581 ring
->irq_get
= gen8_ring_get_irq
;
2582 ring
->irq_put
= gen8_ring_put_irq
;
2583 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2584 ring
->get_seqno
= gen6_ring_get_seqno
;
2585 ring
->set_seqno
= ring_set_seqno
;
2586 if (i915_semaphore_is_enabled(dev
)) {
2587 WARN_ON(!dev_priv
->semaphore_obj
);
2588 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2589 ring
->semaphore
.signal
= gen8_rcs_signal
;
2590 GEN8_RING_SEMAPHORE_INIT
;
2592 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2593 ring
->add_request
= gen6_add_request
;
2594 ring
->flush
= gen7_render_ring_flush
;
2595 if (INTEL_INFO(dev
)->gen
== 6)
2596 ring
->flush
= gen6_render_ring_flush
;
2597 ring
->irq_get
= gen6_ring_get_irq
;
2598 ring
->irq_put
= gen6_ring_put_irq
;
2599 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2600 ring
->get_seqno
= gen6_ring_get_seqno
;
2601 ring
->set_seqno
= ring_set_seqno
;
2602 if (i915_semaphore_is_enabled(dev
)) {
2603 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2604 ring
->semaphore
.signal
= gen6_signal
;
2606 * The current semaphore is only applied on pre-gen8
2607 * platform. And there is no VCS2 ring on the pre-gen8
2608 * platform. So the semaphore between RCS and VCS2 is
2609 * initialized as INVALID. Gen8 will initialize the
2610 * sema between VCS2 and RCS later.
2612 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2613 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2614 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2615 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2616 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2617 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2618 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2619 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2620 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2621 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2623 } else if (IS_GEN5(dev
)) {
2624 ring
->add_request
= pc_render_add_request
;
2625 ring
->flush
= gen4_render_ring_flush
;
2626 ring
->get_seqno
= pc_render_get_seqno
;
2627 ring
->set_seqno
= pc_render_set_seqno
;
2628 ring
->irq_get
= gen5_ring_get_irq
;
2629 ring
->irq_put
= gen5_ring_put_irq
;
2630 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2631 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2633 ring
->add_request
= i9xx_add_request
;
2634 if (INTEL_INFO(dev
)->gen
< 4)
2635 ring
->flush
= gen2_render_ring_flush
;
2637 ring
->flush
= gen4_render_ring_flush
;
2638 ring
->get_seqno
= ring_get_seqno
;
2639 ring
->set_seqno
= ring_set_seqno
;
2641 ring
->irq_get
= i8xx_ring_get_irq
;
2642 ring
->irq_put
= i8xx_ring_put_irq
;
2644 ring
->irq_get
= i9xx_ring_get_irq
;
2645 ring
->irq_put
= i9xx_ring_put_irq
;
2647 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2649 ring
->write_tail
= ring_write_tail
;
2651 if (IS_HASWELL(dev
))
2652 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2653 else if (IS_GEN8(dev
))
2654 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2655 else if (INTEL_INFO(dev
)->gen
>= 6)
2656 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2657 else if (INTEL_INFO(dev
)->gen
>= 4)
2658 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2659 else if (IS_I830(dev
) || IS_845G(dev
))
2660 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2662 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2663 ring
->init_hw
= init_render_ring
;
2664 ring
->cleanup
= render_ring_cleanup
;
2666 /* Workaround batchbuffer to combat CS tlb bug. */
2667 if (HAS_BROKEN_CS_TLB(dev
)) {
2668 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2670 DRM_ERROR("Failed to allocate batch bo\n");
2674 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2676 drm_gem_object_unreference(&obj
->base
);
2677 DRM_ERROR("Failed to ping batch bo\n");
2681 ring
->scratch
.obj
= obj
;
2682 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2685 ret
= intel_init_ring_buffer(dev
, ring
);
2689 if (INTEL_INFO(dev
)->gen
>= 5) {
2690 ret
= intel_init_pipe_control(ring
);
2698 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2701 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2703 ring
->name
= "bsd ring";
2706 ring
->write_tail
= ring_write_tail
;
2707 if (INTEL_INFO(dev
)->gen
>= 6) {
2708 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2709 /* gen6 bsd needs a special wa for tail updates */
2711 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2712 ring
->flush
= gen6_bsd_ring_flush
;
2713 ring
->add_request
= gen6_add_request
;
2714 ring
->get_seqno
= gen6_ring_get_seqno
;
2715 ring
->set_seqno
= ring_set_seqno
;
2716 if (INTEL_INFO(dev
)->gen
>= 8) {
2717 ring
->irq_enable_mask
=
2718 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2719 ring
->irq_get
= gen8_ring_get_irq
;
2720 ring
->irq_put
= gen8_ring_put_irq
;
2721 ring
->dispatch_execbuffer
=
2722 gen8_ring_dispatch_execbuffer
;
2723 if (i915_semaphore_is_enabled(dev
)) {
2724 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2725 ring
->semaphore
.signal
= gen8_xcs_signal
;
2726 GEN8_RING_SEMAPHORE_INIT
;
2729 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2730 ring
->irq_get
= gen6_ring_get_irq
;
2731 ring
->irq_put
= gen6_ring_put_irq
;
2732 ring
->dispatch_execbuffer
=
2733 gen6_ring_dispatch_execbuffer
;
2734 if (i915_semaphore_is_enabled(dev
)) {
2735 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2736 ring
->semaphore
.signal
= gen6_signal
;
2737 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2738 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2739 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2740 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2741 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2742 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2743 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2744 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2745 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2746 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2750 ring
->mmio_base
= BSD_RING_BASE
;
2751 ring
->flush
= bsd_ring_flush
;
2752 ring
->add_request
= i9xx_add_request
;
2753 ring
->get_seqno
= ring_get_seqno
;
2754 ring
->set_seqno
= ring_set_seqno
;
2756 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2757 ring
->irq_get
= gen5_ring_get_irq
;
2758 ring
->irq_put
= gen5_ring_put_irq
;
2760 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2761 ring
->irq_get
= i9xx_ring_get_irq
;
2762 ring
->irq_put
= i9xx_ring_put_irq
;
2764 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2766 ring
->init_hw
= init_ring_common
;
2768 return intel_init_ring_buffer(dev
, ring
);
2772 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2774 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2777 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2779 ring
->name
= "bsd2 ring";
2782 ring
->write_tail
= ring_write_tail
;
2783 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2784 ring
->flush
= gen6_bsd_ring_flush
;
2785 ring
->add_request
= gen6_add_request
;
2786 ring
->get_seqno
= gen6_ring_get_seqno
;
2787 ring
->set_seqno
= ring_set_seqno
;
2788 ring
->irq_enable_mask
=
2789 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2790 ring
->irq_get
= gen8_ring_get_irq
;
2791 ring
->irq_put
= gen8_ring_put_irq
;
2792 ring
->dispatch_execbuffer
=
2793 gen8_ring_dispatch_execbuffer
;
2794 if (i915_semaphore_is_enabled(dev
)) {
2795 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2796 ring
->semaphore
.signal
= gen8_xcs_signal
;
2797 GEN8_RING_SEMAPHORE_INIT
;
2799 ring
->init_hw
= init_ring_common
;
2801 return intel_init_ring_buffer(dev
, ring
);
2804 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2807 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2809 ring
->name
= "blitter ring";
2812 ring
->mmio_base
= BLT_RING_BASE
;
2813 ring
->write_tail
= ring_write_tail
;
2814 ring
->flush
= gen6_ring_flush
;
2815 ring
->add_request
= gen6_add_request
;
2816 ring
->get_seqno
= gen6_ring_get_seqno
;
2817 ring
->set_seqno
= ring_set_seqno
;
2818 if (INTEL_INFO(dev
)->gen
>= 8) {
2819 ring
->irq_enable_mask
=
2820 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2821 ring
->irq_get
= gen8_ring_get_irq
;
2822 ring
->irq_put
= gen8_ring_put_irq
;
2823 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2824 if (i915_semaphore_is_enabled(dev
)) {
2825 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2826 ring
->semaphore
.signal
= gen8_xcs_signal
;
2827 GEN8_RING_SEMAPHORE_INIT
;
2830 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2831 ring
->irq_get
= gen6_ring_get_irq
;
2832 ring
->irq_put
= gen6_ring_put_irq
;
2833 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2834 if (i915_semaphore_is_enabled(dev
)) {
2835 ring
->semaphore
.signal
= gen6_signal
;
2836 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2838 * The current semaphore is only applied on pre-gen8
2839 * platform. And there is no VCS2 ring on the pre-gen8
2840 * platform. So the semaphore between BCS and VCS2 is
2841 * initialized as INVALID. Gen8 will initialize the
2842 * sema between BCS and VCS2 later.
2844 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2845 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2846 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2847 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2848 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2849 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2850 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2851 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2852 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2853 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2856 ring
->init_hw
= init_ring_common
;
2858 return intel_init_ring_buffer(dev
, ring
);
2861 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2864 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2866 ring
->name
= "video enhancement ring";
2869 ring
->mmio_base
= VEBOX_RING_BASE
;
2870 ring
->write_tail
= ring_write_tail
;
2871 ring
->flush
= gen6_ring_flush
;
2872 ring
->add_request
= gen6_add_request
;
2873 ring
->get_seqno
= gen6_ring_get_seqno
;
2874 ring
->set_seqno
= ring_set_seqno
;
2876 if (INTEL_INFO(dev
)->gen
>= 8) {
2877 ring
->irq_enable_mask
=
2878 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2879 ring
->irq_get
= gen8_ring_get_irq
;
2880 ring
->irq_put
= gen8_ring_put_irq
;
2881 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2882 if (i915_semaphore_is_enabled(dev
)) {
2883 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2884 ring
->semaphore
.signal
= gen8_xcs_signal
;
2885 GEN8_RING_SEMAPHORE_INIT
;
2888 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2889 ring
->irq_get
= hsw_vebox_get_irq
;
2890 ring
->irq_put
= hsw_vebox_put_irq
;
2891 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2892 if (i915_semaphore_is_enabled(dev
)) {
2893 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2894 ring
->semaphore
.signal
= gen6_signal
;
2895 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2896 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2897 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2898 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2899 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2900 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2901 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2902 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2903 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2904 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2907 ring
->init_hw
= init_ring_common
;
2909 return intel_init_ring_buffer(dev
, ring
);
2913 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
2915 struct intel_engine_cs
*ring
= req
->ring
;
2918 if (!ring
->gpu_caches_dirty
)
2921 ret
= ring
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
2925 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
2927 ring
->gpu_caches_dirty
= false;
2932 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
2934 struct intel_engine_cs
*ring
= req
->ring
;
2935 uint32_t flush_domains
;
2939 if (ring
->gpu_caches_dirty
)
2940 flush_domains
= I915_GEM_GPU_DOMAINS
;
2942 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2946 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2948 ring
->gpu_caches_dirty
= false;
2953 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2957 if (!intel_ring_initialized(ring
))
2960 ret
= intel_ring_idle(ring
);
2961 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2962 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",