2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
41 struct drm_i915_gem_object
*obj
;
42 volatile u32
*cpu_page
;
46 static inline int ring_space(struct intel_ring_buffer
*ring
)
48 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 struct pipe_control
*pc
= ring
->private;
179 u32 scratch_addr
= pc
->gtt_offset
+ 128;
183 ret
= intel_ring_begin(ring
, 6);
187 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
189 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
190 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
191 intel_ring_emit(ring
, 0); /* low dword */
192 intel_ring_emit(ring
, 0); /* high dword */
193 intel_ring_emit(ring
, MI_NOOP
);
194 intel_ring_advance(ring
);
196 ret
= intel_ring_begin(ring
, 6);
200 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
202 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, MI_NOOP
);
206 intel_ring_advance(ring
);
212 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
213 u32 invalidate_domains
, u32 flush_domains
)
216 struct pipe_control
*pc
= ring
->private;
217 u32 scratch_addr
= pc
->gtt_offset
+ 128;
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret
= intel_emit_post_sync_nonzero_flush(ring
);
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
230 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
231 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
236 flags
|= PIPE_CONTROL_CS_STALL
;
238 if (invalidate_domains
) {
239 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
240 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
244 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
246 * TLB invalidate requires a post-sync write.
248 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
251 ret
= intel_ring_begin(ring
, 4);
255 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring
, flags
);
257 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
258 intel_ring_emit(ring
, 0);
259 intel_ring_advance(ring
);
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
269 ret
= intel_ring_begin(ring
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
275 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
276 intel_ring_emit(ring
, 0);
277 intel_ring_emit(ring
, 0);
278 intel_ring_advance(ring
);
283 static int gen7_ring_fbc_flush(struct intel_ring_buffer
*ring
, u32 value
)
287 if (!ring
->fbc_dirty
)
290 ret
= intel_ring_begin(ring
, 4);
293 intel_ring_emit(ring
, MI_NOOP
);
294 /* WaFbcNukeOn3DBlt:ivb/hsw */
295 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
296 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
297 intel_ring_emit(ring
, value
);
298 intel_ring_advance(ring
);
300 ring
->fbc_dirty
= false;
305 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
306 u32 invalidate_domains
, u32 flush_domains
)
309 struct pipe_control
*pc
= ring
->private;
310 u32 scratch_addr
= pc
->gtt_offset
+ 128;
314 * Ensure that any following seqno writes only happen when the render
315 * cache is indeed flushed.
317 * Workaround: 4th PIPE_CONTROL command (except the ones with only
318 * read-cache invalidate bits set) must have the CS_STALL bit set. We
319 * don't try to be clever and just set it unconditionally.
321 flags
|= PIPE_CONTROL_CS_STALL
;
323 /* Just flush everything. Experiments have shown that reducing the
324 * number of bits based on the write domains has little performance
328 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
329 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
331 if (invalidate_domains
) {
332 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
333 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
334 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
335 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
336 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
337 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
339 * TLB invalidate requires a post-sync write.
341 flags
|= PIPE_CONTROL_QW_WRITE
;
342 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
344 /* Workaround: we must issue a pipe_control with CS-stall bit
345 * set before a pipe_control command that has the state cache
346 * invalidate bit set. */
347 gen7_render_ring_cs_stall_wa(ring
);
350 ret
= intel_ring_begin(ring
, 4);
354 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
355 intel_ring_emit(ring
, flags
);
356 intel_ring_emit(ring
, scratch_addr
);
357 intel_ring_emit(ring
, 0);
358 intel_ring_advance(ring
);
361 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
366 static void ring_write_tail(struct intel_ring_buffer
*ring
,
369 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
370 I915_WRITE_TAIL(ring
, value
);
373 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
375 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
376 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
377 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
379 return I915_READ(acthd_reg
);
382 static int init_ring_common(struct intel_ring_buffer
*ring
)
384 struct drm_device
*dev
= ring
->dev
;
385 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
386 struct drm_i915_gem_object
*obj
= ring
->obj
;
390 if (HAS_FORCE_WAKE(dev
))
391 gen6_gt_force_wake_get(dev_priv
);
393 /* Stop the ring if it's running. */
394 I915_WRITE_CTL(ring
, 0);
395 I915_WRITE_HEAD(ring
, 0);
396 ring
->write_tail(ring
, 0);
398 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
400 /* G45 ring initialization fails to reset head to zero */
402 DRM_DEBUG_KMS("%s head not reset to zero "
403 "ctl %08x head %08x tail %08x start %08x\n",
406 I915_READ_HEAD(ring
),
407 I915_READ_TAIL(ring
),
408 I915_READ_START(ring
));
410 I915_WRITE_HEAD(ring
, 0);
412 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
413 DRM_ERROR("failed to set %s head to zero "
414 "ctl %08x head %08x tail %08x start %08x\n",
417 I915_READ_HEAD(ring
),
418 I915_READ_TAIL(ring
),
419 I915_READ_START(ring
));
423 /* Initialize the ring. This must happen _after_ we've cleared the ring
424 * registers with the above sequence (the readback of the HEAD registers
425 * also enforces ordering), otherwise the hw might lose the new ring
426 * register values. */
427 I915_WRITE_START(ring
, obj
->gtt_offset
);
429 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
432 /* If the head is still not zero, the ring is dead */
433 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
434 I915_READ_START(ring
) == obj
->gtt_offset
&&
435 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
436 DRM_ERROR("%s initialization failed "
437 "ctl %08x head %08x tail %08x start %08x\n",
440 I915_READ_HEAD(ring
),
441 I915_READ_TAIL(ring
),
442 I915_READ_START(ring
));
447 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
448 i915_kernel_lost_context(ring
->dev
);
450 ring
->head
= I915_READ_HEAD(ring
);
451 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
452 ring
->space
= ring_space(ring
);
453 ring
->last_retired_head
= -1;
456 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
459 if (HAS_FORCE_WAKE(dev
))
460 gen6_gt_force_wake_put(dev_priv
);
466 init_pipe_control(struct intel_ring_buffer
*ring
)
468 struct pipe_control
*pc
;
469 struct drm_i915_gem_object
*obj
;
475 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
479 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
481 DRM_ERROR("Failed to allocate seqno page\n");
486 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
488 ret
= i915_gem_object_pin(obj
, 4096, true, false);
492 pc
->gtt_offset
= obj
->gtt_offset
;
493 pc
->cpu_page
= kmap(sg_page(obj
->pages
->sgl
));
494 if (pc
->cpu_page
== NULL
) {
499 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
500 ring
->name
, pc
->gtt_offset
);
507 i915_gem_object_unpin(obj
);
509 drm_gem_object_unreference(&obj
->base
);
516 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
518 struct pipe_control
*pc
= ring
->private;
519 struct drm_i915_gem_object
*obj
;
526 kunmap(sg_page(obj
->pages
->sgl
));
527 i915_gem_object_unpin(obj
);
528 drm_gem_object_unreference(&obj
->base
);
531 ring
->private = NULL
;
534 static int init_render_ring(struct intel_ring_buffer
*ring
)
536 struct drm_device
*dev
= ring
->dev
;
537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
538 int ret
= init_ring_common(ring
);
540 if (INTEL_INFO(dev
)->gen
> 3)
541 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
543 /* We need to disable the AsyncFlip performance optimisations in order
544 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
545 * programmed to '1' on all products.
547 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
549 if (INTEL_INFO(dev
)->gen
>= 6)
550 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
552 /* Required for the hardware to program scanline values for waiting */
553 if (INTEL_INFO(dev
)->gen
== 6)
555 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS
));
558 I915_WRITE(GFX_MODE_GEN7
,
559 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
560 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
562 if (INTEL_INFO(dev
)->gen
>= 5) {
563 ret
= init_pipe_control(ring
);
569 /* From the Sandybridge PRM, volume 1 part 3, page 24:
570 * "If this bit is set, STCunit will have LRA as replacement
571 * policy. [...] This bit must be reset. LRA replacement
572 * policy is not supported."
574 I915_WRITE(CACHE_MODE_0
,
575 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
577 /* This is not explicitly set for GEN6, so read the register.
578 * see intel_ring_mi_set_context() for why we care.
579 * TODO: consider explicitly setting the bit for GEN5
581 ring
->itlb_before_ctx_switch
=
582 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
585 if (INTEL_INFO(dev
)->gen
>= 6)
586 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
588 if (HAS_L3_GPU_CACHE(dev
))
589 I915_WRITE_IMR(ring
, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
594 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
596 struct drm_device
*dev
= ring
->dev
;
601 if (HAS_BROKEN_CS_TLB(dev
))
602 drm_gem_object_unreference(to_gem_object(ring
->private));
604 cleanup_pipe_control(ring
);
608 update_mboxes(struct intel_ring_buffer
*ring
,
611 /* NB: In order to be able to do semaphore MBOX updates for varying number
612 * of rings, it's easiest if we round up each individual update to a
613 * multiple of 2 (since ring updates must always be a multiple of 2)
614 * even though the actual update only requires 3 dwords.
616 #define MBOX_UPDATE_DWORDS 4
617 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
618 intel_ring_emit(ring
, mmio_offset
);
619 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
620 intel_ring_emit(ring
, MI_NOOP
);
624 * gen6_add_request - Update the semaphore mailbox registers
626 * @ring - ring that is adding a request
627 * @seqno - return seqno stuck into the ring
629 * Update the mailbox registers in the *other* rings with the current seqno.
630 * This acts like a signal in the canonical semaphore.
633 gen6_add_request(struct intel_ring_buffer
*ring
)
635 struct drm_device
*dev
= ring
->dev
;
636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
637 struct intel_ring_buffer
*useless
;
640 ret
= intel_ring_begin(ring
, ((I915_NUM_RINGS
-1) *
641 MBOX_UPDATE_DWORDS
) +
645 #undef MBOX_UPDATE_DWORDS
647 for_each_ring(useless
, dev_priv
, i
) {
648 u32 mbox_reg
= ring
->signal_mbox
[i
];
649 if (mbox_reg
!= GEN6_NOSYNC
)
650 update_mboxes(ring
, mbox_reg
);
653 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
654 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
655 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
656 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
657 intel_ring_advance(ring
);
662 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
666 return dev_priv
->last_seqno
< seqno
;
670 * intel_ring_sync - sync the waiter to the signaller on seqno
672 * @waiter - ring that is waiting
673 * @signaller - ring which has, or will signal
674 * @seqno - seqno which the waiter will block on
677 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
678 struct intel_ring_buffer
*signaller
,
682 u32 dw1
= MI_SEMAPHORE_MBOX
|
683 MI_SEMAPHORE_COMPARE
|
684 MI_SEMAPHORE_REGISTER
;
686 /* Throughout all of the GEM code, seqno passed implies our current
687 * seqno is >= the last seqno executed. However for hardware the
688 * comparison is strictly greater than.
692 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
693 MI_SEMAPHORE_SYNC_INVALID
);
695 ret
= intel_ring_begin(waiter
, 4);
699 /* If seqno wrap happened, omit the wait with no-ops */
700 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
701 intel_ring_emit(waiter
,
703 signaller
->semaphore_register
[waiter
->id
]);
704 intel_ring_emit(waiter
, seqno
);
705 intel_ring_emit(waiter
, 0);
706 intel_ring_emit(waiter
, MI_NOOP
);
708 intel_ring_emit(waiter
, MI_NOOP
);
709 intel_ring_emit(waiter
, MI_NOOP
);
710 intel_ring_emit(waiter
, MI_NOOP
);
711 intel_ring_emit(waiter
, MI_NOOP
);
713 intel_ring_advance(waiter
);
718 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
720 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
721 PIPE_CONTROL_DEPTH_STALL); \
722 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
723 intel_ring_emit(ring__, 0); \
724 intel_ring_emit(ring__, 0); \
728 pc_render_add_request(struct intel_ring_buffer
*ring
)
730 struct pipe_control
*pc
= ring
->private;
731 u32 scratch_addr
= pc
->gtt_offset
+ 128;
734 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
735 * incoherent with writes to memory, i.e. completely fubar,
736 * so we need to use PIPE_NOTIFY instead.
738 * However, we also need to workaround the qword write
739 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
740 * memory before requesting an interrupt.
742 ret
= intel_ring_begin(ring
, 32);
746 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
747 PIPE_CONTROL_WRITE_FLUSH
|
748 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
749 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
750 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
751 intel_ring_emit(ring
, 0);
752 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
753 scratch_addr
+= 128; /* write to separate cachelines */
754 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
756 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
758 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
760 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
762 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
764 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
765 PIPE_CONTROL_WRITE_FLUSH
|
766 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
767 PIPE_CONTROL_NOTIFY
);
768 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
769 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
770 intel_ring_emit(ring
, 0);
771 intel_ring_advance(ring
);
777 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
779 /* Workaround to force correct ordering between irq and seqno writes on
780 * ivb (and maybe also on snb) by reading from a CS register (like
781 * ACTHD) before reading the status page. */
783 intel_ring_get_active_head(ring
);
784 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
788 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
790 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
794 ring_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
796 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
800 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
802 struct pipe_control
*pc
= ring
->private;
803 return pc
->cpu_page
[0];
807 pc_render_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
809 struct pipe_control
*pc
= ring
->private;
810 pc
->cpu_page
[0] = seqno
;
814 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
816 struct drm_device
*dev
= ring
->dev
;
817 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
820 if (!dev
->irq_enabled
)
823 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
824 if (ring
->irq_refcount
.gt
++ == 0) {
825 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
826 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
829 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
835 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
837 struct drm_device
*dev
= ring
->dev
;
838 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
841 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
842 if (--ring
->irq_refcount
.gt
== 0) {
843 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
844 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
847 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
851 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
853 struct drm_device
*dev
= ring
->dev
;
854 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
857 if (!dev
->irq_enabled
)
860 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
861 if (ring
->irq_refcount
.gt
++ == 0) {
862 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
863 I915_WRITE(IMR
, dev_priv
->irq_mask
);
866 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
872 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
874 struct drm_device
*dev
= ring
->dev
;
875 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
878 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
879 if (--ring
->irq_refcount
.gt
== 0) {
880 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
881 I915_WRITE(IMR
, dev_priv
->irq_mask
);
884 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
888 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
890 struct drm_device
*dev
= ring
->dev
;
891 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
894 if (!dev
->irq_enabled
)
897 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
898 if (ring
->irq_refcount
.gt
++ == 0) {
899 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
900 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
903 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
909 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
911 struct drm_device
*dev
= ring
->dev
;
912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
915 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
916 if (--ring
->irq_refcount
.gt
== 0) {
917 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
918 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
921 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
924 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
926 struct drm_device
*dev
= ring
->dev
;
927 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
930 /* The ring status page addresses are no longer next to the rest of
931 * the ring registers as of gen7.
936 mmio
= RENDER_HWS_PGA_GEN7
;
939 mmio
= BLT_HWS_PGA_GEN7
;
942 mmio
= BSD_HWS_PGA_GEN7
;
945 mmio
= VEBOX_HWS_PGA_GEN7
;
948 } else if (IS_GEN6(ring
->dev
)) {
949 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
951 mmio
= RING_HWS_PGA(ring
->mmio_base
);
954 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
959 bsd_ring_flush(struct intel_ring_buffer
*ring
,
960 u32 invalidate_domains
,
965 ret
= intel_ring_begin(ring
, 2);
969 intel_ring_emit(ring
, MI_FLUSH
);
970 intel_ring_emit(ring
, MI_NOOP
);
971 intel_ring_advance(ring
);
976 i9xx_add_request(struct intel_ring_buffer
*ring
)
980 ret
= intel_ring_begin(ring
, 4);
984 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
985 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
986 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
987 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
988 intel_ring_advance(ring
);
994 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
996 struct drm_device
*dev
= ring
->dev
;
997 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1000 if (!dev
->irq_enabled
)
1003 /* It looks like we need to prevent the gt from suspending while waiting
1004 * for an notifiy irq, otherwise irqs seem to get lost on at least the
1005 * blt/bsd rings on ivb. */
1006 gen6_gt_force_wake_get(dev_priv
);
1008 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1009 if (ring
->irq_refcount
.gt
++ == 0) {
1010 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
1011 I915_WRITE_IMR(ring
,
1012 ~(ring
->irq_enable_mask
|
1013 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1015 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1016 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
1017 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1018 POSTING_READ(GTIMR
);
1020 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1026 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
1028 struct drm_device
*dev
= ring
->dev
;
1029 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1030 unsigned long flags
;
1032 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1033 if (--ring
->irq_refcount
.gt
== 0) {
1034 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
1035 I915_WRITE_IMR(ring
,
1036 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1038 I915_WRITE_IMR(ring
, ~0);
1039 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
1040 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1041 POSTING_READ(GTIMR
);
1043 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1045 gen6_gt_force_wake_put(dev_priv
);
1049 hsw_vebox_get_irq(struct intel_ring_buffer
*ring
)
1051 struct drm_device
*dev
= ring
->dev
;
1052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1053 unsigned long flags
;
1055 if (!dev
->irq_enabled
)
1058 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
1059 if (ring
->irq_refcount
.pm
++ == 0) {
1060 u32 pm_imr
= I915_READ(GEN6_PMIMR
);
1061 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1062 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~ring
->irq_enable_mask
);
1063 POSTING_READ(GEN6_PMIMR
);
1065 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
1071 hsw_vebox_put_irq(struct intel_ring_buffer
*ring
)
1073 struct drm_device
*dev
= ring
->dev
;
1074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1075 unsigned long flags
;
1077 if (!dev
->irq_enabled
)
1080 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
1081 if (--ring
->irq_refcount
.pm
== 0) {
1082 u32 pm_imr
= I915_READ(GEN6_PMIMR
);
1083 I915_WRITE_IMR(ring
, ~0);
1084 I915_WRITE(GEN6_PMIMR
, pm_imr
| ring
->irq_enable_mask
);
1085 POSTING_READ(GEN6_PMIMR
);
1087 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
1091 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1092 u32 offset
, u32 length
,
1097 ret
= intel_ring_begin(ring
, 2);
1101 intel_ring_emit(ring
,
1102 MI_BATCH_BUFFER_START
|
1104 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1105 intel_ring_emit(ring
, offset
);
1106 intel_ring_advance(ring
);
1111 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1112 #define I830_BATCH_LIMIT (256*1024)
1114 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1115 u32 offset
, u32 len
,
1120 if (flags
& I915_DISPATCH_PINNED
) {
1121 ret
= intel_ring_begin(ring
, 4);
1125 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1126 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1127 intel_ring_emit(ring
, offset
+ len
- 8);
1128 intel_ring_emit(ring
, MI_NOOP
);
1129 intel_ring_advance(ring
);
1131 struct drm_i915_gem_object
*obj
= ring
->private;
1132 u32 cs_offset
= obj
->gtt_offset
;
1134 if (len
> I830_BATCH_LIMIT
)
1137 ret
= intel_ring_begin(ring
, 9+3);
1140 /* Blit the batch (which has now all relocs applied) to the stable batch
1141 * scratch bo area (so that the CS never stumbles over its tlb
1142 * invalidation bug) ... */
1143 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1144 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1145 XY_SRC_COPY_BLT_WRITE_RGB
);
1146 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1147 intel_ring_emit(ring
, 0);
1148 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1149 intel_ring_emit(ring
, cs_offset
);
1150 intel_ring_emit(ring
, 0);
1151 intel_ring_emit(ring
, 4096);
1152 intel_ring_emit(ring
, offset
);
1153 intel_ring_emit(ring
, MI_FLUSH
);
1155 /* ... and execute it. */
1156 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1157 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1158 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1159 intel_ring_advance(ring
);
1166 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1167 u32 offset
, u32 len
,
1172 ret
= intel_ring_begin(ring
, 2);
1176 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1177 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1178 intel_ring_advance(ring
);
1183 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1185 struct drm_i915_gem_object
*obj
;
1187 obj
= ring
->status_page
.obj
;
1191 kunmap(sg_page(obj
->pages
->sgl
));
1192 i915_gem_object_unpin(obj
);
1193 drm_gem_object_unreference(&obj
->base
);
1194 ring
->status_page
.obj
= NULL
;
1197 static int init_status_page(struct intel_ring_buffer
*ring
)
1199 struct drm_device
*dev
= ring
->dev
;
1200 struct drm_i915_gem_object
*obj
;
1203 obj
= i915_gem_alloc_object(dev
, 4096);
1205 DRM_ERROR("Failed to allocate status page\n");
1210 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1212 ret
= i915_gem_object_pin(obj
, 4096, true, false);
1217 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
1218 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1219 if (ring
->status_page
.page_addr
== NULL
) {
1223 ring
->status_page
.obj
= obj
;
1224 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1226 intel_ring_setup_status_page(ring
);
1227 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1228 ring
->name
, ring
->status_page
.gfx_addr
);
1233 i915_gem_object_unpin(obj
);
1235 drm_gem_object_unreference(&obj
->base
);
1240 static int init_phys_hws_pga(struct intel_ring_buffer
*ring
)
1242 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1245 if (!dev_priv
->status_page_dmah
) {
1246 dev_priv
->status_page_dmah
=
1247 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1248 if (!dev_priv
->status_page_dmah
)
1252 addr
= dev_priv
->status_page_dmah
->busaddr
;
1253 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
1254 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
1255 I915_WRITE(HWS_PGA
, addr
);
1257 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1258 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1263 static int intel_init_ring_buffer(struct drm_device
*dev
,
1264 struct intel_ring_buffer
*ring
)
1266 struct drm_i915_gem_object
*obj
;
1267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1271 INIT_LIST_HEAD(&ring
->active_list
);
1272 INIT_LIST_HEAD(&ring
->request_list
);
1273 ring
->size
= 32 * PAGE_SIZE
;
1274 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1276 init_waitqueue_head(&ring
->irq_queue
);
1278 if (I915_NEED_GFX_HWS(dev
)) {
1279 ret
= init_status_page(ring
);
1283 BUG_ON(ring
->id
!= RCS
);
1284 ret
= init_phys_hws_pga(ring
);
1291 obj
= i915_gem_object_create_stolen(dev
, ring
->size
);
1293 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1295 DRM_ERROR("Failed to allocate ringbuffer\n");
1302 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true, false);
1306 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1310 ring
->virtual_start
=
1311 ioremap_wc(dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
,
1313 if (ring
->virtual_start
== NULL
) {
1314 DRM_ERROR("Failed to map ringbuffer.\n");
1319 ret
= ring
->init(ring
);
1323 /* Workaround an erratum on the i830 which causes a hang if
1324 * the TAIL pointer points to within the last 2 cachelines
1327 ring
->effective_size
= ring
->size
;
1328 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1329 ring
->effective_size
-= 128;
1334 iounmap(ring
->virtual_start
);
1336 i915_gem_object_unpin(obj
);
1338 drm_gem_object_unreference(&obj
->base
);
1341 cleanup_status_page(ring
);
1345 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1347 struct drm_i915_private
*dev_priv
;
1350 if (ring
->obj
== NULL
)
1353 /* Disable the ring buffer. The ring must be idle at this point */
1354 dev_priv
= ring
->dev
->dev_private
;
1355 ret
= intel_ring_idle(ring
);
1357 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1360 I915_WRITE_CTL(ring
, 0);
1362 iounmap(ring
->virtual_start
);
1364 i915_gem_object_unpin(ring
->obj
);
1365 drm_gem_object_unreference(&ring
->obj
->base
);
1369 ring
->cleanup(ring
);
1371 cleanup_status_page(ring
);
1374 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1378 ret
= i915_wait_seqno(ring
, seqno
);
1380 i915_gem_retire_requests_ring(ring
);
1385 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1387 struct drm_i915_gem_request
*request
;
1391 i915_gem_retire_requests_ring(ring
);
1393 if (ring
->last_retired_head
!= -1) {
1394 ring
->head
= ring
->last_retired_head
;
1395 ring
->last_retired_head
= -1;
1396 ring
->space
= ring_space(ring
);
1397 if (ring
->space
>= n
)
1401 list_for_each_entry(request
, &ring
->request_list
, list
) {
1404 if (request
->tail
== -1)
1407 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1409 space
+= ring
->size
;
1411 seqno
= request
->seqno
;
1415 /* Consume this request in case we need more space than
1416 * is available and so need to prevent a race between
1417 * updating last_retired_head and direct reads of
1418 * I915_RING_HEAD. It also provides a nice sanity check.
1426 ret
= intel_ring_wait_seqno(ring
, seqno
);
1430 if (WARN_ON(ring
->last_retired_head
== -1))
1433 ring
->head
= ring
->last_retired_head
;
1434 ring
->last_retired_head
= -1;
1435 ring
->space
= ring_space(ring
);
1436 if (WARN_ON(ring
->space
< n
))
1442 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1444 struct drm_device
*dev
= ring
->dev
;
1445 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1449 ret
= intel_ring_wait_request(ring
, n
);
1453 trace_i915_ring_wait_begin(ring
);
1454 /* With GEM the hangcheck timer should kick us out of the loop,
1455 * leaving it early runs the risk of corrupting GEM state (due
1456 * to running on almost untested codepaths). But on resume
1457 * timers don't work yet, so prevent a complete hang in that
1458 * case by choosing an insanely large timeout. */
1459 end
= jiffies
+ 60 * HZ
;
1462 ring
->head
= I915_READ_HEAD(ring
);
1463 ring
->space
= ring_space(ring
);
1464 if (ring
->space
>= n
) {
1465 trace_i915_ring_wait_end(ring
);
1469 if (dev
->primary
->master
) {
1470 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1471 if (master_priv
->sarea_priv
)
1472 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1477 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1478 dev_priv
->mm
.interruptible
);
1481 } while (!time_after(jiffies
, end
));
1482 trace_i915_ring_wait_end(ring
);
1486 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1488 uint32_t __iomem
*virt
;
1489 int rem
= ring
->size
- ring
->tail
;
1491 if (ring
->space
< rem
) {
1492 int ret
= ring_wait_for_space(ring
, rem
);
1497 virt
= ring
->virtual_start
+ ring
->tail
;
1500 iowrite32(MI_NOOP
, virt
++);
1503 ring
->space
= ring_space(ring
);
1508 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1513 /* We need to add any requests required to flush the objects and ring */
1514 if (ring
->outstanding_lazy_request
) {
1515 ret
= i915_add_request(ring
, NULL
, NULL
);
1520 /* Wait upon the last request to be completed */
1521 if (list_empty(&ring
->request_list
))
1524 seqno
= list_entry(ring
->request_list
.prev
,
1525 struct drm_i915_gem_request
,
1528 return i915_wait_seqno(ring
, seqno
);
1532 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1534 if (ring
->outstanding_lazy_request
)
1537 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_request
);
1540 static int __intel_ring_begin(struct intel_ring_buffer
*ring
,
1545 if (unlikely(ring
->tail
+ bytes
> ring
->effective_size
)) {
1546 ret
= intel_wrap_ring_buffer(ring
);
1551 if (unlikely(ring
->space
< bytes
)) {
1552 ret
= ring_wait_for_space(ring
, bytes
);
1557 ring
->space
-= bytes
;
1561 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1564 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1567 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1568 dev_priv
->mm
.interruptible
);
1572 /* Preallocate the olr before touching the ring */
1573 ret
= intel_ring_alloc_seqno(ring
);
1577 return __intel_ring_begin(ring
, num_dwords
* sizeof(uint32_t));
1580 void intel_ring_init_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1582 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1584 BUG_ON(ring
->outstanding_lazy_request
);
1586 if (INTEL_INFO(ring
->dev
)->gen
>= 6) {
1587 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
1588 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
1591 ring
->set_seqno(ring
, seqno
);
1592 ring
->hangcheck
.seqno
= seqno
;
1595 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1597 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1599 ring
->tail
&= ring
->size
- 1;
1600 if (dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
))
1602 ring
->write_tail(ring
, ring
->tail
);
1606 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1609 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1611 /* Every tail move must follow the sequence below */
1613 /* Disable notification that the ring is IDLE. The GT
1614 * will then assume that it is busy and bring it out of rc6.
1616 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1617 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1619 /* Clear the context id. Here be magic! */
1620 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1622 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1623 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1624 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1626 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1628 /* Now that the ring is fully powered up, update the tail */
1629 I915_WRITE_TAIL(ring
, value
);
1630 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1632 /* Let the ring send IDLE messages to the GT again,
1633 * and so let it sleep to conserve power when idle.
1635 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1636 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1639 static int gen6_bsd_ring_flush(struct intel_ring_buffer
*ring
,
1640 u32 invalidate
, u32 flush
)
1645 ret
= intel_ring_begin(ring
, 4);
1651 * Bspec vol 1c.5 - video engine command streamer:
1652 * "If ENABLED, all TLBs will be invalidated once the flush
1653 * operation is complete. This bit is only valid when the
1654 * Post-Sync Operation field is a value of 1h or 3h."
1656 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1657 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1658 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1659 intel_ring_emit(ring
, cmd
);
1660 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1661 intel_ring_emit(ring
, 0);
1662 intel_ring_emit(ring
, MI_NOOP
);
1663 intel_ring_advance(ring
);
1668 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1669 u32 offset
, u32 len
,
1674 ret
= intel_ring_begin(ring
, 2);
1678 intel_ring_emit(ring
,
1679 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1680 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1681 /* bit0-7 is the length on GEN6+ */
1682 intel_ring_emit(ring
, offset
);
1683 intel_ring_advance(ring
);
1689 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1690 u32 offset
, u32 len
,
1695 ret
= intel_ring_begin(ring
, 2);
1699 intel_ring_emit(ring
,
1700 MI_BATCH_BUFFER_START
|
1701 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1702 /* bit0-7 is the length on GEN6+ */
1703 intel_ring_emit(ring
, offset
);
1704 intel_ring_advance(ring
);
1709 /* Blitter support (SandyBridge+) */
1711 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1712 u32 invalidate
, u32 flush
)
1714 struct drm_device
*dev
= ring
->dev
;
1718 ret
= intel_ring_begin(ring
, 4);
1724 * Bspec vol 1c.3 - blitter engine command streamer:
1725 * "If ENABLED, all TLBs will be invalidated once the flush
1726 * operation is complete. This bit is only valid when the
1727 * Post-Sync Operation field is a value of 1h or 3h."
1729 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1730 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1731 MI_FLUSH_DW_OP_STOREDW
;
1732 intel_ring_emit(ring
, cmd
);
1733 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1734 intel_ring_emit(ring
, 0);
1735 intel_ring_emit(ring
, MI_NOOP
);
1736 intel_ring_advance(ring
);
1738 if (IS_GEN7(dev
) && flush
)
1739 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
1744 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1746 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1747 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1749 ring
->name
= "render ring";
1751 ring
->mmio_base
= RENDER_RING_BASE
;
1753 if (INTEL_INFO(dev
)->gen
>= 6) {
1754 ring
->add_request
= gen6_add_request
;
1755 ring
->flush
= gen7_render_ring_flush
;
1756 if (INTEL_INFO(dev
)->gen
== 6)
1757 ring
->flush
= gen6_render_ring_flush
;
1758 ring
->irq_get
= gen6_ring_get_irq
;
1759 ring
->irq_put
= gen6_ring_put_irq
;
1760 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
1761 ring
->get_seqno
= gen6_ring_get_seqno
;
1762 ring
->set_seqno
= ring_set_seqno
;
1763 ring
->sync_to
= gen6_ring_sync
;
1764 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1765 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
1766 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
1767 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
1768 ring
->signal_mbox
[RCS
] = GEN6_NOSYNC
;
1769 ring
->signal_mbox
[VCS
] = GEN6_VRSYNC
;
1770 ring
->signal_mbox
[BCS
] = GEN6_BRSYNC
;
1771 ring
->signal_mbox
[VECS
] = GEN6_VERSYNC
;
1772 } else if (IS_GEN5(dev
)) {
1773 ring
->add_request
= pc_render_add_request
;
1774 ring
->flush
= gen4_render_ring_flush
;
1775 ring
->get_seqno
= pc_render_get_seqno
;
1776 ring
->set_seqno
= pc_render_set_seqno
;
1777 ring
->irq_get
= gen5_ring_get_irq
;
1778 ring
->irq_put
= gen5_ring_put_irq
;
1779 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
1780 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
1782 ring
->add_request
= i9xx_add_request
;
1783 if (INTEL_INFO(dev
)->gen
< 4)
1784 ring
->flush
= gen2_render_ring_flush
;
1786 ring
->flush
= gen4_render_ring_flush
;
1787 ring
->get_seqno
= ring_get_seqno
;
1788 ring
->set_seqno
= ring_set_seqno
;
1790 ring
->irq_get
= i8xx_ring_get_irq
;
1791 ring
->irq_put
= i8xx_ring_put_irq
;
1793 ring
->irq_get
= i9xx_ring_get_irq
;
1794 ring
->irq_put
= i9xx_ring_put_irq
;
1796 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1798 ring
->write_tail
= ring_write_tail
;
1799 if (IS_HASWELL(dev
))
1800 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1801 else if (INTEL_INFO(dev
)->gen
>= 6)
1802 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1803 else if (INTEL_INFO(dev
)->gen
>= 4)
1804 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1805 else if (IS_I830(dev
) || IS_845G(dev
))
1806 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1808 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1809 ring
->init
= init_render_ring
;
1810 ring
->cleanup
= render_ring_cleanup
;
1812 /* Workaround batchbuffer to combat CS tlb bug. */
1813 if (HAS_BROKEN_CS_TLB(dev
)) {
1814 struct drm_i915_gem_object
*obj
;
1817 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
1819 DRM_ERROR("Failed to allocate batch bo\n");
1823 ret
= i915_gem_object_pin(obj
, 0, true, false);
1825 drm_gem_object_unreference(&obj
->base
);
1826 DRM_ERROR("Failed to ping batch bo\n");
1830 ring
->private = obj
;
1833 return intel_init_ring_buffer(dev
, ring
);
1836 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1838 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1839 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1842 ring
->name
= "render ring";
1844 ring
->mmio_base
= RENDER_RING_BASE
;
1846 if (INTEL_INFO(dev
)->gen
>= 6) {
1847 /* non-kms not supported on gen6+ */
1851 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1852 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1853 * the special gen5 functions. */
1854 ring
->add_request
= i9xx_add_request
;
1855 if (INTEL_INFO(dev
)->gen
< 4)
1856 ring
->flush
= gen2_render_ring_flush
;
1858 ring
->flush
= gen4_render_ring_flush
;
1859 ring
->get_seqno
= ring_get_seqno
;
1860 ring
->set_seqno
= ring_set_seqno
;
1862 ring
->irq_get
= i8xx_ring_get_irq
;
1863 ring
->irq_put
= i8xx_ring_put_irq
;
1865 ring
->irq_get
= i9xx_ring_get_irq
;
1866 ring
->irq_put
= i9xx_ring_put_irq
;
1868 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1869 ring
->write_tail
= ring_write_tail
;
1870 if (INTEL_INFO(dev
)->gen
>= 4)
1871 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1872 else if (IS_I830(dev
) || IS_845G(dev
))
1873 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1875 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1876 ring
->init
= init_render_ring
;
1877 ring
->cleanup
= render_ring_cleanup
;
1880 INIT_LIST_HEAD(&ring
->active_list
);
1881 INIT_LIST_HEAD(&ring
->request_list
);
1884 ring
->effective_size
= ring
->size
;
1885 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1886 ring
->effective_size
-= 128;
1888 ring
->virtual_start
= ioremap_wc(start
, size
);
1889 if (ring
->virtual_start
== NULL
) {
1890 DRM_ERROR("can not ioremap virtual address for"
1895 if (!I915_NEED_GFX_HWS(dev
)) {
1896 ret
= init_phys_hws_pga(ring
);
1904 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1907 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1909 ring
->name
= "bsd ring";
1912 ring
->write_tail
= ring_write_tail
;
1913 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1914 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1915 /* gen6 bsd needs a special wa for tail updates */
1917 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1918 ring
->flush
= gen6_bsd_ring_flush
;
1919 ring
->add_request
= gen6_add_request
;
1920 ring
->get_seqno
= gen6_ring_get_seqno
;
1921 ring
->set_seqno
= ring_set_seqno
;
1922 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1923 ring
->irq_get
= gen6_ring_get_irq
;
1924 ring
->irq_put
= gen6_ring_put_irq
;
1925 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1926 ring
->sync_to
= gen6_ring_sync
;
1927 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
1928 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1929 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
1930 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
1931 ring
->signal_mbox
[RCS
] = GEN6_RVSYNC
;
1932 ring
->signal_mbox
[VCS
] = GEN6_NOSYNC
;
1933 ring
->signal_mbox
[BCS
] = GEN6_BVSYNC
;
1934 ring
->signal_mbox
[VECS
] = GEN6_VEVSYNC
;
1936 ring
->mmio_base
= BSD_RING_BASE
;
1937 ring
->flush
= bsd_ring_flush
;
1938 ring
->add_request
= i9xx_add_request
;
1939 ring
->get_seqno
= ring_get_seqno
;
1940 ring
->set_seqno
= ring_set_seqno
;
1942 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
1943 ring
->irq_get
= gen5_ring_get_irq
;
1944 ring
->irq_put
= gen5_ring_put_irq
;
1946 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1947 ring
->irq_get
= i9xx_ring_get_irq
;
1948 ring
->irq_put
= i9xx_ring_put_irq
;
1950 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1952 ring
->init
= init_ring_common
;
1954 return intel_init_ring_buffer(dev
, ring
);
1957 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1959 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1960 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1962 ring
->name
= "blitter ring";
1965 ring
->mmio_base
= BLT_RING_BASE
;
1966 ring
->write_tail
= ring_write_tail
;
1967 ring
->flush
= gen6_ring_flush
;
1968 ring
->add_request
= gen6_add_request
;
1969 ring
->get_seqno
= gen6_ring_get_seqno
;
1970 ring
->set_seqno
= ring_set_seqno
;
1971 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
1972 ring
->irq_get
= gen6_ring_get_irq
;
1973 ring
->irq_put
= gen6_ring_put_irq
;
1974 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1975 ring
->sync_to
= gen6_ring_sync
;
1976 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
1977 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
1978 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1979 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
1980 ring
->signal_mbox
[RCS
] = GEN6_RBSYNC
;
1981 ring
->signal_mbox
[VCS
] = GEN6_VBSYNC
;
1982 ring
->signal_mbox
[BCS
] = GEN6_NOSYNC
;
1983 ring
->signal_mbox
[VECS
] = GEN6_VEBSYNC
;
1984 ring
->init
= init_ring_common
;
1986 return intel_init_ring_buffer(dev
, ring
);
1989 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
1991 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1992 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VECS
];
1994 ring
->name
= "video enhancement ring";
1997 ring
->mmio_base
= VEBOX_RING_BASE
;
1998 ring
->write_tail
= ring_write_tail
;
1999 ring
->flush
= gen6_ring_flush
;
2000 ring
->add_request
= gen6_add_request
;
2001 ring
->get_seqno
= gen6_ring_get_seqno
;
2002 ring
->set_seqno
= ring_set_seqno
;
2003 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
|
2004 PM_VEBOX_CS_ERROR_INTERRUPT
;
2005 ring
->irq_get
= hsw_vebox_get_irq
;
2006 ring
->irq_put
= hsw_vebox_put_irq
;
2007 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2008 ring
->sync_to
= gen6_ring_sync
;
2009 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2010 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2011 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2012 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2013 ring
->signal_mbox
[RCS
] = GEN6_RVESYNC
;
2014 ring
->signal_mbox
[VCS
] = GEN6_VVESYNC
;
2015 ring
->signal_mbox
[BCS
] = GEN6_BVESYNC
;
2016 ring
->signal_mbox
[VECS
] = GEN6_NOSYNC
;
2017 ring
->init
= init_ring_common
;
2019 return intel_init_ring_buffer(dev
, ring
);
2023 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
2027 if (!ring
->gpu_caches_dirty
)
2030 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2034 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2036 ring
->gpu_caches_dirty
= false;
2041 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
2043 uint32_t flush_domains
;
2047 if (ring
->gpu_caches_dirty
)
2048 flush_domains
= I915_GEM_GPU_DOMAINS
;
2050 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2054 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2056 ring
->gpu_caches_dirty
= false;