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drm/i915/dp/mst: Add source port info to debugfs output
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <linux/log2.h>
31 #include <drm/drmP.h>
32 #include "i915_drv.h"
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 int __intel_ring_space(int head, int tail, int size)
38 {
39 int space = head - tail;
40 if (space <= 0)
41 space += size;
42 return space - I915_RING_FREE_SPACE;
43 }
44
45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46 {
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54 }
55
56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
57 {
58 intel_ring_update_space(ringbuf);
59 return ringbuf->space;
60 }
61
62 bool intel_engine_stopped(struct intel_engine_cs *engine)
63 {
64 struct drm_i915_private *dev_priv = engine->dev->dev_private;
65 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
66 }
67
68 static void __intel_ring_advance(struct intel_engine_cs *engine)
69 {
70 struct intel_ringbuffer *ringbuf = engine->buffer;
71 ringbuf->tail &= ringbuf->size - 1;
72 if (intel_engine_stopped(engine))
73 return;
74 engine->write_tail(engine, ringbuf->tail);
75 }
76
77 static int
78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
79 u32 invalidate_domains,
80 u32 flush_domains)
81 {
82 struct intel_engine_cs *engine = req->engine;
83 u32 cmd;
84 int ret;
85
86 cmd = MI_FLUSH;
87 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
88 cmd |= MI_NO_WRITE_FLUSH;
89
90 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
91 cmd |= MI_READ_FLUSH;
92
93 ret = intel_ring_begin(req, 2);
94 if (ret)
95 return ret;
96
97 intel_ring_emit(engine, cmd);
98 intel_ring_emit(engine, MI_NOOP);
99 intel_ring_advance(engine);
100
101 return 0;
102 }
103
104 static int
105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
106 u32 invalidate_domains,
107 u32 flush_domains)
108 {
109 struct intel_engine_cs *engine = req->engine;
110 struct drm_device *dev = engine->dev;
111 u32 cmd;
112 int ret;
113
114 /*
115 * read/write caches:
116 *
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
120 *
121 * read-only caches:
122 *
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
125 *
126 * I915_GEM_DOMAIN_COMMAND may not exist?
127 *
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
130 *
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
133 *
134 * TLBs:
135 *
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
140 */
141
142 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
143 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
144 cmd &= ~MI_NO_WRITE_FLUSH;
145 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
146 cmd |= MI_EXE_FLUSH;
147
148 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
149 (IS_G4X(dev) || IS_GEN5(dev)))
150 cmd |= MI_INVALIDATE_ISP;
151
152 ret = intel_ring_begin(req, 2);
153 if (ret)
154 return ret;
155
156 intel_ring_emit(engine, cmd);
157 intel_ring_emit(engine, MI_NOOP);
158 intel_ring_advance(engine);
159
160 return 0;
161 }
162
163 /**
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
167 *
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * 0.
172 *
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
175 *
176 * And the workaround for these two requires this workaround first:
177 *
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * flushes.
181 *
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * volume 2 part 1:
185 *
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
193 *
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
199 */
200 static int
201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
202 {
203 struct intel_engine_cs *engine = req->engine;
204 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
205 int ret;
206
207 ret = intel_ring_begin(req, 6);
208 if (ret)
209 return ret;
210
211 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
213 PIPE_CONTROL_STALL_AT_SCOREBOARD);
214 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
215 intel_ring_emit(engine, 0); /* low dword */
216 intel_ring_emit(engine, 0); /* high dword */
217 intel_ring_emit(engine, MI_NOOP);
218 intel_ring_advance(engine);
219
220 ret = intel_ring_begin(req, 6);
221 if (ret)
222 return ret;
223
224 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
226 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
227 intel_ring_emit(engine, 0);
228 intel_ring_emit(engine, 0);
229 intel_ring_emit(engine, MI_NOOP);
230 intel_ring_advance(engine);
231
232 return 0;
233 }
234
235 static int
236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
237 u32 invalidate_domains, u32 flush_domains)
238 {
239 struct intel_engine_cs *engine = req->engine;
240 u32 flags = 0;
241 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
242 int ret;
243
244 /* Force SNB workarounds for PIPE_CONTROL flushes */
245 ret = intel_emit_post_sync_nonzero_flush(req);
246 if (ret)
247 return ret;
248
249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
251 * impact.
252 */
253 if (flush_domains) {
254 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
255 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
256 /*
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
259 */
260 flags |= PIPE_CONTROL_CS_STALL;
261 }
262 if (invalidate_domains) {
263 flags |= PIPE_CONTROL_TLB_INVALIDATE;
264 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
269 /*
270 * TLB invalidate requires a post-sync write.
271 */
272 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
273 }
274
275 ret = intel_ring_begin(req, 4);
276 if (ret)
277 return ret;
278
279 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(engine, flags);
281 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
282 intel_ring_emit(engine, 0);
283 intel_ring_advance(engine);
284
285 return 0;
286 }
287
288 static int
289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
290 {
291 struct intel_engine_cs *engine = req->engine;
292 int ret;
293
294 ret = intel_ring_begin(req, 4);
295 if (ret)
296 return ret;
297
298 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
300 PIPE_CONTROL_STALL_AT_SCOREBOARD);
301 intel_ring_emit(engine, 0);
302 intel_ring_emit(engine, 0);
303 intel_ring_advance(engine);
304
305 return 0;
306 }
307
308 static int
309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
310 u32 invalidate_domains, u32 flush_domains)
311 {
312 struct intel_engine_cs *engine = req->engine;
313 u32 flags = 0;
314 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
315 int ret;
316
317 /*
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
320 *
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
324 */
325 flags |= PIPE_CONTROL_CS_STALL;
326
327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
329 * impact.
330 */
331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
336 }
337 if (invalidate_domains) {
338 flags |= PIPE_CONTROL_TLB_INVALIDATE;
339 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
343 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
344 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
345 /*
346 * TLB invalidate requires a post-sync write.
347 */
348 flags |= PIPE_CONTROL_QW_WRITE;
349 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
350
351 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
352
353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
356 gen7_render_ring_cs_stall_wa(req);
357 }
358
359 ret = intel_ring_begin(req, 4);
360 if (ret)
361 return ret;
362
363 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(engine, flags);
365 intel_ring_emit(engine, scratch_addr);
366 intel_ring_emit(engine, 0);
367 intel_ring_advance(engine);
368
369 return 0;
370 }
371
372 static int
373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
374 u32 flags, u32 scratch_addr)
375 {
376 struct intel_engine_cs *engine = req->engine;
377 int ret;
378
379 ret = intel_ring_begin(req, 6);
380 if (ret)
381 return ret;
382
383 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(engine, flags);
385 intel_ring_emit(engine, scratch_addr);
386 intel_ring_emit(engine, 0);
387 intel_ring_emit(engine, 0);
388 intel_ring_emit(engine, 0);
389 intel_ring_advance(engine);
390
391 return 0;
392 }
393
394 static int
395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
396 u32 invalidate_domains, u32 flush_domains)
397 {
398 u32 flags = 0;
399 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
400 int ret;
401
402 flags |= PIPE_CONTROL_CS_STALL;
403
404 if (flush_domains) {
405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
409 }
410 if (invalidate_domains) {
411 flags |= PIPE_CONTROL_TLB_INVALIDATE;
412 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
416 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
417 flags |= PIPE_CONTROL_QW_WRITE;
418 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
419
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
421 ret = gen8_emit_pipe_control(req,
422 PIPE_CONTROL_CS_STALL |
423 PIPE_CONTROL_STALL_AT_SCOREBOARD,
424 0);
425 if (ret)
426 return ret;
427 }
428
429 return gen8_emit_pipe_control(req, flags, scratch_addr);
430 }
431
432 static void ring_write_tail(struct intel_engine_cs *engine,
433 u32 value)
434 {
435 struct drm_i915_private *dev_priv = engine->dev->dev_private;
436 I915_WRITE_TAIL(engine, value);
437 }
438
439 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
440 {
441 struct drm_i915_private *dev_priv = engine->dev->dev_private;
442 u64 acthd;
443
444 if (INTEL_INFO(engine->dev)->gen >= 8)
445 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
446 RING_ACTHD_UDW(engine->mmio_base));
447 else if (INTEL_INFO(engine->dev)->gen >= 4)
448 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
449 else
450 acthd = I915_READ(ACTHD);
451
452 return acthd;
453 }
454
455 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
456 {
457 struct drm_i915_private *dev_priv = engine->dev->dev_private;
458 u32 addr;
459
460 addr = dev_priv->status_page_dmah->busaddr;
461 if (INTEL_INFO(engine->dev)->gen >= 4)
462 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
463 I915_WRITE(HWS_PGA, addr);
464 }
465
466 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
467 {
468 struct drm_device *dev = engine->dev;
469 struct drm_i915_private *dev_priv = engine->dev->dev_private;
470 i915_reg_t mmio;
471
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
474 */
475 if (IS_GEN7(dev)) {
476 switch (engine->id) {
477 case RCS:
478 mmio = RENDER_HWS_PGA_GEN7;
479 break;
480 case BCS:
481 mmio = BLT_HWS_PGA_GEN7;
482 break;
483 /*
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
486 */
487 case VCS2:
488 case VCS:
489 mmio = BSD_HWS_PGA_GEN7;
490 break;
491 case VECS:
492 mmio = VEBOX_HWS_PGA_GEN7;
493 break;
494 }
495 } else if (IS_GEN6(engine->dev)) {
496 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
497 } else {
498 /* XXX: gen8 returns to sanity */
499 mmio = RING_HWS_PGA(engine->mmio_base);
500 }
501
502 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
503 POSTING_READ(mmio);
504
505 /*
506 * Flush the TLB for this page
507 *
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
511 */
512 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
513 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
514
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
517
518 I915_WRITE(reg,
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
520 INSTPM_SYNC_FLUSH));
521 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
522 1000))
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
524 engine->name);
525 }
526 }
527
528 static bool stop_ring(struct intel_engine_cs *engine)
529 {
530 struct drm_i915_private *dev_priv = to_i915(engine->dev);
531
532 if (!IS_GEN2(engine->dev)) {
533 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
534 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n",
536 engine->name);
537 /* Sometimes we observe that the idle flag is not
538 * set even though the ring is empty. So double
539 * check before giving up.
540 */
541 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
542 return false;
543 }
544 }
545
546 I915_WRITE_CTL(engine, 0);
547 I915_WRITE_HEAD(engine, 0);
548 engine->write_tail(engine, 0);
549
550 if (!IS_GEN2(engine->dev)) {
551 (void)I915_READ_CTL(engine);
552 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
553 }
554
555 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
556 }
557
558 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
559 {
560 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
561 }
562
563 static int init_ring_common(struct intel_engine_cs *engine)
564 {
565 struct drm_device *dev = engine->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
567 struct intel_ringbuffer *ringbuf = engine->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
569 int ret = 0;
570
571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
572
573 if (!stop_ring(engine)) {
574 /* G45 ring initialization often fails to reset head to zero */
575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 engine->name,
578 I915_READ_CTL(engine),
579 I915_READ_HEAD(engine),
580 I915_READ_TAIL(engine),
581 I915_READ_START(engine));
582
583 if (!stop_ring(engine)) {
584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 engine->name,
587 I915_READ_CTL(engine),
588 I915_READ_HEAD(engine),
589 I915_READ_TAIL(engine),
590 I915_READ_START(engine));
591 ret = -EIO;
592 goto out;
593 }
594 }
595
596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(engine);
598 else
599 ring_setup_phys_status_page(engine);
600
601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(engine);
603
604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
608 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(engine))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 engine->name, I915_READ_HEAD(engine));
614 I915_WRITE_HEAD(engine, 0);
615 (void)I915_READ_HEAD(engine);
616
617 I915_WRITE_CTL(engine,
618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
619 | RING_VALID);
620
621 /* If the head is still not zero, the ring is dead */
622 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
623 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
624 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
625 DRM_ERROR("%s initialization failed "
626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 engine->name,
628 I915_READ_CTL(engine),
629 I915_READ_CTL(engine) & RING_VALID,
630 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
631 I915_READ_START(engine),
632 (unsigned long)i915_gem_obj_ggtt_offset(obj));
633 ret = -EIO;
634 goto out;
635 }
636
637 ringbuf->last_retired_head = -1;
638 ringbuf->head = I915_READ_HEAD(engine);
639 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
640 intel_ring_update_space(ringbuf);
641
642 intel_engine_init_hangcheck(engine);
643
644 out:
645 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
646
647 return ret;
648 }
649
650 void
651 intel_fini_pipe_control(struct intel_engine_cs *engine)
652 {
653 struct drm_device *dev = engine->dev;
654
655 if (engine->scratch.obj == NULL)
656 return;
657
658 if (INTEL_INFO(dev)->gen >= 5) {
659 kunmap(sg_page(engine->scratch.obj->pages->sgl));
660 i915_gem_object_ggtt_unpin(engine->scratch.obj);
661 }
662
663 drm_gem_object_unreference(&engine->scratch.obj->base);
664 engine->scratch.obj = NULL;
665 }
666
667 int
668 intel_init_pipe_control(struct intel_engine_cs *engine)
669 {
670 int ret;
671
672 WARN_ON(engine->scratch.obj);
673
674 engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
675 if (engine->scratch.obj == NULL) {
676 DRM_ERROR("Failed to allocate seqno page\n");
677 ret = -ENOMEM;
678 goto err;
679 }
680
681 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
682 I915_CACHE_LLC);
683 if (ret)
684 goto err_unref;
685
686 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
687 if (ret)
688 goto err_unref;
689
690 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
691 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
692 if (engine->scratch.cpu_page == NULL) {
693 ret = -ENOMEM;
694 goto err_unpin;
695 }
696
697 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
698 engine->name, engine->scratch.gtt_offset);
699 return 0;
700
701 err_unpin:
702 i915_gem_object_ggtt_unpin(engine->scratch.obj);
703 err_unref:
704 drm_gem_object_unreference(&engine->scratch.obj->base);
705 err:
706 return ret;
707 }
708
709 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
710 {
711 int ret, i;
712 struct intel_engine_cs *engine = req->engine;
713 struct drm_device *dev = engine->dev;
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 struct i915_workarounds *w = &dev_priv->workarounds;
716
717 if (w->count == 0)
718 return 0;
719
720 engine->gpu_caches_dirty = true;
721 ret = intel_ring_flush_all_caches(req);
722 if (ret)
723 return ret;
724
725 ret = intel_ring_begin(req, (w->count * 2 + 2));
726 if (ret)
727 return ret;
728
729 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
730 for (i = 0; i < w->count; i++) {
731 intel_ring_emit_reg(engine, w->reg[i].addr);
732 intel_ring_emit(engine, w->reg[i].value);
733 }
734 intel_ring_emit(engine, MI_NOOP);
735
736 intel_ring_advance(engine);
737
738 engine->gpu_caches_dirty = true;
739 ret = intel_ring_flush_all_caches(req);
740 if (ret)
741 return ret;
742
743 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
744
745 return 0;
746 }
747
748 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
749 {
750 int ret;
751
752 ret = intel_ring_workarounds_emit(req);
753 if (ret != 0)
754 return ret;
755
756 ret = i915_gem_render_state_init(req);
757 if (ret)
758 return ret;
759
760 return 0;
761 }
762
763 static int wa_add(struct drm_i915_private *dev_priv,
764 i915_reg_t addr,
765 const u32 mask, const u32 val)
766 {
767 const u32 idx = dev_priv->workarounds.count;
768
769 if (WARN_ON(idx >= I915_MAX_WA_REGS))
770 return -ENOSPC;
771
772 dev_priv->workarounds.reg[idx].addr = addr;
773 dev_priv->workarounds.reg[idx].value = val;
774 dev_priv->workarounds.reg[idx].mask = mask;
775
776 dev_priv->workarounds.count++;
777
778 return 0;
779 }
780
781 #define WA_REG(addr, mask, val) do { \
782 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
783 if (r) \
784 return r; \
785 } while (0)
786
787 #define WA_SET_BIT_MASKED(addr, mask) \
788 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
789
790 #define WA_CLR_BIT_MASKED(addr, mask) \
791 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
792
793 #define WA_SET_FIELD_MASKED(addr, mask, value) \
794 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
795
796 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
797 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
798
799 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
800
801 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
802 i915_reg_t reg)
803 {
804 struct drm_i915_private *dev_priv = engine->dev->dev_private;
805 struct i915_workarounds *wa = &dev_priv->workarounds;
806 const uint32_t index = wa->hw_whitelist_count[engine->id];
807
808 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
809 return -EINVAL;
810
811 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
812 i915_mmio_reg_offset(reg));
813 wa->hw_whitelist_count[engine->id]++;
814
815 return 0;
816 }
817
818 static int gen8_init_workarounds(struct intel_engine_cs *engine)
819 {
820 struct drm_device *dev = engine->dev;
821 struct drm_i915_private *dev_priv = dev->dev_private;
822
823 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
824
825 /* WaDisableAsyncFlipPerfMode:bdw,chv */
826 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
827
828 /* WaDisablePartialInstShootdown:bdw,chv */
829 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
830 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
831
832 /* Use Force Non-Coherent whenever executing a 3D context. This is a
833 * workaround for for a possible hang in the unlikely event a TLB
834 * invalidation occurs during a PSD flush.
835 */
836 /* WaForceEnableNonCoherent:bdw,chv */
837 /* WaHdcDisableFetchWhenMasked:bdw,chv */
838 WA_SET_BIT_MASKED(HDC_CHICKEN0,
839 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
840 HDC_FORCE_NON_COHERENT);
841
842 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
843 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
844 * polygons in the same 8x4 pixel/sample area to be processed without
845 * stalling waiting for the earlier ones to write to Hierarchical Z
846 * buffer."
847 *
848 * This optimization is off by default for BDW and CHV; turn it on.
849 */
850 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
851
852 /* Wa4x4STCOptimizationDisable:bdw,chv */
853 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
854
855 /*
856 * BSpec recommends 8x4 when MSAA is used,
857 * however in practice 16x4 seems fastest.
858 *
859 * Note that PS/WM thread counts depend on the WIZ hashing
860 * disable bit, which we don't touch here, but it's good
861 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
862 */
863 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
864 GEN6_WIZ_HASHING_MASK,
865 GEN6_WIZ_HASHING_16x4);
866
867 return 0;
868 }
869
870 static int bdw_init_workarounds(struct intel_engine_cs *engine)
871 {
872 int ret;
873 struct drm_device *dev = engine->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875
876 ret = gen8_init_workarounds(engine);
877 if (ret)
878 return ret;
879
880 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
882
883 /* WaDisableDopClockGating:bdw */
884 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
885 DOP_CLOCK_GATING_DISABLE);
886
887 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
888 GEN8_SAMPLER_POWER_BYPASS_DIS);
889
890 WA_SET_BIT_MASKED(HDC_CHICKEN0,
891 /* WaForceContextSaveRestoreNonCoherent:bdw */
892 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
893 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
894 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
895
896 return 0;
897 }
898
899 static int chv_init_workarounds(struct intel_engine_cs *engine)
900 {
901 int ret;
902 struct drm_device *dev = engine->dev;
903 struct drm_i915_private *dev_priv = dev->dev_private;
904
905 ret = gen8_init_workarounds(engine);
906 if (ret)
907 return ret;
908
909 /* WaDisableThreadStallDopClockGating:chv */
910 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
911
912 /* Improve HiZ throughput on CHV. */
913 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
914
915 return 0;
916 }
917
918 static int gen9_init_workarounds(struct intel_engine_cs *engine)
919 {
920 struct drm_device *dev = engine->dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
922 uint32_t tmp;
923 int ret;
924
925 /* WaEnableLbsSlaRetryTimerDecrement:skl */
926 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
927 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
928
929 /* WaDisableKillLogic:bxt,skl */
930 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
931 ECOCHK_DIS_TLB);
932
933 /* WaClearFlowControlGpgpuContextSave:skl,bxt */
934 /* WaDisablePartialInstShootdown:skl,bxt */
935 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
936 FLOW_CONTROL_ENABLE |
937 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
938
939 /* Syncing dependencies between camera and graphics:skl,bxt */
940 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
941 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
942
943 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
944 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
945 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
946 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
947 GEN9_DG_MIRROR_FIX_ENABLE);
948
949 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
950 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
951 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
952 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
953 GEN9_RHWO_OPTIMIZATION_DISABLE);
954 /*
955 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
956 * but we do that in per ctx batchbuffer as there is an issue
957 * with this register not getting restored on ctx restore
958 */
959 }
960
961 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
962 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
963 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
964 GEN9_ENABLE_YV12_BUGFIX);
965
966 /* Wa4x4STCOptimizationDisable:skl,bxt */
967 /* WaDisablePartialResolveInVc:skl,bxt */
968 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
969 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
970
971 /* WaCcsTlbPrefetchDisable:skl,bxt */
972 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
973 GEN9_CCS_TLB_PREFETCH_ENABLE);
974
975 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
976 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
977 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
978 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
979 PIXEL_MASK_CAMMING_DISABLE);
980
981 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
982 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
983 if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
984 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
985 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
986 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
987
988 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
989 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
990 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
991 GEN8_SAMPLER_POWER_BYPASS_DIS);
992
993 /* WaDisableSTUnitPowerOptimization:skl,bxt */
994 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
995
996 /* WaOCLCoherentLineFlush:skl,bxt */
997 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
998 GEN8_LQSC_FLUSH_COHERENT_LINES));
999
1000 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
1001 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1002 if (ret)
1003 return ret;
1004
1005 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
1006 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1007 if (ret)
1008 return ret;
1009
1010 return 0;
1011 }
1012
1013 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1014 {
1015 struct drm_device *dev = engine->dev;
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017 u8 vals[3] = { 0, 0, 0 };
1018 unsigned int i;
1019
1020 for (i = 0; i < 3; i++) {
1021 u8 ss;
1022
1023 /*
1024 * Only consider slices where one, and only one, subslice has 7
1025 * EUs
1026 */
1027 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1028 continue;
1029
1030 /*
1031 * subslice_7eu[i] != 0 (because of the check above) and
1032 * ss_max == 4 (maximum number of subslices possible per slice)
1033 *
1034 * -> 0 <= ss <= 3;
1035 */
1036 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1037 vals[i] = 3 - ss;
1038 }
1039
1040 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1041 return 0;
1042
1043 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1044 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1045 GEN9_IZ_HASHING_MASK(2) |
1046 GEN9_IZ_HASHING_MASK(1) |
1047 GEN9_IZ_HASHING_MASK(0),
1048 GEN9_IZ_HASHING(2, vals[2]) |
1049 GEN9_IZ_HASHING(1, vals[1]) |
1050 GEN9_IZ_HASHING(0, vals[0]));
1051
1052 return 0;
1053 }
1054
1055 static int skl_init_workarounds(struct intel_engine_cs *engine)
1056 {
1057 int ret;
1058 struct drm_device *dev = engine->dev;
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060
1061 ret = gen9_init_workarounds(engine);
1062 if (ret)
1063 return ret;
1064
1065 /*
1066 * Actual WA is to disable percontext preemption granularity control
1067 * until D0 which is the default case so this is equivalent to
1068 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1069 */
1070 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1071 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1072 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1073 }
1074
1075 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1076 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1077 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1078 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1079 }
1080
1081 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1082 * involving this register should also be added to WA batch as required.
1083 */
1084 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1085 /* WaDisableLSQCROPERFforOCL:skl */
1086 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1087 GEN8_LQSC_RO_PERF_DIS);
1088
1089 /* WaEnableGapsTsvCreditFix:skl */
1090 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1091 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1092 GEN9_GAPS_TSV_CREDIT_DISABLE));
1093 }
1094
1095 /* WaDisablePowerCompilerClockGating:skl */
1096 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1097 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1098 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1099
1100 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
1101 /*
1102 *Use Force Non-Coherent whenever executing a 3D context. This
1103 * is a workaround for a possible hang in the unlikely event
1104 * a TLB invalidation occurs during a PSD flush.
1105 */
1106 /* WaForceEnableNonCoherent:skl */
1107 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1108 HDC_FORCE_NON_COHERENT);
1109
1110 /* WaDisableHDCInvalidation:skl */
1111 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1112 BDW_DISABLE_HDC_INVALIDATION);
1113 }
1114
1115 /* WaBarrierPerformanceFixDisable:skl */
1116 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1117 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1118 HDC_FENCE_DEST_SLM_DISABLE |
1119 HDC_BARRIER_PERFORMANCE_DISABLE);
1120
1121 /* WaDisableSbeCacheDispatchPortSharing:skl */
1122 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1123 WA_SET_BIT_MASKED(
1124 GEN7_HALF_SLICE_CHICKEN1,
1125 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1126
1127 /* WaDisableLSQCROPERFforOCL:skl */
1128 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1129 if (ret)
1130 return ret;
1131
1132 return skl_tune_iz_hashing(engine);
1133 }
1134
1135 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1136 {
1137 int ret;
1138 struct drm_device *dev = engine->dev;
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140
1141 ret = gen9_init_workarounds(engine);
1142 if (ret)
1143 return ret;
1144
1145 /* WaStoreMultiplePTEenable:bxt */
1146 /* This is a requirement according to Hardware specification */
1147 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1148 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1149
1150 /* WaSetClckGatingDisableMedia:bxt */
1151 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1152 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1153 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1154 }
1155
1156 /* WaDisableThreadStallDopClockGating:bxt */
1157 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1158 STALL_DOP_GATING_DISABLE);
1159
1160 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1161 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1162 WA_SET_BIT_MASKED(
1163 GEN7_HALF_SLICE_CHICKEN1,
1164 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1165 }
1166
1167 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1168 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1169 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1170 /* WaDisableLSQCROPERFforOCL:bxt */
1171 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1172 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1173 if (ret)
1174 return ret;
1175
1176 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1177 if (ret)
1178 return ret;
1179 }
1180
1181 return 0;
1182 }
1183
1184 int init_workarounds_ring(struct intel_engine_cs *engine)
1185 {
1186 struct drm_device *dev = engine->dev;
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188
1189 WARN_ON(engine->id != RCS);
1190
1191 dev_priv->workarounds.count = 0;
1192 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1193
1194 if (IS_BROADWELL(dev))
1195 return bdw_init_workarounds(engine);
1196
1197 if (IS_CHERRYVIEW(dev))
1198 return chv_init_workarounds(engine);
1199
1200 if (IS_SKYLAKE(dev))
1201 return skl_init_workarounds(engine);
1202
1203 if (IS_BROXTON(dev))
1204 return bxt_init_workarounds(engine);
1205
1206 return 0;
1207 }
1208
1209 static int init_render_ring(struct intel_engine_cs *engine)
1210 {
1211 struct drm_device *dev = engine->dev;
1212 struct drm_i915_private *dev_priv = dev->dev_private;
1213 int ret = init_ring_common(engine);
1214 if (ret)
1215 return ret;
1216
1217 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1218 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1219 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1220
1221 /* We need to disable the AsyncFlip performance optimisations in order
1222 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1223 * programmed to '1' on all products.
1224 *
1225 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1226 */
1227 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1228 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1229
1230 /* Required for the hardware to program scanline values for waiting */
1231 /* WaEnableFlushTlbInvalidationMode:snb */
1232 if (INTEL_INFO(dev)->gen == 6)
1233 I915_WRITE(GFX_MODE,
1234 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1235
1236 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1237 if (IS_GEN7(dev))
1238 I915_WRITE(GFX_MODE_GEN7,
1239 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1240 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1241
1242 if (IS_GEN6(dev)) {
1243 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1244 * "If this bit is set, STCunit will have LRA as replacement
1245 * policy. [...] This bit must be reset. LRA replacement
1246 * policy is not supported."
1247 */
1248 I915_WRITE(CACHE_MODE_0,
1249 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1250 }
1251
1252 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1253 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1254
1255 if (HAS_L3_DPF(dev))
1256 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1257
1258 return init_workarounds_ring(engine);
1259 }
1260
1261 static void render_ring_cleanup(struct intel_engine_cs *engine)
1262 {
1263 struct drm_device *dev = engine->dev;
1264 struct drm_i915_private *dev_priv = dev->dev_private;
1265
1266 if (dev_priv->semaphore_obj) {
1267 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1268 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1269 dev_priv->semaphore_obj = NULL;
1270 }
1271
1272 intel_fini_pipe_control(engine);
1273 }
1274
1275 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1276 unsigned int num_dwords)
1277 {
1278 #define MBOX_UPDATE_DWORDS 8
1279 struct intel_engine_cs *signaller = signaller_req->engine;
1280 struct drm_device *dev = signaller->dev;
1281 struct drm_i915_private *dev_priv = dev->dev_private;
1282 struct intel_engine_cs *waiter;
1283 enum intel_engine_id id;
1284 int ret, num_rings;
1285
1286 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1287 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1288 #undef MBOX_UPDATE_DWORDS
1289
1290 ret = intel_ring_begin(signaller_req, num_dwords);
1291 if (ret)
1292 return ret;
1293
1294 for_each_engine_id(waiter, dev_priv, id) {
1295 u32 seqno;
1296 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1297 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1298 continue;
1299
1300 seqno = i915_gem_request_get_seqno(signaller_req);
1301 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1302 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1303 PIPE_CONTROL_QW_WRITE |
1304 PIPE_CONTROL_FLUSH_ENABLE);
1305 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1306 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1307 intel_ring_emit(signaller, seqno);
1308 intel_ring_emit(signaller, 0);
1309 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1310 MI_SEMAPHORE_TARGET(waiter->id));
1311 intel_ring_emit(signaller, 0);
1312 }
1313
1314 return 0;
1315 }
1316
1317 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1318 unsigned int num_dwords)
1319 {
1320 #define MBOX_UPDATE_DWORDS 6
1321 struct intel_engine_cs *signaller = signaller_req->engine;
1322 struct drm_device *dev = signaller->dev;
1323 struct drm_i915_private *dev_priv = dev->dev_private;
1324 struct intel_engine_cs *waiter;
1325 enum intel_engine_id id;
1326 int ret, num_rings;
1327
1328 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1329 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1330 #undef MBOX_UPDATE_DWORDS
1331
1332 ret = intel_ring_begin(signaller_req, num_dwords);
1333 if (ret)
1334 return ret;
1335
1336 for_each_engine_id(waiter, dev_priv, id) {
1337 u32 seqno;
1338 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1339 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1340 continue;
1341
1342 seqno = i915_gem_request_get_seqno(signaller_req);
1343 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1344 MI_FLUSH_DW_OP_STOREDW);
1345 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1346 MI_FLUSH_DW_USE_GTT);
1347 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1348 intel_ring_emit(signaller, seqno);
1349 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1350 MI_SEMAPHORE_TARGET(waiter->id));
1351 intel_ring_emit(signaller, 0);
1352 }
1353
1354 return 0;
1355 }
1356
1357 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1358 unsigned int num_dwords)
1359 {
1360 struct intel_engine_cs *signaller = signaller_req->engine;
1361 struct drm_device *dev = signaller->dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 struct intel_engine_cs *useless;
1364 enum intel_engine_id id;
1365 int ret, num_rings;
1366
1367 #define MBOX_UPDATE_DWORDS 3
1368 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1369 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1370 #undef MBOX_UPDATE_DWORDS
1371
1372 ret = intel_ring_begin(signaller_req, num_dwords);
1373 if (ret)
1374 return ret;
1375
1376 for_each_engine_id(useless, dev_priv, id) {
1377 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1378
1379 if (i915_mmio_reg_valid(mbox_reg)) {
1380 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1381
1382 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1383 intel_ring_emit_reg(signaller, mbox_reg);
1384 intel_ring_emit(signaller, seqno);
1385 }
1386 }
1387
1388 /* If num_dwords was rounded, make sure the tail pointer is correct */
1389 if (num_rings % 2 == 0)
1390 intel_ring_emit(signaller, MI_NOOP);
1391
1392 return 0;
1393 }
1394
1395 /**
1396 * gen6_add_request - Update the semaphore mailbox registers
1397 *
1398 * @request - request to write to the ring
1399 *
1400 * Update the mailbox registers in the *other* rings with the current seqno.
1401 * This acts like a signal in the canonical semaphore.
1402 */
1403 static int
1404 gen6_add_request(struct drm_i915_gem_request *req)
1405 {
1406 struct intel_engine_cs *engine = req->engine;
1407 int ret;
1408
1409 if (engine->semaphore.signal)
1410 ret = engine->semaphore.signal(req, 4);
1411 else
1412 ret = intel_ring_begin(req, 4);
1413
1414 if (ret)
1415 return ret;
1416
1417 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1418 intel_ring_emit(engine,
1419 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1420 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1421 intel_ring_emit(engine, MI_USER_INTERRUPT);
1422 __intel_ring_advance(engine);
1423
1424 return 0;
1425 }
1426
1427 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1428 u32 seqno)
1429 {
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 return dev_priv->last_seqno < seqno;
1432 }
1433
1434 /**
1435 * intel_ring_sync - sync the waiter to the signaller on seqno
1436 *
1437 * @waiter - ring that is waiting
1438 * @signaller - ring which has, or will signal
1439 * @seqno - seqno which the waiter will block on
1440 */
1441
1442 static int
1443 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1444 struct intel_engine_cs *signaller,
1445 u32 seqno)
1446 {
1447 struct intel_engine_cs *waiter = waiter_req->engine;
1448 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1449 int ret;
1450
1451 ret = intel_ring_begin(waiter_req, 4);
1452 if (ret)
1453 return ret;
1454
1455 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1456 MI_SEMAPHORE_GLOBAL_GTT |
1457 MI_SEMAPHORE_POLL |
1458 MI_SEMAPHORE_SAD_GTE_SDD);
1459 intel_ring_emit(waiter, seqno);
1460 intel_ring_emit(waiter,
1461 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1462 intel_ring_emit(waiter,
1463 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1464 intel_ring_advance(waiter);
1465 return 0;
1466 }
1467
1468 static int
1469 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1470 struct intel_engine_cs *signaller,
1471 u32 seqno)
1472 {
1473 struct intel_engine_cs *waiter = waiter_req->engine;
1474 u32 dw1 = MI_SEMAPHORE_MBOX |
1475 MI_SEMAPHORE_COMPARE |
1476 MI_SEMAPHORE_REGISTER;
1477 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1478 int ret;
1479
1480 /* Throughout all of the GEM code, seqno passed implies our current
1481 * seqno is >= the last seqno executed. However for hardware the
1482 * comparison is strictly greater than.
1483 */
1484 seqno -= 1;
1485
1486 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1487
1488 ret = intel_ring_begin(waiter_req, 4);
1489 if (ret)
1490 return ret;
1491
1492 /* If seqno wrap happened, omit the wait with no-ops */
1493 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1494 intel_ring_emit(waiter, dw1 | wait_mbox);
1495 intel_ring_emit(waiter, seqno);
1496 intel_ring_emit(waiter, 0);
1497 intel_ring_emit(waiter, MI_NOOP);
1498 } else {
1499 intel_ring_emit(waiter, MI_NOOP);
1500 intel_ring_emit(waiter, MI_NOOP);
1501 intel_ring_emit(waiter, MI_NOOP);
1502 intel_ring_emit(waiter, MI_NOOP);
1503 }
1504 intel_ring_advance(waiter);
1505
1506 return 0;
1507 }
1508
1509 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1510 do { \
1511 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1512 PIPE_CONTROL_DEPTH_STALL); \
1513 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1514 intel_ring_emit(ring__, 0); \
1515 intel_ring_emit(ring__, 0); \
1516 } while (0)
1517
1518 static int
1519 pc_render_add_request(struct drm_i915_gem_request *req)
1520 {
1521 struct intel_engine_cs *engine = req->engine;
1522 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1523 int ret;
1524
1525 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1526 * incoherent with writes to memory, i.e. completely fubar,
1527 * so we need to use PIPE_NOTIFY instead.
1528 *
1529 * However, we also need to workaround the qword write
1530 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1531 * memory before requesting an interrupt.
1532 */
1533 ret = intel_ring_begin(req, 32);
1534 if (ret)
1535 return ret;
1536
1537 intel_ring_emit(engine,
1538 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1539 PIPE_CONTROL_WRITE_FLUSH |
1540 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1541 intel_ring_emit(engine,
1542 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1543 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1544 intel_ring_emit(engine, 0);
1545 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1546 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1547 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1548 scratch_addr += 2 * CACHELINE_BYTES;
1549 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1550 scratch_addr += 2 * CACHELINE_BYTES;
1551 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1552 scratch_addr += 2 * CACHELINE_BYTES;
1553 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1554 scratch_addr += 2 * CACHELINE_BYTES;
1555 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1556
1557 intel_ring_emit(engine,
1558 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1559 PIPE_CONTROL_WRITE_FLUSH |
1560 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1561 PIPE_CONTROL_NOTIFY);
1562 intel_ring_emit(engine,
1563 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1564 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1565 intel_ring_emit(engine, 0);
1566 __intel_ring_advance(engine);
1567
1568 return 0;
1569 }
1570
1571 static u32
1572 gen6_ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1573 {
1574 /* Workaround to force correct ordering between irq and seqno writes on
1575 * ivb (and maybe also on snb) by reading from a CS register (like
1576 * ACTHD) before reading the status page. */
1577 if (!lazy_coherency) {
1578 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1579 POSTING_READ(RING_ACTHD(engine->mmio_base));
1580 }
1581
1582 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1583 }
1584
1585 static u32
1586 ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1587 {
1588 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1589 }
1590
1591 static void
1592 ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1593 {
1594 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
1595 }
1596
1597 static u32
1598 pc_render_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
1599 {
1600 return engine->scratch.cpu_page[0];
1601 }
1602
1603 static void
1604 pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
1605 {
1606 engine->scratch.cpu_page[0] = seqno;
1607 }
1608
1609 static bool
1610 gen5_ring_get_irq(struct intel_engine_cs *engine)
1611 {
1612 struct drm_device *dev = engine->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 unsigned long flags;
1615
1616 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1617 return false;
1618
1619 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1620 if (engine->irq_refcount++ == 0)
1621 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1622 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1623
1624 return true;
1625 }
1626
1627 static void
1628 gen5_ring_put_irq(struct intel_engine_cs *engine)
1629 {
1630 struct drm_device *dev = engine->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 unsigned long flags;
1633
1634 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1635 if (--engine->irq_refcount == 0)
1636 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1637 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1638 }
1639
1640 static bool
1641 i9xx_ring_get_irq(struct intel_engine_cs *engine)
1642 {
1643 struct drm_device *dev = engine->dev;
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 unsigned long flags;
1646
1647 if (!intel_irqs_enabled(dev_priv))
1648 return false;
1649
1650 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1651 if (engine->irq_refcount++ == 0) {
1652 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1653 I915_WRITE(IMR, dev_priv->irq_mask);
1654 POSTING_READ(IMR);
1655 }
1656 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1657
1658 return true;
1659 }
1660
1661 static void
1662 i9xx_ring_put_irq(struct intel_engine_cs *engine)
1663 {
1664 struct drm_device *dev = engine->dev;
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 unsigned long flags;
1667
1668 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1669 if (--engine->irq_refcount == 0) {
1670 dev_priv->irq_mask |= engine->irq_enable_mask;
1671 I915_WRITE(IMR, dev_priv->irq_mask);
1672 POSTING_READ(IMR);
1673 }
1674 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1675 }
1676
1677 static bool
1678 i8xx_ring_get_irq(struct intel_engine_cs *engine)
1679 {
1680 struct drm_device *dev = engine->dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 unsigned long flags;
1683
1684 if (!intel_irqs_enabled(dev_priv))
1685 return false;
1686
1687 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1688 if (engine->irq_refcount++ == 0) {
1689 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1690 I915_WRITE16(IMR, dev_priv->irq_mask);
1691 POSTING_READ16(IMR);
1692 }
1693 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1694
1695 return true;
1696 }
1697
1698 static void
1699 i8xx_ring_put_irq(struct intel_engine_cs *engine)
1700 {
1701 struct drm_device *dev = engine->dev;
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 unsigned long flags;
1704
1705 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1706 if (--engine->irq_refcount == 0) {
1707 dev_priv->irq_mask |= engine->irq_enable_mask;
1708 I915_WRITE16(IMR, dev_priv->irq_mask);
1709 POSTING_READ16(IMR);
1710 }
1711 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1712 }
1713
1714 static int
1715 bsd_ring_flush(struct drm_i915_gem_request *req,
1716 u32 invalidate_domains,
1717 u32 flush_domains)
1718 {
1719 struct intel_engine_cs *engine = req->engine;
1720 int ret;
1721
1722 ret = intel_ring_begin(req, 2);
1723 if (ret)
1724 return ret;
1725
1726 intel_ring_emit(engine, MI_FLUSH);
1727 intel_ring_emit(engine, MI_NOOP);
1728 intel_ring_advance(engine);
1729 return 0;
1730 }
1731
1732 static int
1733 i9xx_add_request(struct drm_i915_gem_request *req)
1734 {
1735 struct intel_engine_cs *engine = req->engine;
1736 int ret;
1737
1738 ret = intel_ring_begin(req, 4);
1739 if (ret)
1740 return ret;
1741
1742 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1743 intel_ring_emit(engine,
1744 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1745 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1746 intel_ring_emit(engine, MI_USER_INTERRUPT);
1747 __intel_ring_advance(engine);
1748
1749 return 0;
1750 }
1751
1752 static bool
1753 gen6_ring_get_irq(struct intel_engine_cs *engine)
1754 {
1755 struct drm_device *dev = engine->dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 unsigned long flags;
1758
1759 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1760 return false;
1761
1762 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1763 if (engine->irq_refcount++ == 0) {
1764 if (HAS_L3_DPF(dev) && engine->id == RCS)
1765 I915_WRITE_IMR(engine,
1766 ~(engine->irq_enable_mask |
1767 GT_PARITY_ERROR(dev)));
1768 else
1769 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1770 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1771 }
1772 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1773
1774 return true;
1775 }
1776
1777 static void
1778 gen6_ring_put_irq(struct intel_engine_cs *engine)
1779 {
1780 struct drm_device *dev = engine->dev;
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 unsigned long flags;
1783
1784 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1785 if (--engine->irq_refcount == 0) {
1786 if (HAS_L3_DPF(dev) && engine->id == RCS)
1787 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
1788 else
1789 I915_WRITE_IMR(engine, ~0);
1790 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1791 }
1792 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1793 }
1794
1795 static bool
1796 hsw_vebox_get_irq(struct intel_engine_cs *engine)
1797 {
1798 struct drm_device *dev = engine->dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 unsigned long flags;
1801
1802 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1803 return false;
1804
1805 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1806 if (engine->irq_refcount++ == 0) {
1807 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1808 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1809 }
1810 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1811
1812 return true;
1813 }
1814
1815 static void
1816 hsw_vebox_put_irq(struct intel_engine_cs *engine)
1817 {
1818 struct drm_device *dev = engine->dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 unsigned long flags;
1821
1822 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1823 if (--engine->irq_refcount == 0) {
1824 I915_WRITE_IMR(engine, ~0);
1825 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1826 }
1827 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1828 }
1829
1830 static bool
1831 gen8_ring_get_irq(struct intel_engine_cs *engine)
1832 {
1833 struct drm_device *dev = engine->dev;
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835 unsigned long flags;
1836
1837 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1838 return false;
1839
1840 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1841 if (engine->irq_refcount++ == 0) {
1842 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1843 I915_WRITE_IMR(engine,
1844 ~(engine->irq_enable_mask |
1845 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1846 } else {
1847 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1848 }
1849 POSTING_READ(RING_IMR(engine->mmio_base));
1850 }
1851 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1852
1853 return true;
1854 }
1855
1856 static void
1857 gen8_ring_put_irq(struct intel_engine_cs *engine)
1858 {
1859 struct drm_device *dev = engine->dev;
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861 unsigned long flags;
1862
1863 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1864 if (--engine->irq_refcount == 0) {
1865 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1866 I915_WRITE_IMR(engine,
1867 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1868 } else {
1869 I915_WRITE_IMR(engine, ~0);
1870 }
1871 POSTING_READ(RING_IMR(engine->mmio_base));
1872 }
1873 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1874 }
1875
1876 static int
1877 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1878 u64 offset, u32 length,
1879 unsigned dispatch_flags)
1880 {
1881 struct intel_engine_cs *engine = req->engine;
1882 int ret;
1883
1884 ret = intel_ring_begin(req, 2);
1885 if (ret)
1886 return ret;
1887
1888 intel_ring_emit(engine,
1889 MI_BATCH_BUFFER_START |
1890 MI_BATCH_GTT |
1891 (dispatch_flags & I915_DISPATCH_SECURE ?
1892 0 : MI_BATCH_NON_SECURE_I965));
1893 intel_ring_emit(engine, offset);
1894 intel_ring_advance(engine);
1895
1896 return 0;
1897 }
1898
1899 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1900 #define I830_BATCH_LIMIT (256*1024)
1901 #define I830_TLB_ENTRIES (2)
1902 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1903 static int
1904 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1905 u64 offset, u32 len,
1906 unsigned dispatch_flags)
1907 {
1908 struct intel_engine_cs *engine = req->engine;
1909 u32 cs_offset = engine->scratch.gtt_offset;
1910 int ret;
1911
1912 ret = intel_ring_begin(req, 6);
1913 if (ret)
1914 return ret;
1915
1916 /* Evict the invalid PTE TLBs */
1917 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1918 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1919 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1920 intel_ring_emit(engine, cs_offset);
1921 intel_ring_emit(engine, 0xdeadbeef);
1922 intel_ring_emit(engine, MI_NOOP);
1923 intel_ring_advance(engine);
1924
1925 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1926 if (len > I830_BATCH_LIMIT)
1927 return -ENOSPC;
1928
1929 ret = intel_ring_begin(req, 6 + 2);
1930 if (ret)
1931 return ret;
1932
1933 /* Blit the batch (which has now all relocs applied) to the
1934 * stable batch scratch bo area (so that the CS never
1935 * stumbles over its tlb invalidation bug) ...
1936 */
1937 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1938 intel_ring_emit(engine,
1939 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1940 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1941 intel_ring_emit(engine, cs_offset);
1942 intel_ring_emit(engine, 4096);
1943 intel_ring_emit(engine, offset);
1944
1945 intel_ring_emit(engine, MI_FLUSH);
1946 intel_ring_emit(engine, MI_NOOP);
1947 intel_ring_advance(engine);
1948
1949 /* ... and execute it. */
1950 offset = cs_offset;
1951 }
1952
1953 ret = intel_ring_begin(req, 2);
1954 if (ret)
1955 return ret;
1956
1957 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1958 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1959 0 : MI_BATCH_NON_SECURE));
1960 intel_ring_advance(engine);
1961
1962 return 0;
1963 }
1964
1965 static int
1966 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1967 u64 offset, u32 len,
1968 unsigned dispatch_flags)
1969 {
1970 struct intel_engine_cs *engine = req->engine;
1971 int ret;
1972
1973 ret = intel_ring_begin(req, 2);
1974 if (ret)
1975 return ret;
1976
1977 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1978 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1979 0 : MI_BATCH_NON_SECURE));
1980 intel_ring_advance(engine);
1981
1982 return 0;
1983 }
1984
1985 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1986 {
1987 struct drm_i915_private *dev_priv = to_i915(engine->dev);
1988
1989 if (!dev_priv->status_page_dmah)
1990 return;
1991
1992 drm_pci_free(engine->dev, dev_priv->status_page_dmah);
1993 engine->status_page.page_addr = NULL;
1994 }
1995
1996 static void cleanup_status_page(struct intel_engine_cs *engine)
1997 {
1998 struct drm_i915_gem_object *obj;
1999
2000 obj = engine->status_page.obj;
2001 if (obj == NULL)
2002 return;
2003
2004 kunmap(sg_page(obj->pages->sgl));
2005 i915_gem_object_ggtt_unpin(obj);
2006 drm_gem_object_unreference(&obj->base);
2007 engine->status_page.obj = NULL;
2008 }
2009
2010 static int init_status_page(struct intel_engine_cs *engine)
2011 {
2012 struct drm_i915_gem_object *obj = engine->status_page.obj;
2013
2014 if (obj == NULL) {
2015 unsigned flags;
2016 int ret;
2017
2018 obj = i915_gem_alloc_object(engine->dev, 4096);
2019 if (obj == NULL) {
2020 DRM_ERROR("Failed to allocate status page\n");
2021 return -ENOMEM;
2022 }
2023
2024 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2025 if (ret)
2026 goto err_unref;
2027
2028 flags = 0;
2029 if (!HAS_LLC(engine->dev))
2030 /* On g33, we cannot place HWS above 256MiB, so
2031 * restrict its pinning to the low mappable arena.
2032 * Though this restriction is not documented for
2033 * gen4, gen5, or byt, they also behave similarly
2034 * and hang if the HWS is placed at the top of the
2035 * GTT. To generalise, it appears that all !llc
2036 * platforms have issues with us placing the HWS
2037 * above the mappable region (even though we never
2038 * actualy map it).
2039 */
2040 flags |= PIN_MAPPABLE;
2041 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2042 if (ret) {
2043 err_unref:
2044 drm_gem_object_unreference(&obj->base);
2045 return ret;
2046 }
2047
2048 engine->status_page.obj = obj;
2049 }
2050
2051 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2052 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2053 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2054
2055 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2056 engine->name, engine->status_page.gfx_addr);
2057
2058 return 0;
2059 }
2060
2061 static int init_phys_status_page(struct intel_engine_cs *engine)
2062 {
2063 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2064
2065 if (!dev_priv->status_page_dmah) {
2066 dev_priv->status_page_dmah =
2067 drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
2068 if (!dev_priv->status_page_dmah)
2069 return -ENOMEM;
2070 }
2071
2072 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2073 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
2074
2075 return 0;
2076 }
2077
2078 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2079 {
2080 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2081 vunmap(ringbuf->virtual_start);
2082 else
2083 iounmap(ringbuf->virtual_start);
2084 ringbuf->virtual_start = NULL;
2085 ringbuf->vma = NULL;
2086 i915_gem_object_ggtt_unpin(ringbuf->obj);
2087 }
2088
2089 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2090 {
2091 struct sg_page_iter sg_iter;
2092 struct page **pages;
2093 void *addr;
2094 int i;
2095
2096 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2097 if (pages == NULL)
2098 return NULL;
2099
2100 i = 0;
2101 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2102 pages[i++] = sg_page_iter_page(&sg_iter);
2103
2104 addr = vmap(pages, i, 0, PAGE_KERNEL);
2105 drm_free_large(pages);
2106
2107 return addr;
2108 }
2109
2110 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2111 struct intel_ringbuffer *ringbuf)
2112 {
2113 struct drm_i915_private *dev_priv = to_i915(dev);
2114 struct drm_i915_gem_object *obj = ringbuf->obj;
2115 int ret;
2116
2117 if (HAS_LLC(dev_priv) && !obj->stolen) {
2118 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2119 if (ret)
2120 return ret;
2121
2122 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2123 if (ret) {
2124 i915_gem_object_ggtt_unpin(obj);
2125 return ret;
2126 }
2127
2128 ringbuf->virtual_start = vmap_obj(obj);
2129 if (ringbuf->virtual_start == NULL) {
2130 i915_gem_object_ggtt_unpin(obj);
2131 return -ENOMEM;
2132 }
2133 } else {
2134 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2135 if (ret)
2136 return ret;
2137
2138 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2139 if (ret) {
2140 i915_gem_object_ggtt_unpin(obj);
2141 return ret;
2142 }
2143
2144 /* Access through the GTT requires the device to be awake. */
2145 assert_rpm_wakelock_held(dev_priv);
2146
2147 ringbuf->virtual_start = ioremap_wc(dev_priv->ggtt.mappable_base +
2148 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2149 if (ringbuf->virtual_start == NULL) {
2150 i915_gem_object_ggtt_unpin(obj);
2151 return -EINVAL;
2152 }
2153 }
2154
2155 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2156
2157 return 0;
2158 }
2159
2160 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2161 {
2162 drm_gem_object_unreference(&ringbuf->obj->base);
2163 ringbuf->obj = NULL;
2164 }
2165
2166 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2167 struct intel_ringbuffer *ringbuf)
2168 {
2169 struct drm_i915_gem_object *obj;
2170
2171 obj = NULL;
2172 if (!HAS_LLC(dev))
2173 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2174 if (obj == NULL)
2175 obj = i915_gem_alloc_object(dev, ringbuf->size);
2176 if (obj == NULL)
2177 return -ENOMEM;
2178
2179 /* mark ring buffers as read-only from GPU side by default */
2180 obj->gt_ro = 1;
2181
2182 ringbuf->obj = obj;
2183
2184 return 0;
2185 }
2186
2187 struct intel_ringbuffer *
2188 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2189 {
2190 struct intel_ringbuffer *ring;
2191 int ret;
2192
2193 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2194 if (ring == NULL) {
2195 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2196 engine->name);
2197 return ERR_PTR(-ENOMEM);
2198 }
2199
2200 ring->engine = engine;
2201 list_add(&ring->link, &engine->buffers);
2202
2203 ring->size = size;
2204 /* Workaround an erratum on the i830 which causes a hang if
2205 * the TAIL pointer points to within the last 2 cachelines
2206 * of the buffer.
2207 */
2208 ring->effective_size = size;
2209 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2210 ring->effective_size -= 2 * CACHELINE_BYTES;
2211
2212 ring->last_retired_head = -1;
2213 intel_ring_update_space(ring);
2214
2215 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2216 if (ret) {
2217 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2218 engine->name, ret);
2219 list_del(&ring->link);
2220 kfree(ring);
2221 return ERR_PTR(ret);
2222 }
2223
2224 return ring;
2225 }
2226
2227 void
2228 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2229 {
2230 intel_destroy_ringbuffer_obj(ring);
2231 list_del(&ring->link);
2232 kfree(ring);
2233 }
2234
2235 static int intel_init_ring_buffer(struct drm_device *dev,
2236 struct intel_engine_cs *engine)
2237 {
2238 struct intel_ringbuffer *ringbuf;
2239 int ret;
2240
2241 WARN_ON(engine->buffer);
2242
2243 engine->dev = dev;
2244 INIT_LIST_HEAD(&engine->active_list);
2245 INIT_LIST_HEAD(&engine->request_list);
2246 INIT_LIST_HEAD(&engine->execlist_queue);
2247 INIT_LIST_HEAD(&engine->buffers);
2248 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2249 memset(engine->semaphore.sync_seqno, 0,
2250 sizeof(engine->semaphore.sync_seqno));
2251
2252 init_waitqueue_head(&engine->irq_queue);
2253
2254 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2255 if (IS_ERR(ringbuf)) {
2256 ret = PTR_ERR(ringbuf);
2257 goto error;
2258 }
2259 engine->buffer = ringbuf;
2260
2261 if (I915_NEED_GFX_HWS(dev)) {
2262 ret = init_status_page(engine);
2263 if (ret)
2264 goto error;
2265 } else {
2266 WARN_ON(engine->id != RCS);
2267 ret = init_phys_status_page(engine);
2268 if (ret)
2269 goto error;
2270 }
2271
2272 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2273 if (ret) {
2274 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2275 engine->name, ret);
2276 intel_destroy_ringbuffer_obj(ringbuf);
2277 goto error;
2278 }
2279
2280 ret = i915_cmd_parser_init_ring(engine);
2281 if (ret)
2282 goto error;
2283
2284 return 0;
2285
2286 error:
2287 intel_cleanup_engine(engine);
2288 return ret;
2289 }
2290
2291 void intel_cleanup_engine(struct intel_engine_cs *engine)
2292 {
2293 struct drm_i915_private *dev_priv;
2294
2295 if (!intel_engine_initialized(engine))
2296 return;
2297
2298 dev_priv = to_i915(engine->dev);
2299
2300 if (engine->buffer) {
2301 intel_stop_engine(engine);
2302 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2303
2304 intel_unpin_ringbuffer_obj(engine->buffer);
2305 intel_ringbuffer_free(engine->buffer);
2306 engine->buffer = NULL;
2307 }
2308
2309 if (engine->cleanup)
2310 engine->cleanup(engine);
2311
2312 if (I915_NEED_GFX_HWS(engine->dev)) {
2313 cleanup_status_page(engine);
2314 } else {
2315 WARN_ON(engine->id != RCS);
2316 cleanup_phys_status_page(engine);
2317 }
2318
2319 i915_cmd_parser_fini_ring(engine);
2320 i915_gem_batch_pool_fini(&engine->batch_pool);
2321 engine->dev = NULL;
2322 }
2323
2324 static int ring_wait_for_space(struct intel_engine_cs *engine, int n)
2325 {
2326 struct intel_ringbuffer *ringbuf = engine->buffer;
2327 struct drm_i915_gem_request *request;
2328 unsigned space;
2329 int ret;
2330
2331 if (intel_ring_space(ringbuf) >= n)
2332 return 0;
2333
2334 /* The whole point of reserving space is to not wait! */
2335 WARN_ON(ringbuf->reserved_in_use);
2336
2337 list_for_each_entry(request, &engine->request_list, list) {
2338 space = __intel_ring_space(request->postfix, ringbuf->tail,
2339 ringbuf->size);
2340 if (space >= n)
2341 break;
2342 }
2343
2344 if (WARN_ON(&request->list == &engine->request_list))
2345 return -ENOSPC;
2346
2347 ret = i915_wait_request(request);
2348 if (ret)
2349 return ret;
2350
2351 ringbuf->space = space;
2352 return 0;
2353 }
2354
2355 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2356 {
2357 uint32_t __iomem *virt;
2358 int rem = ringbuf->size - ringbuf->tail;
2359
2360 virt = ringbuf->virtual_start + ringbuf->tail;
2361 rem /= 4;
2362 while (rem--)
2363 iowrite32(MI_NOOP, virt++);
2364
2365 ringbuf->tail = 0;
2366 intel_ring_update_space(ringbuf);
2367 }
2368
2369 int intel_engine_idle(struct intel_engine_cs *engine)
2370 {
2371 struct drm_i915_gem_request *req;
2372
2373 /* Wait upon the last request to be completed */
2374 if (list_empty(&engine->request_list))
2375 return 0;
2376
2377 req = list_entry(engine->request_list.prev,
2378 struct drm_i915_gem_request,
2379 list);
2380
2381 /* Make sure we do not trigger any retires */
2382 return __i915_wait_request(req,
2383 atomic_read(&to_i915(engine->dev)->gpu_error.reset_counter),
2384 to_i915(engine->dev)->mm.interruptible,
2385 NULL, NULL);
2386 }
2387
2388 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2389 {
2390 request->ringbuf = request->engine->buffer;
2391 return 0;
2392 }
2393
2394 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2395 {
2396 /*
2397 * The first call merely notes the reserve request and is common for
2398 * all back ends. The subsequent localised _begin() call actually
2399 * ensures that the reservation is available. Without the begin, if
2400 * the request creator immediately submitted the request without
2401 * adding any commands to it then there might not actually be
2402 * sufficient room for the submission commands.
2403 */
2404 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2405
2406 return intel_ring_begin(request, 0);
2407 }
2408
2409 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2410 {
2411 WARN_ON(ringbuf->reserved_size);
2412 WARN_ON(ringbuf->reserved_in_use);
2413
2414 ringbuf->reserved_size = size;
2415 }
2416
2417 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2418 {
2419 WARN_ON(ringbuf->reserved_in_use);
2420
2421 ringbuf->reserved_size = 0;
2422 ringbuf->reserved_in_use = false;
2423 }
2424
2425 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2426 {
2427 WARN_ON(ringbuf->reserved_in_use);
2428
2429 ringbuf->reserved_in_use = true;
2430 ringbuf->reserved_tail = ringbuf->tail;
2431 }
2432
2433 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2434 {
2435 WARN_ON(!ringbuf->reserved_in_use);
2436 if (ringbuf->tail > ringbuf->reserved_tail) {
2437 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2438 "request reserved size too small: %d vs %d!\n",
2439 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2440 } else {
2441 /*
2442 * The ring was wrapped while the reserved space was in use.
2443 * That means that some unknown amount of the ring tail was
2444 * no-op filled and skipped. Thus simply adding the ring size
2445 * to the tail and doing the above space check will not work.
2446 * Rather than attempt to track how much tail was skipped,
2447 * it is much simpler to say that also skipping the sanity
2448 * check every once in a while is not a big issue.
2449 */
2450 }
2451
2452 ringbuf->reserved_size = 0;
2453 ringbuf->reserved_in_use = false;
2454 }
2455
2456 static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes)
2457 {
2458 struct intel_ringbuffer *ringbuf = engine->buffer;
2459 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2460 int remain_actual = ringbuf->size - ringbuf->tail;
2461 int ret, total_bytes, wait_bytes = 0;
2462 bool need_wrap = false;
2463
2464 if (ringbuf->reserved_in_use)
2465 total_bytes = bytes;
2466 else
2467 total_bytes = bytes + ringbuf->reserved_size;
2468
2469 if (unlikely(bytes > remain_usable)) {
2470 /*
2471 * Not enough space for the basic request. So need to flush
2472 * out the remainder and then wait for base + reserved.
2473 */
2474 wait_bytes = remain_actual + total_bytes;
2475 need_wrap = true;
2476 } else {
2477 if (unlikely(total_bytes > remain_usable)) {
2478 /*
2479 * The base request will fit but the reserved space
2480 * falls off the end. So only need to to wait for the
2481 * reserved size after flushing out the remainder.
2482 */
2483 wait_bytes = remain_actual + ringbuf->reserved_size;
2484 need_wrap = true;
2485 } else if (total_bytes > ringbuf->space) {
2486 /* No wrapping required, just waiting. */
2487 wait_bytes = total_bytes;
2488 }
2489 }
2490
2491 if (wait_bytes) {
2492 ret = ring_wait_for_space(engine, wait_bytes);
2493 if (unlikely(ret))
2494 return ret;
2495
2496 if (need_wrap)
2497 __wrap_ring_buffer(ringbuf);
2498 }
2499
2500 return 0;
2501 }
2502
2503 int intel_ring_begin(struct drm_i915_gem_request *req,
2504 int num_dwords)
2505 {
2506 struct intel_engine_cs *engine;
2507 struct drm_i915_private *dev_priv;
2508 int ret;
2509
2510 WARN_ON(req == NULL);
2511 engine = req->engine;
2512 dev_priv = req->i915;
2513
2514 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2515 dev_priv->mm.interruptible);
2516 if (ret)
2517 return ret;
2518
2519 ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
2520 if (ret)
2521 return ret;
2522
2523 engine->buffer->space -= num_dwords * sizeof(uint32_t);
2524 return 0;
2525 }
2526
2527 /* Align the ring tail to a cacheline boundary */
2528 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2529 {
2530 struct intel_engine_cs *engine = req->engine;
2531 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2532 int ret;
2533
2534 if (num_dwords == 0)
2535 return 0;
2536
2537 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2538 ret = intel_ring_begin(req, num_dwords);
2539 if (ret)
2540 return ret;
2541
2542 while (num_dwords--)
2543 intel_ring_emit(engine, MI_NOOP);
2544
2545 intel_ring_advance(engine);
2546
2547 return 0;
2548 }
2549
2550 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2551 {
2552 struct drm_device *dev = engine->dev;
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554
2555 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2556 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2557 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2558 if (HAS_VEBOX(dev))
2559 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2560 }
2561
2562 engine->set_seqno(engine, seqno);
2563 engine->hangcheck.seqno = seqno;
2564 }
2565
2566 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2567 u32 value)
2568 {
2569 struct drm_i915_private *dev_priv = engine->dev->dev_private;
2570
2571 /* Every tail move must follow the sequence below */
2572
2573 /* Disable notification that the ring is IDLE. The GT
2574 * will then assume that it is busy and bring it out of rc6.
2575 */
2576 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2577 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2578
2579 /* Clear the context id. Here be magic! */
2580 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2581
2582 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2583 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2584 GEN6_BSD_SLEEP_INDICATOR) == 0,
2585 50))
2586 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2587
2588 /* Now that the ring is fully powered up, update the tail */
2589 I915_WRITE_TAIL(engine, value);
2590 POSTING_READ(RING_TAIL(engine->mmio_base));
2591
2592 /* Let the ring send IDLE messages to the GT again,
2593 * and so let it sleep to conserve power when idle.
2594 */
2595 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2596 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2597 }
2598
2599 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2600 u32 invalidate, u32 flush)
2601 {
2602 struct intel_engine_cs *engine = req->engine;
2603 uint32_t cmd;
2604 int ret;
2605
2606 ret = intel_ring_begin(req, 4);
2607 if (ret)
2608 return ret;
2609
2610 cmd = MI_FLUSH_DW;
2611 if (INTEL_INFO(engine->dev)->gen >= 8)
2612 cmd += 1;
2613
2614 /* We always require a command barrier so that subsequent
2615 * commands, such as breadcrumb interrupts, are strictly ordered
2616 * wrt the contents of the write cache being flushed to memory
2617 * (and thus being coherent from the CPU).
2618 */
2619 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2620
2621 /*
2622 * Bspec vol 1c.5 - video engine command streamer:
2623 * "If ENABLED, all TLBs will be invalidated once the flush
2624 * operation is complete. This bit is only valid when the
2625 * Post-Sync Operation field is a value of 1h or 3h."
2626 */
2627 if (invalidate & I915_GEM_GPU_DOMAINS)
2628 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2629
2630 intel_ring_emit(engine, cmd);
2631 intel_ring_emit(engine,
2632 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2633 if (INTEL_INFO(engine->dev)->gen >= 8) {
2634 intel_ring_emit(engine, 0); /* upper addr */
2635 intel_ring_emit(engine, 0); /* value */
2636 } else {
2637 intel_ring_emit(engine, 0);
2638 intel_ring_emit(engine, MI_NOOP);
2639 }
2640 intel_ring_advance(engine);
2641 return 0;
2642 }
2643
2644 static int
2645 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2646 u64 offset, u32 len,
2647 unsigned dispatch_flags)
2648 {
2649 struct intel_engine_cs *engine = req->engine;
2650 bool ppgtt = USES_PPGTT(engine->dev) &&
2651 !(dispatch_flags & I915_DISPATCH_SECURE);
2652 int ret;
2653
2654 ret = intel_ring_begin(req, 4);
2655 if (ret)
2656 return ret;
2657
2658 /* FIXME(BDW): Address space and security selectors. */
2659 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2660 (dispatch_flags & I915_DISPATCH_RS ?
2661 MI_BATCH_RESOURCE_STREAMER : 0));
2662 intel_ring_emit(engine, lower_32_bits(offset));
2663 intel_ring_emit(engine, upper_32_bits(offset));
2664 intel_ring_emit(engine, MI_NOOP);
2665 intel_ring_advance(engine);
2666
2667 return 0;
2668 }
2669
2670 static int
2671 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2672 u64 offset, u32 len,
2673 unsigned dispatch_flags)
2674 {
2675 struct intel_engine_cs *engine = req->engine;
2676 int ret;
2677
2678 ret = intel_ring_begin(req, 2);
2679 if (ret)
2680 return ret;
2681
2682 intel_ring_emit(engine,
2683 MI_BATCH_BUFFER_START |
2684 (dispatch_flags & I915_DISPATCH_SECURE ?
2685 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2686 (dispatch_flags & I915_DISPATCH_RS ?
2687 MI_BATCH_RESOURCE_STREAMER : 0));
2688 /* bit0-7 is the length on GEN6+ */
2689 intel_ring_emit(engine, offset);
2690 intel_ring_advance(engine);
2691
2692 return 0;
2693 }
2694
2695 static int
2696 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2697 u64 offset, u32 len,
2698 unsigned dispatch_flags)
2699 {
2700 struct intel_engine_cs *engine = req->engine;
2701 int ret;
2702
2703 ret = intel_ring_begin(req, 2);
2704 if (ret)
2705 return ret;
2706
2707 intel_ring_emit(engine,
2708 MI_BATCH_BUFFER_START |
2709 (dispatch_flags & I915_DISPATCH_SECURE ?
2710 0 : MI_BATCH_NON_SECURE_I965));
2711 /* bit0-7 is the length on GEN6+ */
2712 intel_ring_emit(engine, offset);
2713 intel_ring_advance(engine);
2714
2715 return 0;
2716 }
2717
2718 /* Blitter support (SandyBridge+) */
2719
2720 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2721 u32 invalidate, u32 flush)
2722 {
2723 struct intel_engine_cs *engine = req->engine;
2724 struct drm_device *dev = engine->dev;
2725 uint32_t cmd;
2726 int ret;
2727
2728 ret = intel_ring_begin(req, 4);
2729 if (ret)
2730 return ret;
2731
2732 cmd = MI_FLUSH_DW;
2733 if (INTEL_INFO(dev)->gen >= 8)
2734 cmd += 1;
2735
2736 /* We always require a command barrier so that subsequent
2737 * commands, such as breadcrumb interrupts, are strictly ordered
2738 * wrt the contents of the write cache being flushed to memory
2739 * (and thus being coherent from the CPU).
2740 */
2741 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2742
2743 /*
2744 * Bspec vol 1c.3 - blitter engine command streamer:
2745 * "If ENABLED, all TLBs will be invalidated once the flush
2746 * operation is complete. This bit is only valid when the
2747 * Post-Sync Operation field is a value of 1h or 3h."
2748 */
2749 if (invalidate & I915_GEM_DOMAIN_RENDER)
2750 cmd |= MI_INVALIDATE_TLB;
2751 intel_ring_emit(engine, cmd);
2752 intel_ring_emit(engine,
2753 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2754 if (INTEL_INFO(dev)->gen >= 8) {
2755 intel_ring_emit(engine, 0); /* upper addr */
2756 intel_ring_emit(engine, 0); /* value */
2757 } else {
2758 intel_ring_emit(engine, 0);
2759 intel_ring_emit(engine, MI_NOOP);
2760 }
2761 intel_ring_advance(engine);
2762
2763 return 0;
2764 }
2765
2766 int intel_init_render_ring_buffer(struct drm_device *dev)
2767 {
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2770 struct drm_i915_gem_object *obj;
2771 int ret;
2772
2773 engine->name = "render ring";
2774 engine->id = RCS;
2775 engine->exec_id = I915_EXEC_RENDER;
2776 engine->mmio_base = RENDER_RING_BASE;
2777
2778 if (INTEL_INFO(dev)->gen >= 8) {
2779 if (i915_semaphore_is_enabled(dev)) {
2780 obj = i915_gem_alloc_object(dev, 4096);
2781 if (obj == NULL) {
2782 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2783 i915.semaphores = 0;
2784 } else {
2785 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2786 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2787 if (ret != 0) {
2788 drm_gem_object_unreference(&obj->base);
2789 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2790 i915.semaphores = 0;
2791 } else
2792 dev_priv->semaphore_obj = obj;
2793 }
2794 }
2795
2796 engine->init_context = intel_rcs_ctx_init;
2797 engine->add_request = gen6_add_request;
2798 engine->flush = gen8_render_ring_flush;
2799 engine->irq_get = gen8_ring_get_irq;
2800 engine->irq_put = gen8_ring_put_irq;
2801 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2802 engine->get_seqno = gen6_ring_get_seqno;
2803 engine->set_seqno = ring_set_seqno;
2804 if (i915_semaphore_is_enabled(dev)) {
2805 WARN_ON(!dev_priv->semaphore_obj);
2806 engine->semaphore.sync_to = gen8_ring_sync;
2807 engine->semaphore.signal = gen8_rcs_signal;
2808 GEN8_RING_SEMAPHORE_INIT(engine);
2809 }
2810 } else if (INTEL_INFO(dev)->gen >= 6) {
2811 engine->init_context = intel_rcs_ctx_init;
2812 engine->add_request = gen6_add_request;
2813 engine->flush = gen7_render_ring_flush;
2814 if (INTEL_INFO(dev)->gen == 6)
2815 engine->flush = gen6_render_ring_flush;
2816 engine->irq_get = gen6_ring_get_irq;
2817 engine->irq_put = gen6_ring_put_irq;
2818 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2819 engine->get_seqno = gen6_ring_get_seqno;
2820 engine->set_seqno = ring_set_seqno;
2821 if (i915_semaphore_is_enabled(dev)) {
2822 engine->semaphore.sync_to = gen6_ring_sync;
2823 engine->semaphore.signal = gen6_signal;
2824 /*
2825 * The current semaphore is only applied on pre-gen8
2826 * platform. And there is no VCS2 ring on the pre-gen8
2827 * platform. So the semaphore between RCS and VCS2 is
2828 * initialized as INVALID. Gen8 will initialize the
2829 * sema between VCS2 and RCS later.
2830 */
2831 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2832 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2833 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2834 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2835 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2836 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2837 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2838 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2839 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2840 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2841 }
2842 } else if (IS_GEN5(dev)) {
2843 engine->add_request = pc_render_add_request;
2844 engine->flush = gen4_render_ring_flush;
2845 engine->get_seqno = pc_render_get_seqno;
2846 engine->set_seqno = pc_render_set_seqno;
2847 engine->irq_get = gen5_ring_get_irq;
2848 engine->irq_put = gen5_ring_put_irq;
2849 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2850 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2851 } else {
2852 engine->add_request = i9xx_add_request;
2853 if (INTEL_INFO(dev)->gen < 4)
2854 engine->flush = gen2_render_ring_flush;
2855 else
2856 engine->flush = gen4_render_ring_flush;
2857 engine->get_seqno = ring_get_seqno;
2858 engine->set_seqno = ring_set_seqno;
2859 if (IS_GEN2(dev)) {
2860 engine->irq_get = i8xx_ring_get_irq;
2861 engine->irq_put = i8xx_ring_put_irq;
2862 } else {
2863 engine->irq_get = i9xx_ring_get_irq;
2864 engine->irq_put = i9xx_ring_put_irq;
2865 }
2866 engine->irq_enable_mask = I915_USER_INTERRUPT;
2867 }
2868 engine->write_tail = ring_write_tail;
2869
2870 if (IS_HASWELL(dev))
2871 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2872 else if (IS_GEN8(dev))
2873 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2874 else if (INTEL_INFO(dev)->gen >= 6)
2875 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2876 else if (INTEL_INFO(dev)->gen >= 4)
2877 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2878 else if (IS_I830(dev) || IS_845G(dev))
2879 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2880 else
2881 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2882 engine->init_hw = init_render_ring;
2883 engine->cleanup = render_ring_cleanup;
2884
2885 /* Workaround batchbuffer to combat CS tlb bug. */
2886 if (HAS_BROKEN_CS_TLB(dev)) {
2887 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2888 if (obj == NULL) {
2889 DRM_ERROR("Failed to allocate batch bo\n");
2890 return -ENOMEM;
2891 }
2892
2893 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2894 if (ret != 0) {
2895 drm_gem_object_unreference(&obj->base);
2896 DRM_ERROR("Failed to ping batch bo\n");
2897 return ret;
2898 }
2899
2900 engine->scratch.obj = obj;
2901 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2902 }
2903
2904 ret = intel_init_ring_buffer(dev, engine);
2905 if (ret)
2906 return ret;
2907
2908 if (INTEL_INFO(dev)->gen >= 5) {
2909 ret = intel_init_pipe_control(engine);
2910 if (ret)
2911 return ret;
2912 }
2913
2914 return 0;
2915 }
2916
2917 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2918 {
2919 struct drm_i915_private *dev_priv = dev->dev_private;
2920 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2921
2922 engine->name = "bsd ring";
2923 engine->id = VCS;
2924 engine->exec_id = I915_EXEC_BSD;
2925
2926 engine->write_tail = ring_write_tail;
2927 if (INTEL_INFO(dev)->gen >= 6) {
2928 engine->mmio_base = GEN6_BSD_RING_BASE;
2929 /* gen6 bsd needs a special wa for tail updates */
2930 if (IS_GEN6(dev))
2931 engine->write_tail = gen6_bsd_ring_write_tail;
2932 engine->flush = gen6_bsd_ring_flush;
2933 engine->add_request = gen6_add_request;
2934 engine->get_seqno = gen6_ring_get_seqno;
2935 engine->set_seqno = ring_set_seqno;
2936 if (INTEL_INFO(dev)->gen >= 8) {
2937 engine->irq_enable_mask =
2938 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2939 engine->irq_get = gen8_ring_get_irq;
2940 engine->irq_put = gen8_ring_put_irq;
2941 engine->dispatch_execbuffer =
2942 gen8_ring_dispatch_execbuffer;
2943 if (i915_semaphore_is_enabled(dev)) {
2944 engine->semaphore.sync_to = gen8_ring_sync;
2945 engine->semaphore.signal = gen8_xcs_signal;
2946 GEN8_RING_SEMAPHORE_INIT(engine);
2947 }
2948 } else {
2949 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2950 engine->irq_get = gen6_ring_get_irq;
2951 engine->irq_put = gen6_ring_put_irq;
2952 engine->dispatch_execbuffer =
2953 gen6_ring_dispatch_execbuffer;
2954 if (i915_semaphore_is_enabled(dev)) {
2955 engine->semaphore.sync_to = gen6_ring_sync;
2956 engine->semaphore.signal = gen6_signal;
2957 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2958 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2959 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2960 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2961 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2962 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2963 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2964 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2965 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2966 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2967 }
2968 }
2969 } else {
2970 engine->mmio_base = BSD_RING_BASE;
2971 engine->flush = bsd_ring_flush;
2972 engine->add_request = i9xx_add_request;
2973 engine->get_seqno = ring_get_seqno;
2974 engine->set_seqno = ring_set_seqno;
2975 if (IS_GEN5(dev)) {
2976 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2977 engine->irq_get = gen5_ring_get_irq;
2978 engine->irq_put = gen5_ring_put_irq;
2979 } else {
2980 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2981 engine->irq_get = i9xx_ring_get_irq;
2982 engine->irq_put = i9xx_ring_put_irq;
2983 }
2984 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2985 }
2986 engine->init_hw = init_ring_common;
2987
2988 return intel_init_ring_buffer(dev, engine);
2989 }
2990
2991 /**
2992 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2993 */
2994 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2995 {
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2998
2999 engine->name = "bsd2 ring";
3000 engine->id = VCS2;
3001 engine->exec_id = I915_EXEC_BSD;
3002
3003 engine->write_tail = ring_write_tail;
3004 engine->mmio_base = GEN8_BSD2_RING_BASE;
3005 engine->flush = gen6_bsd_ring_flush;
3006 engine->add_request = gen6_add_request;
3007 engine->get_seqno = gen6_ring_get_seqno;
3008 engine->set_seqno = ring_set_seqno;
3009 engine->irq_enable_mask =
3010 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
3011 engine->irq_get = gen8_ring_get_irq;
3012 engine->irq_put = gen8_ring_put_irq;
3013 engine->dispatch_execbuffer =
3014 gen8_ring_dispatch_execbuffer;
3015 if (i915_semaphore_is_enabled(dev)) {
3016 engine->semaphore.sync_to = gen8_ring_sync;
3017 engine->semaphore.signal = gen8_xcs_signal;
3018 GEN8_RING_SEMAPHORE_INIT(engine);
3019 }
3020 engine->init_hw = init_ring_common;
3021
3022 return intel_init_ring_buffer(dev, engine);
3023 }
3024
3025 int intel_init_blt_ring_buffer(struct drm_device *dev)
3026 {
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
3029
3030 engine->name = "blitter ring";
3031 engine->id = BCS;
3032 engine->exec_id = I915_EXEC_BLT;
3033
3034 engine->mmio_base = BLT_RING_BASE;
3035 engine->write_tail = ring_write_tail;
3036 engine->flush = gen6_ring_flush;
3037 engine->add_request = gen6_add_request;
3038 engine->get_seqno = gen6_ring_get_seqno;
3039 engine->set_seqno = ring_set_seqno;
3040 if (INTEL_INFO(dev)->gen >= 8) {
3041 engine->irq_enable_mask =
3042 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3043 engine->irq_get = gen8_ring_get_irq;
3044 engine->irq_put = gen8_ring_put_irq;
3045 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3046 if (i915_semaphore_is_enabled(dev)) {
3047 engine->semaphore.sync_to = gen8_ring_sync;
3048 engine->semaphore.signal = gen8_xcs_signal;
3049 GEN8_RING_SEMAPHORE_INIT(engine);
3050 }
3051 } else {
3052 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3053 engine->irq_get = gen6_ring_get_irq;
3054 engine->irq_put = gen6_ring_put_irq;
3055 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3056 if (i915_semaphore_is_enabled(dev)) {
3057 engine->semaphore.signal = gen6_signal;
3058 engine->semaphore.sync_to = gen6_ring_sync;
3059 /*
3060 * The current semaphore is only applied on pre-gen8
3061 * platform. And there is no VCS2 ring on the pre-gen8
3062 * platform. So the semaphore between BCS and VCS2 is
3063 * initialized as INVALID. Gen8 will initialize the
3064 * sema between BCS and VCS2 later.
3065 */
3066 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3067 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3068 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3069 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3070 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3071 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3072 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3073 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3074 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3075 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3076 }
3077 }
3078 engine->init_hw = init_ring_common;
3079
3080 return intel_init_ring_buffer(dev, engine);
3081 }
3082
3083 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3084 {
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
3087
3088 engine->name = "video enhancement ring";
3089 engine->id = VECS;
3090 engine->exec_id = I915_EXEC_VEBOX;
3091
3092 engine->mmio_base = VEBOX_RING_BASE;
3093 engine->write_tail = ring_write_tail;
3094 engine->flush = gen6_ring_flush;
3095 engine->add_request = gen6_add_request;
3096 engine->get_seqno = gen6_ring_get_seqno;
3097 engine->set_seqno = ring_set_seqno;
3098
3099 if (INTEL_INFO(dev)->gen >= 8) {
3100 engine->irq_enable_mask =
3101 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3102 engine->irq_get = gen8_ring_get_irq;
3103 engine->irq_put = gen8_ring_put_irq;
3104 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3105 if (i915_semaphore_is_enabled(dev)) {
3106 engine->semaphore.sync_to = gen8_ring_sync;
3107 engine->semaphore.signal = gen8_xcs_signal;
3108 GEN8_RING_SEMAPHORE_INIT(engine);
3109 }
3110 } else {
3111 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3112 engine->irq_get = hsw_vebox_get_irq;
3113 engine->irq_put = hsw_vebox_put_irq;
3114 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3115 if (i915_semaphore_is_enabled(dev)) {
3116 engine->semaphore.sync_to = gen6_ring_sync;
3117 engine->semaphore.signal = gen6_signal;
3118 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3119 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3120 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3121 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3122 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3123 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3124 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3125 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3126 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3127 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3128 }
3129 }
3130 engine->init_hw = init_ring_common;
3131
3132 return intel_init_ring_buffer(dev, engine);
3133 }
3134
3135 int
3136 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3137 {
3138 struct intel_engine_cs *engine = req->engine;
3139 int ret;
3140
3141 if (!engine->gpu_caches_dirty)
3142 return 0;
3143
3144 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3145 if (ret)
3146 return ret;
3147
3148 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3149
3150 engine->gpu_caches_dirty = false;
3151 return 0;
3152 }
3153
3154 int
3155 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3156 {
3157 struct intel_engine_cs *engine = req->engine;
3158 uint32_t flush_domains;
3159 int ret;
3160
3161 flush_domains = 0;
3162 if (engine->gpu_caches_dirty)
3163 flush_domains = I915_GEM_GPU_DOMAINS;
3164
3165 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3166 if (ret)
3167 return ret;
3168
3169 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3170
3171 engine->gpu_caches_dirty = false;
3172 return 0;
3173 }
3174
3175 void
3176 intel_stop_engine(struct intel_engine_cs *engine)
3177 {
3178 int ret;
3179
3180 if (!intel_engine_initialized(engine))
3181 return;
3182
3183 ret = intel_engine_idle(engine);
3184 if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
3185 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3186 engine->name, ret);
3187
3188 stop_ring(engine);
3189 }
Linux kernel - Deliverables
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