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drm/i915: Initialize workarounds in logical ring mode too
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - (tail + I915_RING_FREE_SPACE);
56 if (space < 0)
57 space += size;
58 return space;
59 }
60
61 int intel_ring_space(struct intel_ringbuffer *ringbuf)
62 {
63 return __intel_ring_space(ringbuf->head & HEAD_ADDR,
64 ringbuf->tail, ringbuf->size);
65 }
66
67 bool intel_ring_stopped(struct intel_engine_cs *ring)
68 {
69 struct drm_i915_private *dev_priv = ring->dev->dev_private;
70 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
71 }
72
73 void __intel_ring_advance(struct intel_engine_cs *ring)
74 {
75 struct intel_ringbuffer *ringbuf = ring->buffer;
76 ringbuf->tail &= ringbuf->size - 1;
77 if (intel_ring_stopped(ring))
78 return;
79 ring->write_tail(ring, ringbuf->tail);
80 }
81
82 static int
83 gen2_render_ring_flush(struct intel_engine_cs *ring,
84 u32 invalidate_domains,
85 u32 flush_domains)
86 {
87 u32 cmd;
88 int ret;
89
90 cmd = MI_FLUSH;
91 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
92 cmd |= MI_NO_WRITE_FLUSH;
93
94 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95 cmd |= MI_READ_FLUSH;
96
97 ret = intel_ring_begin(ring, 2);
98 if (ret)
99 return ret;
100
101 intel_ring_emit(ring, cmd);
102 intel_ring_emit(ring, MI_NOOP);
103 intel_ring_advance(ring);
104
105 return 0;
106 }
107
108 static int
109 gen4_render_ring_flush(struct intel_engine_cs *ring,
110 u32 invalidate_domains,
111 u32 flush_domains)
112 {
113 struct drm_device *dev = ring->dev;
114 u32 cmd;
115 int ret;
116
117 /*
118 * read/write caches:
119 *
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
123 *
124 * read-only caches:
125 *
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
128 *
129 * I915_GEM_DOMAIN_COMMAND may not exist?
130 *
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
133 *
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
136 *
137 * TLBs:
138 *
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
143 */
144
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
146 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
147 cmd &= ~MI_NO_WRITE_FLUSH;
148 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
149 cmd |= MI_EXE_FLUSH;
150
151 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
152 (IS_G4X(dev) || IS_GEN5(dev)))
153 cmd |= MI_INVALIDATE_ISP;
154
155 ret = intel_ring_begin(ring, 2);
156 if (ret)
157 return ret;
158
159 intel_ring_emit(ring, cmd);
160 intel_ring_emit(ring, MI_NOOP);
161 intel_ring_advance(ring);
162
163 return 0;
164 }
165
166 /**
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
170 *
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
174 * 0.
175 *
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
178 *
179 * And the workaround for these two requires this workaround first:
180 *
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
183 * flushes.
184 *
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
187 * volume 2 part 1:
188 *
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
196 *
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
202 */
203 static int
204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
205 {
206 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
207 int ret;
208
209
210 ret = intel_ring_begin(ring, 6);
211 if (ret)
212 return ret;
213
214 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
216 PIPE_CONTROL_STALL_AT_SCOREBOARD);
217 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
218 intel_ring_emit(ring, 0); /* low dword */
219 intel_ring_emit(ring, 0); /* high dword */
220 intel_ring_emit(ring, MI_NOOP);
221 intel_ring_advance(ring);
222
223 ret = intel_ring_begin(ring, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
229 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
230 intel_ring_emit(ring, 0);
231 intel_ring_emit(ring, 0);
232 intel_ring_emit(ring, MI_NOOP);
233 intel_ring_advance(ring);
234
235 return 0;
236 }
237
238 static int
239 gen6_render_ring_flush(struct intel_engine_cs *ring,
240 u32 invalidate_domains, u32 flush_domains)
241 {
242 u32 flags = 0;
243 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
244 int ret;
245
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret = intel_emit_post_sync_nonzero_flush(ring);
248 if (ret)
249 return ret;
250
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
253 * impact.
254 */
255 if (flush_domains) {
256 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
257 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
258 /*
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
261 */
262 flags |= PIPE_CONTROL_CS_STALL;
263 }
264 if (invalidate_domains) {
265 flags |= PIPE_CONTROL_TLB_INVALIDATE;
266 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
269 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
270 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
271 /*
272 * TLB invalidate requires a post-sync write.
273 */
274 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
275 }
276
277 ret = intel_ring_begin(ring, 4);
278 if (ret)
279 return ret;
280
281 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring, flags);
283 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
284 intel_ring_emit(ring, 0);
285 intel_ring_advance(ring);
286
287 return 0;
288 }
289
290 static int
291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
292 {
293 int ret;
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
301 PIPE_CONTROL_STALL_AT_SCOREBOARD);
302 intel_ring_emit(ring, 0);
303 intel_ring_emit(ring, 0);
304 intel_ring_advance(ring);
305
306 return 0;
307 }
308
309 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
310 {
311 int ret;
312
313 if (!ring->fbc_dirty)
314 return 0;
315
316 ret = intel_ring_begin(ring, 6);
317 if (ret)
318 return ret;
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring, MSG_FBC_REND_STATE);
322 intel_ring_emit(ring, value);
323 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
324 intel_ring_emit(ring, MSG_FBC_REND_STATE);
325 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
326 intel_ring_advance(ring);
327
328 ring->fbc_dirty = false;
329 return 0;
330 }
331
332 static int
333 gen7_render_ring_flush(struct intel_engine_cs *ring,
334 u32 invalidate_domains, u32 flush_domains)
335 {
336 u32 flags = 0;
337 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
338 int ret;
339
340 /*
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
343 *
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
347 */
348 flags |= PIPE_CONTROL_CS_STALL;
349
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
352 * impact.
353 */
354 if (flush_domains) {
355 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
356 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
357 }
358 if (invalidate_domains) {
359 flags |= PIPE_CONTROL_TLB_INVALIDATE;
360 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
361 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
362 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
363 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
364 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
365 /*
366 * TLB invalidate requires a post-sync write.
367 */
368 flags |= PIPE_CONTROL_QW_WRITE;
369 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
370
371 /* Workaround: we must issue a pipe_control with CS-stall bit
372 * set before a pipe_control command that has the state cache
373 * invalidate bit set. */
374 gen7_render_ring_cs_stall_wa(ring);
375 }
376
377 ret = intel_ring_begin(ring, 4);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
382 intel_ring_emit(ring, flags);
383 intel_ring_emit(ring, scratch_addr);
384 intel_ring_emit(ring, 0);
385 intel_ring_advance(ring);
386
387 if (!invalidate_domains && flush_domains)
388 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
389
390 return 0;
391 }
392
393 static int
394 gen8_emit_pipe_control(struct intel_engine_cs *ring,
395 u32 flags, u32 scratch_addr)
396 {
397 int ret;
398
399 ret = intel_ring_begin(ring, 6);
400 if (ret)
401 return ret;
402
403 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
404 intel_ring_emit(ring, flags);
405 intel_ring_emit(ring, scratch_addr);
406 intel_ring_emit(ring, 0);
407 intel_ring_emit(ring, 0);
408 intel_ring_emit(ring, 0);
409 intel_ring_advance(ring);
410
411 return 0;
412 }
413
414 static int
415 gen8_render_ring_flush(struct intel_engine_cs *ring,
416 u32 invalidate_domains, u32 flush_domains)
417 {
418 u32 flags = 0;
419 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
420 int ret;
421
422 flags |= PIPE_CONTROL_CS_STALL;
423
424 if (flush_domains) {
425 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
426 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
427 }
428 if (invalidate_domains) {
429 flags |= PIPE_CONTROL_TLB_INVALIDATE;
430 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
431 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
432 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
433 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
434 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
435 flags |= PIPE_CONTROL_QW_WRITE;
436 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
437
438 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
439 ret = gen8_emit_pipe_control(ring,
440 PIPE_CONTROL_CS_STALL |
441 PIPE_CONTROL_STALL_AT_SCOREBOARD,
442 0);
443 if (ret)
444 return ret;
445 }
446
447 ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
448 if (ret)
449 return ret;
450
451 if (!invalidate_domains && flush_domains)
452 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
453
454 return 0;
455 }
456
457 static void ring_write_tail(struct intel_engine_cs *ring,
458 u32 value)
459 {
460 struct drm_i915_private *dev_priv = ring->dev->dev_private;
461 I915_WRITE_TAIL(ring, value);
462 }
463
464 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
465 {
466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
467 u64 acthd;
468
469 if (INTEL_INFO(ring->dev)->gen >= 8)
470 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
471 RING_ACTHD_UDW(ring->mmio_base));
472 else if (INTEL_INFO(ring->dev)->gen >= 4)
473 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
474 else
475 acthd = I915_READ(ACTHD);
476
477 return acthd;
478 }
479
480 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
481 {
482 struct drm_i915_private *dev_priv = ring->dev->dev_private;
483 u32 addr;
484
485 addr = dev_priv->status_page_dmah->busaddr;
486 if (INTEL_INFO(ring->dev)->gen >= 4)
487 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
488 I915_WRITE(HWS_PGA, addr);
489 }
490
491 static bool stop_ring(struct intel_engine_cs *ring)
492 {
493 struct drm_i915_private *dev_priv = to_i915(ring->dev);
494
495 if (!IS_GEN2(ring->dev)) {
496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
497 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
498 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
499 /* Sometimes we observe that the idle flag is not
500 * set even though the ring is empty. So double
501 * check before giving up.
502 */
503 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
504 return false;
505 }
506 }
507
508 I915_WRITE_CTL(ring, 0);
509 I915_WRITE_HEAD(ring, 0);
510 ring->write_tail(ring, 0);
511
512 if (!IS_GEN2(ring->dev)) {
513 (void)I915_READ_CTL(ring);
514 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
515 }
516
517 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
518 }
519
520 static int init_ring_common(struct intel_engine_cs *ring)
521 {
522 struct drm_device *dev = ring->dev;
523 struct drm_i915_private *dev_priv = dev->dev_private;
524 struct intel_ringbuffer *ringbuf = ring->buffer;
525 struct drm_i915_gem_object *obj = ringbuf->obj;
526 int ret = 0;
527
528 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
529
530 if (!stop_ring(ring)) {
531 /* G45 ring initialization often fails to reset head to zero */
532 DRM_DEBUG_KMS("%s head not reset to zero "
533 "ctl %08x head %08x tail %08x start %08x\n",
534 ring->name,
535 I915_READ_CTL(ring),
536 I915_READ_HEAD(ring),
537 I915_READ_TAIL(ring),
538 I915_READ_START(ring));
539
540 if (!stop_ring(ring)) {
541 DRM_ERROR("failed to set %s head to zero "
542 "ctl %08x head %08x tail %08x start %08x\n",
543 ring->name,
544 I915_READ_CTL(ring),
545 I915_READ_HEAD(ring),
546 I915_READ_TAIL(ring),
547 I915_READ_START(ring));
548 ret = -EIO;
549 goto out;
550 }
551 }
552
553 if (I915_NEED_GFX_HWS(dev))
554 intel_ring_setup_status_page(ring);
555 else
556 ring_setup_phys_status_page(ring);
557
558 /* Enforce ordering by reading HEAD register back */
559 I915_READ_HEAD(ring);
560
561 /* Initialize the ring. This must happen _after_ we've cleared the ring
562 * registers with the above sequence (the readback of the HEAD registers
563 * also enforces ordering), otherwise the hw might lose the new ring
564 * register values. */
565 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
566
567 /* WaClearRingBufHeadRegAtInit:ctg,elk */
568 if (I915_READ_HEAD(ring))
569 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
570 ring->name, I915_READ_HEAD(ring));
571 I915_WRITE_HEAD(ring, 0);
572 (void)I915_READ_HEAD(ring);
573
574 I915_WRITE_CTL(ring,
575 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
576 | RING_VALID);
577
578 /* If the head is still not zero, the ring is dead */
579 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
580 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
581 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
582 DRM_ERROR("%s initialization failed "
583 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
584 ring->name,
585 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
586 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
587 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
588 ret = -EIO;
589 goto out;
590 }
591
592 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
593 i915_kernel_lost_context(ring->dev);
594 else {
595 ringbuf->head = I915_READ_HEAD(ring);
596 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
597 ringbuf->space = intel_ring_space(ringbuf);
598 ringbuf->last_retired_head = -1;
599 }
600
601 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
602
603 out:
604 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
605
606 return ret;
607 }
608
609 void
610 intel_fini_pipe_control(struct intel_engine_cs *ring)
611 {
612 struct drm_device *dev = ring->dev;
613
614 if (ring->scratch.obj == NULL)
615 return;
616
617 if (INTEL_INFO(dev)->gen >= 5) {
618 kunmap(sg_page(ring->scratch.obj->pages->sgl));
619 i915_gem_object_ggtt_unpin(ring->scratch.obj);
620 }
621
622 drm_gem_object_unreference(&ring->scratch.obj->base);
623 ring->scratch.obj = NULL;
624 }
625
626 int
627 intel_init_pipe_control(struct intel_engine_cs *ring)
628 {
629 int ret;
630
631 if (ring->scratch.obj)
632 return 0;
633
634 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
635 if (ring->scratch.obj == NULL) {
636 DRM_ERROR("Failed to allocate seqno page\n");
637 ret = -ENOMEM;
638 goto err;
639 }
640
641 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
642 if (ret)
643 goto err_unref;
644
645 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
646 if (ret)
647 goto err_unref;
648
649 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
650 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
651 if (ring->scratch.cpu_page == NULL) {
652 ret = -ENOMEM;
653 goto err_unpin;
654 }
655
656 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
657 ring->name, ring->scratch.gtt_offset);
658 return 0;
659
660 err_unpin:
661 i915_gem_object_ggtt_unpin(ring->scratch.obj);
662 err_unref:
663 drm_gem_object_unreference(&ring->scratch.obj->base);
664 err:
665 return ret;
666 }
667
668 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
669 struct intel_context *ctx)
670 {
671 int ret, i;
672 struct drm_device *dev = ring->dev;
673 struct drm_i915_private *dev_priv = dev->dev_private;
674 struct i915_workarounds *w = &dev_priv->workarounds;
675
676 if (WARN_ON(w->count == 0))
677 return 0;
678
679 ring->gpu_caches_dirty = true;
680 ret = intel_ring_flush_all_caches(ring);
681 if (ret)
682 return ret;
683
684 ret = intel_ring_begin(ring, (w->count * 2 + 2));
685 if (ret)
686 return ret;
687
688 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
689 for (i = 0; i < w->count; i++) {
690 intel_ring_emit(ring, w->reg[i].addr);
691 intel_ring_emit(ring, w->reg[i].value);
692 }
693 intel_ring_emit(ring, MI_NOOP);
694
695 intel_ring_advance(ring);
696
697 ring->gpu_caches_dirty = true;
698 ret = intel_ring_flush_all_caches(ring);
699 if (ret)
700 return ret;
701
702 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
703
704 return 0;
705 }
706
707 static int wa_add(struct drm_i915_private *dev_priv,
708 const u32 addr, const u32 val, const u32 mask)
709 {
710 const u32 idx = dev_priv->workarounds.count;
711
712 if (WARN_ON(idx >= I915_MAX_WA_REGS))
713 return -ENOSPC;
714
715 dev_priv->workarounds.reg[idx].addr = addr;
716 dev_priv->workarounds.reg[idx].value = val;
717 dev_priv->workarounds.reg[idx].mask = mask;
718
719 dev_priv->workarounds.count++;
720
721 return 0;
722 }
723
724 #define WA_REG(addr, val, mask) { \
725 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
726 if (r) \
727 return r; \
728 }
729
730 #define WA_SET_BIT_MASKED(addr, mask) \
731 WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
732
733 #define WA_CLR_BIT_MASKED(addr, mask) \
734 WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
735
736 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
737 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
738
739 #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
740
741 static int bdw_init_workarounds(struct intel_engine_cs *ring)
742 {
743 struct drm_device *dev = ring->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745
746 /* WaDisablePartialInstShootdown:bdw */
747 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
748 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
749 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
750 STALL_DOP_GATING_DISABLE);
751
752 /* WaDisableDopClockGating:bdw */
753 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
754 DOP_CLOCK_GATING_DISABLE);
755
756 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
757 GEN8_SAMPLER_POWER_BYPASS_DIS);
758
759 /* Use Force Non-Coherent whenever executing a 3D context. This is a
760 * workaround for for a possible hang in the unlikely event a TLB
761 * invalidation occurs during a PSD flush.
762 */
763 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
764 WA_SET_BIT_MASKED(HDC_CHICKEN0,
765 HDC_FORCE_NON_COHERENT |
766 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
767
768 /* Wa4x4STCOptimizationDisable:bdw */
769 WA_SET_BIT_MASKED(CACHE_MODE_1,
770 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
771
772 /*
773 * BSpec recommends 8x4 when MSAA is used,
774 * however in practice 16x4 seems fastest.
775 *
776 * Note that PS/WM thread counts depend on the WIZ hashing
777 * disable bit, which we don't touch here, but it's good
778 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
779 */
780 WA_SET_BIT_MASKED(GEN7_GT_MODE,
781 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
782
783 return 0;
784 }
785
786 static int chv_init_workarounds(struct intel_engine_cs *ring)
787 {
788 struct drm_device *dev = ring->dev;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* WaDisablePartialInstShootdown:chv */
792 /* WaDisableThreadStallDopClockGating:chv */
793 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
794 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
795 STALL_DOP_GATING_DISABLE);
796
797 /* Use Force Non-Coherent whenever executing a 3D context. This is a
798 * workaround for a possible hang in the unlikely event a TLB
799 * invalidation occurs during a PSD flush.
800 */
801 /* WaForceEnableNonCoherent:chv */
802 /* WaHdcDisableFetchWhenMasked:chv */
803 WA_SET_BIT_MASKED(HDC_CHICKEN0,
804 HDC_FORCE_NON_COHERENT |
805 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
806
807 return 0;
808 }
809
810 int init_workarounds_ring(struct intel_engine_cs *ring)
811 {
812 struct drm_device *dev = ring->dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814
815 WARN_ON(ring->id != RCS);
816
817 dev_priv->workarounds.count = 0;
818
819 if (IS_BROADWELL(dev))
820 return bdw_init_workarounds(ring);
821
822 if (IS_CHERRYVIEW(dev))
823 return chv_init_workarounds(ring);
824
825 return 0;
826 }
827
828 static int init_render_ring(struct intel_engine_cs *ring)
829 {
830 struct drm_device *dev = ring->dev;
831 struct drm_i915_private *dev_priv = dev->dev_private;
832 int ret = init_ring_common(ring);
833 if (ret)
834 return ret;
835
836 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
837 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
838 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
839
840 /* We need to disable the AsyncFlip performance optimisations in order
841 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
842 * programmed to '1' on all products.
843 *
844 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
845 */
846 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
847 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
848
849 /* Required for the hardware to program scanline values for waiting */
850 /* WaEnableFlushTlbInvalidationMode:snb */
851 if (INTEL_INFO(dev)->gen == 6)
852 I915_WRITE(GFX_MODE,
853 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
854
855 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
856 if (IS_GEN7(dev))
857 I915_WRITE(GFX_MODE_GEN7,
858 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
859 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
860
861 if (INTEL_INFO(dev)->gen >= 5) {
862 ret = intel_init_pipe_control(ring);
863 if (ret)
864 return ret;
865 }
866
867 if (IS_GEN6(dev)) {
868 /* From the Sandybridge PRM, volume 1 part 3, page 24:
869 * "If this bit is set, STCunit will have LRA as replacement
870 * policy. [...] This bit must be reset. LRA replacement
871 * policy is not supported."
872 */
873 I915_WRITE(CACHE_MODE_0,
874 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
875 }
876
877 if (INTEL_INFO(dev)->gen >= 6)
878 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
879
880 if (HAS_L3_DPF(dev))
881 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
882
883 return init_workarounds_ring(ring);
884 }
885
886 static void render_ring_cleanup(struct intel_engine_cs *ring)
887 {
888 struct drm_device *dev = ring->dev;
889 struct drm_i915_private *dev_priv = dev->dev_private;
890
891 if (dev_priv->semaphore_obj) {
892 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
893 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
894 dev_priv->semaphore_obj = NULL;
895 }
896
897 intel_fini_pipe_control(ring);
898 }
899
900 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
901 unsigned int num_dwords)
902 {
903 #define MBOX_UPDATE_DWORDS 8
904 struct drm_device *dev = signaller->dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 struct intel_engine_cs *waiter;
907 int i, ret, num_rings;
908
909 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
910 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
911 #undef MBOX_UPDATE_DWORDS
912
913 ret = intel_ring_begin(signaller, num_dwords);
914 if (ret)
915 return ret;
916
917 for_each_ring(waiter, dev_priv, i) {
918 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
919 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
920 continue;
921
922 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
923 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
924 PIPE_CONTROL_QW_WRITE |
925 PIPE_CONTROL_FLUSH_ENABLE);
926 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
927 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
928 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
929 intel_ring_emit(signaller, 0);
930 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
931 MI_SEMAPHORE_TARGET(waiter->id));
932 intel_ring_emit(signaller, 0);
933 }
934
935 return 0;
936 }
937
938 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
939 unsigned int num_dwords)
940 {
941 #define MBOX_UPDATE_DWORDS 6
942 struct drm_device *dev = signaller->dev;
943 struct drm_i915_private *dev_priv = dev->dev_private;
944 struct intel_engine_cs *waiter;
945 int i, ret, num_rings;
946
947 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
948 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
949 #undef MBOX_UPDATE_DWORDS
950
951 ret = intel_ring_begin(signaller, num_dwords);
952 if (ret)
953 return ret;
954
955 for_each_ring(waiter, dev_priv, i) {
956 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
957 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
958 continue;
959
960 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
961 MI_FLUSH_DW_OP_STOREDW);
962 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
963 MI_FLUSH_DW_USE_GTT);
964 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
965 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
966 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
967 MI_SEMAPHORE_TARGET(waiter->id));
968 intel_ring_emit(signaller, 0);
969 }
970
971 return 0;
972 }
973
974 static int gen6_signal(struct intel_engine_cs *signaller,
975 unsigned int num_dwords)
976 {
977 struct drm_device *dev = signaller->dev;
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 struct intel_engine_cs *useless;
980 int i, ret, num_rings;
981
982 #define MBOX_UPDATE_DWORDS 3
983 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
984 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
985 #undef MBOX_UPDATE_DWORDS
986
987 ret = intel_ring_begin(signaller, num_dwords);
988 if (ret)
989 return ret;
990
991 for_each_ring(useless, dev_priv, i) {
992 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
993 if (mbox_reg != GEN6_NOSYNC) {
994 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
995 intel_ring_emit(signaller, mbox_reg);
996 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
997 }
998 }
999
1000 /* If num_dwords was rounded, make sure the tail pointer is correct */
1001 if (num_rings % 2 == 0)
1002 intel_ring_emit(signaller, MI_NOOP);
1003
1004 return 0;
1005 }
1006
1007 /**
1008 * gen6_add_request - Update the semaphore mailbox registers
1009 *
1010 * @ring - ring that is adding a request
1011 * @seqno - return seqno stuck into the ring
1012 *
1013 * Update the mailbox registers in the *other* rings with the current seqno.
1014 * This acts like a signal in the canonical semaphore.
1015 */
1016 static int
1017 gen6_add_request(struct intel_engine_cs *ring)
1018 {
1019 int ret;
1020
1021 if (ring->semaphore.signal)
1022 ret = ring->semaphore.signal(ring, 4);
1023 else
1024 ret = intel_ring_begin(ring, 4);
1025
1026 if (ret)
1027 return ret;
1028
1029 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1030 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1031 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1032 intel_ring_emit(ring, MI_USER_INTERRUPT);
1033 __intel_ring_advance(ring);
1034
1035 return 0;
1036 }
1037
1038 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1039 u32 seqno)
1040 {
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 return dev_priv->last_seqno < seqno;
1043 }
1044
1045 /**
1046 * intel_ring_sync - sync the waiter to the signaller on seqno
1047 *
1048 * @waiter - ring that is waiting
1049 * @signaller - ring which has, or will signal
1050 * @seqno - seqno which the waiter will block on
1051 */
1052
1053 static int
1054 gen8_ring_sync(struct intel_engine_cs *waiter,
1055 struct intel_engine_cs *signaller,
1056 u32 seqno)
1057 {
1058 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1059 int ret;
1060
1061 ret = intel_ring_begin(waiter, 4);
1062 if (ret)
1063 return ret;
1064
1065 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1066 MI_SEMAPHORE_GLOBAL_GTT |
1067 MI_SEMAPHORE_POLL |
1068 MI_SEMAPHORE_SAD_GTE_SDD);
1069 intel_ring_emit(waiter, seqno);
1070 intel_ring_emit(waiter,
1071 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1072 intel_ring_emit(waiter,
1073 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1074 intel_ring_advance(waiter);
1075 return 0;
1076 }
1077
1078 static int
1079 gen6_ring_sync(struct intel_engine_cs *waiter,
1080 struct intel_engine_cs *signaller,
1081 u32 seqno)
1082 {
1083 u32 dw1 = MI_SEMAPHORE_MBOX |
1084 MI_SEMAPHORE_COMPARE |
1085 MI_SEMAPHORE_REGISTER;
1086 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1087 int ret;
1088
1089 /* Throughout all of the GEM code, seqno passed implies our current
1090 * seqno is >= the last seqno executed. However for hardware the
1091 * comparison is strictly greater than.
1092 */
1093 seqno -= 1;
1094
1095 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1096
1097 ret = intel_ring_begin(waiter, 4);
1098 if (ret)
1099 return ret;
1100
1101 /* If seqno wrap happened, omit the wait with no-ops */
1102 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1103 intel_ring_emit(waiter, dw1 | wait_mbox);
1104 intel_ring_emit(waiter, seqno);
1105 intel_ring_emit(waiter, 0);
1106 intel_ring_emit(waiter, MI_NOOP);
1107 } else {
1108 intel_ring_emit(waiter, MI_NOOP);
1109 intel_ring_emit(waiter, MI_NOOP);
1110 intel_ring_emit(waiter, MI_NOOP);
1111 intel_ring_emit(waiter, MI_NOOP);
1112 }
1113 intel_ring_advance(waiter);
1114
1115 return 0;
1116 }
1117
1118 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1119 do { \
1120 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1121 PIPE_CONTROL_DEPTH_STALL); \
1122 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1123 intel_ring_emit(ring__, 0); \
1124 intel_ring_emit(ring__, 0); \
1125 } while (0)
1126
1127 static int
1128 pc_render_add_request(struct intel_engine_cs *ring)
1129 {
1130 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1131 int ret;
1132
1133 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1134 * incoherent with writes to memory, i.e. completely fubar,
1135 * so we need to use PIPE_NOTIFY instead.
1136 *
1137 * However, we also need to workaround the qword write
1138 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1139 * memory before requesting an interrupt.
1140 */
1141 ret = intel_ring_begin(ring, 32);
1142 if (ret)
1143 return ret;
1144
1145 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1146 PIPE_CONTROL_WRITE_FLUSH |
1147 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1148 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1149 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1150 intel_ring_emit(ring, 0);
1151 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1152 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1153 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1154 scratch_addr += 2 * CACHELINE_BYTES;
1155 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1156 scratch_addr += 2 * CACHELINE_BYTES;
1157 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1158 scratch_addr += 2 * CACHELINE_BYTES;
1159 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1160 scratch_addr += 2 * CACHELINE_BYTES;
1161 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1162
1163 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1164 PIPE_CONTROL_WRITE_FLUSH |
1165 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1166 PIPE_CONTROL_NOTIFY);
1167 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1168 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1169 intel_ring_emit(ring, 0);
1170 __intel_ring_advance(ring);
1171
1172 return 0;
1173 }
1174
1175 static u32
1176 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1177 {
1178 /* Workaround to force correct ordering between irq and seqno writes on
1179 * ivb (and maybe also on snb) by reading from a CS register (like
1180 * ACTHD) before reading the status page. */
1181 if (!lazy_coherency) {
1182 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1183 POSTING_READ(RING_ACTHD(ring->mmio_base));
1184 }
1185
1186 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1187 }
1188
1189 static u32
1190 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1191 {
1192 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1193 }
1194
1195 static void
1196 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1197 {
1198 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1199 }
1200
1201 static u32
1202 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1203 {
1204 return ring->scratch.cpu_page[0];
1205 }
1206
1207 static void
1208 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1209 {
1210 ring->scratch.cpu_page[0] = seqno;
1211 }
1212
1213 static bool
1214 gen5_ring_get_irq(struct intel_engine_cs *ring)
1215 {
1216 struct drm_device *dev = ring->dev;
1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 unsigned long flags;
1219
1220 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1221 return false;
1222
1223 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1224 if (ring->irq_refcount++ == 0)
1225 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1226 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1227
1228 return true;
1229 }
1230
1231 static void
1232 gen5_ring_put_irq(struct intel_engine_cs *ring)
1233 {
1234 struct drm_device *dev = ring->dev;
1235 struct drm_i915_private *dev_priv = dev->dev_private;
1236 unsigned long flags;
1237
1238 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1239 if (--ring->irq_refcount == 0)
1240 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1241 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1242 }
1243
1244 static bool
1245 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1246 {
1247 struct drm_device *dev = ring->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 unsigned long flags;
1250
1251 if (!intel_irqs_enabled(dev_priv))
1252 return false;
1253
1254 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1255 if (ring->irq_refcount++ == 0) {
1256 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1257 I915_WRITE(IMR, dev_priv->irq_mask);
1258 POSTING_READ(IMR);
1259 }
1260 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1261
1262 return true;
1263 }
1264
1265 static void
1266 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1267 {
1268 struct drm_device *dev = ring->dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 unsigned long flags;
1271
1272 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1273 if (--ring->irq_refcount == 0) {
1274 dev_priv->irq_mask |= ring->irq_enable_mask;
1275 I915_WRITE(IMR, dev_priv->irq_mask);
1276 POSTING_READ(IMR);
1277 }
1278 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1279 }
1280
1281 static bool
1282 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1283 {
1284 struct drm_device *dev = ring->dev;
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 unsigned long flags;
1287
1288 if (!intel_irqs_enabled(dev_priv))
1289 return false;
1290
1291 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1292 if (ring->irq_refcount++ == 0) {
1293 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1294 I915_WRITE16(IMR, dev_priv->irq_mask);
1295 POSTING_READ16(IMR);
1296 }
1297 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1298
1299 return true;
1300 }
1301
1302 static void
1303 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1304 {
1305 struct drm_device *dev = ring->dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 unsigned long flags;
1308
1309 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1310 if (--ring->irq_refcount == 0) {
1311 dev_priv->irq_mask |= ring->irq_enable_mask;
1312 I915_WRITE16(IMR, dev_priv->irq_mask);
1313 POSTING_READ16(IMR);
1314 }
1315 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1316 }
1317
1318 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1319 {
1320 struct drm_device *dev = ring->dev;
1321 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1322 u32 mmio = 0;
1323
1324 /* The ring status page addresses are no longer next to the rest of
1325 * the ring registers as of gen7.
1326 */
1327 if (IS_GEN7(dev)) {
1328 switch (ring->id) {
1329 case RCS:
1330 mmio = RENDER_HWS_PGA_GEN7;
1331 break;
1332 case BCS:
1333 mmio = BLT_HWS_PGA_GEN7;
1334 break;
1335 /*
1336 * VCS2 actually doesn't exist on Gen7. Only shut up
1337 * gcc switch check warning
1338 */
1339 case VCS2:
1340 case VCS:
1341 mmio = BSD_HWS_PGA_GEN7;
1342 break;
1343 case VECS:
1344 mmio = VEBOX_HWS_PGA_GEN7;
1345 break;
1346 }
1347 } else if (IS_GEN6(ring->dev)) {
1348 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1349 } else {
1350 /* XXX: gen8 returns to sanity */
1351 mmio = RING_HWS_PGA(ring->mmio_base);
1352 }
1353
1354 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1355 POSTING_READ(mmio);
1356
1357 /*
1358 * Flush the TLB for this page
1359 *
1360 * FIXME: These two bits have disappeared on gen8, so a question
1361 * arises: do we still need this and if so how should we go about
1362 * invalidating the TLB?
1363 */
1364 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1365 u32 reg = RING_INSTPM(ring->mmio_base);
1366
1367 /* ring should be idle before issuing a sync flush*/
1368 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1369
1370 I915_WRITE(reg,
1371 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1372 INSTPM_SYNC_FLUSH));
1373 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1374 1000))
1375 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1376 ring->name);
1377 }
1378 }
1379
1380 static int
1381 bsd_ring_flush(struct intel_engine_cs *ring,
1382 u32 invalidate_domains,
1383 u32 flush_domains)
1384 {
1385 int ret;
1386
1387 ret = intel_ring_begin(ring, 2);
1388 if (ret)
1389 return ret;
1390
1391 intel_ring_emit(ring, MI_FLUSH);
1392 intel_ring_emit(ring, MI_NOOP);
1393 intel_ring_advance(ring);
1394 return 0;
1395 }
1396
1397 static int
1398 i9xx_add_request(struct intel_engine_cs *ring)
1399 {
1400 int ret;
1401
1402 ret = intel_ring_begin(ring, 4);
1403 if (ret)
1404 return ret;
1405
1406 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1407 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1408 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1409 intel_ring_emit(ring, MI_USER_INTERRUPT);
1410 __intel_ring_advance(ring);
1411
1412 return 0;
1413 }
1414
1415 static bool
1416 gen6_ring_get_irq(struct intel_engine_cs *ring)
1417 {
1418 struct drm_device *dev = ring->dev;
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1420 unsigned long flags;
1421
1422 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1423 return false;
1424
1425 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1426 if (ring->irq_refcount++ == 0) {
1427 if (HAS_L3_DPF(dev) && ring->id == RCS)
1428 I915_WRITE_IMR(ring,
1429 ~(ring->irq_enable_mask |
1430 GT_PARITY_ERROR(dev)));
1431 else
1432 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1433 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1434 }
1435 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1436
1437 return true;
1438 }
1439
1440 static void
1441 gen6_ring_put_irq(struct intel_engine_cs *ring)
1442 {
1443 struct drm_device *dev = ring->dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 unsigned long flags;
1446
1447 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1448 if (--ring->irq_refcount == 0) {
1449 if (HAS_L3_DPF(dev) && ring->id == RCS)
1450 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1451 else
1452 I915_WRITE_IMR(ring, ~0);
1453 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1454 }
1455 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1456 }
1457
1458 static bool
1459 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1460 {
1461 struct drm_device *dev = ring->dev;
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463 unsigned long flags;
1464
1465 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1466 return false;
1467
1468 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1469 if (ring->irq_refcount++ == 0) {
1470 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1471 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1472 }
1473 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1474
1475 return true;
1476 }
1477
1478 static void
1479 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1480 {
1481 struct drm_device *dev = ring->dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483 unsigned long flags;
1484
1485 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1486 if (--ring->irq_refcount == 0) {
1487 I915_WRITE_IMR(ring, ~0);
1488 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1489 }
1490 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1491 }
1492
1493 static bool
1494 gen8_ring_get_irq(struct intel_engine_cs *ring)
1495 {
1496 struct drm_device *dev = ring->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 unsigned long flags;
1499
1500 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1501 return false;
1502
1503 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1504 if (ring->irq_refcount++ == 0) {
1505 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1506 I915_WRITE_IMR(ring,
1507 ~(ring->irq_enable_mask |
1508 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1509 } else {
1510 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1511 }
1512 POSTING_READ(RING_IMR(ring->mmio_base));
1513 }
1514 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1515
1516 return true;
1517 }
1518
1519 static void
1520 gen8_ring_put_irq(struct intel_engine_cs *ring)
1521 {
1522 struct drm_device *dev = ring->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 unsigned long flags;
1525
1526 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1527 if (--ring->irq_refcount == 0) {
1528 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1529 I915_WRITE_IMR(ring,
1530 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1531 } else {
1532 I915_WRITE_IMR(ring, ~0);
1533 }
1534 POSTING_READ(RING_IMR(ring->mmio_base));
1535 }
1536 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1537 }
1538
1539 static int
1540 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1541 u64 offset, u32 length,
1542 unsigned flags)
1543 {
1544 int ret;
1545
1546 ret = intel_ring_begin(ring, 2);
1547 if (ret)
1548 return ret;
1549
1550 intel_ring_emit(ring,
1551 MI_BATCH_BUFFER_START |
1552 MI_BATCH_GTT |
1553 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1554 intel_ring_emit(ring, offset);
1555 intel_ring_advance(ring);
1556
1557 return 0;
1558 }
1559
1560 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1561 #define I830_BATCH_LIMIT (256*1024)
1562 #define I830_TLB_ENTRIES (2)
1563 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1564 static int
1565 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1566 u64 offset, u32 len,
1567 unsigned flags)
1568 {
1569 u32 cs_offset = ring->scratch.gtt_offset;
1570 int ret;
1571
1572 ret = intel_ring_begin(ring, 6);
1573 if (ret)
1574 return ret;
1575
1576 /* Evict the invalid PTE TLBs */
1577 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1578 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1579 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1580 intel_ring_emit(ring, cs_offset);
1581 intel_ring_emit(ring, 0xdeadbeef);
1582 intel_ring_emit(ring, MI_NOOP);
1583 intel_ring_advance(ring);
1584
1585 if ((flags & I915_DISPATCH_PINNED) == 0) {
1586 if (len > I830_BATCH_LIMIT)
1587 return -ENOSPC;
1588
1589 ret = intel_ring_begin(ring, 6 + 2);
1590 if (ret)
1591 return ret;
1592
1593 /* Blit the batch (which has now all relocs applied) to the
1594 * stable batch scratch bo area (so that the CS never
1595 * stumbles over its tlb invalidation bug) ...
1596 */
1597 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1598 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1599 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1600 intel_ring_emit(ring, cs_offset);
1601 intel_ring_emit(ring, 4096);
1602 intel_ring_emit(ring, offset);
1603
1604 intel_ring_emit(ring, MI_FLUSH);
1605 intel_ring_emit(ring, MI_NOOP);
1606 intel_ring_advance(ring);
1607
1608 /* ... and execute it. */
1609 offset = cs_offset;
1610 }
1611
1612 ret = intel_ring_begin(ring, 4);
1613 if (ret)
1614 return ret;
1615
1616 intel_ring_emit(ring, MI_BATCH_BUFFER);
1617 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1618 intel_ring_emit(ring, offset + len - 8);
1619 intel_ring_emit(ring, MI_NOOP);
1620 intel_ring_advance(ring);
1621
1622 return 0;
1623 }
1624
1625 static int
1626 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1627 u64 offset, u32 len,
1628 unsigned flags)
1629 {
1630 int ret;
1631
1632 ret = intel_ring_begin(ring, 2);
1633 if (ret)
1634 return ret;
1635
1636 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1637 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1638 intel_ring_advance(ring);
1639
1640 return 0;
1641 }
1642
1643 static void cleanup_status_page(struct intel_engine_cs *ring)
1644 {
1645 struct drm_i915_gem_object *obj;
1646
1647 obj = ring->status_page.obj;
1648 if (obj == NULL)
1649 return;
1650
1651 kunmap(sg_page(obj->pages->sgl));
1652 i915_gem_object_ggtt_unpin(obj);
1653 drm_gem_object_unreference(&obj->base);
1654 ring->status_page.obj = NULL;
1655 }
1656
1657 static int init_status_page(struct intel_engine_cs *ring)
1658 {
1659 struct drm_i915_gem_object *obj;
1660
1661 if ((obj = ring->status_page.obj) == NULL) {
1662 unsigned flags;
1663 int ret;
1664
1665 obj = i915_gem_alloc_object(ring->dev, 4096);
1666 if (obj == NULL) {
1667 DRM_ERROR("Failed to allocate status page\n");
1668 return -ENOMEM;
1669 }
1670
1671 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1672 if (ret)
1673 goto err_unref;
1674
1675 flags = 0;
1676 if (!HAS_LLC(ring->dev))
1677 /* On g33, we cannot place HWS above 256MiB, so
1678 * restrict its pinning to the low mappable arena.
1679 * Though this restriction is not documented for
1680 * gen4, gen5, or byt, they also behave similarly
1681 * and hang if the HWS is placed at the top of the
1682 * GTT. To generalise, it appears that all !llc
1683 * platforms have issues with us placing the HWS
1684 * above the mappable region (even though we never
1685 * actualy map it).
1686 */
1687 flags |= PIN_MAPPABLE;
1688 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1689 if (ret) {
1690 err_unref:
1691 drm_gem_object_unreference(&obj->base);
1692 return ret;
1693 }
1694
1695 ring->status_page.obj = obj;
1696 }
1697
1698 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1699 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1700 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1701
1702 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1703 ring->name, ring->status_page.gfx_addr);
1704
1705 return 0;
1706 }
1707
1708 static int init_phys_status_page(struct intel_engine_cs *ring)
1709 {
1710 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1711
1712 if (!dev_priv->status_page_dmah) {
1713 dev_priv->status_page_dmah =
1714 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1715 if (!dev_priv->status_page_dmah)
1716 return -ENOMEM;
1717 }
1718
1719 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1720 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1721
1722 return 0;
1723 }
1724
1725 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1726 {
1727 if (!ringbuf->obj)
1728 return;
1729
1730 iounmap(ringbuf->virtual_start);
1731 i915_gem_object_ggtt_unpin(ringbuf->obj);
1732 drm_gem_object_unreference(&ringbuf->obj->base);
1733 ringbuf->obj = NULL;
1734 }
1735
1736 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1737 struct intel_ringbuffer *ringbuf)
1738 {
1739 struct drm_i915_private *dev_priv = to_i915(dev);
1740 struct drm_i915_gem_object *obj;
1741 int ret;
1742
1743 if (ringbuf->obj)
1744 return 0;
1745
1746 obj = NULL;
1747 if (!HAS_LLC(dev))
1748 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1749 if (obj == NULL)
1750 obj = i915_gem_alloc_object(dev, ringbuf->size);
1751 if (obj == NULL)
1752 return -ENOMEM;
1753
1754 /* mark ring buffers as read-only from GPU side by default */
1755 obj->gt_ro = 1;
1756
1757 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1758 if (ret)
1759 goto err_unref;
1760
1761 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1762 if (ret)
1763 goto err_unpin;
1764
1765 ringbuf->virtual_start =
1766 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1767 ringbuf->size);
1768 if (ringbuf->virtual_start == NULL) {
1769 ret = -EINVAL;
1770 goto err_unpin;
1771 }
1772
1773 ringbuf->obj = obj;
1774 return 0;
1775
1776 err_unpin:
1777 i915_gem_object_ggtt_unpin(obj);
1778 err_unref:
1779 drm_gem_object_unreference(&obj->base);
1780 return ret;
1781 }
1782
1783 static int intel_init_ring_buffer(struct drm_device *dev,
1784 struct intel_engine_cs *ring)
1785 {
1786 struct intel_ringbuffer *ringbuf = ring->buffer;
1787 int ret;
1788
1789 if (ringbuf == NULL) {
1790 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1791 if (!ringbuf)
1792 return -ENOMEM;
1793 ring->buffer = ringbuf;
1794 }
1795
1796 ring->dev = dev;
1797 INIT_LIST_HEAD(&ring->active_list);
1798 INIT_LIST_HEAD(&ring->request_list);
1799 INIT_LIST_HEAD(&ring->execlist_queue);
1800 ringbuf->size = 32 * PAGE_SIZE;
1801 ringbuf->ring = ring;
1802 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1803
1804 init_waitqueue_head(&ring->irq_queue);
1805
1806 if (I915_NEED_GFX_HWS(dev)) {
1807 ret = init_status_page(ring);
1808 if (ret)
1809 goto error;
1810 } else {
1811 BUG_ON(ring->id != RCS);
1812 ret = init_phys_status_page(ring);
1813 if (ret)
1814 goto error;
1815 }
1816
1817 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1818 if (ret) {
1819 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1820 goto error;
1821 }
1822
1823 /* Workaround an erratum on the i830 which causes a hang if
1824 * the TAIL pointer points to within the last 2 cachelines
1825 * of the buffer.
1826 */
1827 ringbuf->effective_size = ringbuf->size;
1828 if (IS_I830(dev) || IS_845G(dev))
1829 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1830
1831 ret = i915_cmd_parser_init_ring(ring);
1832 if (ret)
1833 goto error;
1834
1835 ret = ring->init(ring);
1836 if (ret)
1837 goto error;
1838
1839 return 0;
1840
1841 error:
1842 kfree(ringbuf);
1843 ring->buffer = NULL;
1844 return ret;
1845 }
1846
1847 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1848 {
1849 struct drm_i915_private *dev_priv;
1850 struct intel_ringbuffer *ringbuf;
1851
1852 if (!intel_ring_initialized(ring))
1853 return;
1854
1855 dev_priv = to_i915(ring->dev);
1856 ringbuf = ring->buffer;
1857
1858 intel_stop_ring_buffer(ring);
1859 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1860
1861 intel_destroy_ringbuffer_obj(ringbuf);
1862 ring->preallocated_lazy_request = NULL;
1863 ring->outstanding_lazy_seqno = 0;
1864
1865 if (ring->cleanup)
1866 ring->cleanup(ring);
1867
1868 cleanup_status_page(ring);
1869
1870 i915_cmd_parser_fini_ring(ring);
1871
1872 kfree(ringbuf);
1873 ring->buffer = NULL;
1874 }
1875
1876 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1877 {
1878 struct intel_ringbuffer *ringbuf = ring->buffer;
1879 struct drm_i915_gem_request *request;
1880 u32 seqno = 0;
1881 int ret;
1882
1883 if (ringbuf->last_retired_head != -1) {
1884 ringbuf->head = ringbuf->last_retired_head;
1885 ringbuf->last_retired_head = -1;
1886
1887 ringbuf->space = intel_ring_space(ringbuf);
1888 if (ringbuf->space >= n)
1889 return 0;
1890 }
1891
1892 list_for_each_entry(request, &ring->request_list, list) {
1893 if (__intel_ring_space(request->tail, ringbuf->tail,
1894 ringbuf->size) >= n) {
1895 seqno = request->seqno;
1896 break;
1897 }
1898 }
1899
1900 if (seqno == 0)
1901 return -ENOSPC;
1902
1903 ret = i915_wait_seqno(ring, seqno);
1904 if (ret)
1905 return ret;
1906
1907 i915_gem_retire_requests_ring(ring);
1908 ringbuf->head = ringbuf->last_retired_head;
1909 ringbuf->last_retired_head = -1;
1910
1911 ringbuf->space = intel_ring_space(ringbuf);
1912 return 0;
1913 }
1914
1915 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1916 {
1917 struct drm_device *dev = ring->dev;
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919 struct intel_ringbuffer *ringbuf = ring->buffer;
1920 unsigned long end;
1921 int ret;
1922
1923 ret = intel_ring_wait_request(ring, n);
1924 if (ret != -ENOSPC)
1925 return ret;
1926
1927 /* force the tail write in case we have been skipping them */
1928 __intel_ring_advance(ring);
1929
1930 /* With GEM the hangcheck timer should kick us out of the loop,
1931 * leaving it early runs the risk of corrupting GEM state (due
1932 * to running on almost untested codepaths). But on resume
1933 * timers don't work yet, so prevent a complete hang in that
1934 * case by choosing an insanely large timeout. */
1935 end = jiffies + 60 * HZ;
1936
1937 trace_i915_ring_wait_begin(ring);
1938 do {
1939 ringbuf->head = I915_READ_HEAD(ring);
1940 ringbuf->space = intel_ring_space(ringbuf);
1941 if (ringbuf->space >= n) {
1942 ret = 0;
1943 break;
1944 }
1945
1946 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1947 dev->primary->master) {
1948 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1949 if (master_priv->sarea_priv)
1950 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1951 }
1952
1953 msleep(1);
1954
1955 if (dev_priv->mm.interruptible && signal_pending(current)) {
1956 ret = -ERESTARTSYS;
1957 break;
1958 }
1959
1960 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1961 dev_priv->mm.interruptible);
1962 if (ret)
1963 break;
1964
1965 if (time_after(jiffies, end)) {
1966 ret = -EBUSY;
1967 break;
1968 }
1969 } while (1);
1970 trace_i915_ring_wait_end(ring);
1971 return ret;
1972 }
1973
1974 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1975 {
1976 uint32_t __iomem *virt;
1977 struct intel_ringbuffer *ringbuf = ring->buffer;
1978 int rem = ringbuf->size - ringbuf->tail;
1979
1980 if (ringbuf->space < rem) {
1981 int ret = ring_wait_for_space(ring, rem);
1982 if (ret)
1983 return ret;
1984 }
1985
1986 virt = ringbuf->virtual_start + ringbuf->tail;
1987 rem /= 4;
1988 while (rem--)
1989 iowrite32(MI_NOOP, virt++);
1990
1991 ringbuf->tail = 0;
1992 ringbuf->space = intel_ring_space(ringbuf);
1993
1994 return 0;
1995 }
1996
1997 int intel_ring_idle(struct intel_engine_cs *ring)
1998 {
1999 u32 seqno;
2000 int ret;
2001
2002 /* We need to add any requests required to flush the objects and ring */
2003 if (ring->outstanding_lazy_seqno) {
2004 ret = i915_add_request(ring, NULL);
2005 if (ret)
2006 return ret;
2007 }
2008
2009 /* Wait upon the last request to be completed */
2010 if (list_empty(&ring->request_list))
2011 return 0;
2012
2013 seqno = list_entry(ring->request_list.prev,
2014 struct drm_i915_gem_request,
2015 list)->seqno;
2016
2017 return i915_wait_seqno(ring, seqno);
2018 }
2019
2020 static int
2021 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
2022 {
2023 if (ring->outstanding_lazy_seqno)
2024 return 0;
2025
2026 if (ring->preallocated_lazy_request == NULL) {
2027 struct drm_i915_gem_request *request;
2028
2029 request = kmalloc(sizeof(*request), GFP_KERNEL);
2030 if (request == NULL)
2031 return -ENOMEM;
2032
2033 ring->preallocated_lazy_request = request;
2034 }
2035
2036 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
2037 }
2038
2039 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2040 int bytes)
2041 {
2042 struct intel_ringbuffer *ringbuf = ring->buffer;
2043 int ret;
2044
2045 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2046 ret = intel_wrap_ring_buffer(ring);
2047 if (unlikely(ret))
2048 return ret;
2049 }
2050
2051 if (unlikely(ringbuf->space < bytes)) {
2052 ret = ring_wait_for_space(ring, bytes);
2053 if (unlikely(ret))
2054 return ret;
2055 }
2056
2057 return 0;
2058 }
2059
2060 int intel_ring_begin(struct intel_engine_cs *ring,
2061 int num_dwords)
2062 {
2063 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2064 int ret;
2065
2066 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2067 dev_priv->mm.interruptible);
2068 if (ret)
2069 return ret;
2070
2071 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2072 if (ret)
2073 return ret;
2074
2075 /* Preallocate the olr before touching the ring */
2076 ret = intel_ring_alloc_seqno(ring);
2077 if (ret)
2078 return ret;
2079
2080 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2081 return 0;
2082 }
2083
2084 /* Align the ring tail to a cacheline boundary */
2085 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2086 {
2087 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2088 int ret;
2089
2090 if (num_dwords == 0)
2091 return 0;
2092
2093 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2094 ret = intel_ring_begin(ring, num_dwords);
2095 if (ret)
2096 return ret;
2097
2098 while (num_dwords--)
2099 intel_ring_emit(ring, MI_NOOP);
2100
2101 intel_ring_advance(ring);
2102
2103 return 0;
2104 }
2105
2106 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2107 {
2108 struct drm_device *dev = ring->dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110
2111 BUG_ON(ring->outstanding_lazy_seqno);
2112
2113 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2114 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2115 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2116 if (HAS_VEBOX(dev))
2117 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2118 }
2119
2120 ring->set_seqno(ring, seqno);
2121 ring->hangcheck.seqno = seqno;
2122 }
2123
2124 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2125 u32 value)
2126 {
2127 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2128
2129 /* Every tail move must follow the sequence below */
2130
2131 /* Disable notification that the ring is IDLE. The GT
2132 * will then assume that it is busy and bring it out of rc6.
2133 */
2134 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2135 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2136
2137 /* Clear the context id. Here be magic! */
2138 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2139
2140 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2141 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2142 GEN6_BSD_SLEEP_INDICATOR) == 0,
2143 50))
2144 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2145
2146 /* Now that the ring is fully powered up, update the tail */
2147 I915_WRITE_TAIL(ring, value);
2148 POSTING_READ(RING_TAIL(ring->mmio_base));
2149
2150 /* Let the ring send IDLE messages to the GT again,
2151 * and so let it sleep to conserve power when idle.
2152 */
2153 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2154 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2155 }
2156
2157 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2158 u32 invalidate, u32 flush)
2159 {
2160 uint32_t cmd;
2161 int ret;
2162
2163 ret = intel_ring_begin(ring, 4);
2164 if (ret)
2165 return ret;
2166
2167 cmd = MI_FLUSH_DW;
2168 if (INTEL_INFO(ring->dev)->gen >= 8)
2169 cmd += 1;
2170 /*
2171 * Bspec vol 1c.5 - video engine command streamer:
2172 * "If ENABLED, all TLBs will be invalidated once the flush
2173 * operation is complete. This bit is only valid when the
2174 * Post-Sync Operation field is a value of 1h or 3h."
2175 */
2176 if (invalidate & I915_GEM_GPU_DOMAINS)
2177 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2178 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2179 intel_ring_emit(ring, cmd);
2180 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2181 if (INTEL_INFO(ring->dev)->gen >= 8) {
2182 intel_ring_emit(ring, 0); /* upper addr */
2183 intel_ring_emit(ring, 0); /* value */
2184 } else {
2185 intel_ring_emit(ring, 0);
2186 intel_ring_emit(ring, MI_NOOP);
2187 }
2188 intel_ring_advance(ring);
2189 return 0;
2190 }
2191
2192 static int
2193 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2194 u64 offset, u32 len,
2195 unsigned flags)
2196 {
2197 bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2198 int ret;
2199
2200 ret = intel_ring_begin(ring, 4);
2201 if (ret)
2202 return ret;
2203
2204 /* FIXME(BDW): Address space and security selectors. */
2205 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2206 intel_ring_emit(ring, lower_32_bits(offset));
2207 intel_ring_emit(ring, upper_32_bits(offset));
2208 intel_ring_emit(ring, MI_NOOP);
2209 intel_ring_advance(ring);
2210
2211 return 0;
2212 }
2213
2214 static int
2215 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2216 u64 offset, u32 len,
2217 unsigned flags)
2218 {
2219 int ret;
2220
2221 ret = intel_ring_begin(ring, 2);
2222 if (ret)
2223 return ret;
2224
2225 intel_ring_emit(ring,
2226 MI_BATCH_BUFFER_START |
2227 (flags & I915_DISPATCH_SECURE ?
2228 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2229 /* bit0-7 is the length on GEN6+ */
2230 intel_ring_emit(ring, offset);
2231 intel_ring_advance(ring);
2232
2233 return 0;
2234 }
2235
2236 static int
2237 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2238 u64 offset, u32 len,
2239 unsigned flags)
2240 {
2241 int ret;
2242
2243 ret = intel_ring_begin(ring, 2);
2244 if (ret)
2245 return ret;
2246
2247 intel_ring_emit(ring,
2248 MI_BATCH_BUFFER_START |
2249 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2250 /* bit0-7 is the length on GEN6+ */
2251 intel_ring_emit(ring, offset);
2252 intel_ring_advance(ring);
2253
2254 return 0;
2255 }
2256
2257 /* Blitter support (SandyBridge+) */
2258
2259 static int gen6_ring_flush(struct intel_engine_cs *ring,
2260 u32 invalidate, u32 flush)
2261 {
2262 struct drm_device *dev = ring->dev;
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264 uint32_t cmd;
2265 int ret;
2266
2267 ret = intel_ring_begin(ring, 4);
2268 if (ret)
2269 return ret;
2270
2271 cmd = MI_FLUSH_DW;
2272 if (INTEL_INFO(ring->dev)->gen >= 8)
2273 cmd += 1;
2274 /*
2275 * Bspec vol 1c.3 - blitter engine command streamer:
2276 * "If ENABLED, all TLBs will be invalidated once the flush
2277 * operation is complete. This bit is only valid when the
2278 * Post-Sync Operation field is a value of 1h or 3h."
2279 */
2280 if (invalidate & I915_GEM_DOMAIN_RENDER)
2281 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2282 MI_FLUSH_DW_OP_STOREDW;
2283 intel_ring_emit(ring, cmd);
2284 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2285 if (INTEL_INFO(ring->dev)->gen >= 8) {
2286 intel_ring_emit(ring, 0); /* upper addr */
2287 intel_ring_emit(ring, 0); /* value */
2288 } else {
2289 intel_ring_emit(ring, 0);
2290 intel_ring_emit(ring, MI_NOOP);
2291 }
2292 intel_ring_advance(ring);
2293
2294 if (!invalidate && flush) {
2295 if (IS_GEN7(dev))
2296 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2297 else if (IS_BROADWELL(dev))
2298 dev_priv->fbc.need_sw_cache_clean = true;
2299 }
2300
2301 return 0;
2302 }
2303
2304 int intel_init_render_ring_buffer(struct drm_device *dev)
2305 {
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2308 struct drm_i915_gem_object *obj;
2309 int ret;
2310
2311 ring->name = "render ring";
2312 ring->id = RCS;
2313 ring->mmio_base = RENDER_RING_BASE;
2314
2315 if (INTEL_INFO(dev)->gen >= 8) {
2316 if (i915_semaphore_is_enabled(dev)) {
2317 obj = i915_gem_alloc_object(dev, 4096);
2318 if (obj == NULL) {
2319 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2320 i915.semaphores = 0;
2321 } else {
2322 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2323 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2324 if (ret != 0) {
2325 drm_gem_object_unreference(&obj->base);
2326 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2327 i915.semaphores = 0;
2328 } else
2329 dev_priv->semaphore_obj = obj;
2330 }
2331 }
2332
2333 ring->init_context = intel_ring_workarounds_emit;
2334 ring->add_request = gen6_add_request;
2335 ring->flush = gen8_render_ring_flush;
2336 ring->irq_get = gen8_ring_get_irq;
2337 ring->irq_put = gen8_ring_put_irq;
2338 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2339 ring->get_seqno = gen6_ring_get_seqno;
2340 ring->set_seqno = ring_set_seqno;
2341 if (i915_semaphore_is_enabled(dev)) {
2342 WARN_ON(!dev_priv->semaphore_obj);
2343 ring->semaphore.sync_to = gen8_ring_sync;
2344 ring->semaphore.signal = gen8_rcs_signal;
2345 GEN8_RING_SEMAPHORE_INIT;
2346 }
2347 } else if (INTEL_INFO(dev)->gen >= 6) {
2348 ring->add_request = gen6_add_request;
2349 ring->flush = gen7_render_ring_flush;
2350 if (INTEL_INFO(dev)->gen == 6)
2351 ring->flush = gen6_render_ring_flush;
2352 ring->irq_get = gen6_ring_get_irq;
2353 ring->irq_put = gen6_ring_put_irq;
2354 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2355 ring->get_seqno = gen6_ring_get_seqno;
2356 ring->set_seqno = ring_set_seqno;
2357 if (i915_semaphore_is_enabled(dev)) {
2358 ring->semaphore.sync_to = gen6_ring_sync;
2359 ring->semaphore.signal = gen6_signal;
2360 /*
2361 * The current semaphore is only applied on pre-gen8
2362 * platform. And there is no VCS2 ring on the pre-gen8
2363 * platform. So the semaphore between RCS and VCS2 is
2364 * initialized as INVALID. Gen8 will initialize the
2365 * sema between VCS2 and RCS later.
2366 */
2367 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2368 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2369 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2370 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2371 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2372 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2373 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2374 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2375 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2376 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2377 }
2378 } else if (IS_GEN5(dev)) {
2379 ring->add_request = pc_render_add_request;
2380 ring->flush = gen4_render_ring_flush;
2381 ring->get_seqno = pc_render_get_seqno;
2382 ring->set_seqno = pc_render_set_seqno;
2383 ring->irq_get = gen5_ring_get_irq;
2384 ring->irq_put = gen5_ring_put_irq;
2385 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2386 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2387 } else {
2388 ring->add_request = i9xx_add_request;
2389 if (INTEL_INFO(dev)->gen < 4)
2390 ring->flush = gen2_render_ring_flush;
2391 else
2392 ring->flush = gen4_render_ring_flush;
2393 ring->get_seqno = ring_get_seqno;
2394 ring->set_seqno = ring_set_seqno;
2395 if (IS_GEN2(dev)) {
2396 ring->irq_get = i8xx_ring_get_irq;
2397 ring->irq_put = i8xx_ring_put_irq;
2398 } else {
2399 ring->irq_get = i9xx_ring_get_irq;
2400 ring->irq_put = i9xx_ring_put_irq;
2401 }
2402 ring->irq_enable_mask = I915_USER_INTERRUPT;
2403 }
2404 ring->write_tail = ring_write_tail;
2405
2406 if (IS_HASWELL(dev))
2407 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2408 else if (IS_GEN8(dev))
2409 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2410 else if (INTEL_INFO(dev)->gen >= 6)
2411 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2412 else if (INTEL_INFO(dev)->gen >= 4)
2413 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2414 else if (IS_I830(dev) || IS_845G(dev))
2415 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2416 else
2417 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2418 ring->init = init_render_ring;
2419 ring->cleanup = render_ring_cleanup;
2420
2421 /* Workaround batchbuffer to combat CS tlb bug. */
2422 if (HAS_BROKEN_CS_TLB(dev)) {
2423 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2424 if (obj == NULL) {
2425 DRM_ERROR("Failed to allocate batch bo\n");
2426 return -ENOMEM;
2427 }
2428
2429 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2430 if (ret != 0) {
2431 drm_gem_object_unreference(&obj->base);
2432 DRM_ERROR("Failed to ping batch bo\n");
2433 return ret;
2434 }
2435
2436 ring->scratch.obj = obj;
2437 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2438 }
2439
2440 return intel_init_ring_buffer(dev, ring);
2441 }
2442
2443 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2444 {
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2447 struct intel_ringbuffer *ringbuf = ring->buffer;
2448 int ret;
2449
2450 if (ringbuf == NULL) {
2451 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2452 if (!ringbuf)
2453 return -ENOMEM;
2454 ring->buffer = ringbuf;
2455 }
2456
2457 ring->name = "render ring";
2458 ring->id = RCS;
2459 ring->mmio_base = RENDER_RING_BASE;
2460
2461 if (INTEL_INFO(dev)->gen >= 6) {
2462 /* non-kms not supported on gen6+ */
2463 ret = -ENODEV;
2464 goto err_ringbuf;
2465 }
2466
2467 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2468 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2469 * the special gen5 functions. */
2470 ring->add_request = i9xx_add_request;
2471 if (INTEL_INFO(dev)->gen < 4)
2472 ring->flush = gen2_render_ring_flush;
2473 else
2474 ring->flush = gen4_render_ring_flush;
2475 ring->get_seqno = ring_get_seqno;
2476 ring->set_seqno = ring_set_seqno;
2477 if (IS_GEN2(dev)) {
2478 ring->irq_get = i8xx_ring_get_irq;
2479 ring->irq_put = i8xx_ring_put_irq;
2480 } else {
2481 ring->irq_get = i9xx_ring_get_irq;
2482 ring->irq_put = i9xx_ring_put_irq;
2483 }
2484 ring->irq_enable_mask = I915_USER_INTERRUPT;
2485 ring->write_tail = ring_write_tail;
2486 if (INTEL_INFO(dev)->gen >= 4)
2487 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2488 else if (IS_I830(dev) || IS_845G(dev))
2489 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2490 else
2491 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2492 ring->init = init_render_ring;
2493 ring->cleanup = render_ring_cleanup;
2494
2495 ring->dev = dev;
2496 INIT_LIST_HEAD(&ring->active_list);
2497 INIT_LIST_HEAD(&ring->request_list);
2498
2499 ringbuf->size = size;
2500 ringbuf->effective_size = ringbuf->size;
2501 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2502 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2503
2504 ringbuf->virtual_start = ioremap_wc(start, size);
2505 if (ringbuf->virtual_start == NULL) {
2506 DRM_ERROR("can not ioremap virtual address for"
2507 " ring buffer\n");
2508 ret = -ENOMEM;
2509 goto err_ringbuf;
2510 }
2511
2512 if (!I915_NEED_GFX_HWS(dev)) {
2513 ret = init_phys_status_page(ring);
2514 if (ret)
2515 goto err_vstart;
2516 }
2517
2518 return 0;
2519
2520 err_vstart:
2521 iounmap(ringbuf->virtual_start);
2522 err_ringbuf:
2523 kfree(ringbuf);
2524 ring->buffer = NULL;
2525 return ret;
2526 }
2527
2528 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2529 {
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2532
2533 ring->name = "bsd ring";
2534 ring->id = VCS;
2535
2536 ring->write_tail = ring_write_tail;
2537 if (INTEL_INFO(dev)->gen >= 6) {
2538 ring->mmio_base = GEN6_BSD_RING_BASE;
2539 /* gen6 bsd needs a special wa for tail updates */
2540 if (IS_GEN6(dev))
2541 ring->write_tail = gen6_bsd_ring_write_tail;
2542 ring->flush = gen6_bsd_ring_flush;
2543 ring->add_request = gen6_add_request;
2544 ring->get_seqno = gen6_ring_get_seqno;
2545 ring->set_seqno = ring_set_seqno;
2546 if (INTEL_INFO(dev)->gen >= 8) {
2547 ring->irq_enable_mask =
2548 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2549 ring->irq_get = gen8_ring_get_irq;
2550 ring->irq_put = gen8_ring_put_irq;
2551 ring->dispatch_execbuffer =
2552 gen8_ring_dispatch_execbuffer;
2553 if (i915_semaphore_is_enabled(dev)) {
2554 ring->semaphore.sync_to = gen8_ring_sync;
2555 ring->semaphore.signal = gen8_xcs_signal;
2556 GEN8_RING_SEMAPHORE_INIT;
2557 }
2558 } else {
2559 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2560 ring->irq_get = gen6_ring_get_irq;
2561 ring->irq_put = gen6_ring_put_irq;
2562 ring->dispatch_execbuffer =
2563 gen6_ring_dispatch_execbuffer;
2564 if (i915_semaphore_is_enabled(dev)) {
2565 ring->semaphore.sync_to = gen6_ring_sync;
2566 ring->semaphore.signal = gen6_signal;
2567 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2568 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2569 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2570 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2571 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2572 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2573 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2574 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2575 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2576 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2577 }
2578 }
2579 } else {
2580 ring->mmio_base = BSD_RING_BASE;
2581 ring->flush = bsd_ring_flush;
2582 ring->add_request = i9xx_add_request;
2583 ring->get_seqno = ring_get_seqno;
2584 ring->set_seqno = ring_set_seqno;
2585 if (IS_GEN5(dev)) {
2586 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2587 ring->irq_get = gen5_ring_get_irq;
2588 ring->irq_put = gen5_ring_put_irq;
2589 } else {
2590 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2591 ring->irq_get = i9xx_ring_get_irq;
2592 ring->irq_put = i9xx_ring_put_irq;
2593 }
2594 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2595 }
2596 ring->init = init_ring_common;
2597
2598 return intel_init_ring_buffer(dev, ring);
2599 }
2600
2601 /**
2602 * Initialize the second BSD ring for Broadwell GT3.
2603 * It is noted that this only exists on Broadwell GT3.
2604 */
2605 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2606 {
2607 struct drm_i915_private *dev_priv = dev->dev_private;
2608 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2609
2610 if ((INTEL_INFO(dev)->gen != 8)) {
2611 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2612 return -EINVAL;
2613 }
2614
2615 ring->name = "bsd2 ring";
2616 ring->id = VCS2;
2617
2618 ring->write_tail = ring_write_tail;
2619 ring->mmio_base = GEN8_BSD2_RING_BASE;
2620 ring->flush = gen6_bsd_ring_flush;
2621 ring->add_request = gen6_add_request;
2622 ring->get_seqno = gen6_ring_get_seqno;
2623 ring->set_seqno = ring_set_seqno;
2624 ring->irq_enable_mask =
2625 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2626 ring->irq_get = gen8_ring_get_irq;
2627 ring->irq_put = gen8_ring_put_irq;
2628 ring->dispatch_execbuffer =
2629 gen8_ring_dispatch_execbuffer;
2630 if (i915_semaphore_is_enabled(dev)) {
2631 ring->semaphore.sync_to = gen8_ring_sync;
2632 ring->semaphore.signal = gen8_xcs_signal;
2633 GEN8_RING_SEMAPHORE_INIT;
2634 }
2635 ring->init = init_ring_common;
2636
2637 return intel_init_ring_buffer(dev, ring);
2638 }
2639
2640 int intel_init_blt_ring_buffer(struct drm_device *dev)
2641 {
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2644
2645 ring->name = "blitter ring";
2646 ring->id = BCS;
2647
2648 ring->mmio_base = BLT_RING_BASE;
2649 ring->write_tail = ring_write_tail;
2650 ring->flush = gen6_ring_flush;
2651 ring->add_request = gen6_add_request;
2652 ring->get_seqno = gen6_ring_get_seqno;
2653 ring->set_seqno = ring_set_seqno;
2654 if (INTEL_INFO(dev)->gen >= 8) {
2655 ring->irq_enable_mask =
2656 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2657 ring->irq_get = gen8_ring_get_irq;
2658 ring->irq_put = gen8_ring_put_irq;
2659 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2660 if (i915_semaphore_is_enabled(dev)) {
2661 ring->semaphore.sync_to = gen8_ring_sync;
2662 ring->semaphore.signal = gen8_xcs_signal;
2663 GEN8_RING_SEMAPHORE_INIT;
2664 }
2665 } else {
2666 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2667 ring->irq_get = gen6_ring_get_irq;
2668 ring->irq_put = gen6_ring_put_irq;
2669 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2670 if (i915_semaphore_is_enabled(dev)) {
2671 ring->semaphore.signal = gen6_signal;
2672 ring->semaphore.sync_to = gen6_ring_sync;
2673 /*
2674 * The current semaphore is only applied on pre-gen8
2675 * platform. And there is no VCS2 ring on the pre-gen8
2676 * platform. So the semaphore between BCS and VCS2 is
2677 * initialized as INVALID. Gen8 will initialize the
2678 * sema between BCS and VCS2 later.
2679 */
2680 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2681 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2682 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2683 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2684 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2685 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2686 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2687 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2688 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2689 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2690 }
2691 }
2692 ring->init = init_ring_common;
2693
2694 return intel_init_ring_buffer(dev, ring);
2695 }
2696
2697 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2698 {
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2701
2702 ring->name = "video enhancement ring";
2703 ring->id = VECS;
2704
2705 ring->mmio_base = VEBOX_RING_BASE;
2706 ring->write_tail = ring_write_tail;
2707 ring->flush = gen6_ring_flush;
2708 ring->add_request = gen6_add_request;
2709 ring->get_seqno = gen6_ring_get_seqno;
2710 ring->set_seqno = ring_set_seqno;
2711
2712 if (INTEL_INFO(dev)->gen >= 8) {
2713 ring->irq_enable_mask =
2714 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2715 ring->irq_get = gen8_ring_get_irq;
2716 ring->irq_put = gen8_ring_put_irq;
2717 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2718 if (i915_semaphore_is_enabled(dev)) {
2719 ring->semaphore.sync_to = gen8_ring_sync;
2720 ring->semaphore.signal = gen8_xcs_signal;
2721 GEN8_RING_SEMAPHORE_INIT;
2722 }
2723 } else {
2724 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2725 ring->irq_get = hsw_vebox_get_irq;
2726 ring->irq_put = hsw_vebox_put_irq;
2727 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2728 if (i915_semaphore_is_enabled(dev)) {
2729 ring->semaphore.sync_to = gen6_ring_sync;
2730 ring->semaphore.signal = gen6_signal;
2731 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2732 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2733 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2734 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2735 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2736 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2737 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2738 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2739 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2740 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2741 }
2742 }
2743 ring->init = init_ring_common;
2744
2745 return intel_init_ring_buffer(dev, ring);
2746 }
2747
2748 int
2749 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2750 {
2751 int ret;
2752
2753 if (!ring->gpu_caches_dirty)
2754 return 0;
2755
2756 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2757 if (ret)
2758 return ret;
2759
2760 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2761
2762 ring->gpu_caches_dirty = false;
2763 return 0;
2764 }
2765
2766 int
2767 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2768 {
2769 uint32_t flush_domains;
2770 int ret;
2771
2772 flush_domains = 0;
2773 if (ring->gpu_caches_dirty)
2774 flush_domains = I915_GEM_GPU_DOMAINS;
2775
2776 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2777 if (ret)
2778 return ret;
2779
2780 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2781
2782 ring->gpu_caches_dirty = false;
2783 return 0;
2784 }
2785
2786 void
2787 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2788 {
2789 int ret;
2790
2791 if (!intel_ring_initialized(ring))
2792 return;
2793
2794 ret = intel_ring_idle(ring);
2795 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2796 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2797 ring->name, ret);
2798
2799 stop_ring(ring);
2800 }
Linux kernel - Deliverables
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