2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head
, int tail
, int size
)
44 int space
= head
- tail
;
47 return space
- I915_RING_FREE_SPACE
;
50 void intel_ring_update_space(struct intel_ring
*ring
)
52 if (ring
->last_retired_head
!= -1) {
53 ring
->head
= ring
->last_retired_head
;
54 ring
->last_retired_head
= -1;
57 ring
->space
= __intel_ring_space(ring
->head
& HEAD_ADDR
,
58 ring
->tail
, ring
->size
);
62 gen2_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
64 struct intel_ring
*ring
= req
->ring
;
70 if (mode
& EMIT_INVALIDATE
)
73 ret
= intel_ring_begin(req
, 2);
77 intel_ring_emit(ring
, cmd
);
78 intel_ring_emit(ring
, MI_NOOP
);
79 intel_ring_advance(ring
);
85 gen4_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
87 struct intel_ring
*ring
= req
->ring
;
94 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
95 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
96 * also flushed at 2d versus 3d pipeline switches.
100 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
101 * MI_READ_FLUSH is set, and is always flushed on 965.
103 * I915_GEM_DOMAIN_COMMAND may not exist?
105 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
106 * invalidated when MI_EXE_FLUSH is set.
108 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
109 * invalidated with every MI_FLUSH.
113 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
114 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
115 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
116 * are flushed at any MI_FLUSH.
120 if (mode
& EMIT_INVALIDATE
) {
122 if (IS_G4X(req
->i915
) || IS_GEN5(req
->i915
))
123 cmd
|= MI_INVALIDATE_ISP
;
126 ret
= intel_ring_begin(req
, 2);
130 intel_ring_emit(ring
, cmd
);
131 intel_ring_emit(ring
, MI_NOOP
);
132 intel_ring_advance(ring
);
138 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
139 * implementing two workarounds on gen6. From section 1.4.7.1
140 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
143 * produced by non-pipelined state commands), software needs to first
144 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
148 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 * And the workaround for these two requires this workaround first:
152 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
153 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * And this last workaround is tricky because of the requirements on
157 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * "1 of the following must also be set:
161 * - Render Target Cache Flush Enable ([12] of DW1)
162 * - Depth Cache Flush Enable ([0] of DW1)
163 * - Stall at Pixel Scoreboard ([1] of DW1)
164 * - Depth Stall ([13] of DW1)
165 * - Post-Sync Operation ([13] of DW1)
166 * - Notify Enable ([8] of DW1)"
168 * The cache flushes require the workaround flush that triggered this
169 * one, so we can't use it. Depth stall would trigger the same.
170 * Post-sync nonzero is what triggered this second workaround, so we
171 * can't use that one either. Notify enable is IRQs, which aren't
172 * really our business. That leaves only stall at scoreboard.
175 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
177 struct intel_ring
*ring
= req
->ring
;
179 req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
182 ret
= intel_ring_begin(req
, 6);
186 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
188 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
189 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
190 intel_ring_emit(ring
, 0); /* low dword */
191 intel_ring_emit(ring
, 0); /* high dword */
192 intel_ring_emit(ring
, MI_NOOP
);
193 intel_ring_advance(ring
);
195 ret
= intel_ring_begin(req
, 6);
199 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
201 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
202 intel_ring_emit(ring
, 0);
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, MI_NOOP
);
205 intel_ring_advance(ring
);
211 gen6_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
213 struct intel_ring
*ring
= req
->ring
;
215 req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
219 /* Force SNB workarounds for PIPE_CONTROL flushes */
220 ret
= intel_emit_post_sync_nonzero_flush(req
);
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
228 if (mode
& EMIT_FLUSH
) {
229 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
230 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
232 * Ensure that any following seqno writes only happen
233 * when the render cache is indeed flushed.
235 flags
|= PIPE_CONTROL_CS_STALL
;
237 if (mode
& EMIT_INVALIDATE
) {
238 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
239 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
240 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
245 * TLB invalidate requires a post-sync write.
247 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
250 ret
= intel_ring_begin(req
, 4);
254 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
255 intel_ring_emit(ring
, flags
);
256 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
257 intel_ring_emit(ring
, 0);
258 intel_ring_advance(ring
);
264 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
266 struct intel_ring
*ring
= req
->ring
;
269 ret
= intel_ring_begin(req
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
,
275 PIPE_CONTROL_CS_STALL
|
276 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
277 intel_ring_emit(ring
, 0);
278 intel_ring_emit(ring
, 0);
279 intel_ring_advance(ring
);
285 gen7_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
287 struct intel_ring
*ring
= req
->ring
;
289 req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
294 * Ensure that any following seqno writes only happen when the render
295 * cache is indeed flushed.
297 * Workaround: 4th PIPE_CONTROL command (except the ones with only
298 * read-cache invalidate bits set) must have the CS_STALL bit set. We
299 * don't try to be clever and just set it unconditionally.
301 flags
|= PIPE_CONTROL_CS_STALL
;
303 /* Just flush everything. Experiments have shown that reducing the
304 * number of bits based on the write domains has little performance
307 if (mode
& EMIT_FLUSH
) {
308 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
309 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
310 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
311 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
313 if (mode
& EMIT_INVALIDATE
) {
314 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
315 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
316 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
317 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
318 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
319 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
320 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
322 * TLB invalidate requires a post-sync write.
324 flags
|= PIPE_CONTROL_QW_WRITE
;
325 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
327 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
329 /* Workaround: we must issue a pipe_control with CS-stall bit
330 * set before a pipe_control command that has the state cache
331 * invalidate bit set. */
332 gen7_render_ring_cs_stall_wa(req
);
335 ret
= intel_ring_begin(req
, 4);
339 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
340 intel_ring_emit(ring
, flags
);
341 intel_ring_emit(ring
, scratch_addr
);
342 intel_ring_emit(ring
, 0);
343 intel_ring_advance(ring
);
349 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
350 u32 flags
, u32 scratch_addr
)
352 struct intel_ring
*ring
= req
->ring
;
355 ret
= intel_ring_begin(req
, 6);
359 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
360 intel_ring_emit(ring
, flags
);
361 intel_ring_emit(ring
, scratch_addr
);
362 intel_ring_emit(ring
, 0);
363 intel_ring_emit(ring
, 0);
364 intel_ring_emit(ring
, 0);
365 intel_ring_advance(ring
);
371 gen8_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
373 u32 scratch_addr
= req
->engine
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
377 flags
|= PIPE_CONTROL_CS_STALL
;
379 if (mode
& EMIT_FLUSH
) {
380 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
381 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
382 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
383 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
385 if (mode
& EMIT_INVALIDATE
) {
386 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
387 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
388 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
389 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
390 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
391 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
392 flags
|= PIPE_CONTROL_QW_WRITE
;
393 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
395 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
396 ret
= gen8_emit_pipe_control(req
,
397 PIPE_CONTROL_CS_STALL
|
398 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
404 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
407 u64
intel_engine_get_active_head(struct intel_engine_cs
*engine
)
409 struct drm_i915_private
*dev_priv
= engine
->i915
;
412 if (INTEL_GEN(dev_priv
) >= 8)
413 acthd
= I915_READ64_2x32(RING_ACTHD(engine
->mmio_base
),
414 RING_ACTHD_UDW(engine
->mmio_base
));
415 else if (INTEL_GEN(dev_priv
) >= 4)
416 acthd
= I915_READ(RING_ACTHD(engine
->mmio_base
));
418 acthd
= I915_READ(ACTHD
);
423 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
425 struct drm_i915_private
*dev_priv
= engine
->i915
;
428 addr
= dev_priv
->status_page_dmah
->busaddr
;
429 if (INTEL_GEN(dev_priv
) >= 4)
430 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
431 I915_WRITE(HWS_PGA
, addr
);
434 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
436 struct drm_i915_private
*dev_priv
= engine
->i915
;
439 /* The ring status page addresses are no longer next to the rest of
440 * the ring registers as of gen7.
442 if (IS_GEN7(dev_priv
)) {
443 switch (engine
->id
) {
445 mmio
= RENDER_HWS_PGA_GEN7
;
448 mmio
= BLT_HWS_PGA_GEN7
;
451 * VCS2 actually doesn't exist on Gen7. Only shut up
452 * gcc switch check warning
456 mmio
= BSD_HWS_PGA_GEN7
;
459 mmio
= VEBOX_HWS_PGA_GEN7
;
462 } else if (IS_GEN6(dev_priv
)) {
463 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
465 /* XXX: gen8 returns to sanity */
466 mmio
= RING_HWS_PGA(engine
->mmio_base
);
469 I915_WRITE(mmio
, engine
->status_page
.ggtt_offset
);
473 * Flush the TLB for this page
475 * FIXME: These two bits have disappeared on gen8, so a question
476 * arises: do we still need this and if so how should we go about
477 * invalidating the TLB?
479 if (IS_GEN(dev_priv
, 6, 7)) {
480 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
482 /* ring should be idle before issuing a sync flush*/
483 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
486 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
488 if (intel_wait_for_register(dev_priv
,
489 reg
, INSTPM_SYNC_FLUSH
, 0,
491 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
496 static bool stop_ring(struct intel_engine_cs
*engine
)
498 struct drm_i915_private
*dev_priv
= engine
->i915
;
500 if (!IS_GEN2(dev_priv
)) {
501 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
502 if (intel_wait_for_register(dev_priv
,
503 RING_MI_MODE(engine
->mmio_base
),
507 DRM_ERROR("%s : timed out trying to stop ring\n",
509 /* Sometimes we observe that the idle flag is not
510 * set even though the ring is empty. So double
511 * check before giving up.
513 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
518 I915_WRITE_CTL(engine
, 0);
519 I915_WRITE_HEAD(engine
, 0);
520 I915_WRITE_TAIL(engine
, 0);
522 if (!IS_GEN2(dev_priv
)) {
523 (void)I915_READ_CTL(engine
);
524 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
527 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
530 static int init_ring_common(struct intel_engine_cs
*engine
)
532 struct drm_i915_private
*dev_priv
= engine
->i915
;
533 struct intel_ring
*ring
= engine
->buffer
;
536 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
538 if (!stop_ring(engine
)) {
539 /* G45 ring initialization often fails to reset head to zero */
540 DRM_DEBUG_KMS("%s head not reset to zero "
541 "ctl %08x head %08x tail %08x start %08x\n",
543 I915_READ_CTL(engine
),
544 I915_READ_HEAD(engine
),
545 I915_READ_TAIL(engine
),
546 I915_READ_START(engine
));
548 if (!stop_ring(engine
)) {
549 DRM_ERROR("failed to set %s head to zero "
550 "ctl %08x head %08x tail %08x start %08x\n",
552 I915_READ_CTL(engine
),
553 I915_READ_HEAD(engine
),
554 I915_READ_TAIL(engine
),
555 I915_READ_START(engine
));
561 if (I915_NEED_GFX_HWS(dev_priv
))
562 intel_ring_setup_status_page(engine
);
564 ring_setup_phys_status_page(engine
);
566 /* Enforce ordering by reading HEAD register back */
567 I915_READ_HEAD(engine
);
569 /* Initialize the ring. This must happen _after_ we've cleared the ring
570 * registers with the above sequence (the readback of the HEAD registers
571 * also enforces ordering), otherwise the hw might lose the new ring
572 * register values. */
573 I915_WRITE_START(engine
, ring
->vma
->node
.start
);
575 /* WaClearRingBufHeadRegAtInit:ctg,elk */
576 if (I915_READ_HEAD(engine
))
577 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
578 engine
->name
, I915_READ_HEAD(engine
));
579 I915_WRITE_HEAD(engine
, 0);
580 (void)I915_READ_HEAD(engine
);
582 I915_WRITE_CTL(engine
,
583 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
586 /* If the head is still not zero, the ring is dead */
587 if (wait_for((I915_READ_CTL(engine
) & RING_VALID
) != 0 &&
588 I915_READ_START(engine
) == ring
->vma
->node
.start
&&
589 (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0, 50)) {
590 DRM_ERROR("%s initialization failed "
591 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08llx]\n",
593 I915_READ_CTL(engine
),
594 I915_READ_CTL(engine
) & RING_VALID
,
595 I915_READ_HEAD(engine
), I915_READ_TAIL(engine
),
596 I915_READ_START(engine
),
597 ring
->vma
->node
.start
);
602 ring
->last_retired_head
= -1;
603 ring
->head
= I915_READ_HEAD(engine
);
604 ring
->tail
= I915_READ_TAIL(engine
) & TAIL_ADDR
;
605 intel_ring_update_space(ring
);
607 intel_engine_init_hangcheck(engine
);
610 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
615 void intel_fini_pipe_control(struct intel_engine_cs
*engine
)
617 if (engine
->scratch
.obj
== NULL
)
620 i915_gem_object_ggtt_unpin(engine
->scratch
.obj
);
621 i915_gem_object_put(engine
->scratch
.obj
);
622 engine
->scratch
.obj
= NULL
;
625 int intel_init_pipe_control(struct intel_engine_cs
*engine
, int size
)
627 struct drm_i915_gem_object
*obj
;
630 WARN_ON(engine
->scratch
.obj
);
632 obj
= i915_gem_object_create_stolen(&engine
->i915
->drm
, size
);
634 obj
= i915_gem_object_create(&engine
->i915
->drm
, size
);
636 DRM_ERROR("Failed to allocate scratch page\n");
641 ret
= i915_gem_object_ggtt_pin(obj
, NULL
, 0, 4096, PIN_HIGH
);
645 engine
->scratch
.obj
= obj
;
646 engine
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
647 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
648 engine
->name
, engine
->scratch
.gtt_offset
);
652 i915_gem_object_put(engine
->scratch
.obj
);
657 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
659 struct intel_ring
*ring
= req
->ring
;
660 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
666 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
670 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
674 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
675 for (i
= 0; i
< w
->count
; i
++) {
676 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
677 intel_ring_emit(ring
, w
->reg
[i
].value
);
679 intel_ring_emit(ring
, MI_NOOP
);
681 intel_ring_advance(ring
);
683 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
687 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
692 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
696 ret
= intel_ring_workarounds_emit(req
);
700 ret
= i915_gem_render_state_init(req
);
707 static int wa_add(struct drm_i915_private
*dev_priv
,
709 const u32 mask
, const u32 val
)
711 const u32 idx
= dev_priv
->workarounds
.count
;
713 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
716 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
717 dev_priv
->workarounds
.reg
[idx
].value
= val
;
718 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
720 dev_priv
->workarounds
.count
++;
725 #define WA_REG(addr, mask, val) do { \
726 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
731 #define WA_SET_BIT_MASKED(addr, mask) \
732 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
734 #define WA_CLR_BIT_MASKED(addr, mask) \
735 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
737 #define WA_SET_FIELD_MASKED(addr, mask, value) \
738 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
740 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
741 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
743 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
745 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
748 struct drm_i915_private
*dev_priv
= engine
->i915
;
749 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
750 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
752 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
755 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
756 i915_mmio_reg_offset(reg
));
757 wa
->hw_whitelist_count
[engine
->id
]++;
762 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
764 struct drm_i915_private
*dev_priv
= engine
->i915
;
766 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
768 /* WaDisableAsyncFlipPerfMode:bdw,chv */
769 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
771 /* WaDisablePartialInstShootdown:bdw,chv */
772 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
773 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
775 /* Use Force Non-Coherent whenever executing a 3D context. This is a
776 * workaround for for a possible hang in the unlikely event a TLB
777 * invalidation occurs during a PSD flush.
779 /* WaForceEnableNonCoherent:bdw,chv */
780 /* WaHdcDisableFetchWhenMasked:bdw,chv */
781 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
782 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
783 HDC_FORCE_NON_COHERENT
);
785 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
786 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
787 * polygons in the same 8x4 pixel/sample area to be processed without
788 * stalling waiting for the earlier ones to write to Hierarchical Z
791 * This optimization is off by default for BDW and CHV; turn it on.
793 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
795 /* Wa4x4STCOptimizationDisable:bdw,chv */
796 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
799 * BSpec recommends 8x4 when MSAA is used,
800 * however in practice 16x4 seems fastest.
802 * Note that PS/WM thread counts depend on the WIZ hashing
803 * disable bit, which we don't touch here, but it's good
804 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
806 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
807 GEN6_WIZ_HASHING_MASK
,
808 GEN6_WIZ_HASHING_16x4
);
813 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
815 struct drm_i915_private
*dev_priv
= engine
->i915
;
818 ret
= gen8_init_workarounds(engine
);
822 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
823 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
825 /* WaDisableDopClockGating:bdw */
826 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
827 DOP_CLOCK_GATING_DISABLE
);
829 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
830 GEN8_SAMPLER_POWER_BYPASS_DIS
);
832 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
835 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
836 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
841 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
843 struct drm_i915_private
*dev_priv
= engine
->i915
;
846 ret
= gen8_init_workarounds(engine
);
850 /* WaDisableThreadStallDopClockGating:chv */
851 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
853 /* Improve HiZ throughput on CHV. */
854 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
859 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
861 struct drm_i915_private
*dev_priv
= engine
->i915
;
864 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
865 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
867 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
868 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
869 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
871 /* WaDisableKillLogic:bxt,skl,kbl */
872 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
875 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
876 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
877 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
878 FLOW_CONTROL_ENABLE
|
879 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
881 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
882 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
883 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
885 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
886 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
887 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
888 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
889 GEN9_DG_MIRROR_FIX_ENABLE
);
891 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
892 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_B0
) ||
893 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
894 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
895 GEN9_RHWO_OPTIMIZATION_DISABLE
);
897 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
898 * but we do that in per ctx batchbuffer as there is an issue
899 * with this register not getting restored on ctx restore
903 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
904 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
905 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
906 GEN9_ENABLE_YV12_BUGFIX
|
907 GEN9_ENABLE_GPGPU_PREEMPTION
);
909 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
910 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
911 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
912 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
914 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
915 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
916 GEN9_CCS_TLB_PREFETCH_ENABLE
);
918 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
919 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_C0
) ||
920 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
921 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
922 PIXEL_MASK_CAMMING_DISABLE
);
924 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
925 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
926 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
927 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
929 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
930 * both tied to WaForceContextSaveRestoreNonCoherent
931 * in some hsds for skl. We keep the tie for all gen9. The
932 * documentation is a bit hazy and so we want to get common behaviour,
933 * even though there is no clear evidence we would need both on kbl/bxt.
934 * This area has been source of system hangs so we play it safe
935 * and mimic the skl regardless of what bspec says.
937 * Use Force Non-Coherent whenever executing a 3D context. This
938 * is a workaround for a possible hang in the unlikely event
939 * a TLB invalidation occurs during a PSD flush.
942 /* WaForceEnableNonCoherent:skl,bxt,kbl */
943 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
944 HDC_FORCE_NON_COHERENT
);
946 /* WaDisableHDCInvalidation:skl,bxt,kbl */
947 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
948 BDW_DISABLE_HDC_INVALIDATION
);
950 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
951 if (IS_SKYLAKE(dev_priv
) ||
952 IS_KABYLAKE(dev_priv
) ||
953 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
954 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
955 GEN8_SAMPLER_POWER_BYPASS_DIS
);
957 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
958 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
960 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
961 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
962 GEN8_LQSC_FLUSH_COHERENT_LINES
));
964 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
965 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
969 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
970 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
974 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
975 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
982 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
984 struct drm_i915_private
*dev_priv
= engine
->i915
;
985 u8 vals
[3] = { 0, 0, 0 };
988 for (i
= 0; i
< 3; i
++) {
992 * Only consider slices where one, and only one, subslice has 7
995 if (!is_power_of_2(dev_priv
->info
.subslice_7eu
[i
]))
999 * subslice_7eu[i] != 0 (because of the check above) and
1000 * ss_max == 4 (maximum number of subslices possible per slice)
1004 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1008 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1011 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1013 GEN9_IZ_HASHING_MASK(2) |
1014 GEN9_IZ_HASHING_MASK(1) |
1015 GEN9_IZ_HASHING_MASK(0),
1016 GEN9_IZ_HASHING(2, vals
[2]) |
1017 GEN9_IZ_HASHING(1, vals
[1]) |
1018 GEN9_IZ_HASHING(0, vals
[0]));
1023 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
1025 struct drm_i915_private
*dev_priv
= engine
->i915
;
1028 ret
= gen9_init_workarounds(engine
);
1033 * Actual WA is to disable percontext preemption granularity control
1034 * until D0 which is the default case so this is equivalent to
1035 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1037 if (IS_SKL_REVID(dev_priv
, SKL_REVID_E0
, REVID_FOREVER
)) {
1038 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
1039 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
1042 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
)) {
1043 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1044 I915_WRITE(FF_SLICE_CS_CHICKEN2
,
1045 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE
));
1048 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1049 * involving this register should also be added to WA batch as required.
1051 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_E0
))
1052 /* WaDisableLSQCROPERFforOCL:skl */
1053 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1054 GEN8_LQSC_RO_PERF_DIS
);
1056 /* WaEnableGapsTsvCreditFix:skl */
1057 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, REVID_FOREVER
)) {
1058 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1059 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1062 /* WaDisablePowerCompilerClockGating:skl */
1063 if (IS_SKL_REVID(dev_priv
, SKL_REVID_B0
, SKL_REVID_B0
))
1064 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1065 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1067 /* WaBarrierPerformanceFixDisable:skl */
1068 if (IS_SKL_REVID(dev_priv
, SKL_REVID_C0
, SKL_REVID_D0
))
1069 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1070 HDC_FENCE_DEST_SLM_DISABLE
|
1071 HDC_BARRIER_PERFORMANCE_DISABLE
);
1073 /* WaDisableSbeCacheDispatchPortSharing:skl */
1074 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_F0
))
1076 GEN7_HALF_SLICE_CHICKEN1
,
1077 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1079 /* WaDisableGafsUnitClkGating:skl */
1080 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1082 /* WaInPlaceDecompressionHang:skl */
1083 if (IS_SKL_REVID(dev_priv
, SKL_REVID_H0
, REVID_FOREVER
))
1084 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1085 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1087 /* WaDisableLSQCROPERFforOCL:skl */
1088 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1092 return skl_tune_iz_hashing(engine
);
1095 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1097 struct drm_i915_private
*dev_priv
= engine
->i915
;
1100 ret
= gen9_init_workarounds(engine
);
1104 /* WaStoreMultiplePTEenable:bxt */
1105 /* This is a requirement according to Hardware specification */
1106 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1107 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1109 /* WaSetClckGatingDisableMedia:bxt */
1110 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1111 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1112 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1115 /* WaDisableThreadStallDopClockGating:bxt */
1116 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1117 STALL_DOP_GATING_DISABLE
);
1119 /* WaDisablePooledEuLoadBalancingFix:bxt */
1120 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1121 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2
,
1122 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
);
1125 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1126 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1128 GEN7_HALF_SLICE_CHICKEN1
,
1129 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1132 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1133 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1134 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1135 /* WaDisableLSQCROPERFforOCL:bxt */
1136 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1137 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1141 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1146 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1147 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
1148 I915_WRITE(GEN8_L3SQCREG1
, L3_GENERAL_PRIO_CREDITS(62) |
1149 L3_HIGH_PRIO_CREDITS(2));
1151 /* WaToEnableHwFixForPushConstHWBug:bxt */
1152 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1153 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1154 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1156 /* WaInPlaceDecompressionHang:bxt */
1157 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1158 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1159 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1164 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1166 struct drm_i915_private
*dev_priv
= engine
->i915
;
1169 ret
= gen9_init_workarounds(engine
);
1173 /* WaEnableGapsTsvCreditFix:kbl */
1174 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1175 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1177 /* WaDisableDynamicCreditSharing:kbl */
1178 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1179 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1180 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1182 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1183 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1184 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1185 HDC_FENCE_DEST_SLM_DISABLE
);
1187 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1188 * involving this register should also be added to WA batch as required.
1190 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1191 /* WaDisableLSQCROPERFforOCL:kbl */
1192 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1193 GEN8_LQSC_RO_PERF_DIS
);
1195 /* WaToEnableHwFixForPushConstHWBug:kbl */
1196 if (IS_KBL_REVID(dev_priv
, KBL_REVID_C0
, REVID_FOREVER
))
1197 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1198 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1200 /* WaDisableGafsUnitClkGating:kbl */
1201 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1203 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1205 GEN7_HALF_SLICE_CHICKEN1
,
1206 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1208 /* WaInPlaceDecompressionHang:kbl */
1209 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1210 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1212 /* WaDisableLSQCROPERFforOCL:kbl */
1213 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1220 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1222 struct drm_i915_private
*dev_priv
= engine
->i915
;
1224 WARN_ON(engine
->id
!= RCS
);
1226 dev_priv
->workarounds
.count
= 0;
1227 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1229 if (IS_BROADWELL(dev_priv
))
1230 return bdw_init_workarounds(engine
);
1232 if (IS_CHERRYVIEW(dev_priv
))
1233 return chv_init_workarounds(engine
);
1235 if (IS_SKYLAKE(dev_priv
))
1236 return skl_init_workarounds(engine
);
1238 if (IS_BROXTON(dev_priv
))
1239 return bxt_init_workarounds(engine
);
1241 if (IS_KABYLAKE(dev_priv
))
1242 return kbl_init_workarounds(engine
);
1247 static int init_render_ring(struct intel_engine_cs
*engine
)
1249 struct drm_i915_private
*dev_priv
= engine
->i915
;
1250 int ret
= init_ring_common(engine
);
1254 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1255 if (IS_GEN(dev_priv
, 4, 6))
1256 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1258 /* We need to disable the AsyncFlip performance optimisations in order
1259 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1260 * programmed to '1' on all products.
1262 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1264 if (IS_GEN(dev_priv
, 6, 7))
1265 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1267 /* Required for the hardware to program scanline values for waiting */
1268 /* WaEnableFlushTlbInvalidationMode:snb */
1269 if (IS_GEN6(dev_priv
))
1270 I915_WRITE(GFX_MODE
,
1271 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1273 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1274 if (IS_GEN7(dev_priv
))
1275 I915_WRITE(GFX_MODE_GEN7
,
1276 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1277 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1279 if (IS_GEN6(dev_priv
)) {
1280 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1281 * "If this bit is set, STCunit will have LRA as replacement
1282 * policy. [...] This bit must be reset. LRA replacement
1283 * policy is not supported."
1285 I915_WRITE(CACHE_MODE_0
,
1286 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1289 if (IS_GEN(dev_priv
, 6, 7))
1290 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1292 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1293 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1295 return init_workarounds_ring(engine
);
1298 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1300 struct drm_i915_private
*dev_priv
= engine
->i915
;
1302 if (dev_priv
->semaphore_obj
) {
1303 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1304 i915_gem_object_put(dev_priv
->semaphore_obj
);
1305 dev_priv
->semaphore_obj
= NULL
;
1308 intel_fini_pipe_control(engine
);
1311 static int gen8_rcs_signal(struct drm_i915_gem_request
*req
)
1313 struct intel_ring
*ring
= req
->ring
;
1314 struct drm_i915_private
*dev_priv
= req
->i915
;
1315 struct intel_engine_cs
*waiter
;
1316 enum intel_engine_id id
;
1319 num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
1320 ret
= intel_ring_begin(req
, (num_rings
-1) * 8);
1324 for_each_engine_id(waiter
, dev_priv
, id
) {
1325 u64 gtt_offset
= req
->engine
->semaphore
.signal_ggtt
[id
];
1326 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1329 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1330 intel_ring_emit(ring
,
1331 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1332 PIPE_CONTROL_QW_WRITE
|
1333 PIPE_CONTROL_CS_STALL
);
1334 intel_ring_emit(ring
, lower_32_bits(gtt_offset
));
1335 intel_ring_emit(ring
, upper_32_bits(gtt_offset
));
1336 intel_ring_emit(ring
, req
->fence
.seqno
);
1337 intel_ring_emit(ring
, 0);
1338 intel_ring_emit(ring
,
1339 MI_SEMAPHORE_SIGNAL
|
1340 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1341 intel_ring_emit(ring
, 0);
1343 intel_ring_advance(ring
);
1348 static int gen8_xcs_signal(struct drm_i915_gem_request
*req
)
1350 struct intel_ring
*ring
= req
->ring
;
1351 struct drm_i915_private
*dev_priv
= req
->i915
;
1352 struct intel_engine_cs
*waiter
;
1353 enum intel_engine_id id
;
1356 num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
1357 ret
= intel_ring_begin(req
, (num_rings
-1) * 6);
1361 for_each_engine_id(waiter
, dev_priv
, id
) {
1362 u64 gtt_offset
= req
->engine
->semaphore
.signal_ggtt
[id
];
1363 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1366 intel_ring_emit(ring
,
1367 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1368 intel_ring_emit(ring
,
1369 lower_32_bits(gtt_offset
) |
1370 MI_FLUSH_DW_USE_GTT
);
1371 intel_ring_emit(ring
, upper_32_bits(gtt_offset
));
1372 intel_ring_emit(ring
, req
->fence
.seqno
);
1373 intel_ring_emit(ring
,
1374 MI_SEMAPHORE_SIGNAL
|
1375 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1376 intel_ring_emit(ring
, 0);
1378 intel_ring_advance(ring
);
1383 static int gen6_signal(struct drm_i915_gem_request
*req
)
1385 struct intel_ring
*ring
= req
->ring
;
1386 struct drm_i915_private
*dev_priv
= req
->i915
;
1387 struct intel_engine_cs
*useless
;
1388 enum intel_engine_id id
;
1391 num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
1392 ret
= intel_ring_begin(req
, round_up((num_rings
-1) * 3, 2));
1396 for_each_engine_id(useless
, dev_priv
, id
) {
1397 i915_reg_t mbox_reg
= req
->engine
->semaphore
.mbox
.signal
[id
];
1399 if (i915_mmio_reg_valid(mbox_reg
)) {
1400 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1401 intel_ring_emit_reg(ring
, mbox_reg
);
1402 intel_ring_emit(ring
, req
->fence
.seqno
);
1406 /* If num_dwords was rounded, make sure the tail pointer is correct */
1407 if (num_rings
% 2 == 0)
1408 intel_ring_emit(ring
, MI_NOOP
);
1409 intel_ring_advance(ring
);
1414 static void i9xx_submit_request(struct drm_i915_gem_request
*request
)
1416 struct drm_i915_private
*dev_priv
= request
->i915
;
1418 I915_WRITE_TAIL(request
->engine
,
1419 intel_ring_offset(request
->ring
, request
->tail
));
1422 static int i9xx_emit_request(struct drm_i915_gem_request
*req
)
1424 struct intel_ring
*ring
= req
->ring
;
1427 ret
= intel_ring_begin(req
, 4);
1431 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1432 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1433 intel_ring_emit(ring
, req
->fence
.seqno
);
1434 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1435 intel_ring_advance(ring
);
1437 req
->tail
= ring
->tail
;
1443 * gen6_sema_emit_request - Update the semaphore mailbox registers
1445 * @request - request to write to the ring
1447 * Update the mailbox registers in the *other* rings with the current seqno.
1448 * This acts like a signal in the canonical semaphore.
1450 static int gen6_sema_emit_request(struct drm_i915_gem_request
*req
)
1454 ret
= req
->engine
->semaphore
.signal(req
);
1458 return i9xx_emit_request(req
);
1461 static int gen8_render_emit_request(struct drm_i915_gem_request
*req
)
1463 struct intel_engine_cs
*engine
= req
->engine
;
1464 struct intel_ring
*ring
= req
->ring
;
1467 if (engine
->semaphore
.signal
) {
1468 ret
= engine
->semaphore
.signal(req
);
1473 ret
= intel_ring_begin(req
, 8);
1477 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1478 intel_ring_emit(ring
, (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1479 PIPE_CONTROL_CS_STALL
|
1480 PIPE_CONTROL_QW_WRITE
));
1481 intel_ring_emit(ring
, intel_hws_seqno_address(engine
));
1482 intel_ring_emit(ring
, 0);
1483 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1484 /* We're thrashing one dword of HWS. */
1485 intel_ring_emit(ring
, 0);
1486 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1487 intel_ring_emit(ring
, MI_NOOP
);
1488 intel_ring_advance(ring
);
1490 req
->tail
= ring
->tail
;
1496 * intel_ring_sync - sync the waiter to the signaller on seqno
1498 * @waiter - ring that is waiting
1499 * @signaller - ring which has, or will signal
1500 * @seqno - seqno which the waiter will block on
1504 gen8_ring_sync_to(struct drm_i915_gem_request
*req
,
1505 struct drm_i915_gem_request
*signal
)
1507 struct intel_ring
*ring
= req
->ring
;
1508 struct drm_i915_private
*dev_priv
= req
->i915
;
1509 u64 offset
= GEN8_WAIT_OFFSET(req
->engine
, signal
->engine
->id
);
1510 struct i915_hw_ppgtt
*ppgtt
;
1513 ret
= intel_ring_begin(req
, 4);
1517 intel_ring_emit(ring
,
1519 MI_SEMAPHORE_GLOBAL_GTT
|
1520 MI_SEMAPHORE_SAD_GTE_SDD
);
1521 intel_ring_emit(ring
, signal
->fence
.seqno
);
1522 intel_ring_emit(ring
, lower_32_bits(offset
));
1523 intel_ring_emit(ring
, upper_32_bits(offset
));
1524 intel_ring_advance(ring
);
1526 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1527 * pagetables and we must reload them before executing the batch.
1528 * We do this on the i915_switch_context() following the wait and
1529 * before the dispatch.
1531 ppgtt
= req
->ctx
->ppgtt
;
1532 if (ppgtt
&& req
->engine
->id
!= RCS
)
1533 ppgtt
->pd_dirty_rings
|= intel_engine_flag(req
->engine
);
1538 gen6_ring_sync_to(struct drm_i915_gem_request
*req
,
1539 struct drm_i915_gem_request
*signal
)
1541 struct intel_ring
*ring
= req
->ring
;
1542 u32 dw1
= MI_SEMAPHORE_MBOX
|
1543 MI_SEMAPHORE_COMPARE
|
1544 MI_SEMAPHORE_REGISTER
;
1545 u32 wait_mbox
= signal
->engine
->semaphore
.mbox
.wait
[req
->engine
->id
];
1548 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1550 ret
= intel_ring_begin(req
, 4);
1554 intel_ring_emit(ring
, dw1
| wait_mbox
);
1555 /* Throughout all of the GEM code, seqno passed implies our current
1556 * seqno is >= the last seqno executed. However for hardware the
1557 * comparison is strictly greater than.
1559 intel_ring_emit(ring
, signal
->fence
.seqno
- 1);
1560 intel_ring_emit(ring
, 0);
1561 intel_ring_emit(ring
, MI_NOOP
);
1562 intel_ring_advance(ring
);
1568 gen5_seqno_barrier(struct intel_engine_cs
*engine
)
1570 /* MI_STORE are internally buffered by the GPU and not flushed
1571 * either by MI_FLUSH or SyncFlush or any other combination of
1574 * "Only the submission of the store operation is guaranteed.
1575 * The write result will be complete (coherent) some time later
1576 * (this is practically a finite period but there is no guaranteed
1579 * Empirically, we observe that we need a delay of at least 75us to
1580 * be sure that the seqno write is visible by the CPU.
1582 usleep_range(125, 250);
1586 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1588 struct drm_i915_private
*dev_priv
= engine
->i915
;
1590 /* Workaround to force correct ordering between irq and seqno writes on
1591 * ivb (and maybe also on snb) by reading from a CS register (like
1592 * ACTHD) before reading the status page.
1594 * Note that this effectively stalls the read by the time it takes to
1595 * do a memory transaction, which more or less ensures that the write
1596 * from the GPU has sufficient time to invalidate the CPU cacheline.
1597 * Alternatively we could delay the interrupt from the CS ring to give
1598 * the write time to land, but that would incur a delay after every
1599 * batch i.e. much more frequent than a delay when waiting for the
1600 * interrupt (with the same net latency).
1602 * Also note that to prevent whole machine hangs on gen7, we have to
1603 * take the spinlock to guard against concurrent cacheline access.
1605 spin_lock_irq(&dev_priv
->uncore
.lock
);
1606 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1607 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1611 gen5_irq_enable(struct intel_engine_cs
*engine
)
1613 gen5_enable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1617 gen5_irq_disable(struct intel_engine_cs
*engine
)
1619 gen5_disable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1623 i9xx_irq_enable(struct intel_engine_cs
*engine
)
1625 struct drm_i915_private
*dev_priv
= engine
->i915
;
1627 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1628 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1629 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1633 i9xx_irq_disable(struct intel_engine_cs
*engine
)
1635 struct drm_i915_private
*dev_priv
= engine
->i915
;
1637 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1638 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1642 i8xx_irq_enable(struct intel_engine_cs
*engine
)
1644 struct drm_i915_private
*dev_priv
= engine
->i915
;
1646 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1647 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1648 POSTING_READ16(RING_IMR(engine
->mmio_base
));
1652 i8xx_irq_disable(struct intel_engine_cs
*engine
)
1654 struct drm_i915_private
*dev_priv
= engine
->i915
;
1656 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1657 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1661 bsd_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
1663 struct intel_ring
*ring
= req
->ring
;
1666 ret
= intel_ring_begin(req
, 2);
1670 intel_ring_emit(ring
, MI_FLUSH
);
1671 intel_ring_emit(ring
, MI_NOOP
);
1672 intel_ring_advance(ring
);
1677 gen6_irq_enable(struct intel_engine_cs
*engine
)
1679 struct drm_i915_private
*dev_priv
= engine
->i915
;
1681 I915_WRITE_IMR(engine
,
1682 ~(engine
->irq_enable_mask
|
1683 engine
->irq_keep_mask
));
1684 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1688 gen6_irq_disable(struct intel_engine_cs
*engine
)
1690 struct drm_i915_private
*dev_priv
= engine
->i915
;
1692 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1693 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1697 hsw_vebox_irq_enable(struct intel_engine_cs
*engine
)
1699 struct drm_i915_private
*dev_priv
= engine
->i915
;
1701 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1702 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1706 hsw_vebox_irq_disable(struct intel_engine_cs
*engine
)
1708 struct drm_i915_private
*dev_priv
= engine
->i915
;
1710 I915_WRITE_IMR(engine
, ~0);
1711 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1715 gen8_irq_enable(struct intel_engine_cs
*engine
)
1717 struct drm_i915_private
*dev_priv
= engine
->i915
;
1719 I915_WRITE_IMR(engine
,
1720 ~(engine
->irq_enable_mask
|
1721 engine
->irq_keep_mask
));
1722 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1726 gen8_irq_disable(struct intel_engine_cs
*engine
)
1728 struct drm_i915_private
*dev_priv
= engine
->i915
;
1730 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1734 i965_emit_bb_start(struct drm_i915_gem_request
*req
,
1735 u64 offset
, u32 length
,
1736 unsigned int dispatch_flags
)
1738 struct intel_ring
*ring
= req
->ring
;
1741 ret
= intel_ring_begin(req
, 2);
1745 intel_ring_emit(ring
,
1746 MI_BATCH_BUFFER_START
|
1748 (dispatch_flags
& I915_DISPATCH_SECURE
?
1749 0 : MI_BATCH_NON_SECURE_I965
));
1750 intel_ring_emit(ring
, offset
);
1751 intel_ring_advance(ring
);
1756 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1757 #define I830_BATCH_LIMIT (256*1024)
1758 #define I830_TLB_ENTRIES (2)
1759 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1761 i830_emit_bb_start(struct drm_i915_gem_request
*req
,
1762 u64 offset
, u32 len
,
1763 unsigned int dispatch_flags
)
1765 struct intel_ring
*ring
= req
->ring
;
1766 u32 cs_offset
= req
->engine
->scratch
.gtt_offset
;
1769 ret
= intel_ring_begin(req
, 6);
1773 /* Evict the invalid PTE TLBs */
1774 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1775 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1776 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1777 intel_ring_emit(ring
, cs_offset
);
1778 intel_ring_emit(ring
, 0xdeadbeef);
1779 intel_ring_emit(ring
, MI_NOOP
);
1780 intel_ring_advance(ring
);
1782 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1783 if (len
> I830_BATCH_LIMIT
)
1786 ret
= intel_ring_begin(req
, 6 + 2);
1790 /* Blit the batch (which has now all relocs applied) to the
1791 * stable batch scratch bo area (so that the CS never
1792 * stumbles over its tlb invalidation bug) ...
1794 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1795 intel_ring_emit(ring
,
1796 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1797 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1798 intel_ring_emit(ring
, cs_offset
);
1799 intel_ring_emit(ring
, 4096);
1800 intel_ring_emit(ring
, offset
);
1802 intel_ring_emit(ring
, MI_FLUSH
);
1803 intel_ring_emit(ring
, MI_NOOP
);
1804 intel_ring_advance(ring
);
1806 /* ... and execute it. */
1810 ret
= intel_ring_begin(req
, 2);
1814 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1815 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1816 0 : MI_BATCH_NON_SECURE
));
1817 intel_ring_advance(ring
);
1823 i915_emit_bb_start(struct drm_i915_gem_request
*req
,
1824 u64 offset
, u32 len
,
1825 unsigned int dispatch_flags
)
1827 struct intel_ring
*ring
= req
->ring
;
1830 ret
= intel_ring_begin(req
, 2);
1834 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1835 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1836 0 : MI_BATCH_NON_SECURE
));
1837 intel_ring_advance(ring
);
1842 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
1844 struct drm_i915_private
*dev_priv
= engine
->i915
;
1846 if (!dev_priv
->status_page_dmah
)
1849 drm_pci_free(&dev_priv
->drm
, dev_priv
->status_page_dmah
);
1850 engine
->status_page
.page_addr
= NULL
;
1853 static void cleanup_status_page(struct intel_engine_cs
*engine
)
1855 struct i915_vma
*vma
;
1857 vma
= fetch_and_zero(&engine
->status_page
.vma
);
1861 i915_vma_unpin(vma
);
1862 i915_gem_object_unpin_map(vma
->obj
);
1866 static int init_status_page(struct intel_engine_cs
*engine
)
1868 struct drm_i915_gem_object
*obj
;
1869 struct i915_vma
*vma
;
1873 obj
= i915_gem_object_create(&engine
->i915
->drm
, 4096);
1875 DRM_ERROR("Failed to allocate status page\n");
1876 return PTR_ERR(obj
);
1879 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1883 vma
= i915_vma_create(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1890 if (!HAS_LLC(engine
->i915
))
1891 /* On g33, we cannot place HWS above 256MiB, so
1892 * restrict its pinning to the low mappable arena.
1893 * Though this restriction is not documented for
1894 * gen4, gen5, or byt, they also behave similarly
1895 * and hang if the HWS is placed at the top of the
1896 * GTT. To generalise, it appears that all !llc
1897 * platforms have issues with us placing the HWS
1898 * above the mappable region (even though we never
1901 flags
|= PIN_MAPPABLE
;
1902 ret
= i915_vma_pin(vma
, 0, 4096, flags
);
1906 engine
->status_page
.vma
= vma
;
1907 engine
->status_page
.ggtt_offset
= vma
->node
.start
;
1908 engine
->status_page
.page_addr
=
1909 i915_gem_object_pin_map(obj
, I915_MAP_WB
);
1911 DRM_DEBUG_DRIVER("%s hws offset: 0x%08llx\n",
1912 engine
->name
, vma
->node
.start
);
1916 i915_gem_object_put(obj
);
1920 static int init_phys_status_page(struct intel_engine_cs
*engine
)
1922 struct drm_i915_private
*dev_priv
= engine
->i915
;
1924 dev_priv
->status_page_dmah
=
1925 drm_pci_alloc(&dev_priv
->drm
, PAGE_SIZE
, PAGE_SIZE
);
1926 if (!dev_priv
->status_page_dmah
)
1929 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1930 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
1935 int intel_ring_pin(struct intel_ring
*ring
)
1937 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1938 unsigned int flags
= PIN_GLOBAL
| PIN_OFFSET_BIAS
| 4096;
1939 struct i915_vma
*vma
= ring
->vma
;
1943 GEM_BUG_ON(ring
->vaddr
);
1945 if (ring
->needs_iomap
)
1946 flags
|= PIN_MAPPABLE
;
1948 if (!(vma
->flags
& I915_VMA_GLOBAL_BIND
)) {
1949 if (flags
& PIN_MAPPABLE
)
1950 ret
= i915_gem_object_set_to_gtt_domain(vma
->obj
, true);
1952 ret
= i915_gem_object_set_to_cpu_domain(vma
->obj
, true);
1957 ret
= i915_vma_pin(vma
, 0, PAGE_SIZE
, flags
);
1961 if (flags
& PIN_MAPPABLE
)
1962 addr
= (void __force
*)i915_vma_pin_iomap(vma
);
1964 addr
= i915_gem_object_pin_map(vma
->obj
, I915_MAP_WB
);
1972 i915_vma_unpin(vma
);
1973 return PTR_ERR(addr
);
1976 void intel_ring_unpin(struct intel_ring
*ring
)
1978 GEM_BUG_ON(!ring
->vma
);
1979 GEM_BUG_ON(!ring
->vaddr
);
1981 if (ring
->needs_iomap
)
1982 i915_vma_unpin_iomap(ring
->vma
);
1984 i915_gem_object_unpin_map(ring
->vma
->obj
);
1987 i915_vma_unpin(ring
->vma
);
1990 static struct i915_vma
*
1991 intel_ring_create_vma(struct drm_i915_private
*dev_priv
, int size
)
1993 struct drm_i915_gem_object
*obj
;
1994 struct i915_vma
*vma
;
1996 obj
= ERR_PTR(-ENODEV
);
1997 if (!HAS_LLC(dev_priv
))
1998 obj
= i915_gem_object_create_stolen(&dev_priv
->drm
, size
);
2000 obj
= i915_gem_object_create(&dev_priv
->drm
, size
);
2002 return ERR_CAST(obj
);
2004 /* mark ring buffers as read-only from GPU side by default */
2007 vma
= i915_vma_create(obj
, &dev_priv
->ggtt
.base
, NULL
);
2014 i915_gem_object_put(obj
);
2019 intel_engine_create_ring(struct intel_engine_cs
*engine
, int size
)
2021 struct intel_ring
*ring
;
2022 struct i915_vma
*vma
;
2024 GEM_BUG_ON(!is_power_of_2(size
));
2026 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
2028 return ERR_PTR(-ENOMEM
);
2030 ring
->engine
= engine
;
2032 INIT_LIST_HEAD(&ring
->request_list
);
2035 /* Workaround an erratum on the i830 which causes a hang if
2036 * the TAIL pointer points to within the last 2 cachelines
2039 ring
->effective_size
= size
;
2040 if (IS_I830(engine
->i915
) || IS_845G(engine
->i915
))
2041 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
2043 ring
->last_retired_head
= -1;
2044 intel_ring_update_space(ring
);
2046 vma
= intel_ring_create_vma(engine
->i915
, size
);
2049 return ERR_CAST(vma
);
2052 if (!HAS_LLC(engine
->i915
) || vma
->obj
->stolen
)
2053 ring
->needs_iomap
= true;
2055 list_add(&ring
->link
, &engine
->buffers
);
2060 intel_ring_free(struct intel_ring
*ring
)
2062 i915_vma_put(ring
->vma
);
2063 list_del(&ring
->link
);
2067 static int intel_ring_context_pin(struct i915_gem_context
*ctx
,
2068 struct intel_engine_cs
*engine
)
2070 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2073 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
2075 if (ce
->pin_count
++)
2079 ret
= i915_gem_object_set_to_gtt_domain(ce
->state
->obj
, false);
2083 ret
= i915_vma_pin(ce
->state
, 0, ctx
->ggtt_alignment
,
2084 PIN_GLOBAL
| PIN_HIGH
);
2089 /* The kernel context is only used as a placeholder for flushing the
2090 * active context. It is never used for submitting user rendering and
2091 * as such never requires the golden render context, and so we can skip
2092 * emitting it when we switch to the kernel context. This is required
2093 * as during eviction we cannot allocate and pin the renderstate in
2094 * order to initialise the context.
2096 if (ctx
== ctx
->i915
->kernel_context
)
2097 ce
->initialised
= true;
2099 i915_gem_context_get(ctx
);
2107 static void intel_ring_context_unpin(struct i915_gem_context
*ctx
,
2108 struct intel_engine_cs
*engine
)
2110 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2112 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
2114 if (--ce
->pin_count
)
2118 i915_vma_unpin(ce
->state
);
2120 i915_gem_context_put(ctx
);
2123 static int intel_init_ring_buffer(struct intel_engine_cs
*engine
)
2125 struct drm_i915_private
*dev_priv
= engine
->i915
;
2126 struct intel_ring
*ring
;
2129 WARN_ON(engine
->buffer
);
2131 intel_engine_setup_common(engine
);
2133 memset(engine
->semaphore
.sync_seqno
, 0,
2134 sizeof(engine
->semaphore
.sync_seqno
));
2136 ret
= intel_engine_init_common(engine
);
2140 /* We may need to do things with the shrinker which
2141 * require us to immediately switch back to the default
2142 * context. This can cause a problem as pinning the
2143 * default context also requires GTT space which may not
2144 * be available. To avoid this we always pin the default
2147 ret
= intel_ring_context_pin(dev_priv
->kernel_context
, engine
);
2151 ring
= intel_engine_create_ring(engine
, 32 * PAGE_SIZE
);
2153 ret
= PTR_ERR(ring
);
2157 if (I915_NEED_GFX_HWS(dev_priv
)) {
2158 ret
= init_status_page(engine
);
2162 WARN_ON(engine
->id
!= RCS
);
2163 ret
= init_phys_status_page(engine
);
2168 ret
= intel_ring_pin(ring
);
2170 intel_ring_free(ring
);
2173 engine
->buffer
= ring
;
2178 intel_engine_cleanup(engine
);
2182 void intel_engine_cleanup(struct intel_engine_cs
*engine
)
2184 struct drm_i915_private
*dev_priv
;
2186 if (!intel_engine_initialized(engine
))
2189 dev_priv
= engine
->i915
;
2191 if (engine
->buffer
) {
2192 WARN_ON(!IS_GEN2(dev_priv
) && (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2194 intel_ring_unpin(engine
->buffer
);
2195 intel_ring_free(engine
->buffer
);
2196 engine
->buffer
= NULL
;
2199 if (engine
->cleanup
)
2200 engine
->cleanup(engine
);
2202 if (I915_NEED_GFX_HWS(dev_priv
)) {
2203 cleanup_status_page(engine
);
2205 WARN_ON(engine
->id
!= RCS
);
2206 cleanup_phys_status_page(engine
);
2209 intel_engine_cleanup_common(engine
);
2211 intel_ring_context_unpin(dev_priv
->kernel_context
, engine
);
2213 engine
->i915
= NULL
;
2216 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2220 /* Flush enough space to reduce the likelihood of waiting after
2221 * we start building the request - in which case we will just
2222 * have to repeat work.
2224 request
->reserved_space
+= LEGACY_REQUEST_SIZE
;
2226 request
->ring
= request
->engine
->buffer
;
2228 ret
= intel_ring_begin(request
, 0);
2232 request
->reserved_space
-= LEGACY_REQUEST_SIZE
;
2236 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2238 struct intel_ring
*ring
= req
->ring
;
2239 struct drm_i915_gem_request
*target
;
2242 intel_ring_update_space(ring
);
2243 if (ring
->space
>= bytes
)
2247 * Space is reserved in the ringbuffer for finalising the request,
2248 * as that cannot be allowed to fail. During request finalisation,
2249 * reserved_space is set to 0 to stop the overallocation and the
2250 * assumption is that then we never need to wait (which has the
2251 * risk of failing with EINTR).
2253 * See also i915_gem_request_alloc() and i915_add_request().
2255 GEM_BUG_ON(!req
->reserved_space
);
2257 list_for_each_entry(target
, &ring
->request_list
, ring_link
) {
2260 /* Would completion of this request free enough space? */
2261 space
= __intel_ring_space(target
->postfix
, ring
->tail
,
2267 if (WARN_ON(&target
->ring_link
== &ring
->request_list
))
2270 ret
= i915_wait_request(target
, true, NULL
, NO_WAITBOOST
);
2274 if (i915_reset_in_progress(&target
->i915
->gpu_error
))
2277 i915_gem_request_retire_upto(target
);
2279 intel_ring_update_space(ring
);
2280 GEM_BUG_ON(ring
->space
< bytes
);
2284 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2286 struct intel_ring
*ring
= req
->ring
;
2287 int remain_actual
= ring
->size
- ring
->tail
;
2288 int remain_usable
= ring
->effective_size
- ring
->tail
;
2289 int bytes
= num_dwords
* sizeof(u32
);
2290 int total_bytes
, wait_bytes
;
2291 bool need_wrap
= false;
2293 total_bytes
= bytes
+ req
->reserved_space
;
2295 if (unlikely(bytes
> remain_usable
)) {
2297 * Not enough space for the basic request. So need to flush
2298 * out the remainder and then wait for base + reserved.
2300 wait_bytes
= remain_actual
+ total_bytes
;
2302 } else if (unlikely(total_bytes
> remain_usable
)) {
2304 * The base request will fit but the reserved space
2305 * falls off the end. So we don't need an immediate wrap
2306 * and only need to effectively wait for the reserved
2307 * size space from the start of ringbuffer.
2309 wait_bytes
= remain_actual
+ req
->reserved_space
;
2311 /* No wrapping required, just waiting. */
2312 wait_bytes
= total_bytes
;
2315 if (wait_bytes
> ring
->space
) {
2316 int ret
= wait_for_space(req
, wait_bytes
);
2321 if (unlikely(need_wrap
)) {
2322 GEM_BUG_ON(remain_actual
> ring
->space
);
2323 GEM_BUG_ON(ring
->tail
+ remain_actual
> ring
->size
);
2325 /* Fill the tail with MI_NOOP */
2326 memset(ring
->vaddr
+ ring
->tail
, 0, remain_actual
);
2328 ring
->space
-= remain_actual
;
2331 ring
->space
-= bytes
;
2332 GEM_BUG_ON(ring
->space
< 0);
2336 /* Align the ring tail to a cacheline boundary */
2337 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2339 struct intel_ring
*ring
= req
->ring
;
2341 (ring
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2344 if (num_dwords
== 0)
2347 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2348 ret
= intel_ring_begin(req
, num_dwords
);
2352 while (num_dwords
--)
2353 intel_ring_emit(ring
, MI_NOOP
);
2355 intel_ring_advance(ring
);
2360 void intel_engine_init_seqno(struct intel_engine_cs
*engine
, u32 seqno
)
2362 struct drm_i915_private
*dev_priv
= engine
->i915
;
2364 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2365 * so long as the semaphore value in the register/page is greater
2366 * than the sync value), so whenever we reset the seqno,
2367 * so long as we reset the tracking semaphore value to 0, it will
2368 * always be before the next request's seqno. If we don't reset
2369 * the semaphore value, then when the seqno moves backwards all
2370 * future waits will complete instantly (causing rendering corruption).
2372 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
)) {
2373 I915_WRITE(RING_SYNC_0(engine
->mmio_base
), 0);
2374 I915_WRITE(RING_SYNC_1(engine
->mmio_base
), 0);
2375 if (HAS_VEBOX(dev_priv
))
2376 I915_WRITE(RING_SYNC_2(engine
->mmio_base
), 0);
2378 if (dev_priv
->semaphore_obj
) {
2379 struct drm_i915_gem_object
*obj
= dev_priv
->semaphore_obj
;
2380 struct page
*page
= i915_gem_object_get_dirty_page(obj
, 0);
2381 void *semaphores
= kmap(page
);
2382 memset(semaphores
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, 0),
2383 0, I915_NUM_ENGINES
* gen8_semaphore_seqno_size
);
2386 memset(engine
->semaphore
.sync_seqno
, 0,
2387 sizeof(engine
->semaphore
.sync_seqno
));
2389 intel_write_status_page(engine
, I915_GEM_HWS_INDEX
, seqno
);
2390 if (engine
->irq_seqno_barrier
)
2391 engine
->irq_seqno_barrier(engine
);
2392 engine
->last_submitted_seqno
= seqno
;
2394 engine
->hangcheck
.seqno
= seqno
;
2396 /* After manually advancing the seqno, fake the interrupt in case
2397 * there are any waiters for that seqno.
2399 intel_engine_wakeup(engine
);
2402 static void gen6_bsd_submit_request(struct drm_i915_gem_request
*request
)
2404 struct drm_i915_private
*dev_priv
= request
->i915
;
2406 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
2408 /* Every tail move must follow the sequence below */
2410 /* Disable notification that the ring is IDLE. The GT
2411 * will then assume that it is busy and bring it out of rc6.
2413 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2414 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2416 /* Clear the context id. Here be magic! */
2417 I915_WRITE64_FW(GEN6_BSD_RNCID
, 0x0);
2419 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2420 if (intel_wait_for_register_fw(dev_priv
,
2421 GEN6_BSD_SLEEP_PSMI_CONTROL
,
2422 GEN6_BSD_SLEEP_INDICATOR
,
2425 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2427 /* Now that the ring is fully powered up, update the tail */
2428 i9xx_submit_request(request
);
2430 /* Let the ring send IDLE messages to the GT again,
2431 * and so let it sleep to conserve power when idle.
2433 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2434 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2436 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
2439 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
2441 struct intel_ring
*ring
= req
->ring
;
2445 ret
= intel_ring_begin(req
, 4);
2450 if (INTEL_GEN(req
->i915
) >= 8)
2453 /* We always require a command barrier so that subsequent
2454 * commands, such as breadcrumb interrupts, are strictly ordered
2455 * wrt the contents of the write cache being flushed to memory
2456 * (and thus being coherent from the CPU).
2458 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2461 * Bspec vol 1c.5 - video engine command streamer:
2462 * "If ENABLED, all TLBs will be invalidated once the flush
2463 * operation is complete. This bit is only valid when the
2464 * Post-Sync Operation field is a value of 1h or 3h."
2466 if (mode
& EMIT_INVALIDATE
)
2467 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2469 intel_ring_emit(ring
, cmd
);
2470 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2471 if (INTEL_GEN(req
->i915
) >= 8) {
2472 intel_ring_emit(ring
, 0); /* upper addr */
2473 intel_ring_emit(ring
, 0); /* value */
2475 intel_ring_emit(ring
, 0);
2476 intel_ring_emit(ring
, MI_NOOP
);
2478 intel_ring_advance(ring
);
2483 gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
2484 u64 offset
, u32 len
,
2485 unsigned int dispatch_flags
)
2487 struct intel_ring
*ring
= req
->ring
;
2488 bool ppgtt
= USES_PPGTT(req
->i915
) &&
2489 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2492 ret
= intel_ring_begin(req
, 4);
2496 /* FIXME(BDW): Address space and security selectors. */
2497 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2498 (dispatch_flags
& I915_DISPATCH_RS
?
2499 MI_BATCH_RESOURCE_STREAMER
: 0));
2500 intel_ring_emit(ring
, lower_32_bits(offset
));
2501 intel_ring_emit(ring
, upper_32_bits(offset
));
2502 intel_ring_emit(ring
, MI_NOOP
);
2503 intel_ring_advance(ring
);
2509 hsw_emit_bb_start(struct drm_i915_gem_request
*req
,
2510 u64 offset
, u32 len
,
2511 unsigned int dispatch_flags
)
2513 struct intel_ring
*ring
= req
->ring
;
2516 ret
= intel_ring_begin(req
, 2);
2520 intel_ring_emit(ring
,
2521 MI_BATCH_BUFFER_START
|
2522 (dispatch_flags
& I915_DISPATCH_SECURE
?
2523 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2524 (dispatch_flags
& I915_DISPATCH_RS
?
2525 MI_BATCH_RESOURCE_STREAMER
: 0));
2526 /* bit0-7 is the length on GEN6+ */
2527 intel_ring_emit(ring
, offset
);
2528 intel_ring_advance(ring
);
2534 gen6_emit_bb_start(struct drm_i915_gem_request
*req
,
2535 u64 offset
, u32 len
,
2536 unsigned int dispatch_flags
)
2538 struct intel_ring
*ring
= req
->ring
;
2541 ret
= intel_ring_begin(req
, 2);
2545 intel_ring_emit(ring
,
2546 MI_BATCH_BUFFER_START
|
2547 (dispatch_flags
& I915_DISPATCH_SECURE
?
2548 0 : MI_BATCH_NON_SECURE_I965
));
2549 /* bit0-7 is the length on GEN6+ */
2550 intel_ring_emit(ring
, offset
);
2551 intel_ring_advance(ring
);
2556 /* Blitter support (SandyBridge+) */
2558 static int gen6_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
2560 struct intel_ring
*ring
= req
->ring
;
2564 ret
= intel_ring_begin(req
, 4);
2569 if (INTEL_GEN(req
->i915
) >= 8)
2572 /* We always require a command barrier so that subsequent
2573 * commands, such as breadcrumb interrupts, are strictly ordered
2574 * wrt the contents of the write cache being flushed to memory
2575 * (and thus being coherent from the CPU).
2577 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2580 * Bspec vol 1c.3 - blitter engine command streamer:
2581 * "If ENABLED, all TLBs will be invalidated once the flush
2582 * operation is complete. This bit is only valid when the
2583 * Post-Sync Operation field is a value of 1h or 3h."
2585 if (mode
& EMIT_INVALIDATE
)
2586 cmd
|= MI_INVALIDATE_TLB
;
2587 intel_ring_emit(ring
, cmd
);
2588 intel_ring_emit(ring
,
2589 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2590 if (INTEL_GEN(req
->i915
) >= 8) {
2591 intel_ring_emit(ring
, 0); /* upper addr */
2592 intel_ring_emit(ring
, 0); /* value */
2594 intel_ring_emit(ring
, 0);
2595 intel_ring_emit(ring
, MI_NOOP
);
2597 intel_ring_advance(ring
);
2602 static void intel_ring_init_semaphores(struct drm_i915_private
*dev_priv
,
2603 struct intel_engine_cs
*engine
)
2605 struct drm_i915_gem_object
*obj
;
2608 if (!i915
.semaphores
)
2611 if (INTEL_GEN(dev_priv
) >= 8 && !dev_priv
->semaphore_obj
) {
2612 obj
= i915_gem_object_create(&dev_priv
->drm
, 4096);
2614 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2615 i915
.semaphores
= 0;
2617 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2618 ret
= i915_gem_object_ggtt_pin(obj
, NULL
,
2621 i915_gem_object_put(obj
);
2622 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2623 i915
.semaphores
= 0;
2625 dev_priv
->semaphore_obj
= obj
;
2630 if (!i915
.semaphores
)
2633 if (INTEL_GEN(dev_priv
) >= 8) {
2634 u64 offset
= i915_gem_obj_ggtt_offset(dev_priv
->semaphore_obj
);
2636 engine
->semaphore
.sync_to
= gen8_ring_sync_to
;
2637 engine
->semaphore
.signal
= gen8_xcs_signal
;
2639 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2642 if (i
!= engine
->id
)
2643 ring_offset
= offset
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, i
);
2645 ring_offset
= MI_SEMAPHORE_SYNC_INVALID
;
2647 engine
->semaphore
.signal_ggtt
[i
] = ring_offset
;
2649 } else if (INTEL_GEN(dev_priv
) >= 6) {
2650 engine
->semaphore
.sync_to
= gen6_ring_sync_to
;
2651 engine
->semaphore
.signal
= gen6_signal
;
2654 * The current semaphore is only applied on pre-gen8
2655 * platform. And there is no VCS2 ring on the pre-gen8
2656 * platform. So the semaphore between RCS and VCS2 is
2657 * initialized as INVALID. Gen8 will initialize the
2658 * sema between VCS2 and RCS later.
2660 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2661 static const struct {
2663 i915_reg_t mbox_reg
;
2664 } sem_data
[I915_NUM_ENGINES
][I915_NUM_ENGINES
] = {
2666 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RV
, .mbox_reg
= GEN6_VRSYNC
},
2667 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RB
, .mbox_reg
= GEN6_BRSYNC
},
2668 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RVE
, .mbox_reg
= GEN6_VERSYNC
},
2671 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VR
, .mbox_reg
= GEN6_RVSYNC
},
2672 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VB
, .mbox_reg
= GEN6_BVSYNC
},
2673 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VVE
, .mbox_reg
= GEN6_VEVSYNC
},
2676 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BR
, .mbox_reg
= GEN6_RBSYNC
},
2677 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BV
, .mbox_reg
= GEN6_VBSYNC
},
2678 [VECS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BVE
, .mbox_reg
= GEN6_VEBSYNC
},
2681 [RCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VER
, .mbox_reg
= GEN6_RVESYNC
},
2682 [VCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEV
, .mbox_reg
= GEN6_VVESYNC
},
2683 [BCS
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEB
, .mbox_reg
= GEN6_BVESYNC
},
2687 i915_reg_t mbox_reg
;
2689 if (i
== engine
->id
|| i
== VCS2
) {
2690 wait_mbox
= MI_SEMAPHORE_SYNC_INVALID
;
2691 mbox_reg
= GEN6_NOSYNC
;
2693 wait_mbox
= sem_data
[engine
->id
][i
].wait_mbox
;
2694 mbox_reg
= sem_data
[engine
->id
][i
].mbox_reg
;
2697 engine
->semaphore
.mbox
.wait
[i
] = wait_mbox
;
2698 engine
->semaphore
.mbox
.signal
[i
] = mbox_reg
;
2703 static void intel_ring_init_irq(struct drm_i915_private
*dev_priv
,
2704 struct intel_engine_cs
*engine
)
2706 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< engine
->irq_shift
;
2708 if (INTEL_GEN(dev_priv
) >= 8) {
2709 engine
->irq_enable
= gen8_irq_enable
;
2710 engine
->irq_disable
= gen8_irq_disable
;
2711 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2712 } else if (INTEL_GEN(dev_priv
) >= 6) {
2713 engine
->irq_enable
= gen6_irq_enable
;
2714 engine
->irq_disable
= gen6_irq_disable
;
2715 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2716 } else if (INTEL_GEN(dev_priv
) >= 5) {
2717 engine
->irq_enable
= gen5_irq_enable
;
2718 engine
->irq_disable
= gen5_irq_disable
;
2719 engine
->irq_seqno_barrier
= gen5_seqno_barrier
;
2720 } else if (INTEL_GEN(dev_priv
) >= 3) {
2721 engine
->irq_enable
= i9xx_irq_enable
;
2722 engine
->irq_disable
= i9xx_irq_disable
;
2724 engine
->irq_enable
= i8xx_irq_enable
;
2725 engine
->irq_disable
= i8xx_irq_disable
;
2729 static void intel_ring_default_vfuncs(struct drm_i915_private
*dev_priv
,
2730 struct intel_engine_cs
*engine
)
2732 intel_ring_init_irq(dev_priv
, engine
);
2733 intel_ring_init_semaphores(dev_priv
, engine
);
2735 engine
->init_hw
= init_ring_common
;
2737 engine
->emit_request
= i9xx_emit_request
;
2738 if (i915
.semaphores
)
2739 engine
->emit_request
= gen6_sema_emit_request
;
2740 engine
->submit_request
= i9xx_submit_request
;
2742 if (INTEL_GEN(dev_priv
) >= 8)
2743 engine
->emit_bb_start
= gen8_emit_bb_start
;
2744 else if (INTEL_GEN(dev_priv
) >= 6)
2745 engine
->emit_bb_start
= gen6_emit_bb_start
;
2746 else if (INTEL_GEN(dev_priv
) >= 4)
2747 engine
->emit_bb_start
= i965_emit_bb_start
;
2748 else if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
2749 engine
->emit_bb_start
= i830_emit_bb_start
;
2751 engine
->emit_bb_start
= i915_emit_bb_start
;
2754 int intel_init_render_ring_buffer(struct intel_engine_cs
*engine
)
2756 struct drm_i915_private
*dev_priv
= engine
->i915
;
2759 intel_ring_default_vfuncs(dev_priv
, engine
);
2761 if (HAS_L3_DPF(dev_priv
))
2762 engine
->irq_keep_mask
= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2764 if (INTEL_GEN(dev_priv
) >= 8) {
2765 engine
->init_context
= intel_rcs_ctx_init
;
2766 engine
->emit_request
= gen8_render_emit_request
;
2767 engine
->emit_flush
= gen8_render_ring_flush
;
2768 if (i915
.semaphores
)
2769 engine
->semaphore
.signal
= gen8_rcs_signal
;
2770 } else if (INTEL_GEN(dev_priv
) >= 6) {
2771 engine
->init_context
= intel_rcs_ctx_init
;
2772 engine
->emit_flush
= gen7_render_ring_flush
;
2773 if (IS_GEN6(dev_priv
))
2774 engine
->emit_flush
= gen6_render_ring_flush
;
2775 } else if (IS_GEN5(dev_priv
)) {
2776 engine
->emit_flush
= gen4_render_ring_flush
;
2778 if (INTEL_GEN(dev_priv
) < 4)
2779 engine
->emit_flush
= gen2_render_ring_flush
;
2781 engine
->emit_flush
= gen4_render_ring_flush
;
2782 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2785 if (IS_HASWELL(dev_priv
))
2786 engine
->emit_bb_start
= hsw_emit_bb_start
;
2788 engine
->init_hw
= init_render_ring
;
2789 engine
->cleanup
= render_ring_cleanup
;
2791 ret
= intel_init_ring_buffer(engine
);
2795 if (INTEL_GEN(dev_priv
) >= 6) {
2796 ret
= intel_init_pipe_control(engine
, 4096);
2799 } else if (HAS_BROKEN_CS_TLB(dev_priv
)) {
2800 ret
= intel_init_pipe_control(engine
, I830_WA_SIZE
);
2808 int intel_init_bsd_ring_buffer(struct intel_engine_cs
*engine
)
2810 struct drm_i915_private
*dev_priv
= engine
->i915
;
2812 intel_ring_default_vfuncs(dev_priv
, engine
);
2814 if (INTEL_GEN(dev_priv
) >= 6) {
2815 /* gen6 bsd needs a special wa for tail updates */
2816 if (IS_GEN6(dev_priv
))
2817 engine
->submit_request
= gen6_bsd_submit_request
;
2818 engine
->emit_flush
= gen6_bsd_ring_flush
;
2819 if (INTEL_GEN(dev_priv
) < 8)
2820 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2822 engine
->mmio_base
= BSD_RING_BASE
;
2823 engine
->emit_flush
= bsd_ring_flush
;
2824 if (IS_GEN5(dev_priv
))
2825 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2827 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2830 return intel_init_ring_buffer(engine
);
2834 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2836 int intel_init_bsd2_ring_buffer(struct intel_engine_cs
*engine
)
2838 struct drm_i915_private
*dev_priv
= engine
->i915
;
2840 intel_ring_default_vfuncs(dev_priv
, engine
);
2842 engine
->emit_flush
= gen6_bsd_ring_flush
;
2844 return intel_init_ring_buffer(engine
);
2847 int intel_init_blt_ring_buffer(struct intel_engine_cs
*engine
)
2849 struct drm_i915_private
*dev_priv
= engine
->i915
;
2851 intel_ring_default_vfuncs(dev_priv
, engine
);
2853 engine
->emit_flush
= gen6_ring_flush
;
2854 if (INTEL_GEN(dev_priv
) < 8)
2855 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2857 return intel_init_ring_buffer(engine
);
2860 int intel_init_vebox_ring_buffer(struct intel_engine_cs
*engine
)
2862 struct drm_i915_private
*dev_priv
= engine
->i915
;
2864 intel_ring_default_vfuncs(dev_priv
, engine
);
2866 engine
->emit_flush
= gen6_ring_flush
;
2868 if (INTEL_GEN(dev_priv
) < 8) {
2869 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2870 engine
->irq_enable
= hsw_vebox_irq_enable
;
2871 engine
->irq_disable
= hsw_vebox_irq_disable
;
2874 return intel_init_ring_buffer(engine
);