2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 static u32
i915_gem_get_seqno(struct drm_device
*dev
)
39 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
42 seqno
= dev_priv
->next_seqno
;
44 /* reserve 0 for non-seqno */
45 if (++dev_priv
->next_seqno
== 0)
46 dev_priv
->next_seqno
= 1;
52 render_ring_flush(struct drm_device
*dev
,
53 struct intel_ring_buffer
*ring
,
54 u32 invalidate_domains
,
57 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
61 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
62 invalidate_domains
, flush_domains
);
65 trace_i915_gem_request_flush(dev
, dev_priv
->next_seqno
,
66 invalidate_domains
, flush_domains
);
68 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
81 * I915_GEM_DOMAIN_COMMAND may not exist?
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
97 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
98 if ((invalidate_domains
|flush_domains
) &
99 I915_GEM_DOMAIN_RENDER
)
100 cmd
&= ~MI_NO_WRITE_FLUSH
;
101 if (INTEL_INFO(dev
)->gen
< 4) {
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
106 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
107 cmd
|= MI_READ_FLUSH
;
109 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
113 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
115 intel_ring_begin(dev
, ring
, 2);
116 intel_ring_emit(dev
, ring
, cmd
);
117 intel_ring_emit(dev
, ring
, MI_NOOP
);
118 intel_ring_advance(dev
, ring
);
122 static unsigned int render_ring_get_head(struct drm_device
*dev
,
123 struct intel_ring_buffer
*ring
)
125 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
126 return I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
129 static unsigned int render_ring_get_tail(struct drm_device
*dev
,
130 struct intel_ring_buffer
*ring
)
132 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
133 return I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
136 static inline void render_ring_set_tail(struct drm_device
*dev
, u32 value
)
138 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
139 I915_WRITE(PRB0_TAIL
, value
);
142 static unsigned int render_ring_get_active_head(struct drm_device
*dev
,
143 struct intel_ring_buffer
*ring
)
145 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
146 u32 acthd_reg
= INTEL_INFO(dev
)->gen
? ACTHD_I965
: ACTHD
;
148 return I915_READ(acthd_reg
);
151 static int init_ring_common(struct drm_device
*dev
,
152 struct intel_ring_buffer
*ring
)
155 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
156 struct drm_i915_gem_object
*obj_priv
;
157 obj_priv
= to_intel_bo(ring
->gem_object
);
159 /* Stop the ring if it's running. */
160 I915_WRITE(ring
->regs
.ctl
, 0);
161 I915_WRITE(ring
->regs
.head
, 0);
162 ring
->set_tail(dev
, 0);
164 /* Initialize the ring. */
165 I915_WRITE(ring
->regs
.start
, obj_priv
->gtt_offset
);
166 head
= ring
->get_head(dev
, ring
);
168 /* G45 ring initialization fails to reset head to zero */
170 DRM_ERROR("%s head not reset to zero "
171 "ctl %08x head %08x tail %08x start %08x\n",
173 I915_READ(ring
->regs
.ctl
),
174 I915_READ(ring
->regs
.head
),
175 I915_READ(ring
->regs
.tail
),
176 I915_READ(ring
->regs
.start
));
178 I915_WRITE(ring
->regs
.head
, 0);
180 DRM_ERROR("%s head forced to zero "
181 "ctl %08x head %08x tail %08x start %08x\n",
183 I915_READ(ring
->regs
.ctl
),
184 I915_READ(ring
->regs
.head
),
185 I915_READ(ring
->regs
.tail
),
186 I915_READ(ring
->regs
.start
));
189 I915_WRITE(ring
->regs
.ctl
,
190 ((ring
->gem_object
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
191 | RING_NO_REPORT
| RING_VALID
);
193 head
= I915_READ(ring
->regs
.head
) & HEAD_ADDR
;
194 /* If the head is still not zero, the ring is dead */
196 DRM_ERROR("%s initialization failed "
197 "ctl %08x head %08x tail %08x start %08x\n",
199 I915_READ(ring
->regs
.ctl
),
200 I915_READ(ring
->regs
.head
),
201 I915_READ(ring
->regs
.tail
),
202 I915_READ(ring
->regs
.start
));
206 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
207 i915_kernel_lost_context(dev
);
209 ring
->head
= ring
->get_head(dev
, ring
);
210 ring
->tail
= ring
->get_tail(dev
, ring
);
211 ring
->space
= ring
->head
- (ring
->tail
+ 8);
213 ring
->space
+= ring
->size
;
218 static int init_render_ring(struct drm_device
*dev
,
219 struct intel_ring_buffer
*ring
)
221 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
222 int ret
= init_ring_common(dev
, ring
);
225 if (INTEL_INFO(dev
)->gen
> 3) {
226 mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
228 mode
|= MI_FLUSH_ENABLE
<< 16 | MI_FLUSH_ENABLE
;
229 I915_WRITE(MI_MODE
, mode
);
234 #define PIPE_CONTROL_FLUSH(addr) \
236 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
237 PIPE_CONTROL_DEPTH_STALL | 2); \
238 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
244 * Creates a new sequence number, emitting a write of it to the status page
245 * plus an interrupt, which will trigger i915_user_interrupt_handler.
247 * Must be called with struct_lock held.
249 * Returned sequence numbers are nonzero on success.
252 render_ring_add_request(struct drm_device
*dev
,
253 struct intel_ring_buffer
*ring
,
254 struct drm_file
*file_priv
,
257 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
260 seqno
= i915_gem_get_seqno(dev
);
264 OUT_RING(GFX_OP_PIPE_CONTROL
| 3);
265 OUT_RING(PIPE_CONTROL_QW_WRITE
|
266 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_IS_FLUSH
|
267 PIPE_CONTROL_NOTIFY
);
268 OUT_RING(dev_priv
->seqno_gfx_addr
| PIPE_CONTROL_GLOBAL_GTT
);
273 } else if (HAS_PIPE_CONTROL(dev
)) {
274 u32 scratch_addr
= dev_priv
->seqno_gfx_addr
+ 128;
277 * Workaround qword write incoherence by flushing the
278 * PIPE_NOTIFY buffers out to memory before requesting
282 OUT_RING(GFX_OP_PIPE_CONTROL
| PIPE_CONTROL_QW_WRITE
|
283 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_TC_FLUSH
);
284 OUT_RING(dev_priv
->seqno_gfx_addr
| PIPE_CONTROL_GLOBAL_GTT
);
287 PIPE_CONTROL_FLUSH(scratch_addr
);
288 scratch_addr
+= 128; /* write to separate cachelines */
289 PIPE_CONTROL_FLUSH(scratch_addr
);
291 PIPE_CONTROL_FLUSH(scratch_addr
);
293 PIPE_CONTROL_FLUSH(scratch_addr
);
295 PIPE_CONTROL_FLUSH(scratch_addr
);
297 PIPE_CONTROL_FLUSH(scratch_addr
);
298 OUT_RING(GFX_OP_PIPE_CONTROL
| PIPE_CONTROL_QW_WRITE
|
299 PIPE_CONTROL_WC_FLUSH
| PIPE_CONTROL_TC_FLUSH
|
300 PIPE_CONTROL_NOTIFY
);
301 OUT_RING(dev_priv
->seqno_gfx_addr
| PIPE_CONTROL_GLOBAL_GTT
);
307 OUT_RING(MI_STORE_DWORD_INDEX
);
308 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
311 OUT_RING(MI_USER_INTERRUPT
);
318 render_ring_get_gem_seqno(struct drm_device
*dev
,
319 struct intel_ring_buffer
*ring
)
321 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
322 if (HAS_PIPE_CONTROL(dev
))
323 return ((volatile u32
*)(dev_priv
->seqno_page
))[0];
325 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
329 render_ring_get_user_irq(struct drm_device
*dev
,
330 struct intel_ring_buffer
*ring
)
332 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
333 unsigned long irqflags
;
335 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
336 if (dev
->irq_enabled
&& (++ring
->user_irq_refcount
== 1)) {
337 if (HAS_PCH_SPLIT(dev
))
338 ironlake_enable_graphics_irq(dev_priv
, GT_PIPE_NOTIFY
);
340 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
342 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
346 render_ring_put_user_irq(struct drm_device
*dev
,
347 struct intel_ring_buffer
*ring
)
349 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
350 unsigned long irqflags
;
352 spin_lock_irqsave(&dev_priv
->user_irq_lock
, irqflags
);
353 BUG_ON(dev
->irq_enabled
&& ring
->user_irq_refcount
<= 0);
354 if (dev
->irq_enabled
&& (--ring
->user_irq_refcount
== 0)) {
355 if (HAS_PCH_SPLIT(dev
))
356 ironlake_disable_graphics_irq(dev_priv
, GT_PIPE_NOTIFY
);
358 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
360 spin_unlock_irqrestore(&dev_priv
->user_irq_lock
, irqflags
);
363 static void render_setup_status_page(struct drm_device
*dev
,
364 struct intel_ring_buffer
*ring
)
366 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
368 I915_WRITE(HWS_PGA_GEN6
, ring
->status_page
.gfx_addr
);
369 I915_READ(HWS_PGA_GEN6
); /* posting read */
371 I915_WRITE(HWS_PGA
, ring
->status_page
.gfx_addr
);
372 I915_READ(HWS_PGA
); /* posting read */
378 bsd_ring_flush(struct drm_device
*dev
,
379 struct intel_ring_buffer
*ring
,
380 u32 invalidate_domains
,
383 intel_ring_begin(dev
, ring
, 2);
384 intel_ring_emit(dev
, ring
, MI_FLUSH
);
385 intel_ring_emit(dev
, ring
, MI_NOOP
);
386 intel_ring_advance(dev
, ring
);
389 static inline unsigned int bsd_ring_get_head(struct drm_device
*dev
,
390 struct intel_ring_buffer
*ring
)
392 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
393 return I915_READ(BSD_RING_HEAD
) & HEAD_ADDR
;
396 static inline unsigned int bsd_ring_get_tail(struct drm_device
*dev
,
397 struct intel_ring_buffer
*ring
)
399 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
400 return I915_READ(BSD_RING_TAIL
) & TAIL_ADDR
;
403 static inline void bsd_ring_set_tail(struct drm_device
*dev
, u32 value
)
405 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
406 I915_WRITE(BSD_RING_TAIL
, value
);
409 static inline unsigned int bsd_ring_get_active_head(struct drm_device
*dev
,
410 struct intel_ring_buffer
*ring
)
412 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
413 return I915_READ(BSD_RING_ACTHD
);
416 static int init_bsd_ring(struct drm_device
*dev
,
417 struct intel_ring_buffer
*ring
)
419 return init_ring_common(dev
, ring
);
423 bsd_ring_add_request(struct drm_device
*dev
,
424 struct intel_ring_buffer
*ring
,
425 struct drm_file
*file_priv
,
430 seqno
= i915_gem_get_seqno(dev
);
432 intel_ring_begin(dev
, ring
, 4);
433 intel_ring_emit(dev
, ring
, MI_STORE_DWORD_INDEX
);
434 intel_ring_emit(dev
, ring
,
435 I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
436 intel_ring_emit(dev
, ring
, seqno
);
437 intel_ring_emit(dev
, ring
, MI_USER_INTERRUPT
);
438 intel_ring_advance(dev
, ring
);
440 DRM_DEBUG_DRIVER("%s %d\n", ring
->name
, seqno
);
445 static void bsd_setup_status_page(struct drm_device
*dev
,
446 struct intel_ring_buffer
*ring
)
448 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
449 I915_WRITE(BSD_HWS_PGA
, ring
->status_page
.gfx_addr
);
450 I915_READ(BSD_HWS_PGA
);
454 bsd_ring_get_user_irq(struct drm_device
*dev
,
455 struct intel_ring_buffer
*ring
)
460 bsd_ring_put_user_irq(struct drm_device
*dev
,
461 struct intel_ring_buffer
*ring
)
467 bsd_ring_get_gem_seqno(struct drm_device
*dev
,
468 struct intel_ring_buffer
*ring
)
470 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
474 bsd_ring_dispatch_gem_execbuffer(struct drm_device
*dev
,
475 struct intel_ring_buffer
*ring
,
476 struct drm_i915_gem_execbuffer2
*exec
,
477 struct drm_clip_rect
*cliprects
,
478 uint64_t exec_offset
)
481 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
482 intel_ring_begin(dev
, ring
, 2);
483 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER_START
|
484 (2 << 6) | MI_BATCH_NON_SECURE_I965
);
485 intel_ring_emit(dev
, ring
, exec_start
);
486 intel_ring_advance(dev
, ring
);
492 render_ring_dispatch_gem_execbuffer(struct drm_device
*dev
,
493 struct intel_ring_buffer
*ring
,
494 struct drm_i915_gem_execbuffer2
*exec
,
495 struct drm_clip_rect
*cliprects
,
496 uint64_t exec_offset
)
498 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
499 int nbox
= exec
->num_cliprects
;
501 uint32_t exec_start
, exec_len
;
502 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
503 exec_len
= (uint32_t) exec
->batch_len
;
505 trace_i915_gem_request_submit(dev
, dev_priv
->next_seqno
+ 1);
507 count
= nbox
? nbox
: 1;
509 for (i
= 0; i
< count
; i
++) {
511 int ret
= i915_emit_box(dev
, cliprects
, i
,
512 exec
->DR1
, exec
->DR4
);
517 if (IS_I830(dev
) || IS_845G(dev
)) {
518 intel_ring_begin(dev
, ring
, 4);
519 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER
);
520 intel_ring_emit(dev
, ring
,
521 exec_start
| MI_BATCH_NON_SECURE
);
522 intel_ring_emit(dev
, ring
, exec_start
+ exec_len
- 4);
523 intel_ring_emit(dev
, ring
, 0);
525 intel_ring_begin(dev
, ring
, 4);
526 if (INTEL_INFO(dev
)->gen
>= 4) {
527 intel_ring_emit(dev
, ring
,
528 MI_BATCH_BUFFER_START
| (2 << 6)
529 | MI_BATCH_NON_SECURE_I965
);
530 intel_ring_emit(dev
, ring
, exec_start
);
532 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER_START
534 intel_ring_emit(dev
, ring
, exec_start
|
535 MI_BATCH_NON_SECURE
);
538 intel_ring_advance(dev
, ring
);
541 if (IS_G4X(dev
) || IS_IRONLAKE(dev
)) {
542 intel_ring_begin(dev
, ring
, 2);
543 intel_ring_emit(dev
, ring
, MI_FLUSH
|
546 intel_ring_emit(dev
, ring
, MI_NOOP
);
547 intel_ring_advance(dev
, ring
);
554 static void cleanup_status_page(struct drm_device
*dev
,
555 struct intel_ring_buffer
*ring
)
557 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
558 struct drm_gem_object
*obj
;
559 struct drm_i915_gem_object
*obj_priv
;
561 obj
= ring
->status_page
.obj
;
564 obj_priv
= to_intel_bo(obj
);
566 kunmap(obj_priv
->pages
[0]);
567 i915_gem_object_unpin(obj
);
568 drm_gem_object_unreference(obj
);
569 ring
->status_page
.obj
= NULL
;
571 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
574 static int init_status_page(struct drm_device
*dev
,
575 struct intel_ring_buffer
*ring
)
577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
578 struct drm_gem_object
*obj
;
579 struct drm_i915_gem_object
*obj_priv
;
582 obj
= i915_gem_alloc_object(dev
, 4096);
584 DRM_ERROR("Failed to allocate status page\n");
588 obj_priv
= to_intel_bo(obj
);
589 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
591 ret
= i915_gem_object_pin(obj
, 4096);
596 ring
->status_page
.gfx_addr
= obj_priv
->gtt_offset
;
597 ring
->status_page
.page_addr
= kmap(obj_priv
->pages
[0]);
598 if (ring
->status_page
.page_addr
== NULL
) {
599 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
602 ring
->status_page
.obj
= obj
;
603 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
605 ring
->setup_status_page(dev
, ring
);
606 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
607 ring
->name
, ring
->status_page
.gfx_addr
);
612 i915_gem_object_unpin(obj
);
614 drm_gem_object_unreference(obj
);
620 int intel_init_ring_buffer(struct drm_device
*dev
,
621 struct intel_ring_buffer
*ring
)
623 struct drm_i915_gem_object
*obj_priv
;
624 struct drm_gem_object
*obj
;
629 if (I915_NEED_GFX_HWS(dev
)) {
630 ret
= init_status_page(dev
, ring
);
635 obj
= i915_gem_alloc_object(dev
, ring
->size
);
637 DRM_ERROR("Failed to allocate ringbuffer\n");
642 ring
->gem_object
= obj
;
644 ret
= i915_gem_object_pin(obj
, ring
->alignment
);
648 obj_priv
= to_intel_bo(obj
);
649 ring
->map
.size
= ring
->size
;
650 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
655 drm_core_ioremap_wc(&ring
->map
, dev
);
656 if (ring
->map
.handle
== NULL
) {
657 DRM_ERROR("Failed to map ringbuffer.\n");
662 ring
->virtual_start
= ring
->map
.handle
;
663 ret
= ring
->init(dev
, ring
);
667 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
668 i915_kernel_lost_context(dev
);
670 ring
->head
= ring
->get_head(dev
, ring
);
671 ring
->tail
= ring
->get_tail(dev
, ring
);
672 ring
->space
= ring
->head
- (ring
->tail
+ 8);
674 ring
->space
+= ring
->size
;
676 INIT_LIST_HEAD(&ring
->active_list
);
677 INIT_LIST_HEAD(&ring
->request_list
);
681 drm_core_ioremapfree(&ring
->map
, dev
);
683 i915_gem_object_unpin(obj
);
685 drm_gem_object_unreference(obj
);
686 ring
->gem_object
= NULL
;
688 cleanup_status_page(dev
, ring
);
692 void intel_cleanup_ring_buffer(struct drm_device
*dev
,
693 struct intel_ring_buffer
*ring
)
695 if (ring
->gem_object
== NULL
)
698 drm_core_ioremapfree(&ring
->map
, dev
);
700 i915_gem_object_unpin(ring
->gem_object
);
701 drm_gem_object_unreference(ring
->gem_object
);
702 ring
->gem_object
= NULL
;
703 cleanup_status_page(dev
, ring
);
706 int intel_wrap_ring_buffer(struct drm_device
*dev
,
707 struct intel_ring_buffer
*ring
)
711 rem
= ring
->size
- ring
->tail
;
713 if (ring
->space
< rem
) {
714 int ret
= intel_wait_ring_buffer(dev
, ring
, rem
);
719 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
727 ring
->space
= ring
->head
- 8;
732 int intel_wait_ring_buffer(struct drm_device
*dev
,
733 struct intel_ring_buffer
*ring
, int n
)
737 trace_i915_ring_wait_begin (dev
);
738 end
= jiffies
+ 3 * HZ
;
740 ring
->head
= ring
->get_head(dev
, ring
);
741 ring
->space
= ring
->head
- (ring
->tail
+ 8);
743 ring
->space
+= ring
->size
;
744 if (ring
->space
>= n
) {
745 trace_i915_ring_wait_end (dev
);
749 if (dev
->primary
->master
) {
750 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
751 if (master_priv
->sarea_priv
)
752 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
756 } while (!time_after(jiffies
, end
));
757 trace_i915_ring_wait_end (dev
);
761 void intel_ring_begin(struct drm_device
*dev
,
762 struct intel_ring_buffer
*ring
, int num_dwords
)
764 int n
= 4*num_dwords
;
765 if (unlikely(ring
->tail
+ n
> ring
->size
))
766 intel_wrap_ring_buffer(dev
, ring
);
767 if (unlikely(ring
->space
< n
))
768 intel_wait_ring_buffer(dev
, ring
, n
);
773 void intel_ring_advance(struct drm_device
*dev
,
774 struct intel_ring_buffer
*ring
)
776 ring
->tail
&= ring
->size
- 1;
777 ring
->set_tail(dev
, ring
->tail
);
780 void intel_fill_struct(struct drm_device
*dev
,
781 struct intel_ring_buffer
*ring
,
785 unsigned int *virt
= ring
->virtual_start
+ ring
->tail
;
786 BUG_ON((len
&~(4-1)) != 0);
787 intel_ring_begin(dev
, ring
, len
/4);
788 memcpy(virt
, data
, len
);
790 ring
->tail
&= ring
->size
- 1;
792 intel_ring_advance(dev
, ring
);
795 static const struct intel_ring_buffer render_ring
= {
796 .name
= "render ring",
804 .mmio_base
= RENDER_RING_BASE
,
805 .size
= 32 * PAGE_SIZE
,
806 .alignment
= PAGE_SIZE
,
807 .virtual_start
= NULL
,
813 .user_irq_refcount
= 0,
815 .waiting_gem_seqno
= 0,
816 .setup_status_page
= render_setup_status_page
,
817 .init
= init_render_ring
,
818 .get_head
= render_ring_get_head
,
819 .get_tail
= render_ring_get_tail
,
820 .set_tail
= render_ring_set_tail
,
821 .get_active_head
= render_ring_get_active_head
,
822 .flush
= render_ring_flush
,
823 .add_request
= render_ring_add_request
,
824 .get_gem_seqno
= render_ring_get_gem_seqno
,
825 .user_irq_get
= render_ring_get_user_irq
,
826 .user_irq_put
= render_ring_put_user_irq
,
827 .dispatch_gem_execbuffer
= render_ring_dispatch_gem_execbuffer
,
828 .status_page
= {NULL
, 0, NULL
},
832 /* ring buffer for bit-stream decoder */
834 static const struct intel_ring_buffer bsd_ring
= {
839 .head
= BSD_RING_HEAD
,
840 .tail
= BSD_RING_TAIL
,
841 .start
= BSD_RING_START
843 .mmio_base
= BSD_RING_BASE
,
844 .size
= 32 * PAGE_SIZE
,
845 .alignment
= PAGE_SIZE
,
846 .virtual_start
= NULL
,
852 .user_irq_refcount
= 0,
854 .waiting_gem_seqno
= 0,
855 .setup_status_page
= bsd_setup_status_page
,
856 .init
= init_bsd_ring
,
857 .get_head
= bsd_ring_get_head
,
858 .get_tail
= bsd_ring_get_tail
,
859 .set_tail
= bsd_ring_set_tail
,
860 .get_active_head
= bsd_ring_get_active_head
,
861 .flush
= bsd_ring_flush
,
862 .add_request
= bsd_ring_add_request
,
863 .get_gem_seqno
= bsd_ring_get_gem_seqno
,
864 .user_irq_get
= bsd_ring_get_user_irq
,
865 .user_irq_put
= bsd_ring_put_user_irq
,
866 .dispatch_gem_execbuffer
= bsd_ring_dispatch_gem_execbuffer
,
867 .status_page
= {NULL
, 0, NULL
},
872 static void gen6_bsd_setup_status_page(struct drm_device
*dev
,
873 struct intel_ring_buffer
*ring
)
875 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
876 I915_WRITE(GEN6_BSD_HWS_PGA
, ring
->status_page
.gfx_addr
);
877 I915_READ(GEN6_BSD_HWS_PGA
);
880 static inline unsigned int gen6_bsd_ring_get_head(struct drm_device
*dev
,
881 struct intel_ring_buffer
*ring
)
883 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
884 return I915_READ(GEN6_BSD_RING_HEAD
) & HEAD_ADDR
;
887 static inline unsigned int gen6_bsd_ring_get_tail(struct drm_device
*dev
,
888 struct intel_ring_buffer
*ring
)
890 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
891 return I915_READ(GEN6_BSD_RING_TAIL
) & TAIL_ADDR
;
894 static inline void gen6_bsd_ring_set_tail(struct drm_device
*dev
,
897 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
899 /* Every tail move must follow the sequence below */
900 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
901 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
902 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE
);
903 I915_WRITE(GEN6_BSD_RNCID
, 0x0);
905 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
906 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR
) == 0,
908 DRM_ERROR("timed out waiting for IDLE Indicator\n");
910 I915_WRITE(GEN6_BSD_RING_TAIL
, value
);
911 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
912 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
913 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE
);
916 static inline unsigned int gen6_bsd_ring_get_active_head(struct drm_device
*dev
,
917 struct intel_ring_buffer
*ring
)
919 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
920 return I915_READ(GEN6_BSD_RING_ACTHD
);
923 static void gen6_bsd_ring_flush(struct drm_device
*dev
,
924 struct intel_ring_buffer
*ring
,
925 u32 invalidate_domains
,
928 intel_ring_begin(dev
, ring
, 4);
929 intel_ring_emit(dev
, ring
, MI_FLUSH_DW
);
930 intel_ring_emit(dev
, ring
, 0);
931 intel_ring_emit(dev
, ring
, 0);
932 intel_ring_emit(dev
, ring
, 0);
933 intel_ring_advance(dev
, ring
);
937 gen6_bsd_ring_dispatch_gem_execbuffer(struct drm_device
*dev
,
938 struct intel_ring_buffer
*ring
,
939 struct drm_i915_gem_execbuffer2
*exec
,
940 struct drm_clip_rect
*cliprects
,
941 uint64_t exec_offset
)
944 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
945 intel_ring_begin(dev
, ring
, 2);
946 intel_ring_emit(dev
, ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
); /* bit0-7 is the length on GEN6+ */
947 intel_ring_emit(dev
, ring
, exec_start
);
948 intel_ring_advance(dev
, ring
);
952 /* ring buffer for Video Codec for Gen6+ */
953 static const struct intel_ring_buffer gen6_bsd_ring
= {
954 .name
= "gen6 bsd ring",
957 .ctl
= GEN6_BSD_RING_CTL
,
958 .head
= GEN6_BSD_RING_HEAD
,
959 .tail
= GEN6_BSD_RING_TAIL
,
960 .start
= GEN6_BSD_RING_START
962 .mmio_base
= GEN6_BSD_RING_BASE
,
963 .size
= 32 * PAGE_SIZE
,
964 .alignment
= PAGE_SIZE
,
965 .virtual_start
= NULL
,
971 .user_irq_refcount
= 0,
973 .waiting_gem_seqno
= 0,
974 .setup_status_page
= gen6_bsd_setup_status_page
,
975 .init
= init_bsd_ring
,
976 .get_head
= gen6_bsd_ring_get_head
,
977 .get_tail
= gen6_bsd_ring_get_tail
,
978 .set_tail
= gen6_bsd_ring_set_tail
,
979 .get_active_head
= gen6_bsd_ring_get_active_head
,
980 .flush
= gen6_bsd_ring_flush
,
981 .add_request
= bsd_ring_add_request
,
982 .get_gem_seqno
= bsd_ring_get_gem_seqno
,
983 .user_irq_get
= bsd_ring_get_user_irq
,
984 .user_irq_put
= bsd_ring_put_user_irq
,
985 .dispatch_gem_execbuffer
= gen6_bsd_ring_dispatch_gem_execbuffer
,
986 .status_page
= {NULL
, 0, NULL
},
990 int intel_init_render_ring_buffer(struct drm_device
*dev
)
992 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
994 dev_priv
->render_ring
= render_ring
;
996 if (!I915_NEED_GFX_HWS(dev
)) {
997 dev_priv
->render_ring
.status_page
.page_addr
998 = dev_priv
->status_page_dmah
->vaddr
;
999 memset(dev_priv
->render_ring
.status_page
.page_addr
,
1003 return intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
1006 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1008 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1011 dev_priv
->bsd_ring
= gen6_bsd_ring
;
1013 dev_priv
->bsd_ring
= bsd_ring
;
1015 return intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);