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drm/i915: Abstract the legacy workload submission mechanism away
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
37 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
38 * to give some inclination as to some of the magic values used in the various
39 * workarounds!
40 */
41 #define CACHELINE_BYTES 64
42
43 static inline int __ring_space(int head, int tail, int size)
44 {
45 int space = head - (tail + I915_RING_FREE_SPACE);
46 if (space < 0)
47 space += size;
48 return space;
49 }
50
51 static inline int ring_space(struct intel_ringbuffer *ringbuf)
52 {
53 return __ring_space(ringbuf->head & HEAD_ADDR, ringbuf->tail, ringbuf->size);
54 }
55
56 static bool intel_ring_stopped(struct intel_engine_cs *ring)
57 {
58 struct drm_i915_private *dev_priv = ring->dev->dev_private;
59 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
60 }
61
62 void __intel_ring_advance(struct intel_engine_cs *ring)
63 {
64 struct intel_ringbuffer *ringbuf = ring->buffer;
65 ringbuf->tail &= ringbuf->size - 1;
66 if (intel_ring_stopped(ring))
67 return;
68 ring->write_tail(ring, ringbuf->tail);
69 }
70
71 static int
72 gen2_render_ring_flush(struct intel_engine_cs *ring,
73 u32 invalidate_domains,
74 u32 flush_domains)
75 {
76 u32 cmd;
77 int ret;
78
79 cmd = MI_FLUSH;
80 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
81 cmd |= MI_NO_WRITE_FLUSH;
82
83 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
84 cmd |= MI_READ_FLUSH;
85
86 ret = intel_ring_begin(ring, 2);
87 if (ret)
88 return ret;
89
90 intel_ring_emit(ring, cmd);
91 intel_ring_emit(ring, MI_NOOP);
92 intel_ring_advance(ring);
93
94 return 0;
95 }
96
97 static int
98 gen4_render_ring_flush(struct intel_engine_cs *ring,
99 u32 invalidate_domains,
100 u32 flush_domains)
101 {
102 struct drm_device *dev = ring->dev;
103 u32 cmd;
104 int ret;
105
106 /*
107 * read/write caches:
108 *
109 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
110 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
111 * also flushed at 2d versus 3d pipeline switches.
112 *
113 * read-only caches:
114 *
115 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
116 * MI_READ_FLUSH is set, and is always flushed on 965.
117 *
118 * I915_GEM_DOMAIN_COMMAND may not exist?
119 *
120 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
121 * invalidated when MI_EXE_FLUSH is set.
122 *
123 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
124 * invalidated with every MI_FLUSH.
125 *
126 * TLBs:
127 *
128 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
129 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
130 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
131 * are flushed at any MI_FLUSH.
132 */
133
134 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
135 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
136 cmd &= ~MI_NO_WRITE_FLUSH;
137 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
138 cmd |= MI_EXE_FLUSH;
139
140 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
141 (IS_G4X(dev) || IS_GEN5(dev)))
142 cmd |= MI_INVALIDATE_ISP;
143
144 ret = intel_ring_begin(ring, 2);
145 if (ret)
146 return ret;
147
148 intel_ring_emit(ring, cmd);
149 intel_ring_emit(ring, MI_NOOP);
150 intel_ring_advance(ring);
151
152 return 0;
153 }
154
155 /**
156 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
157 * implementing two workarounds on gen6. From section 1.4.7.1
158 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
159 *
160 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
161 * produced by non-pipelined state commands), software needs to first
162 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
163 * 0.
164 *
165 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
166 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
167 *
168 * And the workaround for these two requires this workaround first:
169 *
170 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
171 * BEFORE the pipe-control with a post-sync op and no write-cache
172 * flushes.
173 *
174 * And this last workaround is tricky because of the requirements on
175 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
176 * volume 2 part 1:
177 *
178 * "1 of the following must also be set:
179 * - Render Target Cache Flush Enable ([12] of DW1)
180 * - Depth Cache Flush Enable ([0] of DW1)
181 * - Stall at Pixel Scoreboard ([1] of DW1)
182 * - Depth Stall ([13] of DW1)
183 * - Post-Sync Operation ([13] of DW1)
184 * - Notify Enable ([8] of DW1)"
185 *
186 * The cache flushes require the workaround flush that triggered this
187 * one, so we can't use it. Depth stall would trigger the same.
188 * Post-sync nonzero is what triggered this second workaround, so we
189 * can't use that one either. Notify enable is IRQs, which aren't
190 * really our business. That leaves only stall at scoreboard.
191 */
192 static int
193 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
194 {
195 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
196 int ret;
197
198
199 ret = intel_ring_begin(ring, 6);
200 if (ret)
201 return ret;
202
203 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
204 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
205 PIPE_CONTROL_STALL_AT_SCOREBOARD);
206 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
207 intel_ring_emit(ring, 0); /* low dword */
208 intel_ring_emit(ring, 0); /* high dword */
209 intel_ring_emit(ring, MI_NOOP);
210 intel_ring_advance(ring);
211
212 ret = intel_ring_begin(ring, 6);
213 if (ret)
214 return ret;
215
216 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
217 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
218 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
219 intel_ring_emit(ring, 0);
220 intel_ring_emit(ring, 0);
221 intel_ring_emit(ring, MI_NOOP);
222 intel_ring_advance(ring);
223
224 return 0;
225 }
226
227 static int
228 gen6_render_ring_flush(struct intel_engine_cs *ring,
229 u32 invalidate_domains, u32 flush_domains)
230 {
231 u32 flags = 0;
232 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
233 int ret;
234
235 /* Force SNB workarounds for PIPE_CONTROL flushes */
236 ret = intel_emit_post_sync_nonzero_flush(ring);
237 if (ret)
238 return ret;
239
240 /* Just flush everything. Experiments have shown that reducing the
241 * number of bits based on the write domains has little performance
242 * impact.
243 */
244 if (flush_domains) {
245 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
246 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
247 /*
248 * Ensure that any following seqno writes only happen
249 * when the render cache is indeed flushed.
250 */
251 flags |= PIPE_CONTROL_CS_STALL;
252 }
253 if (invalidate_domains) {
254 flags |= PIPE_CONTROL_TLB_INVALIDATE;
255 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
256 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
257 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
258 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
259 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
260 /*
261 * TLB invalidate requires a post-sync write.
262 */
263 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
264 }
265
266 ret = intel_ring_begin(ring, 4);
267 if (ret)
268 return ret;
269
270 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
271 intel_ring_emit(ring, flags);
272 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
273 intel_ring_emit(ring, 0);
274 intel_ring_advance(ring);
275
276 return 0;
277 }
278
279 static int
280 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
281 {
282 int ret;
283
284 ret = intel_ring_begin(ring, 4);
285 if (ret)
286 return ret;
287
288 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
289 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
290 PIPE_CONTROL_STALL_AT_SCOREBOARD);
291 intel_ring_emit(ring, 0);
292 intel_ring_emit(ring, 0);
293 intel_ring_advance(ring);
294
295 return 0;
296 }
297
298 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
299 {
300 int ret;
301
302 if (!ring->fbc_dirty)
303 return 0;
304
305 ret = intel_ring_begin(ring, 6);
306 if (ret)
307 return ret;
308 /* WaFbcNukeOn3DBlt:ivb/hsw */
309 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
310 intel_ring_emit(ring, MSG_FBC_REND_STATE);
311 intel_ring_emit(ring, value);
312 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
313 intel_ring_emit(ring, MSG_FBC_REND_STATE);
314 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
315 intel_ring_advance(ring);
316
317 ring->fbc_dirty = false;
318 return 0;
319 }
320
321 static int
322 gen7_render_ring_flush(struct intel_engine_cs *ring,
323 u32 invalidate_domains, u32 flush_domains)
324 {
325 u32 flags = 0;
326 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
327 int ret;
328
329 /*
330 * Ensure that any following seqno writes only happen when the render
331 * cache is indeed flushed.
332 *
333 * Workaround: 4th PIPE_CONTROL command (except the ones with only
334 * read-cache invalidate bits set) must have the CS_STALL bit set. We
335 * don't try to be clever and just set it unconditionally.
336 */
337 flags |= PIPE_CONTROL_CS_STALL;
338
339 /* Just flush everything. Experiments have shown that reducing the
340 * number of bits based on the write domains has little performance
341 * impact.
342 */
343 if (flush_domains) {
344 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
345 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
346 }
347 if (invalidate_domains) {
348 flags |= PIPE_CONTROL_TLB_INVALIDATE;
349 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
353 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
354 /*
355 * TLB invalidate requires a post-sync write.
356 */
357 flags |= PIPE_CONTROL_QW_WRITE;
358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
359
360 /* Workaround: we must issue a pipe_control with CS-stall bit
361 * set before a pipe_control command that has the state cache
362 * invalidate bit set. */
363 gen7_render_ring_cs_stall_wa(ring);
364 }
365
366 ret = intel_ring_begin(ring, 4);
367 if (ret)
368 return ret;
369
370 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
371 intel_ring_emit(ring, flags);
372 intel_ring_emit(ring, scratch_addr);
373 intel_ring_emit(ring, 0);
374 intel_ring_advance(ring);
375
376 if (!invalidate_domains && flush_domains)
377 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
378
379 return 0;
380 }
381
382 static int
383 gen8_emit_pipe_control(struct intel_engine_cs *ring,
384 u32 flags, u32 scratch_addr)
385 {
386 int ret;
387
388 ret = intel_ring_begin(ring, 6);
389 if (ret)
390 return ret;
391
392 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
393 intel_ring_emit(ring, flags);
394 intel_ring_emit(ring, scratch_addr);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_emit(ring, 0);
398 intel_ring_advance(ring);
399
400 return 0;
401 }
402
403 static int
404 gen8_render_ring_flush(struct intel_engine_cs *ring,
405 u32 invalidate_domains, u32 flush_domains)
406 {
407 u32 flags = 0;
408 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
409 int ret;
410
411 flags |= PIPE_CONTROL_CS_STALL;
412
413 if (flush_domains) {
414 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
415 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
416 }
417 if (invalidate_domains) {
418 flags |= PIPE_CONTROL_TLB_INVALIDATE;
419 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
424 flags |= PIPE_CONTROL_QW_WRITE;
425 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
426
427 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
428 ret = gen8_emit_pipe_control(ring,
429 PIPE_CONTROL_CS_STALL |
430 PIPE_CONTROL_STALL_AT_SCOREBOARD,
431 0);
432 if (ret)
433 return ret;
434 }
435
436 return gen8_emit_pipe_control(ring, flags, scratch_addr);
437 }
438
439 static void ring_write_tail(struct intel_engine_cs *ring,
440 u32 value)
441 {
442 struct drm_i915_private *dev_priv = ring->dev->dev_private;
443 I915_WRITE_TAIL(ring, value);
444 }
445
446 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
447 {
448 struct drm_i915_private *dev_priv = ring->dev->dev_private;
449 u64 acthd;
450
451 if (INTEL_INFO(ring->dev)->gen >= 8)
452 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
453 RING_ACTHD_UDW(ring->mmio_base));
454 else if (INTEL_INFO(ring->dev)->gen >= 4)
455 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
456 else
457 acthd = I915_READ(ACTHD);
458
459 return acthd;
460 }
461
462 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
463 {
464 struct drm_i915_private *dev_priv = ring->dev->dev_private;
465 u32 addr;
466
467 addr = dev_priv->status_page_dmah->busaddr;
468 if (INTEL_INFO(ring->dev)->gen >= 4)
469 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
470 I915_WRITE(HWS_PGA, addr);
471 }
472
473 static bool stop_ring(struct intel_engine_cs *ring)
474 {
475 struct drm_i915_private *dev_priv = to_i915(ring->dev);
476
477 if (!IS_GEN2(ring->dev)) {
478 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
479 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
480 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
481 /* Sometimes we observe that the idle flag is not
482 * set even though the ring is empty. So double
483 * check before giving up.
484 */
485 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
486 return false;
487 }
488 }
489
490 I915_WRITE_CTL(ring, 0);
491 I915_WRITE_HEAD(ring, 0);
492 ring->write_tail(ring, 0);
493
494 if (!IS_GEN2(ring->dev)) {
495 (void)I915_READ_CTL(ring);
496 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
497 }
498
499 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
500 }
501
502 static int init_ring_common(struct intel_engine_cs *ring)
503 {
504 struct drm_device *dev = ring->dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
506 struct intel_ringbuffer *ringbuf = ring->buffer;
507 struct drm_i915_gem_object *obj = ringbuf->obj;
508 int ret = 0;
509
510 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
511
512 if (!stop_ring(ring)) {
513 /* G45 ring initialization often fails to reset head to zero */
514 DRM_DEBUG_KMS("%s head not reset to zero "
515 "ctl %08x head %08x tail %08x start %08x\n",
516 ring->name,
517 I915_READ_CTL(ring),
518 I915_READ_HEAD(ring),
519 I915_READ_TAIL(ring),
520 I915_READ_START(ring));
521
522 if (!stop_ring(ring)) {
523 DRM_ERROR("failed to set %s head to zero "
524 "ctl %08x head %08x tail %08x start %08x\n",
525 ring->name,
526 I915_READ_CTL(ring),
527 I915_READ_HEAD(ring),
528 I915_READ_TAIL(ring),
529 I915_READ_START(ring));
530 ret = -EIO;
531 goto out;
532 }
533 }
534
535 if (I915_NEED_GFX_HWS(dev))
536 intel_ring_setup_status_page(ring);
537 else
538 ring_setup_phys_status_page(ring);
539
540 /* Enforce ordering by reading HEAD register back */
541 I915_READ_HEAD(ring);
542
543 /* Initialize the ring. This must happen _after_ we've cleared the ring
544 * registers with the above sequence (the readback of the HEAD registers
545 * also enforces ordering), otherwise the hw might lose the new ring
546 * register values. */
547 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
548 I915_WRITE_CTL(ring,
549 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
550 | RING_VALID);
551
552 /* If the head is still not zero, the ring is dead */
553 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
554 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
555 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
556 DRM_ERROR("%s initialization failed "
557 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
558 ring->name,
559 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
560 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
561 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
562 ret = -EIO;
563 goto out;
564 }
565
566 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
567 i915_kernel_lost_context(ring->dev);
568 else {
569 ringbuf->head = I915_READ_HEAD(ring);
570 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
571 ringbuf->space = ring_space(ringbuf);
572 ringbuf->last_retired_head = -1;
573 }
574
575 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
576
577 out:
578 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
579
580 return ret;
581 }
582
583 static int
584 init_pipe_control(struct intel_engine_cs *ring)
585 {
586 int ret;
587
588 if (ring->scratch.obj)
589 return 0;
590
591 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
592 if (ring->scratch.obj == NULL) {
593 DRM_ERROR("Failed to allocate seqno page\n");
594 ret = -ENOMEM;
595 goto err;
596 }
597
598 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
599 if (ret)
600 goto err_unref;
601
602 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
603 if (ret)
604 goto err_unref;
605
606 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
607 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
608 if (ring->scratch.cpu_page == NULL) {
609 ret = -ENOMEM;
610 goto err_unpin;
611 }
612
613 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
614 ring->name, ring->scratch.gtt_offset);
615 return 0;
616
617 err_unpin:
618 i915_gem_object_ggtt_unpin(ring->scratch.obj);
619 err_unref:
620 drm_gem_object_unreference(&ring->scratch.obj->base);
621 err:
622 return ret;
623 }
624
625 static int init_render_ring(struct intel_engine_cs *ring)
626 {
627 struct drm_device *dev = ring->dev;
628 struct drm_i915_private *dev_priv = dev->dev_private;
629 int ret = init_ring_common(ring);
630 if (ret)
631 return ret;
632
633 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
634 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
635 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
636
637 /* We need to disable the AsyncFlip performance optimisations in order
638 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
639 * programmed to '1' on all products.
640 *
641 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
642 */
643 if (INTEL_INFO(dev)->gen >= 6)
644 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
645
646 /* Required for the hardware to program scanline values for waiting */
647 /* WaEnableFlushTlbInvalidationMode:snb */
648 if (INTEL_INFO(dev)->gen == 6)
649 I915_WRITE(GFX_MODE,
650 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
651
652 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
653 if (IS_GEN7(dev))
654 I915_WRITE(GFX_MODE_GEN7,
655 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
656 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
657
658 if (INTEL_INFO(dev)->gen >= 5) {
659 ret = init_pipe_control(ring);
660 if (ret)
661 return ret;
662 }
663
664 if (IS_GEN6(dev)) {
665 /* From the Sandybridge PRM, volume 1 part 3, page 24:
666 * "If this bit is set, STCunit will have LRA as replacement
667 * policy. [...] This bit must be reset. LRA replacement
668 * policy is not supported."
669 */
670 I915_WRITE(CACHE_MODE_0,
671 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
672 }
673
674 if (INTEL_INFO(dev)->gen >= 6)
675 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
676
677 if (HAS_L3_DPF(dev))
678 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
679
680 return ret;
681 }
682
683 static void render_ring_cleanup(struct intel_engine_cs *ring)
684 {
685 struct drm_device *dev = ring->dev;
686 struct drm_i915_private *dev_priv = dev->dev_private;
687
688 if (dev_priv->semaphore_obj) {
689 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
690 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
691 dev_priv->semaphore_obj = NULL;
692 }
693
694 if (ring->scratch.obj == NULL)
695 return;
696
697 if (INTEL_INFO(dev)->gen >= 5) {
698 kunmap(sg_page(ring->scratch.obj->pages->sgl));
699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
700 }
701
702 drm_gem_object_unreference(&ring->scratch.obj->base);
703 ring->scratch.obj = NULL;
704 }
705
706 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
707 unsigned int num_dwords)
708 {
709 #define MBOX_UPDATE_DWORDS 8
710 struct drm_device *dev = signaller->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
712 struct intel_engine_cs *waiter;
713 int i, ret, num_rings;
714
715 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
716 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
717 #undef MBOX_UPDATE_DWORDS
718
719 ret = intel_ring_begin(signaller, num_dwords);
720 if (ret)
721 return ret;
722
723 for_each_ring(waiter, dev_priv, i) {
724 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
725 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
726 continue;
727
728 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
729 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
730 PIPE_CONTROL_QW_WRITE |
731 PIPE_CONTROL_FLUSH_ENABLE);
732 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
733 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
734 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
735 intel_ring_emit(signaller, 0);
736 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
737 MI_SEMAPHORE_TARGET(waiter->id));
738 intel_ring_emit(signaller, 0);
739 }
740
741 return 0;
742 }
743
744 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
745 unsigned int num_dwords)
746 {
747 #define MBOX_UPDATE_DWORDS 6
748 struct drm_device *dev = signaller->dev;
749 struct drm_i915_private *dev_priv = dev->dev_private;
750 struct intel_engine_cs *waiter;
751 int i, ret, num_rings;
752
753 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
754 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
755 #undef MBOX_UPDATE_DWORDS
756
757 ret = intel_ring_begin(signaller, num_dwords);
758 if (ret)
759 return ret;
760
761 for_each_ring(waiter, dev_priv, i) {
762 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
763 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
764 continue;
765
766 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
767 MI_FLUSH_DW_OP_STOREDW);
768 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
769 MI_FLUSH_DW_USE_GTT);
770 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
771 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
772 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
773 MI_SEMAPHORE_TARGET(waiter->id));
774 intel_ring_emit(signaller, 0);
775 }
776
777 return 0;
778 }
779
780 static int gen6_signal(struct intel_engine_cs *signaller,
781 unsigned int num_dwords)
782 {
783 struct drm_device *dev = signaller->dev;
784 struct drm_i915_private *dev_priv = dev->dev_private;
785 struct intel_engine_cs *useless;
786 int i, ret, num_rings;
787
788 #define MBOX_UPDATE_DWORDS 3
789 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
790 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
791 #undef MBOX_UPDATE_DWORDS
792
793 ret = intel_ring_begin(signaller, num_dwords);
794 if (ret)
795 return ret;
796
797 for_each_ring(useless, dev_priv, i) {
798 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
799 if (mbox_reg != GEN6_NOSYNC) {
800 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
801 intel_ring_emit(signaller, mbox_reg);
802 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
803 }
804 }
805
806 /* If num_dwords was rounded, make sure the tail pointer is correct */
807 if (num_rings % 2 == 0)
808 intel_ring_emit(signaller, MI_NOOP);
809
810 return 0;
811 }
812
813 /**
814 * gen6_add_request - Update the semaphore mailbox registers
815 *
816 * @ring - ring that is adding a request
817 * @seqno - return seqno stuck into the ring
818 *
819 * Update the mailbox registers in the *other* rings with the current seqno.
820 * This acts like a signal in the canonical semaphore.
821 */
822 static int
823 gen6_add_request(struct intel_engine_cs *ring)
824 {
825 int ret;
826
827 if (ring->semaphore.signal)
828 ret = ring->semaphore.signal(ring, 4);
829 else
830 ret = intel_ring_begin(ring, 4);
831
832 if (ret)
833 return ret;
834
835 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
836 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
837 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
838 intel_ring_emit(ring, MI_USER_INTERRUPT);
839 __intel_ring_advance(ring);
840
841 return 0;
842 }
843
844 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
845 u32 seqno)
846 {
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 return dev_priv->last_seqno < seqno;
849 }
850
851 /**
852 * intel_ring_sync - sync the waiter to the signaller on seqno
853 *
854 * @waiter - ring that is waiting
855 * @signaller - ring which has, or will signal
856 * @seqno - seqno which the waiter will block on
857 */
858
859 static int
860 gen8_ring_sync(struct intel_engine_cs *waiter,
861 struct intel_engine_cs *signaller,
862 u32 seqno)
863 {
864 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
865 int ret;
866
867 ret = intel_ring_begin(waiter, 4);
868 if (ret)
869 return ret;
870
871 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
872 MI_SEMAPHORE_GLOBAL_GTT |
873 MI_SEMAPHORE_POLL |
874 MI_SEMAPHORE_SAD_GTE_SDD);
875 intel_ring_emit(waiter, seqno);
876 intel_ring_emit(waiter,
877 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
878 intel_ring_emit(waiter,
879 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
880 intel_ring_advance(waiter);
881 return 0;
882 }
883
884 static int
885 gen6_ring_sync(struct intel_engine_cs *waiter,
886 struct intel_engine_cs *signaller,
887 u32 seqno)
888 {
889 u32 dw1 = MI_SEMAPHORE_MBOX |
890 MI_SEMAPHORE_COMPARE |
891 MI_SEMAPHORE_REGISTER;
892 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
893 int ret;
894
895 /* Throughout all of the GEM code, seqno passed implies our current
896 * seqno is >= the last seqno executed. However for hardware the
897 * comparison is strictly greater than.
898 */
899 seqno -= 1;
900
901 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
902
903 ret = intel_ring_begin(waiter, 4);
904 if (ret)
905 return ret;
906
907 /* If seqno wrap happened, omit the wait with no-ops */
908 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
909 intel_ring_emit(waiter, dw1 | wait_mbox);
910 intel_ring_emit(waiter, seqno);
911 intel_ring_emit(waiter, 0);
912 intel_ring_emit(waiter, MI_NOOP);
913 } else {
914 intel_ring_emit(waiter, MI_NOOP);
915 intel_ring_emit(waiter, MI_NOOP);
916 intel_ring_emit(waiter, MI_NOOP);
917 intel_ring_emit(waiter, MI_NOOP);
918 }
919 intel_ring_advance(waiter);
920
921 return 0;
922 }
923
924 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
925 do { \
926 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
927 PIPE_CONTROL_DEPTH_STALL); \
928 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
929 intel_ring_emit(ring__, 0); \
930 intel_ring_emit(ring__, 0); \
931 } while (0)
932
933 static int
934 pc_render_add_request(struct intel_engine_cs *ring)
935 {
936 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
937 int ret;
938
939 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
940 * incoherent with writes to memory, i.e. completely fubar,
941 * so we need to use PIPE_NOTIFY instead.
942 *
943 * However, we also need to workaround the qword write
944 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
945 * memory before requesting an interrupt.
946 */
947 ret = intel_ring_begin(ring, 32);
948 if (ret)
949 return ret;
950
951 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
952 PIPE_CONTROL_WRITE_FLUSH |
953 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
954 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
955 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
956 intel_ring_emit(ring, 0);
957 PIPE_CONTROL_FLUSH(ring, scratch_addr);
958 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
959 PIPE_CONTROL_FLUSH(ring, scratch_addr);
960 scratch_addr += 2 * CACHELINE_BYTES;
961 PIPE_CONTROL_FLUSH(ring, scratch_addr);
962 scratch_addr += 2 * CACHELINE_BYTES;
963 PIPE_CONTROL_FLUSH(ring, scratch_addr);
964 scratch_addr += 2 * CACHELINE_BYTES;
965 PIPE_CONTROL_FLUSH(ring, scratch_addr);
966 scratch_addr += 2 * CACHELINE_BYTES;
967 PIPE_CONTROL_FLUSH(ring, scratch_addr);
968
969 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
970 PIPE_CONTROL_WRITE_FLUSH |
971 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
972 PIPE_CONTROL_NOTIFY);
973 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
974 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
975 intel_ring_emit(ring, 0);
976 __intel_ring_advance(ring);
977
978 return 0;
979 }
980
981 static u32
982 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
983 {
984 /* Workaround to force correct ordering between irq and seqno writes on
985 * ivb (and maybe also on snb) by reading from a CS register (like
986 * ACTHD) before reading the status page. */
987 if (!lazy_coherency) {
988 struct drm_i915_private *dev_priv = ring->dev->dev_private;
989 POSTING_READ(RING_ACTHD(ring->mmio_base));
990 }
991
992 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
993 }
994
995 static u32
996 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
997 {
998 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
999 }
1000
1001 static void
1002 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1003 {
1004 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1005 }
1006
1007 static u32
1008 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1009 {
1010 return ring->scratch.cpu_page[0];
1011 }
1012
1013 static void
1014 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1015 {
1016 ring->scratch.cpu_page[0] = seqno;
1017 }
1018
1019 static bool
1020 gen5_ring_get_irq(struct intel_engine_cs *ring)
1021 {
1022 struct drm_device *dev = ring->dev;
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 unsigned long flags;
1025
1026 if (!dev->irq_enabled)
1027 return false;
1028
1029 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1030 if (ring->irq_refcount++ == 0)
1031 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1032 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1033
1034 return true;
1035 }
1036
1037 static void
1038 gen5_ring_put_irq(struct intel_engine_cs *ring)
1039 {
1040 struct drm_device *dev = ring->dev;
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 unsigned long flags;
1043
1044 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1045 if (--ring->irq_refcount == 0)
1046 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1047 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1048 }
1049
1050 static bool
1051 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1052 {
1053 struct drm_device *dev = ring->dev;
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 unsigned long flags;
1056
1057 if (!dev->irq_enabled)
1058 return false;
1059
1060 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1061 if (ring->irq_refcount++ == 0) {
1062 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1063 I915_WRITE(IMR, dev_priv->irq_mask);
1064 POSTING_READ(IMR);
1065 }
1066 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1067
1068 return true;
1069 }
1070
1071 static void
1072 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1073 {
1074 struct drm_device *dev = ring->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 unsigned long flags;
1077
1078 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1079 if (--ring->irq_refcount == 0) {
1080 dev_priv->irq_mask |= ring->irq_enable_mask;
1081 I915_WRITE(IMR, dev_priv->irq_mask);
1082 POSTING_READ(IMR);
1083 }
1084 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1085 }
1086
1087 static bool
1088 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1089 {
1090 struct drm_device *dev = ring->dev;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
1092 unsigned long flags;
1093
1094 if (!dev->irq_enabled)
1095 return false;
1096
1097 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1098 if (ring->irq_refcount++ == 0) {
1099 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1100 I915_WRITE16(IMR, dev_priv->irq_mask);
1101 POSTING_READ16(IMR);
1102 }
1103 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1104
1105 return true;
1106 }
1107
1108 static void
1109 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1110 {
1111 struct drm_device *dev = ring->dev;
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 unsigned long flags;
1114
1115 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1116 if (--ring->irq_refcount == 0) {
1117 dev_priv->irq_mask |= ring->irq_enable_mask;
1118 I915_WRITE16(IMR, dev_priv->irq_mask);
1119 POSTING_READ16(IMR);
1120 }
1121 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1122 }
1123
1124 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1125 {
1126 struct drm_device *dev = ring->dev;
1127 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1128 u32 mmio = 0;
1129
1130 /* The ring status page addresses are no longer next to the rest of
1131 * the ring registers as of gen7.
1132 */
1133 if (IS_GEN7(dev)) {
1134 switch (ring->id) {
1135 case RCS:
1136 mmio = RENDER_HWS_PGA_GEN7;
1137 break;
1138 case BCS:
1139 mmio = BLT_HWS_PGA_GEN7;
1140 break;
1141 /*
1142 * VCS2 actually doesn't exist on Gen7. Only shut up
1143 * gcc switch check warning
1144 */
1145 case VCS2:
1146 case VCS:
1147 mmio = BSD_HWS_PGA_GEN7;
1148 break;
1149 case VECS:
1150 mmio = VEBOX_HWS_PGA_GEN7;
1151 break;
1152 }
1153 } else if (IS_GEN6(ring->dev)) {
1154 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1155 } else {
1156 /* XXX: gen8 returns to sanity */
1157 mmio = RING_HWS_PGA(ring->mmio_base);
1158 }
1159
1160 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1161 POSTING_READ(mmio);
1162
1163 /*
1164 * Flush the TLB for this page
1165 *
1166 * FIXME: These two bits have disappeared on gen8, so a question
1167 * arises: do we still need this and if so how should we go about
1168 * invalidating the TLB?
1169 */
1170 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1171 u32 reg = RING_INSTPM(ring->mmio_base);
1172
1173 /* ring should be idle before issuing a sync flush*/
1174 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1175
1176 I915_WRITE(reg,
1177 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1178 INSTPM_SYNC_FLUSH));
1179 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1180 1000))
1181 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1182 ring->name);
1183 }
1184 }
1185
1186 static int
1187 bsd_ring_flush(struct intel_engine_cs *ring,
1188 u32 invalidate_domains,
1189 u32 flush_domains)
1190 {
1191 int ret;
1192
1193 ret = intel_ring_begin(ring, 2);
1194 if (ret)
1195 return ret;
1196
1197 intel_ring_emit(ring, MI_FLUSH);
1198 intel_ring_emit(ring, MI_NOOP);
1199 intel_ring_advance(ring);
1200 return 0;
1201 }
1202
1203 static int
1204 i9xx_add_request(struct intel_engine_cs *ring)
1205 {
1206 int ret;
1207
1208 ret = intel_ring_begin(ring, 4);
1209 if (ret)
1210 return ret;
1211
1212 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1213 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1214 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1215 intel_ring_emit(ring, MI_USER_INTERRUPT);
1216 __intel_ring_advance(ring);
1217
1218 return 0;
1219 }
1220
1221 static bool
1222 gen6_ring_get_irq(struct intel_engine_cs *ring)
1223 {
1224 struct drm_device *dev = ring->dev;
1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 unsigned long flags;
1227
1228 if (!dev->irq_enabled)
1229 return false;
1230
1231 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1232 if (ring->irq_refcount++ == 0) {
1233 if (HAS_L3_DPF(dev) && ring->id == RCS)
1234 I915_WRITE_IMR(ring,
1235 ~(ring->irq_enable_mask |
1236 GT_PARITY_ERROR(dev)));
1237 else
1238 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1239 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1240 }
1241 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1242
1243 return true;
1244 }
1245
1246 static void
1247 gen6_ring_put_irq(struct intel_engine_cs *ring)
1248 {
1249 struct drm_device *dev = ring->dev;
1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1254 if (--ring->irq_refcount == 0) {
1255 if (HAS_L3_DPF(dev) && ring->id == RCS)
1256 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1257 else
1258 I915_WRITE_IMR(ring, ~0);
1259 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1260 }
1261 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1262 }
1263
1264 static bool
1265 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1266 {
1267 struct drm_device *dev = ring->dev;
1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 unsigned long flags;
1270
1271 if (!dev->irq_enabled)
1272 return false;
1273
1274 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1275 if (ring->irq_refcount++ == 0) {
1276 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1277 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1278 }
1279 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1280
1281 return true;
1282 }
1283
1284 static void
1285 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1286 {
1287 struct drm_device *dev = ring->dev;
1288 struct drm_i915_private *dev_priv = dev->dev_private;
1289 unsigned long flags;
1290
1291 if (!dev->irq_enabled)
1292 return;
1293
1294 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1295 if (--ring->irq_refcount == 0) {
1296 I915_WRITE_IMR(ring, ~0);
1297 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1298 }
1299 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1300 }
1301
1302 static bool
1303 gen8_ring_get_irq(struct intel_engine_cs *ring)
1304 {
1305 struct drm_device *dev = ring->dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 unsigned long flags;
1308
1309 if (!dev->irq_enabled)
1310 return false;
1311
1312 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1313 if (ring->irq_refcount++ == 0) {
1314 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1315 I915_WRITE_IMR(ring,
1316 ~(ring->irq_enable_mask |
1317 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1318 } else {
1319 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1320 }
1321 POSTING_READ(RING_IMR(ring->mmio_base));
1322 }
1323 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1324
1325 return true;
1326 }
1327
1328 static void
1329 gen8_ring_put_irq(struct intel_engine_cs *ring)
1330 {
1331 struct drm_device *dev = ring->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1336 if (--ring->irq_refcount == 0) {
1337 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1338 I915_WRITE_IMR(ring,
1339 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1340 } else {
1341 I915_WRITE_IMR(ring, ~0);
1342 }
1343 POSTING_READ(RING_IMR(ring->mmio_base));
1344 }
1345 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1346 }
1347
1348 static int
1349 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1350 u64 offset, u32 length,
1351 unsigned flags)
1352 {
1353 int ret;
1354
1355 ret = intel_ring_begin(ring, 2);
1356 if (ret)
1357 return ret;
1358
1359 intel_ring_emit(ring,
1360 MI_BATCH_BUFFER_START |
1361 MI_BATCH_GTT |
1362 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1363 intel_ring_emit(ring, offset);
1364 intel_ring_advance(ring);
1365
1366 return 0;
1367 }
1368
1369 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1370 #define I830_BATCH_LIMIT (256*1024)
1371 static int
1372 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1373 u64 offset, u32 len,
1374 unsigned flags)
1375 {
1376 int ret;
1377
1378 if (flags & I915_DISPATCH_PINNED) {
1379 ret = intel_ring_begin(ring, 4);
1380 if (ret)
1381 return ret;
1382
1383 intel_ring_emit(ring, MI_BATCH_BUFFER);
1384 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1385 intel_ring_emit(ring, offset + len - 8);
1386 intel_ring_emit(ring, MI_NOOP);
1387 intel_ring_advance(ring);
1388 } else {
1389 u32 cs_offset = ring->scratch.gtt_offset;
1390
1391 if (len > I830_BATCH_LIMIT)
1392 return -ENOSPC;
1393
1394 ret = intel_ring_begin(ring, 9+3);
1395 if (ret)
1396 return ret;
1397 /* Blit the batch (which has now all relocs applied) to the stable batch
1398 * scratch bo area (so that the CS never stumbles over its tlb
1399 * invalidation bug) ... */
1400 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1401 XY_SRC_COPY_BLT_WRITE_ALPHA |
1402 XY_SRC_COPY_BLT_WRITE_RGB);
1403 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1404 intel_ring_emit(ring, 0);
1405 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1406 intel_ring_emit(ring, cs_offset);
1407 intel_ring_emit(ring, 0);
1408 intel_ring_emit(ring, 4096);
1409 intel_ring_emit(ring, offset);
1410 intel_ring_emit(ring, MI_FLUSH);
1411
1412 /* ... and execute it. */
1413 intel_ring_emit(ring, MI_BATCH_BUFFER);
1414 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1415 intel_ring_emit(ring, cs_offset + len - 8);
1416 intel_ring_advance(ring);
1417 }
1418
1419 return 0;
1420 }
1421
1422 static int
1423 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1424 u64 offset, u32 len,
1425 unsigned flags)
1426 {
1427 int ret;
1428
1429 ret = intel_ring_begin(ring, 2);
1430 if (ret)
1431 return ret;
1432
1433 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1434 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1435 intel_ring_advance(ring);
1436
1437 return 0;
1438 }
1439
1440 static void cleanup_status_page(struct intel_engine_cs *ring)
1441 {
1442 struct drm_i915_gem_object *obj;
1443
1444 obj = ring->status_page.obj;
1445 if (obj == NULL)
1446 return;
1447
1448 kunmap(sg_page(obj->pages->sgl));
1449 i915_gem_object_ggtt_unpin(obj);
1450 drm_gem_object_unreference(&obj->base);
1451 ring->status_page.obj = NULL;
1452 }
1453
1454 static int init_status_page(struct intel_engine_cs *ring)
1455 {
1456 struct drm_i915_gem_object *obj;
1457
1458 if ((obj = ring->status_page.obj) == NULL) {
1459 unsigned flags;
1460 int ret;
1461
1462 obj = i915_gem_alloc_object(ring->dev, 4096);
1463 if (obj == NULL) {
1464 DRM_ERROR("Failed to allocate status page\n");
1465 return -ENOMEM;
1466 }
1467
1468 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1469 if (ret)
1470 goto err_unref;
1471
1472 flags = 0;
1473 if (!HAS_LLC(ring->dev))
1474 /* On g33, we cannot place HWS above 256MiB, so
1475 * restrict its pinning to the low mappable arena.
1476 * Though this restriction is not documented for
1477 * gen4, gen5, or byt, they also behave similarly
1478 * and hang if the HWS is placed at the top of the
1479 * GTT. To generalise, it appears that all !llc
1480 * platforms have issues with us placing the HWS
1481 * above the mappable region (even though we never
1482 * actualy map it).
1483 */
1484 flags |= PIN_MAPPABLE;
1485 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1486 if (ret) {
1487 err_unref:
1488 drm_gem_object_unreference(&obj->base);
1489 return ret;
1490 }
1491
1492 ring->status_page.obj = obj;
1493 }
1494
1495 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1496 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1497 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1498
1499 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1500 ring->name, ring->status_page.gfx_addr);
1501
1502 return 0;
1503 }
1504
1505 static int init_phys_status_page(struct intel_engine_cs *ring)
1506 {
1507 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1508
1509 if (!dev_priv->status_page_dmah) {
1510 dev_priv->status_page_dmah =
1511 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1512 if (!dev_priv->status_page_dmah)
1513 return -ENOMEM;
1514 }
1515
1516 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1517 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1518
1519 return 0;
1520 }
1521
1522 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1523 {
1524 if (!ringbuf->obj)
1525 return;
1526
1527 iounmap(ringbuf->virtual_start);
1528 i915_gem_object_ggtt_unpin(ringbuf->obj);
1529 drm_gem_object_unreference(&ringbuf->obj->base);
1530 ringbuf->obj = NULL;
1531 }
1532
1533 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1534 struct intel_ringbuffer *ringbuf)
1535 {
1536 struct drm_i915_private *dev_priv = to_i915(dev);
1537 struct drm_i915_gem_object *obj;
1538 int ret;
1539
1540 if (ringbuf->obj)
1541 return 0;
1542
1543 obj = NULL;
1544 if (!HAS_LLC(dev))
1545 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1546 if (obj == NULL)
1547 obj = i915_gem_alloc_object(dev, ringbuf->size);
1548 if (obj == NULL)
1549 return -ENOMEM;
1550
1551 /* mark ring buffers as read-only from GPU side by default */
1552 obj->gt_ro = 1;
1553
1554 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1555 if (ret)
1556 goto err_unref;
1557
1558 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1559 if (ret)
1560 goto err_unpin;
1561
1562 ringbuf->virtual_start =
1563 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1564 ringbuf->size);
1565 if (ringbuf->virtual_start == NULL) {
1566 ret = -EINVAL;
1567 goto err_unpin;
1568 }
1569
1570 ringbuf->obj = obj;
1571 return 0;
1572
1573 err_unpin:
1574 i915_gem_object_ggtt_unpin(obj);
1575 err_unref:
1576 drm_gem_object_unreference(&obj->base);
1577 return ret;
1578 }
1579
1580 static int intel_init_ring_buffer(struct drm_device *dev,
1581 struct intel_engine_cs *ring)
1582 {
1583 struct intel_ringbuffer *ringbuf = ring->buffer;
1584 int ret;
1585
1586 if (ringbuf == NULL) {
1587 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1588 if (!ringbuf)
1589 return -ENOMEM;
1590 ring->buffer = ringbuf;
1591 }
1592
1593 ring->dev = dev;
1594 INIT_LIST_HEAD(&ring->active_list);
1595 INIT_LIST_HEAD(&ring->request_list);
1596 ringbuf->size = 32 * PAGE_SIZE;
1597 ringbuf->ring = ring;
1598 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1599
1600 init_waitqueue_head(&ring->irq_queue);
1601
1602 if (I915_NEED_GFX_HWS(dev)) {
1603 ret = init_status_page(ring);
1604 if (ret)
1605 goto error;
1606 } else {
1607 BUG_ON(ring->id != RCS);
1608 ret = init_phys_status_page(ring);
1609 if (ret)
1610 goto error;
1611 }
1612
1613 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1614 if (ret) {
1615 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1616 goto error;
1617 }
1618
1619 /* Workaround an erratum on the i830 which causes a hang if
1620 * the TAIL pointer points to within the last 2 cachelines
1621 * of the buffer.
1622 */
1623 ringbuf->effective_size = ringbuf->size;
1624 if (IS_I830(dev) || IS_845G(dev))
1625 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1626
1627 ret = i915_cmd_parser_init_ring(ring);
1628 if (ret)
1629 goto error;
1630
1631 ret = ring->init(ring);
1632 if (ret)
1633 goto error;
1634
1635 return 0;
1636
1637 error:
1638 kfree(ringbuf);
1639 ring->buffer = NULL;
1640 return ret;
1641 }
1642
1643 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1644 {
1645 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1646 struct intel_ringbuffer *ringbuf = ring->buffer;
1647
1648 if (!intel_ring_initialized(ring))
1649 return;
1650
1651 intel_stop_ring_buffer(ring);
1652 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1653
1654 intel_destroy_ringbuffer_obj(ringbuf);
1655 ring->preallocated_lazy_request = NULL;
1656 ring->outstanding_lazy_seqno = 0;
1657
1658 if (ring->cleanup)
1659 ring->cleanup(ring);
1660
1661 cleanup_status_page(ring);
1662
1663 i915_cmd_parser_fini_ring(ring);
1664
1665 kfree(ringbuf);
1666 ring->buffer = NULL;
1667 }
1668
1669 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1670 {
1671 struct intel_ringbuffer *ringbuf = ring->buffer;
1672 struct drm_i915_gem_request *request;
1673 u32 seqno = 0;
1674 int ret;
1675
1676 if (ringbuf->last_retired_head != -1) {
1677 ringbuf->head = ringbuf->last_retired_head;
1678 ringbuf->last_retired_head = -1;
1679
1680 ringbuf->space = ring_space(ringbuf);
1681 if (ringbuf->space >= n)
1682 return 0;
1683 }
1684
1685 list_for_each_entry(request, &ring->request_list, list) {
1686 if (__ring_space(request->tail, ringbuf->tail, ringbuf->size) >= n) {
1687 seqno = request->seqno;
1688 break;
1689 }
1690 }
1691
1692 if (seqno == 0)
1693 return -ENOSPC;
1694
1695 ret = i915_wait_seqno(ring, seqno);
1696 if (ret)
1697 return ret;
1698
1699 i915_gem_retire_requests_ring(ring);
1700 ringbuf->head = ringbuf->last_retired_head;
1701 ringbuf->last_retired_head = -1;
1702
1703 ringbuf->space = ring_space(ringbuf);
1704 return 0;
1705 }
1706
1707 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1708 {
1709 struct drm_device *dev = ring->dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 struct intel_ringbuffer *ringbuf = ring->buffer;
1712 unsigned long end;
1713 int ret;
1714
1715 ret = intel_ring_wait_request(ring, n);
1716 if (ret != -ENOSPC)
1717 return ret;
1718
1719 /* force the tail write in case we have been skipping them */
1720 __intel_ring_advance(ring);
1721
1722 /* With GEM the hangcheck timer should kick us out of the loop,
1723 * leaving it early runs the risk of corrupting GEM state (due
1724 * to running on almost untested codepaths). But on resume
1725 * timers don't work yet, so prevent a complete hang in that
1726 * case by choosing an insanely large timeout. */
1727 end = jiffies + 60 * HZ;
1728
1729 trace_i915_ring_wait_begin(ring);
1730 do {
1731 ringbuf->head = I915_READ_HEAD(ring);
1732 ringbuf->space = ring_space(ringbuf);
1733 if (ringbuf->space >= n) {
1734 ret = 0;
1735 break;
1736 }
1737
1738 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1739 dev->primary->master) {
1740 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1741 if (master_priv->sarea_priv)
1742 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1743 }
1744
1745 msleep(1);
1746
1747 if (dev_priv->mm.interruptible && signal_pending(current)) {
1748 ret = -ERESTARTSYS;
1749 break;
1750 }
1751
1752 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1753 dev_priv->mm.interruptible);
1754 if (ret)
1755 break;
1756
1757 if (time_after(jiffies, end)) {
1758 ret = -EBUSY;
1759 break;
1760 }
1761 } while (1);
1762 trace_i915_ring_wait_end(ring);
1763 return ret;
1764 }
1765
1766 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1767 {
1768 uint32_t __iomem *virt;
1769 struct intel_ringbuffer *ringbuf = ring->buffer;
1770 int rem = ringbuf->size - ringbuf->tail;
1771
1772 if (ringbuf->space < rem) {
1773 int ret = ring_wait_for_space(ring, rem);
1774 if (ret)
1775 return ret;
1776 }
1777
1778 virt = ringbuf->virtual_start + ringbuf->tail;
1779 rem /= 4;
1780 while (rem--)
1781 iowrite32(MI_NOOP, virt++);
1782
1783 ringbuf->tail = 0;
1784 ringbuf->space = ring_space(ringbuf);
1785
1786 return 0;
1787 }
1788
1789 int intel_ring_idle(struct intel_engine_cs *ring)
1790 {
1791 u32 seqno;
1792 int ret;
1793
1794 /* We need to add any requests required to flush the objects and ring */
1795 if (ring->outstanding_lazy_seqno) {
1796 ret = i915_add_request(ring, NULL);
1797 if (ret)
1798 return ret;
1799 }
1800
1801 /* Wait upon the last request to be completed */
1802 if (list_empty(&ring->request_list))
1803 return 0;
1804
1805 seqno = list_entry(ring->request_list.prev,
1806 struct drm_i915_gem_request,
1807 list)->seqno;
1808
1809 return i915_wait_seqno(ring, seqno);
1810 }
1811
1812 static int
1813 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
1814 {
1815 if (ring->outstanding_lazy_seqno)
1816 return 0;
1817
1818 if (ring->preallocated_lazy_request == NULL) {
1819 struct drm_i915_gem_request *request;
1820
1821 request = kmalloc(sizeof(*request), GFP_KERNEL);
1822 if (request == NULL)
1823 return -ENOMEM;
1824
1825 ring->preallocated_lazy_request = request;
1826 }
1827
1828 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1829 }
1830
1831 static int __intel_ring_prepare(struct intel_engine_cs *ring,
1832 int bytes)
1833 {
1834 struct intel_ringbuffer *ringbuf = ring->buffer;
1835 int ret;
1836
1837 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1838 ret = intel_wrap_ring_buffer(ring);
1839 if (unlikely(ret))
1840 return ret;
1841 }
1842
1843 if (unlikely(ringbuf->space < bytes)) {
1844 ret = ring_wait_for_space(ring, bytes);
1845 if (unlikely(ret))
1846 return ret;
1847 }
1848
1849 return 0;
1850 }
1851
1852 int intel_ring_begin(struct intel_engine_cs *ring,
1853 int num_dwords)
1854 {
1855 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1856 int ret;
1857
1858 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1859 dev_priv->mm.interruptible);
1860 if (ret)
1861 return ret;
1862
1863 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1864 if (ret)
1865 return ret;
1866
1867 /* Preallocate the olr before touching the ring */
1868 ret = intel_ring_alloc_seqno(ring);
1869 if (ret)
1870 return ret;
1871
1872 ring->buffer->space -= num_dwords * sizeof(uint32_t);
1873 return 0;
1874 }
1875
1876 /* Align the ring tail to a cacheline boundary */
1877 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
1878 {
1879 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1880 int ret;
1881
1882 if (num_dwords == 0)
1883 return 0;
1884
1885 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1886 ret = intel_ring_begin(ring, num_dwords);
1887 if (ret)
1888 return ret;
1889
1890 while (num_dwords--)
1891 intel_ring_emit(ring, MI_NOOP);
1892
1893 intel_ring_advance(ring);
1894
1895 return 0;
1896 }
1897
1898 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
1899 {
1900 struct drm_device *dev = ring->dev;
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902
1903 BUG_ON(ring->outstanding_lazy_seqno);
1904
1905 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
1906 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1907 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1908 if (HAS_VEBOX(dev))
1909 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1910 }
1911
1912 ring->set_seqno(ring, seqno);
1913 ring->hangcheck.seqno = seqno;
1914 }
1915
1916 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
1917 u32 value)
1918 {
1919 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1920
1921 /* Every tail move must follow the sequence below */
1922
1923 /* Disable notification that the ring is IDLE. The GT
1924 * will then assume that it is busy and bring it out of rc6.
1925 */
1926 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1927 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1928
1929 /* Clear the context id. Here be magic! */
1930 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1931
1932 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1933 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1934 GEN6_BSD_SLEEP_INDICATOR) == 0,
1935 50))
1936 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1937
1938 /* Now that the ring is fully powered up, update the tail */
1939 I915_WRITE_TAIL(ring, value);
1940 POSTING_READ(RING_TAIL(ring->mmio_base));
1941
1942 /* Let the ring send IDLE messages to the GT again,
1943 * and so let it sleep to conserve power when idle.
1944 */
1945 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1946 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1947 }
1948
1949 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
1950 u32 invalidate, u32 flush)
1951 {
1952 uint32_t cmd;
1953 int ret;
1954
1955 ret = intel_ring_begin(ring, 4);
1956 if (ret)
1957 return ret;
1958
1959 cmd = MI_FLUSH_DW;
1960 if (INTEL_INFO(ring->dev)->gen >= 8)
1961 cmd += 1;
1962 /*
1963 * Bspec vol 1c.5 - video engine command streamer:
1964 * "If ENABLED, all TLBs will be invalidated once the flush
1965 * operation is complete. This bit is only valid when the
1966 * Post-Sync Operation field is a value of 1h or 3h."
1967 */
1968 if (invalidate & I915_GEM_GPU_DOMAINS)
1969 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1970 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1971 intel_ring_emit(ring, cmd);
1972 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1973 if (INTEL_INFO(ring->dev)->gen >= 8) {
1974 intel_ring_emit(ring, 0); /* upper addr */
1975 intel_ring_emit(ring, 0); /* value */
1976 } else {
1977 intel_ring_emit(ring, 0);
1978 intel_ring_emit(ring, MI_NOOP);
1979 }
1980 intel_ring_advance(ring);
1981 return 0;
1982 }
1983
1984 static int
1985 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
1986 u64 offset, u32 len,
1987 unsigned flags)
1988 {
1989 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1990 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1991 !(flags & I915_DISPATCH_SECURE);
1992 int ret;
1993
1994 ret = intel_ring_begin(ring, 4);
1995 if (ret)
1996 return ret;
1997
1998 /* FIXME(BDW): Address space and security selectors. */
1999 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2000 intel_ring_emit(ring, lower_32_bits(offset));
2001 intel_ring_emit(ring, upper_32_bits(offset));
2002 intel_ring_emit(ring, MI_NOOP);
2003 intel_ring_advance(ring);
2004
2005 return 0;
2006 }
2007
2008 static int
2009 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2010 u64 offset, u32 len,
2011 unsigned flags)
2012 {
2013 int ret;
2014
2015 ret = intel_ring_begin(ring, 2);
2016 if (ret)
2017 return ret;
2018
2019 intel_ring_emit(ring,
2020 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
2021 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
2022 /* bit0-7 is the length on GEN6+ */
2023 intel_ring_emit(ring, offset);
2024 intel_ring_advance(ring);
2025
2026 return 0;
2027 }
2028
2029 static int
2030 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2031 u64 offset, u32 len,
2032 unsigned flags)
2033 {
2034 int ret;
2035
2036 ret = intel_ring_begin(ring, 2);
2037 if (ret)
2038 return ret;
2039
2040 intel_ring_emit(ring,
2041 MI_BATCH_BUFFER_START |
2042 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2043 /* bit0-7 is the length on GEN6+ */
2044 intel_ring_emit(ring, offset);
2045 intel_ring_advance(ring);
2046
2047 return 0;
2048 }
2049
2050 /* Blitter support (SandyBridge+) */
2051
2052 static int gen6_ring_flush(struct intel_engine_cs *ring,
2053 u32 invalidate, u32 flush)
2054 {
2055 struct drm_device *dev = ring->dev;
2056 uint32_t cmd;
2057 int ret;
2058
2059 ret = intel_ring_begin(ring, 4);
2060 if (ret)
2061 return ret;
2062
2063 cmd = MI_FLUSH_DW;
2064 if (INTEL_INFO(ring->dev)->gen >= 8)
2065 cmd += 1;
2066 /*
2067 * Bspec vol 1c.3 - blitter engine command streamer:
2068 * "If ENABLED, all TLBs will be invalidated once the flush
2069 * operation is complete. This bit is only valid when the
2070 * Post-Sync Operation field is a value of 1h or 3h."
2071 */
2072 if (invalidate & I915_GEM_DOMAIN_RENDER)
2073 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2074 MI_FLUSH_DW_OP_STOREDW;
2075 intel_ring_emit(ring, cmd);
2076 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2077 if (INTEL_INFO(ring->dev)->gen >= 8) {
2078 intel_ring_emit(ring, 0); /* upper addr */
2079 intel_ring_emit(ring, 0); /* value */
2080 } else {
2081 intel_ring_emit(ring, 0);
2082 intel_ring_emit(ring, MI_NOOP);
2083 }
2084 intel_ring_advance(ring);
2085
2086 if (IS_GEN7(dev) && !invalidate && flush)
2087 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2088
2089 return 0;
2090 }
2091
2092 int intel_init_render_ring_buffer(struct drm_device *dev)
2093 {
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2096 struct drm_i915_gem_object *obj;
2097 int ret;
2098
2099 ring->name = "render ring";
2100 ring->id = RCS;
2101 ring->mmio_base = RENDER_RING_BASE;
2102
2103 if (INTEL_INFO(dev)->gen >= 8) {
2104 if (i915_semaphore_is_enabled(dev)) {
2105 obj = i915_gem_alloc_object(dev, 4096);
2106 if (obj == NULL) {
2107 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2108 i915.semaphores = 0;
2109 } else {
2110 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2111 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2112 if (ret != 0) {
2113 drm_gem_object_unreference(&obj->base);
2114 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2115 i915.semaphores = 0;
2116 } else
2117 dev_priv->semaphore_obj = obj;
2118 }
2119 }
2120 ring->add_request = gen6_add_request;
2121 ring->flush = gen8_render_ring_flush;
2122 ring->irq_get = gen8_ring_get_irq;
2123 ring->irq_put = gen8_ring_put_irq;
2124 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2125 ring->get_seqno = gen6_ring_get_seqno;
2126 ring->set_seqno = ring_set_seqno;
2127 if (i915_semaphore_is_enabled(dev)) {
2128 WARN_ON(!dev_priv->semaphore_obj);
2129 ring->semaphore.sync_to = gen8_ring_sync;
2130 ring->semaphore.signal = gen8_rcs_signal;
2131 GEN8_RING_SEMAPHORE_INIT;
2132 }
2133 } else if (INTEL_INFO(dev)->gen >= 6) {
2134 ring->add_request = gen6_add_request;
2135 ring->flush = gen7_render_ring_flush;
2136 if (INTEL_INFO(dev)->gen == 6)
2137 ring->flush = gen6_render_ring_flush;
2138 ring->irq_get = gen6_ring_get_irq;
2139 ring->irq_put = gen6_ring_put_irq;
2140 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2141 ring->get_seqno = gen6_ring_get_seqno;
2142 ring->set_seqno = ring_set_seqno;
2143 if (i915_semaphore_is_enabled(dev)) {
2144 ring->semaphore.sync_to = gen6_ring_sync;
2145 ring->semaphore.signal = gen6_signal;
2146 /*
2147 * The current semaphore is only applied on pre-gen8
2148 * platform. And there is no VCS2 ring on the pre-gen8
2149 * platform. So the semaphore between RCS and VCS2 is
2150 * initialized as INVALID. Gen8 will initialize the
2151 * sema between VCS2 and RCS later.
2152 */
2153 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2154 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2155 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2156 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2157 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2158 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2159 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2160 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2161 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2162 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2163 }
2164 } else if (IS_GEN5(dev)) {
2165 ring->add_request = pc_render_add_request;
2166 ring->flush = gen4_render_ring_flush;
2167 ring->get_seqno = pc_render_get_seqno;
2168 ring->set_seqno = pc_render_set_seqno;
2169 ring->irq_get = gen5_ring_get_irq;
2170 ring->irq_put = gen5_ring_put_irq;
2171 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2172 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2173 } else {
2174 ring->add_request = i9xx_add_request;
2175 if (INTEL_INFO(dev)->gen < 4)
2176 ring->flush = gen2_render_ring_flush;
2177 else
2178 ring->flush = gen4_render_ring_flush;
2179 ring->get_seqno = ring_get_seqno;
2180 ring->set_seqno = ring_set_seqno;
2181 if (IS_GEN2(dev)) {
2182 ring->irq_get = i8xx_ring_get_irq;
2183 ring->irq_put = i8xx_ring_put_irq;
2184 } else {
2185 ring->irq_get = i9xx_ring_get_irq;
2186 ring->irq_put = i9xx_ring_put_irq;
2187 }
2188 ring->irq_enable_mask = I915_USER_INTERRUPT;
2189 }
2190 ring->write_tail = ring_write_tail;
2191
2192 if (IS_HASWELL(dev))
2193 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2194 else if (IS_GEN8(dev))
2195 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2196 else if (INTEL_INFO(dev)->gen >= 6)
2197 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2198 else if (INTEL_INFO(dev)->gen >= 4)
2199 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2200 else if (IS_I830(dev) || IS_845G(dev))
2201 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2202 else
2203 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2204 ring->init = init_render_ring;
2205 ring->cleanup = render_ring_cleanup;
2206
2207 /* Workaround batchbuffer to combat CS tlb bug. */
2208 if (HAS_BROKEN_CS_TLB(dev)) {
2209 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
2210 if (obj == NULL) {
2211 DRM_ERROR("Failed to allocate batch bo\n");
2212 return -ENOMEM;
2213 }
2214
2215 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2216 if (ret != 0) {
2217 drm_gem_object_unreference(&obj->base);
2218 DRM_ERROR("Failed to ping batch bo\n");
2219 return ret;
2220 }
2221
2222 ring->scratch.obj = obj;
2223 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2224 }
2225
2226 return intel_init_ring_buffer(dev, ring);
2227 }
2228
2229 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2233 struct intel_ringbuffer *ringbuf = ring->buffer;
2234 int ret;
2235
2236 if (ringbuf == NULL) {
2237 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2238 if (!ringbuf)
2239 return -ENOMEM;
2240 ring->buffer = ringbuf;
2241 }
2242
2243 ring->name = "render ring";
2244 ring->id = RCS;
2245 ring->mmio_base = RENDER_RING_BASE;
2246
2247 if (INTEL_INFO(dev)->gen >= 6) {
2248 /* non-kms not supported on gen6+ */
2249 ret = -ENODEV;
2250 goto err_ringbuf;
2251 }
2252
2253 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2254 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2255 * the special gen5 functions. */
2256 ring->add_request = i9xx_add_request;
2257 if (INTEL_INFO(dev)->gen < 4)
2258 ring->flush = gen2_render_ring_flush;
2259 else
2260 ring->flush = gen4_render_ring_flush;
2261 ring->get_seqno = ring_get_seqno;
2262 ring->set_seqno = ring_set_seqno;
2263 if (IS_GEN2(dev)) {
2264 ring->irq_get = i8xx_ring_get_irq;
2265 ring->irq_put = i8xx_ring_put_irq;
2266 } else {
2267 ring->irq_get = i9xx_ring_get_irq;
2268 ring->irq_put = i9xx_ring_put_irq;
2269 }
2270 ring->irq_enable_mask = I915_USER_INTERRUPT;
2271 ring->write_tail = ring_write_tail;
2272 if (INTEL_INFO(dev)->gen >= 4)
2273 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2274 else if (IS_I830(dev) || IS_845G(dev))
2275 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2276 else
2277 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2278 ring->init = init_render_ring;
2279 ring->cleanup = render_ring_cleanup;
2280
2281 ring->dev = dev;
2282 INIT_LIST_HEAD(&ring->active_list);
2283 INIT_LIST_HEAD(&ring->request_list);
2284
2285 ringbuf->size = size;
2286 ringbuf->effective_size = ringbuf->size;
2287 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2288 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2289
2290 ringbuf->virtual_start = ioremap_wc(start, size);
2291 if (ringbuf->virtual_start == NULL) {
2292 DRM_ERROR("can not ioremap virtual address for"
2293 " ring buffer\n");
2294 ret = -ENOMEM;
2295 goto err_ringbuf;
2296 }
2297
2298 if (!I915_NEED_GFX_HWS(dev)) {
2299 ret = init_phys_status_page(ring);
2300 if (ret)
2301 goto err_vstart;
2302 }
2303
2304 return 0;
2305
2306 err_vstart:
2307 iounmap(ringbuf->virtual_start);
2308 err_ringbuf:
2309 kfree(ringbuf);
2310 ring->buffer = NULL;
2311 return ret;
2312 }
2313
2314 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2315 {
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2318
2319 ring->name = "bsd ring";
2320 ring->id = VCS;
2321
2322 ring->write_tail = ring_write_tail;
2323 if (INTEL_INFO(dev)->gen >= 6) {
2324 ring->mmio_base = GEN6_BSD_RING_BASE;
2325 /* gen6 bsd needs a special wa for tail updates */
2326 if (IS_GEN6(dev))
2327 ring->write_tail = gen6_bsd_ring_write_tail;
2328 ring->flush = gen6_bsd_ring_flush;
2329 ring->add_request = gen6_add_request;
2330 ring->get_seqno = gen6_ring_get_seqno;
2331 ring->set_seqno = ring_set_seqno;
2332 if (INTEL_INFO(dev)->gen >= 8) {
2333 ring->irq_enable_mask =
2334 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2335 ring->irq_get = gen8_ring_get_irq;
2336 ring->irq_put = gen8_ring_put_irq;
2337 ring->dispatch_execbuffer =
2338 gen8_ring_dispatch_execbuffer;
2339 if (i915_semaphore_is_enabled(dev)) {
2340 ring->semaphore.sync_to = gen8_ring_sync;
2341 ring->semaphore.signal = gen8_xcs_signal;
2342 GEN8_RING_SEMAPHORE_INIT;
2343 }
2344 } else {
2345 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2346 ring->irq_get = gen6_ring_get_irq;
2347 ring->irq_put = gen6_ring_put_irq;
2348 ring->dispatch_execbuffer =
2349 gen6_ring_dispatch_execbuffer;
2350 if (i915_semaphore_is_enabled(dev)) {
2351 ring->semaphore.sync_to = gen6_ring_sync;
2352 ring->semaphore.signal = gen6_signal;
2353 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2354 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2355 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2356 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2357 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2358 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2359 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2360 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2361 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2362 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2363 }
2364 }
2365 } else {
2366 ring->mmio_base = BSD_RING_BASE;
2367 ring->flush = bsd_ring_flush;
2368 ring->add_request = i9xx_add_request;
2369 ring->get_seqno = ring_get_seqno;
2370 ring->set_seqno = ring_set_seqno;
2371 if (IS_GEN5(dev)) {
2372 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2373 ring->irq_get = gen5_ring_get_irq;
2374 ring->irq_put = gen5_ring_put_irq;
2375 } else {
2376 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2377 ring->irq_get = i9xx_ring_get_irq;
2378 ring->irq_put = i9xx_ring_put_irq;
2379 }
2380 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2381 }
2382 ring->init = init_ring_common;
2383
2384 return intel_init_ring_buffer(dev, ring);
2385 }
2386
2387 /**
2388 * Initialize the second BSD ring for Broadwell GT3.
2389 * It is noted that this only exists on Broadwell GT3.
2390 */
2391 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2392 {
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2395
2396 if ((INTEL_INFO(dev)->gen != 8)) {
2397 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2398 return -EINVAL;
2399 }
2400
2401 ring->name = "bsd2 ring";
2402 ring->id = VCS2;
2403
2404 ring->write_tail = ring_write_tail;
2405 ring->mmio_base = GEN8_BSD2_RING_BASE;
2406 ring->flush = gen6_bsd_ring_flush;
2407 ring->add_request = gen6_add_request;
2408 ring->get_seqno = gen6_ring_get_seqno;
2409 ring->set_seqno = ring_set_seqno;
2410 ring->irq_enable_mask =
2411 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2412 ring->irq_get = gen8_ring_get_irq;
2413 ring->irq_put = gen8_ring_put_irq;
2414 ring->dispatch_execbuffer =
2415 gen8_ring_dispatch_execbuffer;
2416 if (i915_semaphore_is_enabled(dev)) {
2417 ring->semaphore.sync_to = gen8_ring_sync;
2418 ring->semaphore.signal = gen8_xcs_signal;
2419 GEN8_RING_SEMAPHORE_INIT;
2420 }
2421 ring->init = init_ring_common;
2422
2423 return intel_init_ring_buffer(dev, ring);
2424 }
2425
2426 int intel_init_blt_ring_buffer(struct drm_device *dev)
2427 {
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2430
2431 ring->name = "blitter ring";
2432 ring->id = BCS;
2433
2434 ring->mmio_base = BLT_RING_BASE;
2435 ring->write_tail = ring_write_tail;
2436 ring->flush = gen6_ring_flush;
2437 ring->add_request = gen6_add_request;
2438 ring->get_seqno = gen6_ring_get_seqno;
2439 ring->set_seqno = ring_set_seqno;
2440 if (INTEL_INFO(dev)->gen >= 8) {
2441 ring->irq_enable_mask =
2442 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2443 ring->irq_get = gen8_ring_get_irq;
2444 ring->irq_put = gen8_ring_put_irq;
2445 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2446 if (i915_semaphore_is_enabled(dev)) {
2447 ring->semaphore.sync_to = gen8_ring_sync;
2448 ring->semaphore.signal = gen8_xcs_signal;
2449 GEN8_RING_SEMAPHORE_INIT;
2450 }
2451 } else {
2452 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2453 ring->irq_get = gen6_ring_get_irq;
2454 ring->irq_put = gen6_ring_put_irq;
2455 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2456 if (i915_semaphore_is_enabled(dev)) {
2457 ring->semaphore.signal = gen6_signal;
2458 ring->semaphore.sync_to = gen6_ring_sync;
2459 /*
2460 * The current semaphore is only applied on pre-gen8
2461 * platform. And there is no VCS2 ring on the pre-gen8
2462 * platform. So the semaphore between BCS and VCS2 is
2463 * initialized as INVALID. Gen8 will initialize the
2464 * sema between BCS and VCS2 later.
2465 */
2466 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2467 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2468 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2469 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2470 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2471 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2472 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2473 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2474 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2475 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2476 }
2477 }
2478 ring->init = init_ring_common;
2479
2480 return intel_init_ring_buffer(dev, ring);
2481 }
2482
2483 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2484 {
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2487
2488 ring->name = "video enhancement ring";
2489 ring->id = VECS;
2490
2491 ring->mmio_base = VEBOX_RING_BASE;
2492 ring->write_tail = ring_write_tail;
2493 ring->flush = gen6_ring_flush;
2494 ring->add_request = gen6_add_request;
2495 ring->get_seqno = gen6_ring_get_seqno;
2496 ring->set_seqno = ring_set_seqno;
2497
2498 if (INTEL_INFO(dev)->gen >= 8) {
2499 ring->irq_enable_mask =
2500 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2501 ring->irq_get = gen8_ring_get_irq;
2502 ring->irq_put = gen8_ring_put_irq;
2503 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2504 if (i915_semaphore_is_enabled(dev)) {
2505 ring->semaphore.sync_to = gen8_ring_sync;
2506 ring->semaphore.signal = gen8_xcs_signal;
2507 GEN8_RING_SEMAPHORE_INIT;
2508 }
2509 } else {
2510 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2511 ring->irq_get = hsw_vebox_get_irq;
2512 ring->irq_put = hsw_vebox_put_irq;
2513 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2514 if (i915_semaphore_is_enabled(dev)) {
2515 ring->semaphore.sync_to = gen6_ring_sync;
2516 ring->semaphore.signal = gen6_signal;
2517 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2518 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2519 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2520 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2521 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2522 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2523 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2524 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2525 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2526 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2527 }
2528 }
2529 ring->init = init_ring_common;
2530
2531 return intel_init_ring_buffer(dev, ring);
2532 }
2533
2534 int
2535 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2536 {
2537 int ret;
2538
2539 if (!ring->gpu_caches_dirty)
2540 return 0;
2541
2542 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2543 if (ret)
2544 return ret;
2545
2546 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2547
2548 ring->gpu_caches_dirty = false;
2549 return 0;
2550 }
2551
2552 int
2553 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2554 {
2555 uint32_t flush_domains;
2556 int ret;
2557
2558 flush_domains = 0;
2559 if (ring->gpu_caches_dirty)
2560 flush_domains = I915_GEM_GPU_DOMAINS;
2561
2562 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2563 if (ret)
2564 return ret;
2565
2566 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2567
2568 ring->gpu_caches_dirty = false;
2569 return 0;
2570 }
2571
2572 void
2573 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2574 {
2575 int ret;
2576
2577 if (!intel_ring_initialized(ring))
2578 return;
2579
2580 ret = intel_ring_idle(ring);
2581 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2582 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2583 ring->name, ret);
2584
2585 stop_ring(ring);
2586 }
Linux kernel - Deliverables
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