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drm/i915: Update intel_ring_begin() to take a request structure
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 bool
37 intel_ring_initialized(struct intel_engine_cs *ring)
38 {
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51 }
52
53 int __intel_ring_space(int head, int tail, int size)
54 {
55 int space = head - tail;
56 if (space <= 0)
57 space += size;
58 return space - I915_RING_FREE_SPACE;
59 }
60
61 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62 {
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70 }
71
72 int intel_ring_space(struct intel_ringbuffer *ringbuf)
73 {
74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
76 }
77
78 bool intel_ring_stopped(struct intel_engine_cs *ring)
79 {
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82 }
83
84 static void __intel_ring_advance(struct intel_engine_cs *ring)
85 {
86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88 if (intel_ring_stopped(ring))
89 return;
90 ring->write_tail(ring, ringbuf->tail);
91 }
92
93 static int
94 gen2_render_ring_flush(struct drm_i915_gem_request *req,
95 u32 invalidate_domains,
96 u32 flush_domains)
97 {
98 struct intel_engine_cs *ring = req->ring;
99 u32 cmd;
100 int ret;
101
102 cmd = MI_FLUSH;
103 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
104 cmd |= MI_NO_WRITE_FLUSH;
105
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108
109 ret = intel_ring_begin(req, 2);
110 if (ret)
111 return ret;
112
113 intel_ring_emit(ring, cmd);
114 intel_ring_emit(ring, MI_NOOP);
115 intel_ring_advance(ring);
116
117 return 0;
118 }
119
120 static int
121 gen4_render_ring_flush(struct drm_i915_gem_request *req,
122 u32 invalidate_domains,
123 u32 flush_domains)
124 {
125 struct intel_engine_cs *ring = req->ring;
126 struct drm_device *dev = ring->dev;
127 u32 cmd;
128 int ret;
129
130 /*
131 * read/write caches:
132 *
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
136 *
137 * read-only caches:
138 *
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
141 *
142 * I915_GEM_DOMAIN_COMMAND may not exist?
143 *
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
146 *
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
149 *
150 * TLBs:
151 *
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
156 */
157
158 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
159 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
160 cmd &= ~MI_NO_WRITE_FLUSH;
161 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
162 cmd |= MI_EXE_FLUSH;
163
164 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
165 (IS_G4X(dev) || IS_GEN5(dev)))
166 cmd |= MI_INVALIDATE_ISP;
167
168 ret = intel_ring_begin(req, 2);
169 if (ret)
170 return ret;
171
172 intel_ring_emit(ring, cmd);
173 intel_ring_emit(ring, MI_NOOP);
174 intel_ring_advance(ring);
175
176 return 0;
177 }
178
179 /**
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
183 *
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
187 * 0.
188 *
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
191 *
192 * And the workaround for these two requires this workaround first:
193 *
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
196 * flushes.
197 *
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
200 * volume 2 part 1:
201 *
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
209 *
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
215 */
216 static int
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
218 {
219 struct intel_engine_cs *ring = req->ring;
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
221 int ret;
222
223 ret = intel_ring_begin(req, 6);
224 if (ret)
225 return ret;
226
227 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
229 PIPE_CONTROL_STALL_AT_SCOREBOARD);
230 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
231 intel_ring_emit(ring, 0); /* low dword */
232 intel_ring_emit(ring, 0); /* high dword */
233 intel_ring_emit(ring, MI_NOOP);
234 intel_ring_advance(ring);
235
236 ret = intel_ring_begin(req, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
243 intel_ring_emit(ring, 0);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static int
252 gen6_render_ring_flush(struct drm_i915_gem_request *req,
253 u32 invalidate_domains, u32 flush_domains)
254 {
255 struct intel_engine_cs *ring = req->ring;
256 u32 flags = 0;
257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
258 int ret;
259
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret = intel_emit_post_sync_nonzero_flush(req);
262 if (ret)
263 return ret;
264
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
267 * impact.
268 */
269 if (flush_domains) {
270 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
271 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
272 /*
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
275 */
276 flags |= PIPE_CONTROL_CS_STALL;
277 }
278 if (invalidate_domains) {
279 flags |= PIPE_CONTROL_TLB_INVALIDATE;
280 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
284 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
285 /*
286 * TLB invalidate requires a post-sync write.
287 */
288 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
289 }
290
291 ret = intel_ring_begin(req, 4);
292 if (ret)
293 return ret;
294
295 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring, flags);
297 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
298 intel_ring_emit(ring, 0);
299 intel_ring_advance(ring);
300
301 return 0;
302 }
303
304 static int
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
306 {
307 struct intel_engine_cs *ring = req->ring;
308 int ret;
309
310 ret = intel_ring_begin(req, 4);
311 if (ret)
312 return ret;
313
314 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
316 PIPE_CONTROL_STALL_AT_SCOREBOARD);
317 intel_ring_emit(ring, 0);
318 intel_ring_emit(ring, 0);
319 intel_ring_advance(ring);
320
321 return 0;
322 }
323
324 static int
325 gen7_render_ring_flush(struct drm_i915_gem_request *req,
326 u32 invalidate_domains, u32 flush_domains)
327 {
328 struct intel_engine_cs *ring = req->ring;
329 u32 flags = 0;
330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
331 int ret;
332
333 /*
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
336 *
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
340 */
341 flags |= PIPE_CONTROL_CS_STALL;
342
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
345 * impact.
346 */
347 if (flush_domains) {
348 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
349 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
350 }
351 if (invalidate_domains) {
352 flags |= PIPE_CONTROL_TLB_INVALIDATE;
353 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
354 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
355 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
356 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
357 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
358 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
359 /*
360 * TLB invalidate requires a post-sync write.
361 */
362 flags |= PIPE_CONTROL_QW_WRITE;
363 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
364
365 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
366
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req);
371 }
372
373 ret = intel_ring_begin(req, 4);
374 if (ret)
375 return ret;
376
377 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring, flags);
379 intel_ring_emit(ring, scratch_addr);
380 intel_ring_emit(ring, 0);
381 intel_ring_advance(ring);
382
383 return 0;
384 }
385
386 static int
387 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
388 u32 flags, u32 scratch_addr)
389 {
390 struct intel_engine_cs *ring = req->ring;
391 int ret;
392
393 ret = intel_ring_begin(req, 6);
394 if (ret)
395 return ret;
396
397 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring, flags);
399 intel_ring_emit(ring, scratch_addr);
400 intel_ring_emit(ring, 0);
401 intel_ring_emit(ring, 0);
402 intel_ring_emit(ring, 0);
403 intel_ring_advance(ring);
404
405 return 0;
406 }
407
408 static int
409 gen8_render_ring_flush(struct drm_i915_gem_request *req,
410 u32 invalidate_domains, u32 flush_domains)
411 {
412 u32 flags = 0;
413 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
414 int ret;
415
416 flags |= PIPE_CONTROL_CS_STALL;
417
418 if (flush_domains) {
419 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
420 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
421 }
422 if (invalidate_domains) {
423 flags |= PIPE_CONTROL_TLB_INVALIDATE;
424 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
425 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
426 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
427 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
428 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
429 flags |= PIPE_CONTROL_QW_WRITE;
430 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
431
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret = gen8_emit_pipe_control(req,
434 PIPE_CONTROL_CS_STALL |
435 PIPE_CONTROL_STALL_AT_SCOREBOARD,
436 0);
437 if (ret)
438 return ret;
439 }
440
441 return gen8_emit_pipe_control(req, flags, scratch_addr);
442 }
443
444 static void ring_write_tail(struct intel_engine_cs *ring,
445 u32 value)
446 {
447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
448 I915_WRITE_TAIL(ring, value);
449 }
450
451 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
452 {
453 struct drm_i915_private *dev_priv = ring->dev->dev_private;
454 u64 acthd;
455
456 if (INTEL_INFO(ring->dev)->gen >= 8)
457 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
458 RING_ACTHD_UDW(ring->mmio_base));
459 else if (INTEL_INFO(ring->dev)->gen >= 4)
460 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
461 else
462 acthd = I915_READ(ACTHD);
463
464 return acthd;
465 }
466
467 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
468 {
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 u32 addr;
471
472 addr = dev_priv->status_page_dmah->busaddr;
473 if (INTEL_INFO(ring->dev)->gen >= 4)
474 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
475 I915_WRITE(HWS_PGA, addr);
476 }
477
478 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
479 {
480 struct drm_device *dev = ring->dev;
481 struct drm_i915_private *dev_priv = ring->dev->dev_private;
482 u32 mmio = 0;
483
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
486 */
487 if (IS_GEN7(dev)) {
488 switch (ring->id) {
489 case RCS:
490 mmio = RENDER_HWS_PGA_GEN7;
491 break;
492 case BCS:
493 mmio = BLT_HWS_PGA_GEN7;
494 break;
495 /*
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
498 */
499 case VCS2:
500 case VCS:
501 mmio = BSD_HWS_PGA_GEN7;
502 break;
503 case VECS:
504 mmio = VEBOX_HWS_PGA_GEN7;
505 break;
506 }
507 } else if (IS_GEN6(ring->dev)) {
508 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
509 } else {
510 /* XXX: gen8 returns to sanity */
511 mmio = RING_HWS_PGA(ring->mmio_base);
512 }
513
514 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
515 POSTING_READ(mmio);
516
517 /*
518 * Flush the TLB for this page
519 *
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
523 */
524 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
525 u32 reg = RING_INSTPM(ring->mmio_base);
526
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
529
530 I915_WRITE(reg,
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
532 INSTPM_SYNC_FLUSH));
533 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
534 1000))
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
536 ring->name);
537 }
538 }
539
540 static bool stop_ring(struct intel_engine_cs *ring)
541 {
542 struct drm_i915_private *dev_priv = to_i915(ring->dev);
543
544 if (!IS_GEN2(ring->dev)) {
545 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
546 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
551 */
552 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
553 return false;
554 }
555 }
556
557 I915_WRITE_CTL(ring, 0);
558 I915_WRITE_HEAD(ring, 0);
559 ring->write_tail(ring, 0);
560
561 if (!IS_GEN2(ring->dev)) {
562 (void)I915_READ_CTL(ring);
563 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
564 }
565
566 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
567 }
568
569 static int init_ring_common(struct intel_engine_cs *ring)
570 {
571 struct drm_device *dev = ring->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
573 struct intel_ringbuffer *ringbuf = ring->buffer;
574 struct drm_i915_gem_object *obj = ringbuf->obj;
575 int ret = 0;
576
577 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
578
579 if (!stop_ring(ring)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
583 ring->name,
584 I915_READ_CTL(ring),
585 I915_READ_HEAD(ring),
586 I915_READ_TAIL(ring),
587 I915_READ_START(ring));
588
589 if (!stop_ring(ring)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
592 ring->name,
593 I915_READ_CTL(ring),
594 I915_READ_HEAD(ring),
595 I915_READ_TAIL(ring),
596 I915_READ_START(ring));
597 ret = -EIO;
598 goto out;
599 }
600 }
601
602 if (I915_NEED_GFX_HWS(dev))
603 intel_ring_setup_status_page(ring);
604 else
605 ring_setup_phys_status_page(ring);
606
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring);
609
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
615
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring->name, I915_READ_HEAD(ring));
620 I915_WRITE_HEAD(ring, 0);
621 (void)I915_READ_HEAD(ring);
622
623 I915_WRITE_CTL(ring,
624 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
625 | RING_VALID);
626
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
629 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
630 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
633 ring->name,
634 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
635 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
636 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
637 ret = -EIO;
638 goto out;
639 }
640
641 ringbuf->last_retired_head = -1;
642 ringbuf->head = I915_READ_HEAD(ring);
643 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
644 intel_ring_update_space(ringbuf);
645
646 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
647
648 out:
649 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
650
651 return ret;
652 }
653
654 void
655 intel_fini_pipe_control(struct intel_engine_cs *ring)
656 {
657 struct drm_device *dev = ring->dev;
658
659 if (ring->scratch.obj == NULL)
660 return;
661
662 if (INTEL_INFO(dev)->gen >= 5) {
663 kunmap(sg_page(ring->scratch.obj->pages->sgl));
664 i915_gem_object_ggtt_unpin(ring->scratch.obj);
665 }
666
667 drm_gem_object_unreference(&ring->scratch.obj->base);
668 ring->scratch.obj = NULL;
669 }
670
671 int
672 intel_init_pipe_control(struct intel_engine_cs *ring)
673 {
674 int ret;
675
676 WARN_ON(ring->scratch.obj);
677
678 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
679 if (ring->scratch.obj == NULL) {
680 DRM_ERROR("Failed to allocate seqno page\n");
681 ret = -ENOMEM;
682 goto err;
683 }
684
685 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
686 if (ret)
687 goto err_unref;
688
689 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
690 if (ret)
691 goto err_unref;
692
693 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
694 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
695 if (ring->scratch.cpu_page == NULL) {
696 ret = -ENOMEM;
697 goto err_unpin;
698 }
699
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring->name, ring->scratch.gtt_offset);
702 return 0;
703
704 err_unpin:
705 i915_gem_object_ggtt_unpin(ring->scratch.obj);
706 err_unref:
707 drm_gem_object_unreference(&ring->scratch.obj->base);
708 err:
709 return ret;
710 }
711
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
713 {
714 int ret, i;
715 struct intel_engine_cs *ring = req->ring;
716 struct drm_device *dev = ring->dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718 struct i915_workarounds *w = &dev_priv->workarounds;
719
720 if (WARN_ON_ONCE(w->count == 0))
721 return 0;
722
723 ring->gpu_caches_dirty = true;
724 ret = intel_ring_flush_all_caches(req);
725 if (ret)
726 return ret;
727
728 ret = intel_ring_begin(req, (w->count * 2 + 2));
729 if (ret)
730 return ret;
731
732 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
733 for (i = 0; i < w->count; i++) {
734 intel_ring_emit(ring, w->reg[i].addr);
735 intel_ring_emit(ring, w->reg[i].value);
736 }
737 intel_ring_emit(ring, MI_NOOP);
738
739 intel_ring_advance(ring);
740
741 ring->gpu_caches_dirty = true;
742 ret = intel_ring_flush_all_caches(req);
743 if (ret)
744 return ret;
745
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
747
748 return 0;
749 }
750
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
752 {
753 int ret;
754
755 ret = intel_ring_workarounds_emit(req);
756 if (ret != 0)
757 return ret;
758
759 ret = i915_gem_render_state_init(req);
760 if (ret)
761 DRM_ERROR("init render state: %d\n", ret);
762
763 return ret;
764 }
765
766 static int wa_add(struct drm_i915_private *dev_priv,
767 const u32 addr, const u32 mask, const u32 val)
768 {
769 const u32 idx = dev_priv->workarounds.count;
770
771 if (WARN_ON(idx >= I915_MAX_WA_REGS))
772 return -ENOSPC;
773
774 dev_priv->workarounds.reg[idx].addr = addr;
775 dev_priv->workarounds.reg[idx].value = val;
776 dev_priv->workarounds.reg[idx].mask = mask;
777
778 dev_priv->workarounds.count++;
779
780 return 0;
781 }
782
783 #define WA_REG(addr, mask, val) { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
785 if (r) \
786 return r; \
787 }
788
789 #define WA_SET_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
791
792 #define WA_CLR_BIT_MASKED(addr, mask) \
793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
794
795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
797
798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
800
801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
802
803 static int bdw_init_workarounds(struct intel_engine_cs *ring)
804 {
805 struct drm_device *dev = ring->dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807
808 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
809
810 /* WaDisableAsyncFlipPerfMode:bdw */
811 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
812
813 /* WaDisablePartialInstShootdown:bdw */
814 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
817 STALL_DOP_GATING_DISABLE);
818
819 /* WaDisableDopClockGating:bdw */
820 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
821 DOP_CLOCK_GATING_DISABLE);
822
823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
824 GEN8_SAMPLER_POWER_BYPASS_DIS);
825
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
829 */
830 WA_SET_BIT_MASKED(HDC_CHICKEN0,
831 /* WaForceEnableNonCoherent:bdw */
832 HDC_FORCE_NON_COHERENT |
833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
835 /* WaHdcDisableFetchWhenMasked:bdw */
836 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
837 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
838 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
839
840 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
841 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
842 * polygons in the same 8x4 pixel/sample area to be processed without
843 * stalling waiting for the earlier ones to write to Hierarchical Z
844 * buffer."
845 *
846 * This optimization is off by default for Broadwell; turn it on.
847 */
848 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
849
850 /* Wa4x4STCOptimizationDisable:bdw */
851 WA_SET_BIT_MASKED(CACHE_MODE_1,
852 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
853
854 /*
855 * BSpec recommends 8x4 when MSAA is used,
856 * however in practice 16x4 seems fastest.
857 *
858 * Note that PS/WM thread counts depend on the WIZ hashing
859 * disable bit, which we don't touch here, but it's good
860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
861 */
862 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
863 GEN6_WIZ_HASHING_MASK,
864 GEN6_WIZ_HASHING_16x4);
865
866 return 0;
867 }
868
869 static int chv_init_workarounds(struct intel_engine_cs *ring)
870 {
871 struct drm_device *dev = ring->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873
874 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
875
876 /* WaDisableAsyncFlipPerfMode:chv */
877 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
878
879 /* WaDisablePartialInstShootdown:chv */
880 /* WaDisableThreadStallDopClockGating:chv */
881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
882 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
883 STALL_DOP_GATING_DISABLE);
884
885 /* Use Force Non-Coherent whenever executing a 3D context. This is a
886 * workaround for a possible hang in the unlikely event a TLB
887 * invalidation occurs during a PSD flush.
888 */
889 /* WaForceEnableNonCoherent:chv */
890 /* WaHdcDisableFetchWhenMasked:chv */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0,
892 HDC_FORCE_NON_COHERENT |
893 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
894
895 /* According to the CACHE_MODE_0 default value documentation, some
896 * CHV platforms disable this optimization by default. Turn it on.
897 */
898 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
899
900 /* Wa4x4STCOptimizationDisable:chv */
901 WA_SET_BIT_MASKED(CACHE_MODE_1,
902 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
903
904 /* Improve HiZ throughput on CHV. */
905 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
906
907 /*
908 * BSpec recommends 8x4 when MSAA is used,
909 * however in practice 16x4 seems fastest.
910 *
911 * Note that PS/WM thread counts depend on the WIZ hashing
912 * disable bit, which we don't touch here, but it's good
913 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
914 */
915 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
916 GEN6_WIZ_HASHING_MASK,
917 GEN6_WIZ_HASHING_16x4);
918
919 return 0;
920 }
921
922 static int gen9_init_workarounds(struct intel_engine_cs *ring)
923 {
924 struct drm_device *dev = ring->dev;
925 struct drm_i915_private *dev_priv = dev->dev_private;
926 uint32_t tmp;
927
928 /* WaDisablePartialInstShootdown:skl,bxt */
929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
931
932 /* Syncing dependencies between camera and graphics:skl,bxt */
933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
935
936 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
937 INTEL_REVID(dev) == SKL_REVID_B0)) ||
938 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
940 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
941 GEN9_DG_MIRROR_FIX_ENABLE);
942 }
943
944 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
945 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
946 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
948 GEN9_RHWO_OPTIMIZATION_DISABLE);
949 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
950 DISABLE_PIXEL_MASK_CAMMING);
951 }
952
953 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
954 IS_BROXTON(dev)) {
955 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
956 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
957 GEN9_ENABLE_YV12_BUGFIX);
958 }
959
960 /* Wa4x4STCOptimizationDisable:skl,bxt */
961 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
962
963 /* WaDisablePartialResolveInVc:skl,bxt */
964 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
965
966 /* WaCcsTlbPrefetchDisable:skl,bxt */
967 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
968 GEN9_CCS_TLB_PREFETCH_ENABLE);
969
970 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
971 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
972 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
973 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
974 PIXEL_MASK_CAMMING_DISABLE);
975
976 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
977 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
978 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
979 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
980 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
981 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
982
983 return 0;
984 }
985
986 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
987 {
988 struct drm_device *dev = ring->dev;
989 struct drm_i915_private *dev_priv = dev->dev_private;
990 u8 vals[3] = { 0, 0, 0 };
991 unsigned int i;
992
993 for (i = 0; i < 3; i++) {
994 u8 ss;
995
996 /*
997 * Only consider slices where one, and only one, subslice has 7
998 * EUs
999 */
1000 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
1001 continue;
1002
1003 /*
1004 * subslice_7eu[i] != 0 (because of the check above) and
1005 * ss_max == 4 (maximum number of subslices possible per slice)
1006 *
1007 * -> 0 <= ss <= 3;
1008 */
1009 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1010 vals[i] = 3 - ss;
1011 }
1012
1013 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1014 return 0;
1015
1016 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1017 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1018 GEN9_IZ_HASHING_MASK(2) |
1019 GEN9_IZ_HASHING_MASK(1) |
1020 GEN9_IZ_HASHING_MASK(0),
1021 GEN9_IZ_HASHING(2, vals[2]) |
1022 GEN9_IZ_HASHING(1, vals[1]) |
1023 GEN9_IZ_HASHING(0, vals[0]));
1024
1025 return 0;
1026 }
1027
1028
1029 static int skl_init_workarounds(struct intel_engine_cs *ring)
1030 {
1031 struct drm_device *dev = ring->dev;
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033
1034 gen9_init_workarounds(ring);
1035
1036 /* WaDisablePowerCompilerClockGating:skl */
1037 if (INTEL_REVID(dev) == SKL_REVID_B0)
1038 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1039 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1040
1041 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1042 /*
1043 *Use Force Non-Coherent whenever executing a 3D context. This
1044 * is a workaround for a possible hang in the unlikely event
1045 * a TLB invalidation occurs during a PSD flush.
1046 */
1047 /* WaForceEnableNonCoherent:skl */
1048 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1049 HDC_FORCE_NON_COHERENT);
1050 }
1051
1052 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
1053 INTEL_REVID(dev) == SKL_REVID_D0)
1054 /* WaBarrierPerformanceFixDisable:skl */
1055 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1056 HDC_FENCE_DEST_SLM_DISABLE |
1057 HDC_BARRIER_PERFORMANCE_DISABLE);
1058
1059 return skl_tune_iz_hashing(ring);
1060 }
1061
1062 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1063 {
1064 struct drm_device *dev = ring->dev;
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1066
1067 gen9_init_workarounds(ring);
1068
1069 /* WaDisableThreadStallDopClockGating:bxt */
1070 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1071 STALL_DOP_GATING_DISABLE);
1072
1073 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1074 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1075 WA_SET_BIT_MASKED(
1076 GEN7_HALF_SLICE_CHICKEN1,
1077 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1078 }
1079
1080 return 0;
1081 }
1082
1083 int init_workarounds_ring(struct intel_engine_cs *ring)
1084 {
1085 struct drm_device *dev = ring->dev;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087
1088 WARN_ON(ring->id != RCS);
1089
1090 dev_priv->workarounds.count = 0;
1091
1092 if (IS_BROADWELL(dev))
1093 return bdw_init_workarounds(ring);
1094
1095 if (IS_CHERRYVIEW(dev))
1096 return chv_init_workarounds(ring);
1097
1098 if (IS_SKYLAKE(dev))
1099 return skl_init_workarounds(ring);
1100
1101 if (IS_BROXTON(dev))
1102 return bxt_init_workarounds(ring);
1103
1104 return 0;
1105 }
1106
1107 static int init_render_ring(struct intel_engine_cs *ring)
1108 {
1109 struct drm_device *dev = ring->dev;
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111 int ret = init_ring_common(ring);
1112 if (ret)
1113 return ret;
1114
1115 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1116 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1117 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1118
1119 /* We need to disable the AsyncFlip performance optimisations in order
1120 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1121 * programmed to '1' on all products.
1122 *
1123 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1124 */
1125 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1126 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1127
1128 /* Required for the hardware to program scanline values for waiting */
1129 /* WaEnableFlushTlbInvalidationMode:snb */
1130 if (INTEL_INFO(dev)->gen == 6)
1131 I915_WRITE(GFX_MODE,
1132 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1133
1134 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1135 if (IS_GEN7(dev))
1136 I915_WRITE(GFX_MODE_GEN7,
1137 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1138 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1139
1140 if (IS_GEN6(dev)) {
1141 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1142 * "If this bit is set, STCunit will have LRA as replacement
1143 * policy. [...] This bit must be reset. LRA replacement
1144 * policy is not supported."
1145 */
1146 I915_WRITE(CACHE_MODE_0,
1147 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1148 }
1149
1150 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1151 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1152
1153 if (HAS_L3_DPF(dev))
1154 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1155
1156 return init_workarounds_ring(ring);
1157 }
1158
1159 static void render_ring_cleanup(struct intel_engine_cs *ring)
1160 {
1161 struct drm_device *dev = ring->dev;
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163
1164 if (dev_priv->semaphore_obj) {
1165 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1166 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1167 dev_priv->semaphore_obj = NULL;
1168 }
1169
1170 intel_fini_pipe_control(ring);
1171 }
1172
1173 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1174 unsigned int num_dwords)
1175 {
1176 #define MBOX_UPDATE_DWORDS 8
1177 struct intel_engine_cs *signaller = signaller_req->ring;
1178 struct drm_device *dev = signaller->dev;
1179 struct drm_i915_private *dev_priv = dev->dev_private;
1180 struct intel_engine_cs *waiter;
1181 int i, ret, num_rings;
1182
1183 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1184 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1185 #undef MBOX_UPDATE_DWORDS
1186
1187 ret = intel_ring_begin(signaller_req, num_dwords);
1188 if (ret)
1189 return ret;
1190
1191 for_each_ring(waiter, dev_priv, i) {
1192 u32 seqno;
1193 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1194 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1195 continue;
1196
1197 seqno = i915_gem_request_get_seqno(signaller_req);
1198 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1199 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1200 PIPE_CONTROL_QW_WRITE |
1201 PIPE_CONTROL_FLUSH_ENABLE);
1202 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1203 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1204 intel_ring_emit(signaller, seqno);
1205 intel_ring_emit(signaller, 0);
1206 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1207 MI_SEMAPHORE_TARGET(waiter->id));
1208 intel_ring_emit(signaller, 0);
1209 }
1210
1211 return 0;
1212 }
1213
1214 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1215 unsigned int num_dwords)
1216 {
1217 #define MBOX_UPDATE_DWORDS 6
1218 struct intel_engine_cs *signaller = signaller_req->ring;
1219 struct drm_device *dev = signaller->dev;
1220 struct drm_i915_private *dev_priv = dev->dev_private;
1221 struct intel_engine_cs *waiter;
1222 int i, ret, num_rings;
1223
1224 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1225 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1226 #undef MBOX_UPDATE_DWORDS
1227
1228 ret = intel_ring_begin(signaller_req, num_dwords);
1229 if (ret)
1230 return ret;
1231
1232 for_each_ring(waiter, dev_priv, i) {
1233 u32 seqno;
1234 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1235 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1236 continue;
1237
1238 seqno = i915_gem_request_get_seqno(signaller_req);
1239 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1240 MI_FLUSH_DW_OP_STOREDW);
1241 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1242 MI_FLUSH_DW_USE_GTT);
1243 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1244 intel_ring_emit(signaller, seqno);
1245 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1246 MI_SEMAPHORE_TARGET(waiter->id));
1247 intel_ring_emit(signaller, 0);
1248 }
1249
1250 return 0;
1251 }
1252
1253 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1254 unsigned int num_dwords)
1255 {
1256 struct intel_engine_cs *signaller = signaller_req->ring;
1257 struct drm_device *dev = signaller->dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 struct intel_engine_cs *useless;
1260 int i, ret, num_rings;
1261
1262 #define MBOX_UPDATE_DWORDS 3
1263 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1264 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1265 #undef MBOX_UPDATE_DWORDS
1266
1267 ret = intel_ring_begin(signaller_req, num_dwords);
1268 if (ret)
1269 return ret;
1270
1271 for_each_ring(useless, dev_priv, i) {
1272 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1273 if (mbox_reg != GEN6_NOSYNC) {
1274 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1275 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1276 intel_ring_emit(signaller, mbox_reg);
1277 intel_ring_emit(signaller, seqno);
1278 }
1279 }
1280
1281 /* If num_dwords was rounded, make sure the tail pointer is correct */
1282 if (num_rings % 2 == 0)
1283 intel_ring_emit(signaller, MI_NOOP);
1284
1285 return 0;
1286 }
1287
1288 /**
1289 * gen6_add_request - Update the semaphore mailbox registers
1290 *
1291 * @request - request to write to the ring
1292 *
1293 * Update the mailbox registers in the *other* rings with the current seqno.
1294 * This acts like a signal in the canonical semaphore.
1295 */
1296 static int
1297 gen6_add_request(struct drm_i915_gem_request *req)
1298 {
1299 struct intel_engine_cs *ring = req->ring;
1300 int ret;
1301
1302 if (ring->semaphore.signal)
1303 ret = ring->semaphore.signal(req, 4);
1304 else
1305 ret = intel_ring_begin(req, 4);
1306
1307 if (ret)
1308 return ret;
1309
1310 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1311 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1312 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1313 intel_ring_emit(ring, MI_USER_INTERRUPT);
1314 __intel_ring_advance(ring);
1315
1316 return 0;
1317 }
1318
1319 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1320 u32 seqno)
1321 {
1322 struct drm_i915_private *dev_priv = dev->dev_private;
1323 return dev_priv->last_seqno < seqno;
1324 }
1325
1326 /**
1327 * intel_ring_sync - sync the waiter to the signaller on seqno
1328 *
1329 * @waiter - ring that is waiting
1330 * @signaller - ring which has, or will signal
1331 * @seqno - seqno which the waiter will block on
1332 */
1333
1334 static int
1335 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1336 struct intel_engine_cs *signaller,
1337 u32 seqno)
1338 {
1339 struct intel_engine_cs *waiter = waiter_req->ring;
1340 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1341 int ret;
1342
1343 ret = intel_ring_begin(waiter_req, 4);
1344 if (ret)
1345 return ret;
1346
1347 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1348 MI_SEMAPHORE_GLOBAL_GTT |
1349 MI_SEMAPHORE_POLL |
1350 MI_SEMAPHORE_SAD_GTE_SDD);
1351 intel_ring_emit(waiter, seqno);
1352 intel_ring_emit(waiter,
1353 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1354 intel_ring_emit(waiter,
1355 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1356 intel_ring_advance(waiter);
1357 return 0;
1358 }
1359
1360 static int
1361 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1362 struct intel_engine_cs *signaller,
1363 u32 seqno)
1364 {
1365 struct intel_engine_cs *waiter = waiter_req->ring;
1366 u32 dw1 = MI_SEMAPHORE_MBOX |
1367 MI_SEMAPHORE_COMPARE |
1368 MI_SEMAPHORE_REGISTER;
1369 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1370 int ret;
1371
1372 /* Throughout all of the GEM code, seqno passed implies our current
1373 * seqno is >= the last seqno executed. However for hardware the
1374 * comparison is strictly greater than.
1375 */
1376 seqno -= 1;
1377
1378 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1379
1380 ret = intel_ring_begin(waiter_req, 4);
1381 if (ret)
1382 return ret;
1383
1384 /* If seqno wrap happened, omit the wait with no-ops */
1385 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1386 intel_ring_emit(waiter, dw1 | wait_mbox);
1387 intel_ring_emit(waiter, seqno);
1388 intel_ring_emit(waiter, 0);
1389 intel_ring_emit(waiter, MI_NOOP);
1390 } else {
1391 intel_ring_emit(waiter, MI_NOOP);
1392 intel_ring_emit(waiter, MI_NOOP);
1393 intel_ring_emit(waiter, MI_NOOP);
1394 intel_ring_emit(waiter, MI_NOOP);
1395 }
1396 intel_ring_advance(waiter);
1397
1398 return 0;
1399 }
1400
1401 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1402 do { \
1403 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1404 PIPE_CONTROL_DEPTH_STALL); \
1405 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1406 intel_ring_emit(ring__, 0); \
1407 intel_ring_emit(ring__, 0); \
1408 } while (0)
1409
1410 static int
1411 pc_render_add_request(struct drm_i915_gem_request *req)
1412 {
1413 struct intel_engine_cs *ring = req->ring;
1414 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1415 int ret;
1416
1417 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1418 * incoherent with writes to memory, i.e. completely fubar,
1419 * so we need to use PIPE_NOTIFY instead.
1420 *
1421 * However, we also need to workaround the qword write
1422 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1423 * memory before requesting an interrupt.
1424 */
1425 ret = intel_ring_begin(req, 32);
1426 if (ret)
1427 return ret;
1428
1429 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1430 PIPE_CONTROL_WRITE_FLUSH |
1431 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1432 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1433 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1434 intel_ring_emit(ring, 0);
1435 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1436 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1437 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1438 scratch_addr += 2 * CACHELINE_BYTES;
1439 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1440 scratch_addr += 2 * CACHELINE_BYTES;
1441 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1442 scratch_addr += 2 * CACHELINE_BYTES;
1443 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1444 scratch_addr += 2 * CACHELINE_BYTES;
1445 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1446
1447 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1448 PIPE_CONTROL_WRITE_FLUSH |
1449 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1450 PIPE_CONTROL_NOTIFY);
1451 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1452 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1453 intel_ring_emit(ring, 0);
1454 __intel_ring_advance(ring);
1455
1456 return 0;
1457 }
1458
1459 static u32
1460 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1461 {
1462 /* Workaround to force correct ordering between irq and seqno writes on
1463 * ivb (and maybe also on snb) by reading from a CS register (like
1464 * ACTHD) before reading the status page. */
1465 if (!lazy_coherency) {
1466 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1467 POSTING_READ(RING_ACTHD(ring->mmio_base));
1468 }
1469
1470 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1471 }
1472
1473 static u32
1474 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1475 {
1476 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1477 }
1478
1479 static void
1480 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1481 {
1482 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1483 }
1484
1485 static u32
1486 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1487 {
1488 return ring->scratch.cpu_page[0];
1489 }
1490
1491 static void
1492 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1493 {
1494 ring->scratch.cpu_page[0] = seqno;
1495 }
1496
1497 static bool
1498 gen5_ring_get_irq(struct intel_engine_cs *ring)
1499 {
1500 struct drm_device *dev = ring->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 unsigned long flags;
1503
1504 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1505 return false;
1506
1507 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1508 if (ring->irq_refcount++ == 0)
1509 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1510 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1511
1512 return true;
1513 }
1514
1515 static void
1516 gen5_ring_put_irq(struct intel_engine_cs *ring)
1517 {
1518 struct drm_device *dev = ring->dev;
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 unsigned long flags;
1521
1522 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1523 if (--ring->irq_refcount == 0)
1524 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1525 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1526 }
1527
1528 static bool
1529 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1530 {
1531 struct drm_device *dev = ring->dev;
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 unsigned long flags;
1534
1535 if (!intel_irqs_enabled(dev_priv))
1536 return false;
1537
1538 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1539 if (ring->irq_refcount++ == 0) {
1540 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1541 I915_WRITE(IMR, dev_priv->irq_mask);
1542 POSTING_READ(IMR);
1543 }
1544 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1545
1546 return true;
1547 }
1548
1549 static void
1550 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1551 {
1552 struct drm_device *dev = ring->dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 unsigned long flags;
1555
1556 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1557 if (--ring->irq_refcount == 0) {
1558 dev_priv->irq_mask |= ring->irq_enable_mask;
1559 I915_WRITE(IMR, dev_priv->irq_mask);
1560 POSTING_READ(IMR);
1561 }
1562 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1563 }
1564
1565 static bool
1566 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1567 {
1568 struct drm_device *dev = ring->dev;
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 unsigned long flags;
1571
1572 if (!intel_irqs_enabled(dev_priv))
1573 return false;
1574
1575 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1576 if (ring->irq_refcount++ == 0) {
1577 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1578 I915_WRITE16(IMR, dev_priv->irq_mask);
1579 POSTING_READ16(IMR);
1580 }
1581 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1582
1583 return true;
1584 }
1585
1586 static void
1587 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1588 {
1589 struct drm_device *dev = ring->dev;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 unsigned long flags;
1592
1593 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1594 if (--ring->irq_refcount == 0) {
1595 dev_priv->irq_mask |= ring->irq_enable_mask;
1596 I915_WRITE16(IMR, dev_priv->irq_mask);
1597 POSTING_READ16(IMR);
1598 }
1599 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1600 }
1601
1602 static int
1603 bsd_ring_flush(struct drm_i915_gem_request *req,
1604 u32 invalidate_domains,
1605 u32 flush_domains)
1606 {
1607 struct intel_engine_cs *ring = req->ring;
1608 int ret;
1609
1610 ret = intel_ring_begin(req, 2);
1611 if (ret)
1612 return ret;
1613
1614 intel_ring_emit(ring, MI_FLUSH);
1615 intel_ring_emit(ring, MI_NOOP);
1616 intel_ring_advance(ring);
1617 return 0;
1618 }
1619
1620 static int
1621 i9xx_add_request(struct drm_i915_gem_request *req)
1622 {
1623 struct intel_engine_cs *ring = req->ring;
1624 int ret;
1625
1626 ret = intel_ring_begin(req, 4);
1627 if (ret)
1628 return ret;
1629
1630 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1631 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1632 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1633 intel_ring_emit(ring, MI_USER_INTERRUPT);
1634 __intel_ring_advance(ring);
1635
1636 return 0;
1637 }
1638
1639 static bool
1640 gen6_ring_get_irq(struct intel_engine_cs *ring)
1641 {
1642 struct drm_device *dev = ring->dev;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 unsigned long flags;
1645
1646 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1647 return false;
1648
1649 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1650 if (ring->irq_refcount++ == 0) {
1651 if (HAS_L3_DPF(dev) && ring->id == RCS)
1652 I915_WRITE_IMR(ring,
1653 ~(ring->irq_enable_mask |
1654 GT_PARITY_ERROR(dev)));
1655 else
1656 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1657 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1658 }
1659 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1660
1661 return true;
1662 }
1663
1664 static void
1665 gen6_ring_put_irq(struct intel_engine_cs *ring)
1666 {
1667 struct drm_device *dev = ring->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 unsigned long flags;
1670
1671 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1672 if (--ring->irq_refcount == 0) {
1673 if (HAS_L3_DPF(dev) && ring->id == RCS)
1674 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1675 else
1676 I915_WRITE_IMR(ring, ~0);
1677 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1678 }
1679 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1680 }
1681
1682 static bool
1683 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1684 {
1685 struct drm_device *dev = ring->dev;
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 unsigned long flags;
1688
1689 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1690 return false;
1691
1692 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1693 if (ring->irq_refcount++ == 0) {
1694 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1695 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1696 }
1697 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1698
1699 return true;
1700 }
1701
1702 static void
1703 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1704 {
1705 struct drm_device *dev = ring->dev;
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 unsigned long flags;
1708
1709 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1710 if (--ring->irq_refcount == 0) {
1711 I915_WRITE_IMR(ring, ~0);
1712 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1713 }
1714 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1715 }
1716
1717 static bool
1718 gen8_ring_get_irq(struct intel_engine_cs *ring)
1719 {
1720 struct drm_device *dev = ring->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 unsigned long flags;
1723
1724 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1725 return false;
1726
1727 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1728 if (ring->irq_refcount++ == 0) {
1729 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1730 I915_WRITE_IMR(ring,
1731 ~(ring->irq_enable_mask |
1732 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1733 } else {
1734 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1735 }
1736 POSTING_READ(RING_IMR(ring->mmio_base));
1737 }
1738 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1739
1740 return true;
1741 }
1742
1743 static void
1744 gen8_ring_put_irq(struct intel_engine_cs *ring)
1745 {
1746 struct drm_device *dev = ring->dev;
1747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 unsigned long flags;
1749
1750 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1751 if (--ring->irq_refcount == 0) {
1752 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1753 I915_WRITE_IMR(ring,
1754 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1755 } else {
1756 I915_WRITE_IMR(ring, ~0);
1757 }
1758 POSTING_READ(RING_IMR(ring->mmio_base));
1759 }
1760 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1761 }
1762
1763 static int
1764 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1765 u64 offset, u32 length,
1766 unsigned dispatch_flags)
1767 {
1768 struct intel_engine_cs *ring = req->ring;
1769 int ret;
1770
1771 ret = intel_ring_begin(req, 2);
1772 if (ret)
1773 return ret;
1774
1775 intel_ring_emit(ring,
1776 MI_BATCH_BUFFER_START |
1777 MI_BATCH_GTT |
1778 (dispatch_flags & I915_DISPATCH_SECURE ?
1779 0 : MI_BATCH_NON_SECURE_I965));
1780 intel_ring_emit(ring, offset);
1781 intel_ring_advance(ring);
1782
1783 return 0;
1784 }
1785
1786 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1787 #define I830_BATCH_LIMIT (256*1024)
1788 #define I830_TLB_ENTRIES (2)
1789 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1790 static int
1791 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1792 u64 offset, u32 len,
1793 unsigned dispatch_flags)
1794 {
1795 struct intel_engine_cs *ring = req->ring;
1796 u32 cs_offset = ring->scratch.gtt_offset;
1797 int ret;
1798
1799 ret = intel_ring_begin(req, 6);
1800 if (ret)
1801 return ret;
1802
1803 /* Evict the invalid PTE TLBs */
1804 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1805 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1806 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1807 intel_ring_emit(ring, cs_offset);
1808 intel_ring_emit(ring, 0xdeadbeef);
1809 intel_ring_emit(ring, MI_NOOP);
1810 intel_ring_advance(ring);
1811
1812 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1813 if (len > I830_BATCH_LIMIT)
1814 return -ENOSPC;
1815
1816 ret = intel_ring_begin(req, 6 + 2);
1817 if (ret)
1818 return ret;
1819
1820 /* Blit the batch (which has now all relocs applied) to the
1821 * stable batch scratch bo area (so that the CS never
1822 * stumbles over its tlb invalidation bug) ...
1823 */
1824 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1825 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1826 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1827 intel_ring_emit(ring, cs_offset);
1828 intel_ring_emit(ring, 4096);
1829 intel_ring_emit(ring, offset);
1830
1831 intel_ring_emit(ring, MI_FLUSH);
1832 intel_ring_emit(ring, MI_NOOP);
1833 intel_ring_advance(ring);
1834
1835 /* ... and execute it. */
1836 offset = cs_offset;
1837 }
1838
1839 ret = intel_ring_begin(req, 4);
1840 if (ret)
1841 return ret;
1842
1843 intel_ring_emit(ring, MI_BATCH_BUFFER);
1844 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1845 0 : MI_BATCH_NON_SECURE));
1846 intel_ring_emit(ring, offset + len - 8);
1847 intel_ring_emit(ring, MI_NOOP);
1848 intel_ring_advance(ring);
1849
1850 return 0;
1851 }
1852
1853 static int
1854 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1855 u64 offset, u32 len,
1856 unsigned dispatch_flags)
1857 {
1858 struct intel_engine_cs *ring = req->ring;
1859 int ret;
1860
1861 ret = intel_ring_begin(req, 2);
1862 if (ret)
1863 return ret;
1864
1865 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1866 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1867 0 : MI_BATCH_NON_SECURE));
1868 intel_ring_advance(ring);
1869
1870 return 0;
1871 }
1872
1873 static void cleanup_status_page(struct intel_engine_cs *ring)
1874 {
1875 struct drm_i915_gem_object *obj;
1876
1877 obj = ring->status_page.obj;
1878 if (obj == NULL)
1879 return;
1880
1881 kunmap(sg_page(obj->pages->sgl));
1882 i915_gem_object_ggtt_unpin(obj);
1883 drm_gem_object_unreference(&obj->base);
1884 ring->status_page.obj = NULL;
1885 }
1886
1887 static int init_status_page(struct intel_engine_cs *ring)
1888 {
1889 struct drm_i915_gem_object *obj;
1890
1891 if ((obj = ring->status_page.obj) == NULL) {
1892 unsigned flags;
1893 int ret;
1894
1895 obj = i915_gem_alloc_object(ring->dev, 4096);
1896 if (obj == NULL) {
1897 DRM_ERROR("Failed to allocate status page\n");
1898 return -ENOMEM;
1899 }
1900
1901 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1902 if (ret)
1903 goto err_unref;
1904
1905 flags = 0;
1906 if (!HAS_LLC(ring->dev))
1907 /* On g33, we cannot place HWS above 256MiB, so
1908 * restrict its pinning to the low mappable arena.
1909 * Though this restriction is not documented for
1910 * gen4, gen5, or byt, they also behave similarly
1911 * and hang if the HWS is placed at the top of the
1912 * GTT. To generalise, it appears that all !llc
1913 * platforms have issues with us placing the HWS
1914 * above the mappable region (even though we never
1915 * actualy map it).
1916 */
1917 flags |= PIN_MAPPABLE;
1918 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1919 if (ret) {
1920 err_unref:
1921 drm_gem_object_unreference(&obj->base);
1922 return ret;
1923 }
1924
1925 ring->status_page.obj = obj;
1926 }
1927
1928 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1929 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1930 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1931
1932 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1933 ring->name, ring->status_page.gfx_addr);
1934
1935 return 0;
1936 }
1937
1938 static int init_phys_status_page(struct intel_engine_cs *ring)
1939 {
1940 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1941
1942 if (!dev_priv->status_page_dmah) {
1943 dev_priv->status_page_dmah =
1944 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1945 if (!dev_priv->status_page_dmah)
1946 return -ENOMEM;
1947 }
1948
1949 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1950 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1951
1952 return 0;
1953 }
1954
1955 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1956 {
1957 iounmap(ringbuf->virtual_start);
1958 ringbuf->virtual_start = NULL;
1959 i915_gem_object_ggtt_unpin(ringbuf->obj);
1960 }
1961
1962 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1963 struct intel_ringbuffer *ringbuf)
1964 {
1965 struct drm_i915_private *dev_priv = to_i915(dev);
1966 struct drm_i915_gem_object *obj = ringbuf->obj;
1967 int ret;
1968
1969 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1970 if (ret)
1971 return ret;
1972
1973 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1974 if (ret) {
1975 i915_gem_object_ggtt_unpin(obj);
1976 return ret;
1977 }
1978
1979 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1980 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1981 if (ringbuf->virtual_start == NULL) {
1982 i915_gem_object_ggtt_unpin(obj);
1983 return -EINVAL;
1984 }
1985
1986 return 0;
1987 }
1988
1989 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1990 {
1991 drm_gem_object_unreference(&ringbuf->obj->base);
1992 ringbuf->obj = NULL;
1993 }
1994
1995 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1996 struct intel_ringbuffer *ringbuf)
1997 {
1998 struct drm_i915_gem_object *obj;
1999
2000 obj = NULL;
2001 if (!HAS_LLC(dev))
2002 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2003 if (obj == NULL)
2004 obj = i915_gem_alloc_object(dev, ringbuf->size);
2005 if (obj == NULL)
2006 return -ENOMEM;
2007
2008 /* mark ring buffers as read-only from GPU side by default */
2009 obj->gt_ro = 1;
2010
2011 ringbuf->obj = obj;
2012
2013 return 0;
2014 }
2015
2016 static int intel_init_ring_buffer(struct drm_device *dev,
2017 struct intel_engine_cs *ring)
2018 {
2019 struct intel_ringbuffer *ringbuf;
2020 int ret;
2021
2022 WARN_ON(ring->buffer);
2023
2024 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2025 if (!ringbuf)
2026 return -ENOMEM;
2027 ring->buffer = ringbuf;
2028
2029 ring->dev = dev;
2030 INIT_LIST_HEAD(&ring->active_list);
2031 INIT_LIST_HEAD(&ring->request_list);
2032 INIT_LIST_HEAD(&ring->execlist_queue);
2033 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2034 ringbuf->size = 32 * PAGE_SIZE;
2035 ringbuf->ring = ring;
2036 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2037
2038 init_waitqueue_head(&ring->irq_queue);
2039
2040 if (I915_NEED_GFX_HWS(dev)) {
2041 ret = init_status_page(ring);
2042 if (ret)
2043 goto error;
2044 } else {
2045 BUG_ON(ring->id != RCS);
2046 ret = init_phys_status_page(ring);
2047 if (ret)
2048 goto error;
2049 }
2050
2051 WARN_ON(ringbuf->obj);
2052
2053 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2054 if (ret) {
2055 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2056 ring->name, ret);
2057 goto error;
2058 }
2059
2060 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2061 if (ret) {
2062 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2063 ring->name, ret);
2064 intel_destroy_ringbuffer_obj(ringbuf);
2065 goto error;
2066 }
2067
2068 /* Workaround an erratum on the i830 which causes a hang if
2069 * the TAIL pointer points to within the last 2 cachelines
2070 * of the buffer.
2071 */
2072 ringbuf->effective_size = ringbuf->size;
2073 if (IS_I830(dev) || IS_845G(dev))
2074 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2075
2076 ret = i915_cmd_parser_init_ring(ring);
2077 if (ret)
2078 goto error;
2079
2080 return 0;
2081
2082 error:
2083 kfree(ringbuf);
2084 ring->buffer = NULL;
2085 return ret;
2086 }
2087
2088 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2089 {
2090 struct drm_i915_private *dev_priv;
2091 struct intel_ringbuffer *ringbuf;
2092
2093 if (!intel_ring_initialized(ring))
2094 return;
2095
2096 dev_priv = to_i915(ring->dev);
2097 ringbuf = ring->buffer;
2098
2099 intel_stop_ring_buffer(ring);
2100 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2101
2102 intel_unpin_ringbuffer_obj(ringbuf);
2103 intel_destroy_ringbuffer_obj(ringbuf);
2104 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
2105
2106 if (ring->cleanup)
2107 ring->cleanup(ring);
2108
2109 cleanup_status_page(ring);
2110
2111 i915_cmd_parser_fini_ring(ring);
2112 i915_gem_batch_pool_fini(&ring->batch_pool);
2113
2114 kfree(ringbuf);
2115 ring->buffer = NULL;
2116 }
2117
2118 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2119 {
2120 struct intel_ringbuffer *ringbuf = ring->buffer;
2121 struct drm_i915_gem_request *request;
2122 unsigned space;
2123 int ret;
2124
2125 /* The whole point of reserving space is to not wait! */
2126 WARN_ON(ringbuf->reserved_in_use);
2127
2128 if (intel_ring_space(ringbuf) >= n)
2129 return 0;
2130
2131 list_for_each_entry(request, &ring->request_list, list) {
2132 space = __intel_ring_space(request->postfix, ringbuf->tail,
2133 ringbuf->size);
2134 if (space >= n)
2135 break;
2136 }
2137
2138 if (WARN_ON(&request->list == &ring->request_list))
2139 return -ENOSPC;
2140
2141 ret = i915_wait_request(request);
2142 if (ret)
2143 return ret;
2144
2145 ringbuf->space = space;
2146 return 0;
2147 }
2148
2149 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
2150 {
2151 uint32_t __iomem *virt;
2152 struct intel_ringbuffer *ringbuf = ring->buffer;
2153 int rem = ringbuf->size - ringbuf->tail;
2154
2155 /* Can't wrap if space has already been reserved! */
2156 WARN_ON(ringbuf->reserved_in_use);
2157
2158 if (ringbuf->space < rem) {
2159 int ret = ring_wait_for_space(ring, rem);
2160 if (ret)
2161 return ret;
2162 }
2163
2164 virt = ringbuf->virtual_start + ringbuf->tail;
2165 rem /= 4;
2166 while (rem--)
2167 iowrite32(MI_NOOP, virt++);
2168
2169 ringbuf->tail = 0;
2170 intel_ring_update_space(ringbuf);
2171
2172 return 0;
2173 }
2174
2175 int intel_ring_idle(struct intel_engine_cs *ring)
2176 {
2177 struct drm_i915_gem_request *req;
2178
2179 /* We need to add any requests required to flush the objects and ring */
2180 WARN_ON(ring->outstanding_lazy_request);
2181 if (ring->outstanding_lazy_request)
2182 i915_add_request(ring->outstanding_lazy_request);
2183
2184 /* Wait upon the last request to be completed */
2185 if (list_empty(&ring->request_list))
2186 return 0;
2187
2188 req = list_entry(ring->request_list.prev,
2189 struct drm_i915_gem_request,
2190 list);
2191
2192 /* Make sure we do not trigger any retires */
2193 return __i915_wait_request(req,
2194 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2195 to_i915(ring->dev)->mm.interruptible,
2196 NULL, NULL);
2197 }
2198
2199 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2200 {
2201 request->ringbuf = request->ring->buffer;
2202 return 0;
2203 }
2204
2205 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2206 {
2207 /* NB: Until request management is fully tidied up and the OLR is
2208 * removed, there are too many ways for get false hits on this
2209 * anti-recursion check! */
2210 /*WARN_ON(ringbuf->reserved_size);*/
2211 WARN_ON(ringbuf->reserved_in_use);
2212
2213 ringbuf->reserved_size = size;
2214
2215 /*
2216 * Really need to call _begin() here but that currently leads to
2217 * recursion problems! This will be fixed later but for now just
2218 * return and hope for the best. Note that there is only a real
2219 * problem if the create of the request never actually calls _begin()
2220 * but if they are not submitting any work then why did they create
2221 * the request in the first place?
2222 */
2223 }
2224
2225 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2226 {
2227 WARN_ON(ringbuf->reserved_in_use);
2228
2229 ringbuf->reserved_size = 0;
2230 ringbuf->reserved_in_use = false;
2231 }
2232
2233 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2234 {
2235 WARN_ON(ringbuf->reserved_in_use);
2236
2237 ringbuf->reserved_in_use = true;
2238 ringbuf->reserved_tail = ringbuf->tail;
2239 }
2240
2241 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2242 {
2243 WARN_ON(!ringbuf->reserved_in_use);
2244 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2245 "request reserved size too small: %d vs %d!\n",
2246 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2247
2248 ringbuf->reserved_size = 0;
2249 ringbuf->reserved_in_use = false;
2250 }
2251
2252 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2253 {
2254 struct intel_ringbuffer *ringbuf = ring->buffer;
2255 int ret;
2256
2257 /*
2258 * Add on the reserved size to the request to make sure that after
2259 * the intended commands have been emitted, there is guaranteed to
2260 * still be enough free space to send them to the hardware.
2261 */
2262 if (!ringbuf->reserved_in_use)
2263 bytes += ringbuf->reserved_size;
2264
2265 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2266 ret = intel_wrap_ring_buffer(ring);
2267 if (unlikely(ret))
2268 return ret;
2269
2270 if(ringbuf->reserved_size) {
2271 uint32_t size = ringbuf->reserved_size;
2272
2273 intel_ring_reserved_space_cancel(ringbuf);
2274 intel_ring_reserved_space_reserve(ringbuf, size);
2275 }
2276 }
2277
2278 if (unlikely(ringbuf->space < bytes)) {
2279 ret = ring_wait_for_space(ring, bytes);
2280 if (unlikely(ret))
2281 return ret;
2282 }
2283
2284 return 0;
2285 }
2286
2287 int intel_ring_begin(struct drm_i915_gem_request *req,
2288 int num_dwords)
2289 {
2290 struct intel_engine_cs *ring;
2291 struct drm_i915_private *dev_priv;
2292 int ret;
2293
2294 WARN_ON(req == NULL);
2295 ring = req->ring;
2296 dev_priv = ring->dev->dev_private;
2297
2298 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2299 dev_priv->mm.interruptible);
2300 if (ret)
2301 return ret;
2302
2303 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2304 if (ret)
2305 return ret;
2306
2307 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2308 return 0;
2309 }
2310
2311 /* Align the ring tail to a cacheline boundary */
2312 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2313 {
2314 struct intel_engine_cs *ring = req->ring;
2315 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2316 int ret;
2317
2318 if (num_dwords == 0)
2319 return 0;
2320
2321 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2322 ret = intel_ring_begin(req, num_dwords);
2323 if (ret)
2324 return ret;
2325
2326 while (num_dwords--)
2327 intel_ring_emit(ring, MI_NOOP);
2328
2329 intel_ring_advance(ring);
2330
2331 return 0;
2332 }
2333
2334 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2335 {
2336 struct drm_device *dev = ring->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338
2339 BUG_ON(ring->outstanding_lazy_request);
2340
2341 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2342 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2343 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2344 if (HAS_VEBOX(dev))
2345 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2346 }
2347
2348 ring->set_seqno(ring, seqno);
2349 ring->hangcheck.seqno = seqno;
2350 }
2351
2352 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2353 u32 value)
2354 {
2355 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2356
2357 /* Every tail move must follow the sequence below */
2358
2359 /* Disable notification that the ring is IDLE. The GT
2360 * will then assume that it is busy and bring it out of rc6.
2361 */
2362 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2363 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2364
2365 /* Clear the context id. Here be magic! */
2366 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2367
2368 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2369 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2370 GEN6_BSD_SLEEP_INDICATOR) == 0,
2371 50))
2372 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2373
2374 /* Now that the ring is fully powered up, update the tail */
2375 I915_WRITE_TAIL(ring, value);
2376 POSTING_READ(RING_TAIL(ring->mmio_base));
2377
2378 /* Let the ring send IDLE messages to the GT again,
2379 * and so let it sleep to conserve power when idle.
2380 */
2381 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2382 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2383 }
2384
2385 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2386 u32 invalidate, u32 flush)
2387 {
2388 struct intel_engine_cs *ring = req->ring;
2389 uint32_t cmd;
2390 int ret;
2391
2392 ret = intel_ring_begin(req, 4);
2393 if (ret)
2394 return ret;
2395
2396 cmd = MI_FLUSH_DW;
2397 if (INTEL_INFO(ring->dev)->gen >= 8)
2398 cmd += 1;
2399
2400 /* We always require a command barrier so that subsequent
2401 * commands, such as breadcrumb interrupts, are strictly ordered
2402 * wrt the contents of the write cache being flushed to memory
2403 * (and thus being coherent from the CPU).
2404 */
2405 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2406
2407 /*
2408 * Bspec vol 1c.5 - video engine command streamer:
2409 * "If ENABLED, all TLBs will be invalidated once the flush
2410 * operation is complete. This bit is only valid when the
2411 * Post-Sync Operation field is a value of 1h or 3h."
2412 */
2413 if (invalidate & I915_GEM_GPU_DOMAINS)
2414 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2415
2416 intel_ring_emit(ring, cmd);
2417 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2418 if (INTEL_INFO(ring->dev)->gen >= 8) {
2419 intel_ring_emit(ring, 0); /* upper addr */
2420 intel_ring_emit(ring, 0); /* value */
2421 } else {
2422 intel_ring_emit(ring, 0);
2423 intel_ring_emit(ring, MI_NOOP);
2424 }
2425 intel_ring_advance(ring);
2426 return 0;
2427 }
2428
2429 static int
2430 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2431 u64 offset, u32 len,
2432 unsigned dispatch_flags)
2433 {
2434 struct intel_engine_cs *ring = req->ring;
2435 bool ppgtt = USES_PPGTT(ring->dev) &&
2436 !(dispatch_flags & I915_DISPATCH_SECURE);
2437 int ret;
2438
2439 ret = intel_ring_begin(req, 4);
2440 if (ret)
2441 return ret;
2442
2443 /* FIXME(BDW): Address space and security selectors. */
2444 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2445 intel_ring_emit(ring, lower_32_bits(offset));
2446 intel_ring_emit(ring, upper_32_bits(offset));
2447 intel_ring_emit(ring, MI_NOOP);
2448 intel_ring_advance(ring);
2449
2450 return 0;
2451 }
2452
2453 static int
2454 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2455 u64 offset, u32 len,
2456 unsigned dispatch_flags)
2457 {
2458 struct intel_engine_cs *ring = req->ring;
2459 int ret;
2460
2461 ret = intel_ring_begin(req, 2);
2462 if (ret)
2463 return ret;
2464
2465 intel_ring_emit(ring,
2466 MI_BATCH_BUFFER_START |
2467 (dispatch_flags & I915_DISPATCH_SECURE ?
2468 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2469 /* bit0-7 is the length on GEN6+ */
2470 intel_ring_emit(ring, offset);
2471 intel_ring_advance(ring);
2472
2473 return 0;
2474 }
2475
2476 static int
2477 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2478 u64 offset, u32 len,
2479 unsigned dispatch_flags)
2480 {
2481 struct intel_engine_cs *ring = req->ring;
2482 int ret;
2483
2484 ret = intel_ring_begin(req, 2);
2485 if (ret)
2486 return ret;
2487
2488 intel_ring_emit(ring,
2489 MI_BATCH_BUFFER_START |
2490 (dispatch_flags & I915_DISPATCH_SECURE ?
2491 0 : MI_BATCH_NON_SECURE_I965));
2492 /* bit0-7 is the length on GEN6+ */
2493 intel_ring_emit(ring, offset);
2494 intel_ring_advance(ring);
2495
2496 return 0;
2497 }
2498
2499 /* Blitter support (SandyBridge+) */
2500
2501 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2502 u32 invalidate, u32 flush)
2503 {
2504 struct intel_engine_cs *ring = req->ring;
2505 struct drm_device *dev = ring->dev;
2506 uint32_t cmd;
2507 int ret;
2508
2509 ret = intel_ring_begin(req, 4);
2510 if (ret)
2511 return ret;
2512
2513 cmd = MI_FLUSH_DW;
2514 if (INTEL_INFO(dev)->gen >= 8)
2515 cmd += 1;
2516
2517 /* We always require a command barrier so that subsequent
2518 * commands, such as breadcrumb interrupts, are strictly ordered
2519 * wrt the contents of the write cache being flushed to memory
2520 * (and thus being coherent from the CPU).
2521 */
2522 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2523
2524 /*
2525 * Bspec vol 1c.3 - blitter engine command streamer:
2526 * "If ENABLED, all TLBs will be invalidated once the flush
2527 * operation is complete. This bit is only valid when the
2528 * Post-Sync Operation field is a value of 1h or 3h."
2529 */
2530 if (invalidate & I915_GEM_DOMAIN_RENDER)
2531 cmd |= MI_INVALIDATE_TLB;
2532 intel_ring_emit(ring, cmd);
2533 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2534 if (INTEL_INFO(dev)->gen >= 8) {
2535 intel_ring_emit(ring, 0); /* upper addr */
2536 intel_ring_emit(ring, 0); /* value */
2537 } else {
2538 intel_ring_emit(ring, 0);
2539 intel_ring_emit(ring, MI_NOOP);
2540 }
2541 intel_ring_advance(ring);
2542
2543 return 0;
2544 }
2545
2546 int intel_init_render_ring_buffer(struct drm_device *dev)
2547 {
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2550 struct drm_i915_gem_object *obj;
2551 int ret;
2552
2553 ring->name = "render ring";
2554 ring->id = RCS;
2555 ring->mmio_base = RENDER_RING_BASE;
2556
2557 if (INTEL_INFO(dev)->gen >= 8) {
2558 if (i915_semaphore_is_enabled(dev)) {
2559 obj = i915_gem_alloc_object(dev, 4096);
2560 if (obj == NULL) {
2561 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2562 i915.semaphores = 0;
2563 } else {
2564 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2565 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2566 if (ret != 0) {
2567 drm_gem_object_unreference(&obj->base);
2568 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2569 i915.semaphores = 0;
2570 } else
2571 dev_priv->semaphore_obj = obj;
2572 }
2573 }
2574
2575 ring->init_context = intel_rcs_ctx_init;
2576 ring->add_request = gen6_add_request;
2577 ring->flush = gen8_render_ring_flush;
2578 ring->irq_get = gen8_ring_get_irq;
2579 ring->irq_put = gen8_ring_put_irq;
2580 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2581 ring->get_seqno = gen6_ring_get_seqno;
2582 ring->set_seqno = ring_set_seqno;
2583 if (i915_semaphore_is_enabled(dev)) {
2584 WARN_ON(!dev_priv->semaphore_obj);
2585 ring->semaphore.sync_to = gen8_ring_sync;
2586 ring->semaphore.signal = gen8_rcs_signal;
2587 GEN8_RING_SEMAPHORE_INIT;
2588 }
2589 } else if (INTEL_INFO(dev)->gen >= 6) {
2590 ring->add_request = gen6_add_request;
2591 ring->flush = gen7_render_ring_flush;
2592 if (INTEL_INFO(dev)->gen == 6)
2593 ring->flush = gen6_render_ring_flush;
2594 ring->irq_get = gen6_ring_get_irq;
2595 ring->irq_put = gen6_ring_put_irq;
2596 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2597 ring->get_seqno = gen6_ring_get_seqno;
2598 ring->set_seqno = ring_set_seqno;
2599 if (i915_semaphore_is_enabled(dev)) {
2600 ring->semaphore.sync_to = gen6_ring_sync;
2601 ring->semaphore.signal = gen6_signal;
2602 /*
2603 * The current semaphore is only applied on pre-gen8
2604 * platform. And there is no VCS2 ring on the pre-gen8
2605 * platform. So the semaphore between RCS and VCS2 is
2606 * initialized as INVALID. Gen8 will initialize the
2607 * sema between VCS2 and RCS later.
2608 */
2609 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2610 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2611 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2612 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2613 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2614 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2615 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2616 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2617 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2618 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2619 }
2620 } else if (IS_GEN5(dev)) {
2621 ring->add_request = pc_render_add_request;
2622 ring->flush = gen4_render_ring_flush;
2623 ring->get_seqno = pc_render_get_seqno;
2624 ring->set_seqno = pc_render_set_seqno;
2625 ring->irq_get = gen5_ring_get_irq;
2626 ring->irq_put = gen5_ring_put_irq;
2627 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2628 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2629 } else {
2630 ring->add_request = i9xx_add_request;
2631 if (INTEL_INFO(dev)->gen < 4)
2632 ring->flush = gen2_render_ring_flush;
2633 else
2634 ring->flush = gen4_render_ring_flush;
2635 ring->get_seqno = ring_get_seqno;
2636 ring->set_seqno = ring_set_seqno;
2637 if (IS_GEN2(dev)) {
2638 ring->irq_get = i8xx_ring_get_irq;
2639 ring->irq_put = i8xx_ring_put_irq;
2640 } else {
2641 ring->irq_get = i9xx_ring_get_irq;
2642 ring->irq_put = i9xx_ring_put_irq;
2643 }
2644 ring->irq_enable_mask = I915_USER_INTERRUPT;
2645 }
2646 ring->write_tail = ring_write_tail;
2647
2648 if (IS_HASWELL(dev))
2649 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2650 else if (IS_GEN8(dev))
2651 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2652 else if (INTEL_INFO(dev)->gen >= 6)
2653 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2654 else if (INTEL_INFO(dev)->gen >= 4)
2655 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2656 else if (IS_I830(dev) || IS_845G(dev))
2657 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2658 else
2659 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2660 ring->init_hw = init_render_ring;
2661 ring->cleanup = render_ring_cleanup;
2662
2663 /* Workaround batchbuffer to combat CS tlb bug. */
2664 if (HAS_BROKEN_CS_TLB(dev)) {
2665 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2666 if (obj == NULL) {
2667 DRM_ERROR("Failed to allocate batch bo\n");
2668 return -ENOMEM;
2669 }
2670
2671 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2672 if (ret != 0) {
2673 drm_gem_object_unreference(&obj->base);
2674 DRM_ERROR("Failed to ping batch bo\n");
2675 return ret;
2676 }
2677
2678 ring->scratch.obj = obj;
2679 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2680 }
2681
2682 ret = intel_init_ring_buffer(dev, ring);
2683 if (ret)
2684 return ret;
2685
2686 if (INTEL_INFO(dev)->gen >= 5) {
2687 ret = intel_init_pipe_control(ring);
2688 if (ret)
2689 return ret;
2690 }
2691
2692 return 0;
2693 }
2694
2695 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2696 {
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2699
2700 ring->name = "bsd ring";
2701 ring->id = VCS;
2702
2703 ring->write_tail = ring_write_tail;
2704 if (INTEL_INFO(dev)->gen >= 6) {
2705 ring->mmio_base = GEN6_BSD_RING_BASE;
2706 /* gen6 bsd needs a special wa for tail updates */
2707 if (IS_GEN6(dev))
2708 ring->write_tail = gen6_bsd_ring_write_tail;
2709 ring->flush = gen6_bsd_ring_flush;
2710 ring->add_request = gen6_add_request;
2711 ring->get_seqno = gen6_ring_get_seqno;
2712 ring->set_seqno = ring_set_seqno;
2713 if (INTEL_INFO(dev)->gen >= 8) {
2714 ring->irq_enable_mask =
2715 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2716 ring->irq_get = gen8_ring_get_irq;
2717 ring->irq_put = gen8_ring_put_irq;
2718 ring->dispatch_execbuffer =
2719 gen8_ring_dispatch_execbuffer;
2720 if (i915_semaphore_is_enabled(dev)) {
2721 ring->semaphore.sync_to = gen8_ring_sync;
2722 ring->semaphore.signal = gen8_xcs_signal;
2723 GEN8_RING_SEMAPHORE_INIT;
2724 }
2725 } else {
2726 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2727 ring->irq_get = gen6_ring_get_irq;
2728 ring->irq_put = gen6_ring_put_irq;
2729 ring->dispatch_execbuffer =
2730 gen6_ring_dispatch_execbuffer;
2731 if (i915_semaphore_is_enabled(dev)) {
2732 ring->semaphore.sync_to = gen6_ring_sync;
2733 ring->semaphore.signal = gen6_signal;
2734 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2735 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2736 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2737 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2738 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2739 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2740 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2741 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2742 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2743 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2744 }
2745 }
2746 } else {
2747 ring->mmio_base = BSD_RING_BASE;
2748 ring->flush = bsd_ring_flush;
2749 ring->add_request = i9xx_add_request;
2750 ring->get_seqno = ring_get_seqno;
2751 ring->set_seqno = ring_set_seqno;
2752 if (IS_GEN5(dev)) {
2753 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2754 ring->irq_get = gen5_ring_get_irq;
2755 ring->irq_put = gen5_ring_put_irq;
2756 } else {
2757 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2758 ring->irq_get = i9xx_ring_get_irq;
2759 ring->irq_put = i9xx_ring_put_irq;
2760 }
2761 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2762 }
2763 ring->init_hw = init_ring_common;
2764
2765 return intel_init_ring_buffer(dev, ring);
2766 }
2767
2768 /**
2769 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2770 */
2771 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2772 {
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2775
2776 ring->name = "bsd2 ring";
2777 ring->id = VCS2;
2778
2779 ring->write_tail = ring_write_tail;
2780 ring->mmio_base = GEN8_BSD2_RING_BASE;
2781 ring->flush = gen6_bsd_ring_flush;
2782 ring->add_request = gen6_add_request;
2783 ring->get_seqno = gen6_ring_get_seqno;
2784 ring->set_seqno = ring_set_seqno;
2785 ring->irq_enable_mask =
2786 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2787 ring->irq_get = gen8_ring_get_irq;
2788 ring->irq_put = gen8_ring_put_irq;
2789 ring->dispatch_execbuffer =
2790 gen8_ring_dispatch_execbuffer;
2791 if (i915_semaphore_is_enabled(dev)) {
2792 ring->semaphore.sync_to = gen8_ring_sync;
2793 ring->semaphore.signal = gen8_xcs_signal;
2794 GEN8_RING_SEMAPHORE_INIT;
2795 }
2796 ring->init_hw = init_ring_common;
2797
2798 return intel_init_ring_buffer(dev, ring);
2799 }
2800
2801 int intel_init_blt_ring_buffer(struct drm_device *dev)
2802 {
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2805
2806 ring->name = "blitter ring";
2807 ring->id = BCS;
2808
2809 ring->mmio_base = BLT_RING_BASE;
2810 ring->write_tail = ring_write_tail;
2811 ring->flush = gen6_ring_flush;
2812 ring->add_request = gen6_add_request;
2813 ring->get_seqno = gen6_ring_get_seqno;
2814 ring->set_seqno = ring_set_seqno;
2815 if (INTEL_INFO(dev)->gen >= 8) {
2816 ring->irq_enable_mask =
2817 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2818 ring->irq_get = gen8_ring_get_irq;
2819 ring->irq_put = gen8_ring_put_irq;
2820 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2821 if (i915_semaphore_is_enabled(dev)) {
2822 ring->semaphore.sync_to = gen8_ring_sync;
2823 ring->semaphore.signal = gen8_xcs_signal;
2824 GEN8_RING_SEMAPHORE_INIT;
2825 }
2826 } else {
2827 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2828 ring->irq_get = gen6_ring_get_irq;
2829 ring->irq_put = gen6_ring_put_irq;
2830 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2831 if (i915_semaphore_is_enabled(dev)) {
2832 ring->semaphore.signal = gen6_signal;
2833 ring->semaphore.sync_to = gen6_ring_sync;
2834 /*
2835 * The current semaphore is only applied on pre-gen8
2836 * platform. And there is no VCS2 ring on the pre-gen8
2837 * platform. So the semaphore between BCS and VCS2 is
2838 * initialized as INVALID. Gen8 will initialize the
2839 * sema between BCS and VCS2 later.
2840 */
2841 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2842 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2843 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2844 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2845 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2846 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2847 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2848 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2849 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2850 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2851 }
2852 }
2853 ring->init_hw = init_ring_common;
2854
2855 return intel_init_ring_buffer(dev, ring);
2856 }
2857
2858 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2859 {
2860 struct drm_i915_private *dev_priv = dev->dev_private;
2861 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2862
2863 ring->name = "video enhancement ring";
2864 ring->id = VECS;
2865
2866 ring->mmio_base = VEBOX_RING_BASE;
2867 ring->write_tail = ring_write_tail;
2868 ring->flush = gen6_ring_flush;
2869 ring->add_request = gen6_add_request;
2870 ring->get_seqno = gen6_ring_get_seqno;
2871 ring->set_seqno = ring_set_seqno;
2872
2873 if (INTEL_INFO(dev)->gen >= 8) {
2874 ring->irq_enable_mask =
2875 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2876 ring->irq_get = gen8_ring_get_irq;
2877 ring->irq_put = gen8_ring_put_irq;
2878 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2879 if (i915_semaphore_is_enabled(dev)) {
2880 ring->semaphore.sync_to = gen8_ring_sync;
2881 ring->semaphore.signal = gen8_xcs_signal;
2882 GEN8_RING_SEMAPHORE_INIT;
2883 }
2884 } else {
2885 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2886 ring->irq_get = hsw_vebox_get_irq;
2887 ring->irq_put = hsw_vebox_put_irq;
2888 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2889 if (i915_semaphore_is_enabled(dev)) {
2890 ring->semaphore.sync_to = gen6_ring_sync;
2891 ring->semaphore.signal = gen6_signal;
2892 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2893 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2894 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2895 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2896 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2897 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2898 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2899 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2900 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2901 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2902 }
2903 }
2904 ring->init_hw = init_ring_common;
2905
2906 return intel_init_ring_buffer(dev, ring);
2907 }
2908
2909 int
2910 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
2911 {
2912 struct intel_engine_cs *ring = req->ring;
2913 int ret;
2914
2915 if (!ring->gpu_caches_dirty)
2916 return 0;
2917
2918 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
2919 if (ret)
2920 return ret;
2921
2922 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
2923
2924 ring->gpu_caches_dirty = false;
2925 return 0;
2926 }
2927
2928 int
2929 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
2930 {
2931 struct intel_engine_cs *ring = req->ring;
2932 uint32_t flush_domains;
2933 int ret;
2934
2935 flush_domains = 0;
2936 if (ring->gpu_caches_dirty)
2937 flush_domains = I915_GEM_GPU_DOMAINS;
2938
2939 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2940 if (ret)
2941 return ret;
2942
2943 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
2944
2945 ring->gpu_caches_dirty = false;
2946 return 0;
2947 }
2948
2949 void
2950 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2951 {
2952 int ret;
2953
2954 if (!intel_ring_initialized(ring))
2955 return;
2956
2957 ret = intel_ring_idle(ring);
2958 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2959 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2960 ring->name, ret);
2961
2962 stop_ring(ring);
2963 }
Linux kernel - Deliverables
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