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drm/i915: Lazily apply the SNB+ seqno w/a
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 int ret;
218
219 /* Just flush everything. Experiments have shown that reducing the
220 * number of bits based on the write domains has little performance
221 * impact.
222 */
223 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
224 flags |= PIPE_CONTROL_TLB_INVALIDATE;
225 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
226 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
227 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
228 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
229 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
231 /*
232 * Ensure that any following seqno writes only happen when the render
233 * cache is indeed flushed (but only if the caller actually wants that).
234 */
235 if (flush_domains)
236 flags |= PIPE_CONTROL_CS_STALL;
237
238 ret = intel_ring_begin(ring, 4);
239 if (ret)
240 return ret;
241
242 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
243 intel_ring_emit(ring, flags);
244 intel_ring_emit(ring, 0);
245 intel_ring_emit(ring, 0);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static int
252 gen6_render_ring_flush__wa(struct intel_ring_buffer *ring,
253 u32 invalidate_domains, u32 flush_domains)
254 {
255 int ret;
256
257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
262 return gen6_render_ring_flush(ring, invalidate_domains, flush_domains);
263 }
264
265 static void ring_write_tail(struct intel_ring_buffer *ring,
266 u32 value)
267 {
268 drm_i915_private_t *dev_priv = ring->dev->dev_private;
269 I915_WRITE_TAIL(ring, value);
270 }
271
272 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
273 {
274 drm_i915_private_t *dev_priv = ring->dev->dev_private;
275 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
276 RING_ACTHD(ring->mmio_base) : ACTHD;
277
278 return I915_READ(acthd_reg);
279 }
280
281 static int init_ring_common(struct intel_ring_buffer *ring)
282 {
283 struct drm_device *dev = ring->dev;
284 drm_i915_private_t *dev_priv = dev->dev_private;
285 struct drm_i915_gem_object *obj = ring->obj;
286 int ret = 0;
287 u32 head;
288
289 if (HAS_FORCE_WAKE(dev))
290 gen6_gt_force_wake_get(dev_priv);
291
292 /* Stop the ring if it's running. */
293 I915_WRITE_CTL(ring, 0);
294 I915_WRITE_HEAD(ring, 0);
295 ring->write_tail(ring, 0);
296
297 /* Initialize the ring. */
298 I915_WRITE_START(ring, obj->gtt_offset);
299 head = I915_READ_HEAD(ring) & HEAD_ADDR;
300
301 /* G45 ring initialization fails to reset head to zero */
302 if (head != 0) {
303 DRM_DEBUG_KMS("%s head not reset to zero "
304 "ctl %08x head %08x tail %08x start %08x\n",
305 ring->name,
306 I915_READ_CTL(ring),
307 I915_READ_HEAD(ring),
308 I915_READ_TAIL(ring),
309 I915_READ_START(ring));
310
311 I915_WRITE_HEAD(ring, 0);
312
313 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
314 DRM_ERROR("failed to set %s head to zero "
315 "ctl %08x head %08x tail %08x start %08x\n",
316 ring->name,
317 I915_READ_CTL(ring),
318 I915_READ_HEAD(ring),
319 I915_READ_TAIL(ring),
320 I915_READ_START(ring));
321 }
322 }
323
324 I915_WRITE_CTL(ring,
325 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
326 | RING_VALID);
327
328 /* If the head is still not zero, the ring is dead */
329 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
330 I915_READ_START(ring) == obj->gtt_offset &&
331 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
332 DRM_ERROR("%s initialization failed "
333 "ctl %08x head %08x tail %08x start %08x\n",
334 ring->name,
335 I915_READ_CTL(ring),
336 I915_READ_HEAD(ring),
337 I915_READ_TAIL(ring),
338 I915_READ_START(ring));
339 ret = -EIO;
340 goto out;
341 }
342
343 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
344 i915_kernel_lost_context(ring->dev);
345 else {
346 ring->head = I915_READ_HEAD(ring);
347 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
348 ring->space = ring_space(ring);
349 ring->last_retired_head = -1;
350 }
351
352 out:
353 if (HAS_FORCE_WAKE(dev))
354 gen6_gt_force_wake_put(dev_priv);
355
356 return ret;
357 }
358
359 static int
360 init_pipe_control(struct intel_ring_buffer *ring)
361 {
362 struct pipe_control *pc;
363 struct drm_i915_gem_object *obj;
364 int ret;
365
366 if (ring->private)
367 return 0;
368
369 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
370 if (!pc)
371 return -ENOMEM;
372
373 obj = i915_gem_alloc_object(ring->dev, 4096);
374 if (obj == NULL) {
375 DRM_ERROR("Failed to allocate seqno page\n");
376 ret = -ENOMEM;
377 goto err;
378 }
379
380 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
381
382 ret = i915_gem_object_pin(obj, 4096, true);
383 if (ret)
384 goto err_unref;
385
386 pc->gtt_offset = obj->gtt_offset;
387 pc->cpu_page = kmap(obj->pages[0]);
388 if (pc->cpu_page == NULL)
389 goto err_unpin;
390
391 pc->obj = obj;
392 ring->private = pc;
393 return 0;
394
395 err_unpin:
396 i915_gem_object_unpin(obj);
397 err_unref:
398 drm_gem_object_unreference(&obj->base);
399 err:
400 kfree(pc);
401 return ret;
402 }
403
404 static void
405 cleanup_pipe_control(struct intel_ring_buffer *ring)
406 {
407 struct pipe_control *pc = ring->private;
408 struct drm_i915_gem_object *obj;
409
410 if (!ring->private)
411 return;
412
413 obj = pc->obj;
414 kunmap(obj->pages[0]);
415 i915_gem_object_unpin(obj);
416 drm_gem_object_unreference(&obj->base);
417
418 kfree(pc);
419 ring->private = NULL;
420 }
421
422 static int init_render_ring(struct intel_ring_buffer *ring)
423 {
424 struct drm_device *dev = ring->dev;
425 struct drm_i915_private *dev_priv = dev->dev_private;
426 int ret = init_ring_common(ring);
427
428 if (INTEL_INFO(dev)->gen > 3) {
429 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
430 if (IS_GEN7(dev))
431 I915_WRITE(GFX_MODE_GEN7,
432 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
433 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
434 }
435
436 if (INTEL_INFO(dev)->gen >= 5) {
437 ret = init_pipe_control(ring);
438 if (ret)
439 return ret;
440 }
441
442 if (IS_GEN6(dev)) {
443 /* From the Sandybridge PRM, volume 1 part 3, page 24:
444 * "If this bit is set, STCunit will have LRA as replacement
445 * policy. [...] This bit must be reset. LRA replacement
446 * policy is not supported."
447 */
448 I915_WRITE(CACHE_MODE_0,
449 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
450
451 /* This is not explicitly set for GEN6, so read the register.
452 * see intel_ring_mi_set_context() for why we care.
453 * TODO: consider explicitly setting the bit for GEN5
454 */
455 ring->itlb_before_ctx_switch =
456 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
457 }
458
459 if (INTEL_INFO(dev)->gen >= 6)
460 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
461
462 if (HAS_L3_GPU_CACHE(dev))
463 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
464
465 return ret;
466 }
467
468 static void render_ring_cleanup(struct intel_ring_buffer *ring)
469 {
470 if (!ring->private)
471 return;
472
473 cleanup_pipe_control(ring);
474 }
475
476 static void
477 update_mboxes(struct intel_ring_buffer *ring,
478 u32 seqno,
479 u32 mmio_offset)
480 {
481 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
482 MI_SEMAPHORE_GLOBAL_GTT |
483 MI_SEMAPHORE_REGISTER |
484 MI_SEMAPHORE_UPDATE);
485 intel_ring_emit(ring, seqno);
486 intel_ring_emit(ring, mmio_offset);
487 }
488
489 /**
490 * gen6_add_request - Update the semaphore mailbox registers
491 *
492 * @ring - ring that is adding a request
493 * @seqno - return seqno stuck into the ring
494 *
495 * Update the mailbox registers in the *other* rings with the current seqno.
496 * This acts like a signal in the canonical semaphore.
497 */
498 static int
499 gen6_add_request(struct intel_ring_buffer *ring,
500 u32 *seqno)
501 {
502 u32 mbox1_reg;
503 u32 mbox2_reg;
504 int ret;
505
506 ret = intel_ring_begin(ring, 10);
507 if (ret)
508 return ret;
509
510 mbox1_reg = ring->signal_mbox[0];
511 mbox2_reg = ring->signal_mbox[1];
512
513 *seqno = i915_gem_next_request_seqno(ring);
514
515 update_mboxes(ring, *seqno, mbox1_reg);
516 update_mboxes(ring, *seqno, mbox2_reg);
517 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
518 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
519 intel_ring_emit(ring, *seqno);
520 intel_ring_emit(ring, MI_USER_INTERRUPT);
521 intel_ring_advance(ring);
522
523 return 0;
524 }
525
526 /**
527 * intel_ring_sync - sync the waiter to the signaller on seqno
528 *
529 * @waiter - ring that is waiting
530 * @signaller - ring which has, or will signal
531 * @seqno - seqno which the waiter will block on
532 */
533 static int
534 gen6_ring_sync(struct intel_ring_buffer *waiter,
535 struct intel_ring_buffer *signaller,
536 u32 seqno)
537 {
538 int ret;
539 u32 dw1 = MI_SEMAPHORE_MBOX |
540 MI_SEMAPHORE_COMPARE |
541 MI_SEMAPHORE_REGISTER;
542
543 /* Throughout all of the GEM code, seqno passed implies our current
544 * seqno is >= the last seqno executed. However for hardware the
545 * comparison is strictly greater than.
546 */
547 seqno -= 1;
548
549 WARN_ON(signaller->semaphore_register[waiter->id] ==
550 MI_SEMAPHORE_SYNC_INVALID);
551
552 ret = intel_ring_begin(waiter, 4);
553 if (ret)
554 return ret;
555
556 intel_ring_emit(waiter,
557 dw1 | signaller->semaphore_register[waiter->id]);
558 intel_ring_emit(waiter, seqno);
559 intel_ring_emit(waiter, 0);
560 intel_ring_emit(waiter, MI_NOOP);
561 intel_ring_advance(waiter);
562
563 return 0;
564 }
565
566 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
567 do { \
568 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
569 PIPE_CONTROL_DEPTH_STALL); \
570 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
571 intel_ring_emit(ring__, 0); \
572 intel_ring_emit(ring__, 0); \
573 } while (0)
574
575 static int
576 pc_render_add_request(struct intel_ring_buffer *ring,
577 u32 *result)
578 {
579 u32 seqno = i915_gem_next_request_seqno(ring);
580 struct pipe_control *pc = ring->private;
581 u32 scratch_addr = pc->gtt_offset + 128;
582 int ret;
583
584 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
585 * incoherent with writes to memory, i.e. completely fubar,
586 * so we need to use PIPE_NOTIFY instead.
587 *
588 * However, we also need to workaround the qword write
589 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
590 * memory before requesting an interrupt.
591 */
592 ret = intel_ring_begin(ring, 32);
593 if (ret)
594 return ret;
595
596 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
597 PIPE_CONTROL_WRITE_FLUSH |
598 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
599 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
600 intel_ring_emit(ring, seqno);
601 intel_ring_emit(ring, 0);
602 PIPE_CONTROL_FLUSH(ring, scratch_addr);
603 scratch_addr += 128; /* write to separate cachelines */
604 PIPE_CONTROL_FLUSH(ring, scratch_addr);
605 scratch_addr += 128;
606 PIPE_CONTROL_FLUSH(ring, scratch_addr);
607 scratch_addr += 128;
608 PIPE_CONTROL_FLUSH(ring, scratch_addr);
609 scratch_addr += 128;
610 PIPE_CONTROL_FLUSH(ring, scratch_addr);
611 scratch_addr += 128;
612 PIPE_CONTROL_FLUSH(ring, scratch_addr);
613
614 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
615 PIPE_CONTROL_WRITE_FLUSH |
616 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
617 PIPE_CONTROL_NOTIFY);
618 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
619 intel_ring_emit(ring, seqno);
620 intel_ring_emit(ring, 0);
621 intel_ring_advance(ring);
622
623 *result = seqno;
624 return 0;
625 }
626
627 static u32
628 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
629 {
630 /* Workaround to force correct ordering between irq and seqno writes on
631 * ivb (and maybe also on snb) by reading from a CS register (like
632 * ACTHD) before reading the status page. */
633 if (!lazy_coherency)
634 intel_ring_get_active_head(ring);
635 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
636 }
637
638 static u32
639 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
640 {
641 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
642 }
643
644 static u32
645 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
646 {
647 struct pipe_control *pc = ring->private;
648 return pc->cpu_page[0];
649 }
650
651 static bool
652 gen5_ring_get_irq(struct intel_ring_buffer *ring)
653 {
654 struct drm_device *dev = ring->dev;
655 drm_i915_private_t *dev_priv = dev->dev_private;
656 unsigned long flags;
657
658 if (!dev->irq_enabled)
659 return false;
660
661 spin_lock_irqsave(&dev_priv->irq_lock, flags);
662 if (ring->irq_refcount++ == 0) {
663 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
664 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
665 POSTING_READ(GTIMR);
666 }
667 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
668
669 return true;
670 }
671
672 static void
673 gen5_ring_put_irq(struct intel_ring_buffer *ring)
674 {
675 struct drm_device *dev = ring->dev;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 unsigned long flags;
678
679 spin_lock_irqsave(&dev_priv->irq_lock, flags);
680 if (--ring->irq_refcount == 0) {
681 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
682 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
683 POSTING_READ(GTIMR);
684 }
685 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
686 }
687
688 static bool
689 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
690 {
691 struct drm_device *dev = ring->dev;
692 drm_i915_private_t *dev_priv = dev->dev_private;
693 unsigned long flags;
694
695 if (!dev->irq_enabled)
696 return false;
697
698 spin_lock_irqsave(&dev_priv->irq_lock, flags);
699 if (ring->irq_refcount++ == 0) {
700 dev_priv->irq_mask &= ~ring->irq_enable_mask;
701 I915_WRITE(IMR, dev_priv->irq_mask);
702 POSTING_READ(IMR);
703 }
704 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
705
706 return true;
707 }
708
709 static void
710 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
711 {
712 struct drm_device *dev = ring->dev;
713 drm_i915_private_t *dev_priv = dev->dev_private;
714 unsigned long flags;
715
716 spin_lock_irqsave(&dev_priv->irq_lock, flags);
717 if (--ring->irq_refcount == 0) {
718 dev_priv->irq_mask |= ring->irq_enable_mask;
719 I915_WRITE(IMR, dev_priv->irq_mask);
720 POSTING_READ(IMR);
721 }
722 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
723 }
724
725 static bool
726 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
727 {
728 struct drm_device *dev = ring->dev;
729 drm_i915_private_t *dev_priv = dev->dev_private;
730 unsigned long flags;
731
732 if (!dev->irq_enabled)
733 return false;
734
735 spin_lock_irqsave(&dev_priv->irq_lock, flags);
736 if (ring->irq_refcount++ == 0) {
737 dev_priv->irq_mask &= ~ring->irq_enable_mask;
738 I915_WRITE16(IMR, dev_priv->irq_mask);
739 POSTING_READ16(IMR);
740 }
741 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
742
743 return true;
744 }
745
746 static void
747 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
748 {
749 struct drm_device *dev = ring->dev;
750 drm_i915_private_t *dev_priv = dev->dev_private;
751 unsigned long flags;
752
753 spin_lock_irqsave(&dev_priv->irq_lock, flags);
754 if (--ring->irq_refcount == 0) {
755 dev_priv->irq_mask |= ring->irq_enable_mask;
756 I915_WRITE16(IMR, dev_priv->irq_mask);
757 POSTING_READ16(IMR);
758 }
759 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
760 }
761
762 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
763 {
764 struct drm_device *dev = ring->dev;
765 drm_i915_private_t *dev_priv = ring->dev->dev_private;
766 u32 mmio = 0;
767
768 /* The ring status page addresses are no longer next to the rest of
769 * the ring registers as of gen7.
770 */
771 if (IS_GEN7(dev)) {
772 switch (ring->id) {
773 case RCS:
774 mmio = RENDER_HWS_PGA_GEN7;
775 break;
776 case BCS:
777 mmio = BLT_HWS_PGA_GEN7;
778 break;
779 case VCS:
780 mmio = BSD_HWS_PGA_GEN7;
781 break;
782 }
783 } else if (IS_GEN6(ring->dev)) {
784 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
785 } else {
786 mmio = RING_HWS_PGA(ring->mmio_base);
787 }
788
789 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
790 POSTING_READ(mmio);
791 }
792
793 static int
794 bsd_ring_flush(struct intel_ring_buffer *ring,
795 u32 invalidate_domains,
796 u32 flush_domains)
797 {
798 int ret;
799
800 ret = intel_ring_begin(ring, 2);
801 if (ret)
802 return ret;
803
804 intel_ring_emit(ring, MI_FLUSH);
805 intel_ring_emit(ring, MI_NOOP);
806 intel_ring_advance(ring);
807 return 0;
808 }
809
810 static int
811 i9xx_add_request(struct intel_ring_buffer *ring,
812 u32 *result)
813 {
814 u32 seqno;
815 int ret;
816
817 ret = intel_ring_begin(ring, 4);
818 if (ret)
819 return ret;
820
821 seqno = i915_gem_next_request_seqno(ring);
822
823 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
824 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
825 intel_ring_emit(ring, seqno);
826 intel_ring_emit(ring, MI_USER_INTERRUPT);
827 intel_ring_advance(ring);
828
829 *result = seqno;
830 return 0;
831 }
832
833 static bool
834 gen6_ring_get_irq(struct intel_ring_buffer *ring)
835 {
836 struct drm_device *dev = ring->dev;
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 unsigned long flags;
839
840 if (!dev->irq_enabled)
841 return false;
842
843 /* It looks like we need to prevent the gt from suspending while waiting
844 * for an notifiy irq, otherwise irqs seem to get lost on at least the
845 * blt/bsd rings on ivb. */
846 gen6_gt_force_wake_get(dev_priv);
847
848 spin_lock_irqsave(&dev_priv->irq_lock, flags);
849 if (ring->irq_refcount++ == 0) {
850 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
851 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
852 GEN6_RENDER_L3_PARITY_ERROR));
853 else
854 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
855 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
856 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
857 POSTING_READ(GTIMR);
858 }
859 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
860
861 return true;
862 }
863
864 static void
865 gen6_ring_put_irq(struct intel_ring_buffer *ring)
866 {
867 struct drm_device *dev = ring->dev;
868 drm_i915_private_t *dev_priv = dev->dev_private;
869 unsigned long flags;
870
871 spin_lock_irqsave(&dev_priv->irq_lock, flags);
872 if (--ring->irq_refcount == 0) {
873 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
874 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
875 else
876 I915_WRITE_IMR(ring, ~0);
877 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
878 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
879 POSTING_READ(GTIMR);
880 }
881 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
882
883 gen6_gt_force_wake_put(dev_priv);
884 }
885
886 static int
887 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
888 {
889 int ret;
890
891 ret = intel_ring_begin(ring, 2);
892 if (ret)
893 return ret;
894
895 intel_ring_emit(ring,
896 MI_BATCH_BUFFER_START |
897 MI_BATCH_GTT |
898 MI_BATCH_NON_SECURE_I965);
899 intel_ring_emit(ring, offset);
900 intel_ring_advance(ring);
901
902 return 0;
903 }
904
905 static int
906 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
907 u32 offset, u32 len)
908 {
909 int ret;
910
911 ret = intel_ring_begin(ring, 4);
912 if (ret)
913 return ret;
914
915 intel_ring_emit(ring, MI_BATCH_BUFFER);
916 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
917 intel_ring_emit(ring, offset + len - 8);
918 intel_ring_emit(ring, 0);
919 intel_ring_advance(ring);
920
921 return 0;
922 }
923
924 static int
925 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
926 u32 offset, u32 len)
927 {
928 int ret;
929
930 ret = intel_ring_begin(ring, 2);
931 if (ret)
932 return ret;
933
934 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
935 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
936 intel_ring_advance(ring);
937
938 return 0;
939 }
940
941 static void cleanup_status_page(struct intel_ring_buffer *ring)
942 {
943 struct drm_i915_gem_object *obj;
944
945 obj = ring->status_page.obj;
946 if (obj == NULL)
947 return;
948
949 kunmap(obj->pages[0]);
950 i915_gem_object_unpin(obj);
951 drm_gem_object_unreference(&obj->base);
952 ring->status_page.obj = NULL;
953 }
954
955 static int init_status_page(struct intel_ring_buffer *ring)
956 {
957 struct drm_device *dev = ring->dev;
958 struct drm_i915_gem_object *obj;
959 int ret;
960
961 obj = i915_gem_alloc_object(dev, 4096);
962 if (obj == NULL) {
963 DRM_ERROR("Failed to allocate status page\n");
964 ret = -ENOMEM;
965 goto err;
966 }
967
968 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
969
970 ret = i915_gem_object_pin(obj, 4096, true);
971 if (ret != 0) {
972 goto err_unref;
973 }
974
975 ring->status_page.gfx_addr = obj->gtt_offset;
976 ring->status_page.page_addr = kmap(obj->pages[0]);
977 if (ring->status_page.page_addr == NULL) {
978 ret = -ENOMEM;
979 goto err_unpin;
980 }
981 ring->status_page.obj = obj;
982 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
983
984 intel_ring_setup_status_page(ring);
985 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
986 ring->name, ring->status_page.gfx_addr);
987
988 return 0;
989
990 err_unpin:
991 i915_gem_object_unpin(obj);
992 err_unref:
993 drm_gem_object_unreference(&obj->base);
994 err:
995 return ret;
996 }
997
998 static int intel_init_ring_buffer(struct drm_device *dev,
999 struct intel_ring_buffer *ring)
1000 {
1001 struct drm_i915_gem_object *obj;
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 int ret;
1004
1005 ring->dev = dev;
1006 INIT_LIST_HEAD(&ring->active_list);
1007 INIT_LIST_HEAD(&ring->request_list);
1008 ring->size = 32 * PAGE_SIZE;
1009
1010 init_waitqueue_head(&ring->irq_queue);
1011
1012 if (I915_NEED_GFX_HWS(dev)) {
1013 ret = init_status_page(ring);
1014 if (ret)
1015 return ret;
1016 }
1017
1018 obj = i915_gem_alloc_object(dev, ring->size);
1019 if (obj == NULL) {
1020 DRM_ERROR("Failed to allocate ringbuffer\n");
1021 ret = -ENOMEM;
1022 goto err_hws;
1023 }
1024
1025 ring->obj = obj;
1026
1027 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1028 if (ret)
1029 goto err_unref;
1030
1031 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1032 if (ret)
1033 goto err_unpin;
1034
1035 ring->virtual_start =
1036 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1037 ring->size);
1038 if (ring->virtual_start == NULL) {
1039 DRM_ERROR("Failed to map ringbuffer.\n");
1040 ret = -EINVAL;
1041 goto err_unpin;
1042 }
1043
1044 ret = ring->init(ring);
1045 if (ret)
1046 goto err_unmap;
1047
1048 /* Workaround an erratum on the i830 which causes a hang if
1049 * the TAIL pointer points to within the last 2 cachelines
1050 * of the buffer.
1051 */
1052 ring->effective_size = ring->size;
1053 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1054 ring->effective_size -= 128;
1055
1056 return 0;
1057
1058 err_unmap:
1059 iounmap(ring->virtual_start);
1060 err_unpin:
1061 i915_gem_object_unpin(obj);
1062 err_unref:
1063 drm_gem_object_unreference(&obj->base);
1064 ring->obj = NULL;
1065 err_hws:
1066 cleanup_status_page(ring);
1067 return ret;
1068 }
1069
1070 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1071 {
1072 struct drm_i915_private *dev_priv;
1073 int ret;
1074
1075 if (ring->obj == NULL)
1076 return;
1077
1078 /* Disable the ring buffer. The ring must be idle at this point */
1079 dev_priv = ring->dev->dev_private;
1080 ret = intel_wait_ring_idle(ring);
1081 if (ret)
1082 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1083 ring->name, ret);
1084
1085 I915_WRITE_CTL(ring, 0);
1086
1087 iounmap(ring->virtual_start);
1088
1089 i915_gem_object_unpin(ring->obj);
1090 drm_gem_object_unreference(&ring->obj->base);
1091 ring->obj = NULL;
1092
1093 if (ring->cleanup)
1094 ring->cleanup(ring);
1095
1096 cleanup_status_page(ring);
1097 }
1098
1099 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1100 {
1101 uint32_t __iomem *virt;
1102 int rem = ring->size - ring->tail;
1103
1104 if (ring->space < rem) {
1105 int ret = intel_wait_ring_buffer(ring, rem);
1106 if (ret)
1107 return ret;
1108 }
1109
1110 virt = ring->virtual_start + ring->tail;
1111 rem /= 4;
1112 while (rem--)
1113 iowrite32(MI_NOOP, virt++);
1114
1115 ring->tail = 0;
1116 ring->space = ring_space(ring);
1117
1118 return 0;
1119 }
1120
1121 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1122 {
1123 int ret;
1124
1125 ret = i915_wait_seqno(ring, seqno);
1126 if (!ret)
1127 i915_gem_retire_requests_ring(ring);
1128
1129 return ret;
1130 }
1131
1132 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1133 {
1134 struct drm_i915_gem_request *request;
1135 u32 seqno = 0;
1136 int ret;
1137
1138 i915_gem_retire_requests_ring(ring);
1139
1140 if (ring->last_retired_head != -1) {
1141 ring->head = ring->last_retired_head;
1142 ring->last_retired_head = -1;
1143 ring->space = ring_space(ring);
1144 if (ring->space >= n)
1145 return 0;
1146 }
1147
1148 list_for_each_entry(request, &ring->request_list, list) {
1149 int space;
1150
1151 if (request->tail == -1)
1152 continue;
1153
1154 space = request->tail - (ring->tail + 8);
1155 if (space < 0)
1156 space += ring->size;
1157 if (space >= n) {
1158 seqno = request->seqno;
1159 break;
1160 }
1161
1162 /* Consume this request in case we need more space than
1163 * is available and so need to prevent a race between
1164 * updating last_retired_head and direct reads of
1165 * I915_RING_HEAD. It also provides a nice sanity check.
1166 */
1167 request->tail = -1;
1168 }
1169
1170 if (seqno == 0)
1171 return -ENOSPC;
1172
1173 ret = intel_ring_wait_seqno(ring, seqno);
1174 if (ret)
1175 return ret;
1176
1177 if (WARN_ON(ring->last_retired_head == -1))
1178 return -ENOSPC;
1179
1180 ring->head = ring->last_retired_head;
1181 ring->last_retired_head = -1;
1182 ring->space = ring_space(ring);
1183 if (WARN_ON(ring->space < n))
1184 return -ENOSPC;
1185
1186 return 0;
1187 }
1188
1189 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1190 {
1191 struct drm_device *dev = ring->dev;
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 unsigned long end;
1194 int ret;
1195
1196 ret = intel_ring_wait_request(ring, n);
1197 if (ret != -ENOSPC)
1198 return ret;
1199
1200 trace_i915_ring_wait_begin(ring);
1201 /* With GEM the hangcheck timer should kick us out of the loop,
1202 * leaving it early runs the risk of corrupting GEM state (due
1203 * to running on almost untested codepaths). But on resume
1204 * timers don't work yet, so prevent a complete hang in that
1205 * case by choosing an insanely large timeout. */
1206 end = jiffies + 60 * HZ;
1207
1208 do {
1209 ring->head = I915_READ_HEAD(ring);
1210 ring->space = ring_space(ring);
1211 if (ring->space >= n) {
1212 trace_i915_ring_wait_end(ring);
1213 return 0;
1214 }
1215
1216 if (dev->primary->master) {
1217 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1218 if (master_priv->sarea_priv)
1219 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1220 }
1221
1222 msleep(1);
1223
1224 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1225 if (ret)
1226 return ret;
1227 } while (!time_after(jiffies, end));
1228 trace_i915_ring_wait_end(ring);
1229 return -EBUSY;
1230 }
1231
1232 int intel_ring_begin(struct intel_ring_buffer *ring,
1233 int num_dwords)
1234 {
1235 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1236 int n = 4*num_dwords;
1237 int ret;
1238
1239 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1240 if (ret)
1241 return ret;
1242
1243 if (unlikely(ring->tail + n > ring->effective_size)) {
1244 ret = intel_wrap_ring_buffer(ring);
1245 if (unlikely(ret))
1246 return ret;
1247 }
1248
1249 if (unlikely(ring->space < n)) {
1250 ret = intel_wait_ring_buffer(ring, n);
1251 if (unlikely(ret))
1252 return ret;
1253 }
1254
1255 ring->space -= n;
1256 return 0;
1257 }
1258
1259 void intel_ring_advance(struct intel_ring_buffer *ring)
1260 {
1261 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1262
1263 ring->tail &= ring->size - 1;
1264 if (dev_priv->stop_rings & intel_ring_flag(ring))
1265 return;
1266 ring->write_tail(ring, ring->tail);
1267 }
1268
1269
1270 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1271 u32 value)
1272 {
1273 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1274
1275 /* Every tail move must follow the sequence below */
1276
1277 /* Disable notification that the ring is IDLE. The GT
1278 * will then assume that it is busy and bring it out of rc6.
1279 */
1280 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1281 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1282
1283 /* Clear the context id. Here be magic! */
1284 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1285
1286 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1287 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1288 GEN6_BSD_SLEEP_INDICATOR) == 0,
1289 50))
1290 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1291
1292 /* Now that the ring is fully powered up, update the tail */
1293 I915_WRITE_TAIL(ring, value);
1294 POSTING_READ(RING_TAIL(ring->mmio_base));
1295
1296 /* Let the ring send IDLE messages to the GT again,
1297 * and so let it sleep to conserve power when idle.
1298 */
1299 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1300 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1301 }
1302
1303 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1304 u32 invalidate, u32 flush)
1305 {
1306 uint32_t cmd;
1307 int ret;
1308
1309 ret = intel_ring_begin(ring, 4);
1310 if (ret)
1311 return ret;
1312
1313 cmd = MI_FLUSH_DW;
1314 if (invalidate & I915_GEM_GPU_DOMAINS)
1315 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1316 intel_ring_emit(ring, cmd);
1317 intel_ring_emit(ring, 0);
1318 intel_ring_emit(ring, 0);
1319 intel_ring_emit(ring, MI_NOOP);
1320 intel_ring_advance(ring);
1321 return 0;
1322 }
1323
1324 static int
1325 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1326 u32 offset, u32 len)
1327 {
1328 int ret;
1329
1330 ret = intel_ring_begin(ring, 2);
1331 if (ret)
1332 return ret;
1333
1334 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1335 /* bit0-7 is the length on GEN6+ */
1336 intel_ring_emit(ring, offset);
1337 intel_ring_advance(ring);
1338
1339 return 0;
1340 }
1341
1342 /* Blitter support (SandyBridge+) */
1343
1344 static int blt_ring_flush(struct intel_ring_buffer *ring,
1345 u32 invalidate, u32 flush)
1346 {
1347 uint32_t cmd;
1348 int ret;
1349
1350 ret = intel_ring_begin(ring, 4);
1351 if (ret)
1352 return ret;
1353
1354 cmd = MI_FLUSH_DW;
1355 if (invalidate & I915_GEM_DOMAIN_RENDER)
1356 cmd |= MI_INVALIDATE_TLB;
1357 intel_ring_emit(ring, cmd);
1358 intel_ring_emit(ring, 0);
1359 intel_ring_emit(ring, 0);
1360 intel_ring_emit(ring, MI_NOOP);
1361 intel_ring_advance(ring);
1362 return 0;
1363 }
1364
1365 int intel_init_render_ring_buffer(struct drm_device *dev)
1366 {
1367 drm_i915_private_t *dev_priv = dev->dev_private;
1368 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1369
1370 ring->name = "render ring";
1371 ring->id = RCS;
1372 ring->mmio_base = RENDER_RING_BASE;
1373
1374 if (INTEL_INFO(dev)->gen >= 6) {
1375 ring->add_request = gen6_add_request;
1376 ring->flush = gen6_render_ring_flush;
1377 if (INTEL_INFO(dev)->gen == 6)
1378 ring->flush = gen6_render_ring_flush__wa;
1379 ring->irq_get = gen6_ring_get_irq;
1380 ring->irq_put = gen6_ring_put_irq;
1381 ring->irq_enable_mask = GT_USER_INTERRUPT;
1382 ring->get_seqno = gen6_ring_get_seqno;
1383 ring->sync_to = gen6_ring_sync;
1384 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1385 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1386 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1387 ring->signal_mbox[0] = GEN6_VRSYNC;
1388 ring->signal_mbox[1] = GEN6_BRSYNC;
1389 } else if (IS_GEN5(dev)) {
1390 ring->add_request = pc_render_add_request;
1391 ring->flush = gen4_render_ring_flush;
1392 ring->get_seqno = pc_render_get_seqno;
1393 ring->irq_get = gen5_ring_get_irq;
1394 ring->irq_put = gen5_ring_put_irq;
1395 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1396 } else {
1397 ring->add_request = i9xx_add_request;
1398 if (INTEL_INFO(dev)->gen < 4)
1399 ring->flush = gen2_render_ring_flush;
1400 else
1401 ring->flush = gen4_render_ring_flush;
1402 ring->get_seqno = ring_get_seqno;
1403 if (IS_GEN2(dev)) {
1404 ring->irq_get = i8xx_ring_get_irq;
1405 ring->irq_put = i8xx_ring_put_irq;
1406 } else {
1407 ring->irq_get = i9xx_ring_get_irq;
1408 ring->irq_put = i9xx_ring_put_irq;
1409 }
1410 ring->irq_enable_mask = I915_USER_INTERRUPT;
1411 }
1412 ring->write_tail = ring_write_tail;
1413 if (INTEL_INFO(dev)->gen >= 6)
1414 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1415 else if (INTEL_INFO(dev)->gen >= 4)
1416 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1417 else if (IS_I830(dev) || IS_845G(dev))
1418 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1419 else
1420 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1421 ring->init = init_render_ring;
1422 ring->cleanup = render_ring_cleanup;
1423
1424
1425 if (!I915_NEED_GFX_HWS(dev)) {
1426 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1427 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1428 }
1429
1430 return intel_init_ring_buffer(dev, ring);
1431 }
1432
1433 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1434 {
1435 drm_i915_private_t *dev_priv = dev->dev_private;
1436 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1437
1438 ring->name = "render ring";
1439 ring->id = RCS;
1440 ring->mmio_base = RENDER_RING_BASE;
1441
1442 if (INTEL_INFO(dev)->gen >= 6) {
1443 /* non-kms not supported on gen6+ */
1444 return -ENODEV;
1445 }
1446
1447 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1448 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1449 * the special gen5 functions. */
1450 ring->add_request = i9xx_add_request;
1451 if (INTEL_INFO(dev)->gen < 4)
1452 ring->flush = gen2_render_ring_flush;
1453 else
1454 ring->flush = gen4_render_ring_flush;
1455 ring->get_seqno = ring_get_seqno;
1456 if (IS_GEN2(dev)) {
1457 ring->irq_get = i8xx_ring_get_irq;
1458 ring->irq_put = i8xx_ring_put_irq;
1459 } else {
1460 ring->irq_get = i9xx_ring_get_irq;
1461 ring->irq_put = i9xx_ring_put_irq;
1462 }
1463 ring->irq_enable_mask = I915_USER_INTERRUPT;
1464 ring->write_tail = ring_write_tail;
1465 if (INTEL_INFO(dev)->gen >= 4)
1466 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1467 else if (IS_I830(dev) || IS_845G(dev))
1468 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1469 else
1470 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1471 ring->init = init_render_ring;
1472 ring->cleanup = render_ring_cleanup;
1473
1474 if (!I915_NEED_GFX_HWS(dev))
1475 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1476
1477 ring->dev = dev;
1478 INIT_LIST_HEAD(&ring->active_list);
1479 INIT_LIST_HEAD(&ring->request_list);
1480
1481 ring->size = size;
1482 ring->effective_size = ring->size;
1483 if (IS_I830(ring->dev))
1484 ring->effective_size -= 128;
1485
1486 ring->virtual_start = ioremap_wc(start, size);
1487 if (ring->virtual_start == NULL) {
1488 DRM_ERROR("can not ioremap virtual address for"
1489 " ring buffer\n");
1490 return -ENOMEM;
1491 }
1492
1493 return 0;
1494 }
1495
1496 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1497 {
1498 drm_i915_private_t *dev_priv = dev->dev_private;
1499 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1500
1501 ring->name = "bsd ring";
1502 ring->id = VCS;
1503
1504 ring->write_tail = ring_write_tail;
1505 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1506 ring->mmio_base = GEN6_BSD_RING_BASE;
1507 /* gen6 bsd needs a special wa for tail updates */
1508 if (IS_GEN6(dev))
1509 ring->write_tail = gen6_bsd_ring_write_tail;
1510 ring->flush = gen6_ring_flush;
1511 ring->add_request = gen6_add_request;
1512 ring->get_seqno = gen6_ring_get_seqno;
1513 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1514 ring->irq_get = gen6_ring_get_irq;
1515 ring->irq_put = gen6_ring_put_irq;
1516 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1517 ring->sync_to = gen6_ring_sync;
1518 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1519 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1520 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1521 ring->signal_mbox[0] = GEN6_RVSYNC;
1522 ring->signal_mbox[1] = GEN6_BVSYNC;
1523 } else {
1524 ring->mmio_base = BSD_RING_BASE;
1525 ring->flush = bsd_ring_flush;
1526 ring->add_request = i9xx_add_request;
1527 ring->get_seqno = ring_get_seqno;
1528 if (IS_GEN5(dev)) {
1529 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1530 ring->irq_get = gen5_ring_get_irq;
1531 ring->irq_put = gen5_ring_put_irq;
1532 } else {
1533 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1534 ring->irq_get = i9xx_ring_get_irq;
1535 ring->irq_put = i9xx_ring_put_irq;
1536 }
1537 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1538 }
1539 ring->init = init_ring_common;
1540
1541
1542 return intel_init_ring_buffer(dev, ring);
1543 }
1544
1545 int intel_init_blt_ring_buffer(struct drm_device *dev)
1546 {
1547 drm_i915_private_t *dev_priv = dev->dev_private;
1548 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1549
1550 ring->name = "blitter ring";
1551 ring->id = BCS;
1552
1553 ring->mmio_base = BLT_RING_BASE;
1554 ring->write_tail = ring_write_tail;
1555 ring->flush = blt_ring_flush;
1556 ring->add_request = gen6_add_request;
1557 ring->get_seqno = gen6_ring_get_seqno;
1558 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1559 ring->irq_get = gen6_ring_get_irq;
1560 ring->irq_put = gen6_ring_put_irq;
1561 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1562 ring->sync_to = gen6_ring_sync;
1563 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1564 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1565 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1566 ring->signal_mbox[0] = GEN6_RBSYNC;
1567 ring->signal_mbox[1] = GEN6_VBSYNC;
1568 ring->init = init_ring_common;
1569
1570 return intel_init_ring_buffer(dev, ring);
1571 }
1572
1573 int
1574 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1575 {
1576 int ret;
1577
1578 if (!ring->gpu_caches_dirty)
1579 return 0;
1580
1581 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1582 if (ret)
1583 return ret;
1584
1585 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1586
1587 ring->gpu_caches_dirty = false;
1588 return 0;
1589 }
1590
1591 int
1592 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1593 {
1594 uint32_t flush_domains;
1595 int ret;
1596
1597 flush_domains = 0;
1598 if (ring->gpu_caches_dirty)
1599 flush_domains = I915_GEM_GPU_DOMAINS;
1600
1601 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1602 if (ret)
1603 return ret;
1604
1605 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1606
1607 ring->gpu_caches_dirty = false;
1608 return 0;
1609 }
Linux kernel - Deliverables
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