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drm/i915: Virtualize the ringbuffer signal func
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
37 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
38 * to give some inclination as to some of the magic values used in the various
39 * workarounds!
40 */
41 #define CACHELINE_BYTES 64
42
43 static inline int ring_space(struct intel_ring_buffer *ring)
44 {
45 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
46 if (space < 0)
47 space += ring->size;
48 return space;
49 }
50
51 static bool intel_ring_stopped(struct intel_ring_buffer *ring)
52 {
53 struct drm_i915_private *dev_priv = ring->dev->dev_private;
54 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
55 }
56
57 void __intel_ring_advance(struct intel_ring_buffer *ring)
58 {
59 ring->tail &= ring->size - 1;
60 if (intel_ring_stopped(ring))
61 return;
62 ring->write_tail(ring, ring->tail);
63 }
64
65 static int
66 gen2_render_ring_flush(struct intel_ring_buffer *ring,
67 u32 invalidate_domains,
68 u32 flush_domains)
69 {
70 u32 cmd;
71 int ret;
72
73 cmd = MI_FLUSH;
74 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
75 cmd |= MI_NO_WRITE_FLUSH;
76
77 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
78 cmd |= MI_READ_FLUSH;
79
80 ret = intel_ring_begin(ring, 2);
81 if (ret)
82 return ret;
83
84 intel_ring_emit(ring, cmd);
85 intel_ring_emit(ring, MI_NOOP);
86 intel_ring_advance(ring);
87
88 return 0;
89 }
90
91 static int
92 gen4_render_ring_flush(struct intel_ring_buffer *ring,
93 u32 invalidate_domains,
94 u32 flush_domains)
95 {
96 struct drm_device *dev = ring->dev;
97 u32 cmd;
98 int ret;
99
100 /*
101 * read/write caches:
102 *
103 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
104 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
105 * also flushed at 2d versus 3d pipeline switches.
106 *
107 * read-only caches:
108 *
109 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
110 * MI_READ_FLUSH is set, and is always flushed on 965.
111 *
112 * I915_GEM_DOMAIN_COMMAND may not exist?
113 *
114 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
115 * invalidated when MI_EXE_FLUSH is set.
116 *
117 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
118 * invalidated with every MI_FLUSH.
119 *
120 * TLBs:
121 *
122 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
123 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
124 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
125 * are flushed at any MI_FLUSH.
126 */
127
128 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
129 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
130 cmd &= ~MI_NO_WRITE_FLUSH;
131 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
132 cmd |= MI_EXE_FLUSH;
133
134 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
135 (IS_G4X(dev) || IS_GEN5(dev)))
136 cmd |= MI_INVALIDATE_ISP;
137
138 ret = intel_ring_begin(ring, 2);
139 if (ret)
140 return ret;
141
142 intel_ring_emit(ring, cmd);
143 intel_ring_emit(ring, MI_NOOP);
144 intel_ring_advance(ring);
145
146 return 0;
147 }
148
149 /**
150 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
151 * implementing two workarounds on gen6. From section 1.4.7.1
152 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
153 *
154 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
155 * produced by non-pipelined state commands), software needs to first
156 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
157 * 0.
158 *
159 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
160 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
161 *
162 * And the workaround for these two requires this workaround first:
163 *
164 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
165 * BEFORE the pipe-control with a post-sync op and no write-cache
166 * flushes.
167 *
168 * And this last workaround is tricky because of the requirements on
169 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
170 * volume 2 part 1:
171 *
172 * "1 of the following must also be set:
173 * - Render Target Cache Flush Enable ([12] of DW1)
174 * - Depth Cache Flush Enable ([0] of DW1)
175 * - Stall at Pixel Scoreboard ([1] of DW1)
176 * - Depth Stall ([13] of DW1)
177 * - Post-Sync Operation ([13] of DW1)
178 * - Notify Enable ([8] of DW1)"
179 *
180 * The cache flushes require the workaround flush that triggered this
181 * one, so we can't use it. Depth stall would trigger the same.
182 * Post-sync nonzero is what triggered this second workaround, so we
183 * can't use that one either. Notify enable is IRQs, which aren't
184 * really our business. That leaves only stall at scoreboard.
185 */
186 static int
187 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
188 {
189 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
190 int ret;
191
192
193 ret = intel_ring_begin(ring, 6);
194 if (ret)
195 return ret;
196
197 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
198 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
199 PIPE_CONTROL_STALL_AT_SCOREBOARD);
200 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
201 intel_ring_emit(ring, 0); /* low dword */
202 intel_ring_emit(ring, 0); /* high dword */
203 intel_ring_emit(ring, MI_NOOP);
204 intel_ring_advance(ring);
205
206 ret = intel_ring_begin(ring, 6);
207 if (ret)
208 return ret;
209
210 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
211 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
212 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
213 intel_ring_emit(ring, 0);
214 intel_ring_emit(ring, 0);
215 intel_ring_emit(ring, MI_NOOP);
216 intel_ring_advance(ring);
217
218 return 0;
219 }
220
221 static int
222 gen6_render_ring_flush(struct intel_ring_buffer *ring,
223 u32 invalidate_domains, u32 flush_domains)
224 {
225 u32 flags = 0;
226 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
227 int ret;
228
229 /* Force SNB workarounds for PIPE_CONTROL flushes */
230 ret = intel_emit_post_sync_nonzero_flush(ring);
231 if (ret)
232 return ret;
233
234 /* Just flush everything. Experiments have shown that reducing the
235 * number of bits based on the write domains has little performance
236 * impact.
237 */
238 if (flush_domains) {
239 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
240 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
241 /*
242 * Ensure that any following seqno writes only happen
243 * when the render cache is indeed flushed.
244 */
245 flags |= PIPE_CONTROL_CS_STALL;
246 }
247 if (invalidate_domains) {
248 flags |= PIPE_CONTROL_TLB_INVALIDATE;
249 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
250 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
251 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
252 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
253 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
254 /*
255 * TLB invalidate requires a post-sync write.
256 */
257 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
258 }
259
260 ret = intel_ring_begin(ring, 4);
261 if (ret)
262 return ret;
263
264 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
265 intel_ring_emit(ring, flags);
266 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
267 intel_ring_emit(ring, 0);
268 intel_ring_advance(ring);
269
270 return 0;
271 }
272
273 static int
274 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
275 {
276 int ret;
277
278 ret = intel_ring_begin(ring, 4);
279 if (ret)
280 return ret;
281
282 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
283 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
284 PIPE_CONTROL_STALL_AT_SCOREBOARD);
285 intel_ring_emit(ring, 0);
286 intel_ring_emit(ring, 0);
287 intel_ring_advance(ring);
288
289 return 0;
290 }
291
292 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
293 {
294 int ret;
295
296 if (!ring->fbc_dirty)
297 return 0;
298
299 ret = intel_ring_begin(ring, 6);
300 if (ret)
301 return ret;
302 /* WaFbcNukeOn3DBlt:ivb/hsw */
303 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
304 intel_ring_emit(ring, MSG_FBC_REND_STATE);
305 intel_ring_emit(ring, value);
306 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
307 intel_ring_emit(ring, MSG_FBC_REND_STATE);
308 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
309 intel_ring_advance(ring);
310
311 ring->fbc_dirty = false;
312 return 0;
313 }
314
315 static int
316 gen7_render_ring_flush(struct intel_ring_buffer *ring,
317 u32 invalidate_domains, u32 flush_domains)
318 {
319 u32 flags = 0;
320 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
321 int ret;
322
323 /*
324 * Ensure that any following seqno writes only happen when the render
325 * cache is indeed flushed.
326 *
327 * Workaround: 4th PIPE_CONTROL command (except the ones with only
328 * read-cache invalidate bits set) must have the CS_STALL bit set. We
329 * don't try to be clever and just set it unconditionally.
330 */
331 flags |= PIPE_CONTROL_CS_STALL;
332
333 /* Just flush everything. Experiments have shown that reducing the
334 * number of bits based on the write domains has little performance
335 * impact.
336 */
337 if (flush_domains) {
338 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
339 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
340 }
341 if (invalidate_domains) {
342 flags |= PIPE_CONTROL_TLB_INVALIDATE;
343 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
344 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
345 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
346 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
347 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
348 /*
349 * TLB invalidate requires a post-sync write.
350 */
351 flags |= PIPE_CONTROL_QW_WRITE;
352 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
353
354 /* Workaround: we must issue a pipe_control with CS-stall bit
355 * set before a pipe_control command that has the state cache
356 * invalidate bit set. */
357 gen7_render_ring_cs_stall_wa(ring);
358 }
359
360 ret = intel_ring_begin(ring, 4);
361 if (ret)
362 return ret;
363
364 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
365 intel_ring_emit(ring, flags);
366 intel_ring_emit(ring, scratch_addr);
367 intel_ring_emit(ring, 0);
368 intel_ring_advance(ring);
369
370 if (!invalidate_domains && flush_domains)
371 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
372
373 return 0;
374 }
375
376 static int
377 gen8_render_ring_flush(struct intel_ring_buffer *ring,
378 u32 invalidate_domains, u32 flush_domains)
379 {
380 u32 flags = 0;
381 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
382 int ret;
383
384 flags |= PIPE_CONTROL_CS_STALL;
385
386 if (flush_domains) {
387 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
388 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
389 }
390 if (invalidate_domains) {
391 flags |= PIPE_CONTROL_TLB_INVALIDATE;
392 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
393 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
394 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
395 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
396 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
397 flags |= PIPE_CONTROL_QW_WRITE;
398 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
399 }
400
401 ret = intel_ring_begin(ring, 6);
402 if (ret)
403 return ret;
404
405 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
406 intel_ring_emit(ring, flags);
407 intel_ring_emit(ring, scratch_addr);
408 intel_ring_emit(ring, 0);
409 intel_ring_emit(ring, 0);
410 intel_ring_emit(ring, 0);
411 intel_ring_advance(ring);
412
413 return 0;
414
415 }
416
417 static void ring_write_tail(struct intel_ring_buffer *ring,
418 u32 value)
419 {
420 struct drm_i915_private *dev_priv = ring->dev->dev_private;
421 I915_WRITE_TAIL(ring, value);
422 }
423
424 u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
425 {
426 struct drm_i915_private *dev_priv = ring->dev->dev_private;
427 u64 acthd;
428
429 if (INTEL_INFO(ring->dev)->gen >= 8)
430 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
431 RING_ACTHD_UDW(ring->mmio_base));
432 else if (INTEL_INFO(ring->dev)->gen >= 4)
433 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
434 else
435 acthd = I915_READ(ACTHD);
436
437 return acthd;
438 }
439
440 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
441 {
442 struct drm_i915_private *dev_priv = ring->dev->dev_private;
443 u32 addr;
444
445 addr = dev_priv->status_page_dmah->busaddr;
446 if (INTEL_INFO(ring->dev)->gen >= 4)
447 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
448 I915_WRITE(HWS_PGA, addr);
449 }
450
451 static bool stop_ring(struct intel_ring_buffer *ring)
452 {
453 struct drm_i915_private *dev_priv = to_i915(ring->dev);
454
455 if (!IS_GEN2(ring->dev)) {
456 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
457 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
458 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
459 return false;
460 }
461 }
462
463 I915_WRITE_CTL(ring, 0);
464 I915_WRITE_HEAD(ring, 0);
465 ring->write_tail(ring, 0);
466
467 if (!IS_GEN2(ring->dev)) {
468 (void)I915_READ_CTL(ring);
469 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
470 }
471
472 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
473 }
474
475 static int init_ring_common(struct intel_ring_buffer *ring)
476 {
477 struct drm_device *dev = ring->dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 struct drm_i915_gem_object *obj = ring->obj;
480 int ret = 0;
481
482 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
483
484 if (!stop_ring(ring)) {
485 /* G45 ring initialization often fails to reset head to zero */
486 DRM_DEBUG_KMS("%s head not reset to zero "
487 "ctl %08x head %08x tail %08x start %08x\n",
488 ring->name,
489 I915_READ_CTL(ring),
490 I915_READ_HEAD(ring),
491 I915_READ_TAIL(ring),
492 I915_READ_START(ring));
493
494 if (!stop_ring(ring)) {
495 DRM_ERROR("failed to set %s head to zero "
496 "ctl %08x head %08x tail %08x start %08x\n",
497 ring->name,
498 I915_READ_CTL(ring),
499 I915_READ_HEAD(ring),
500 I915_READ_TAIL(ring),
501 I915_READ_START(ring));
502 ret = -EIO;
503 goto out;
504 }
505 }
506
507 if (I915_NEED_GFX_HWS(dev))
508 intel_ring_setup_status_page(ring);
509 else
510 ring_setup_phys_status_page(ring);
511
512 /* Initialize the ring. This must happen _after_ we've cleared the ring
513 * registers with the above sequence (the readback of the HEAD registers
514 * also enforces ordering), otherwise the hw might lose the new ring
515 * register values. */
516 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
517 I915_WRITE_CTL(ring,
518 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
519 | RING_VALID);
520
521 /* If the head is still not zero, the ring is dead */
522 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
523 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
524 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
525 DRM_ERROR("%s initialization failed "
526 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
527 ring->name,
528 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
529 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
530 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
531 ret = -EIO;
532 goto out;
533 }
534
535 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
536 i915_kernel_lost_context(ring->dev);
537 else {
538 ring->head = I915_READ_HEAD(ring);
539 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
540 ring->space = ring_space(ring);
541 ring->last_retired_head = -1;
542 }
543
544 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
545
546 out:
547 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
548
549 return ret;
550 }
551
552 static int
553 init_pipe_control(struct intel_ring_buffer *ring)
554 {
555 int ret;
556
557 if (ring->scratch.obj)
558 return 0;
559
560 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
561 if (ring->scratch.obj == NULL) {
562 DRM_ERROR("Failed to allocate seqno page\n");
563 ret = -ENOMEM;
564 goto err;
565 }
566
567 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
568 if (ret)
569 goto err_unref;
570
571 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
572 if (ret)
573 goto err_unref;
574
575 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
576 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
577 if (ring->scratch.cpu_page == NULL) {
578 ret = -ENOMEM;
579 goto err_unpin;
580 }
581
582 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
583 ring->name, ring->scratch.gtt_offset);
584 return 0;
585
586 err_unpin:
587 i915_gem_object_ggtt_unpin(ring->scratch.obj);
588 err_unref:
589 drm_gem_object_unreference(&ring->scratch.obj->base);
590 err:
591 return ret;
592 }
593
594 static int init_render_ring(struct intel_ring_buffer *ring)
595 {
596 struct drm_device *dev = ring->dev;
597 struct drm_i915_private *dev_priv = dev->dev_private;
598 int ret = init_ring_common(ring);
599
600 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
601 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
602 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
603
604 /* We need to disable the AsyncFlip performance optimisations in order
605 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
606 * programmed to '1' on all products.
607 *
608 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
609 */
610 if (INTEL_INFO(dev)->gen >= 6)
611 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
612
613 /* Required for the hardware to program scanline values for waiting */
614 /* WaEnableFlushTlbInvalidationMode:snb */
615 if (INTEL_INFO(dev)->gen == 6)
616 I915_WRITE(GFX_MODE,
617 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
618
619 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
620 if (IS_GEN7(dev))
621 I915_WRITE(GFX_MODE_GEN7,
622 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
623 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
624
625 if (INTEL_INFO(dev)->gen >= 5) {
626 ret = init_pipe_control(ring);
627 if (ret)
628 return ret;
629 }
630
631 if (IS_GEN6(dev)) {
632 /* From the Sandybridge PRM, volume 1 part 3, page 24:
633 * "If this bit is set, STCunit will have LRA as replacement
634 * policy. [...] This bit must be reset. LRA replacement
635 * policy is not supported."
636 */
637 I915_WRITE(CACHE_MODE_0,
638 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
639 }
640
641 if (INTEL_INFO(dev)->gen >= 6)
642 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
643
644 if (HAS_L3_DPF(dev))
645 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
646
647 return ret;
648 }
649
650 static void render_ring_cleanup(struct intel_ring_buffer *ring)
651 {
652 struct drm_device *dev = ring->dev;
653
654 if (ring->scratch.obj == NULL)
655 return;
656
657 if (INTEL_INFO(dev)->gen >= 5) {
658 kunmap(sg_page(ring->scratch.obj->pages->sgl));
659 i915_gem_object_ggtt_unpin(ring->scratch.obj);
660 }
661
662 drm_gem_object_unreference(&ring->scratch.obj->base);
663 ring->scratch.obj = NULL;
664 }
665
666 static void gen6_signal(struct intel_ring_buffer *signaller)
667 {
668 struct drm_i915_private *dev_priv = signaller->dev->dev_private;
669 struct intel_ring_buffer *useless;
670 int i;
671
672 /* NB: In order to be able to do semaphore MBOX updates for varying number
673 * of rings, it's easiest if we round up each individual update to a
674 * multiple of 2 (since ring updates must always be a multiple of 2)
675 * even though the actual update only requires 3 dwords.
676 */
677 #define MBOX_UPDATE_DWORDS 4
678 for_each_ring(useless, dev_priv, i) {
679 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
680 if (mbox_reg != GEN6_NOSYNC) {
681 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
682 intel_ring_emit(signaller, mbox_reg);
683 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
684 intel_ring_emit(signaller, MI_NOOP);
685 } else {
686 intel_ring_emit(signaller, MI_NOOP);
687 intel_ring_emit(signaller, MI_NOOP);
688 intel_ring_emit(signaller, MI_NOOP);
689 intel_ring_emit(signaller, MI_NOOP);
690 }
691 }
692 }
693
694 /**
695 * gen6_add_request - Update the semaphore mailbox registers
696 *
697 * @ring - ring that is adding a request
698 * @seqno - return seqno stuck into the ring
699 *
700 * Update the mailbox registers in the *other* rings with the current seqno.
701 * This acts like a signal in the canonical semaphore.
702 */
703 static int
704 gen6_add_request(struct intel_ring_buffer *ring)
705 {
706 struct drm_device *dev = ring->dev;
707 int ret, num_dwords = 4;
708
709 if (i915_semaphore_is_enabled(dev))
710 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
711 #undef MBOX_UPDATE_DWORDS
712
713 ret = intel_ring_begin(ring, num_dwords);
714 if (ret)
715 return ret;
716
717 ring->semaphore.signal(ring);
718
719 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
720 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
721 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
722 intel_ring_emit(ring, MI_USER_INTERRUPT);
723 __intel_ring_advance(ring);
724
725 return 0;
726 }
727
728 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
729 u32 seqno)
730 {
731 struct drm_i915_private *dev_priv = dev->dev_private;
732 return dev_priv->last_seqno < seqno;
733 }
734
735 /**
736 * intel_ring_sync - sync the waiter to the signaller on seqno
737 *
738 * @waiter - ring that is waiting
739 * @signaller - ring which has, or will signal
740 * @seqno - seqno which the waiter will block on
741 */
742 static int
743 gen6_ring_sync(struct intel_ring_buffer *waiter,
744 struct intel_ring_buffer *signaller,
745 u32 seqno)
746 {
747 u32 dw1 = MI_SEMAPHORE_MBOX |
748 MI_SEMAPHORE_COMPARE |
749 MI_SEMAPHORE_REGISTER;
750 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
751 int ret;
752
753 /* Throughout all of the GEM code, seqno passed implies our current
754 * seqno is >= the last seqno executed. However for hardware the
755 * comparison is strictly greater than.
756 */
757 seqno -= 1;
758
759 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
760
761 ret = intel_ring_begin(waiter, 4);
762 if (ret)
763 return ret;
764
765 /* If seqno wrap happened, omit the wait with no-ops */
766 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
767 intel_ring_emit(waiter, dw1 | wait_mbox);
768 intel_ring_emit(waiter, seqno);
769 intel_ring_emit(waiter, 0);
770 intel_ring_emit(waiter, MI_NOOP);
771 } else {
772 intel_ring_emit(waiter, MI_NOOP);
773 intel_ring_emit(waiter, MI_NOOP);
774 intel_ring_emit(waiter, MI_NOOP);
775 intel_ring_emit(waiter, MI_NOOP);
776 }
777 intel_ring_advance(waiter);
778
779 return 0;
780 }
781
782 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
783 do { \
784 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
785 PIPE_CONTROL_DEPTH_STALL); \
786 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
787 intel_ring_emit(ring__, 0); \
788 intel_ring_emit(ring__, 0); \
789 } while (0)
790
791 static int
792 pc_render_add_request(struct intel_ring_buffer *ring)
793 {
794 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
795 int ret;
796
797 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
798 * incoherent with writes to memory, i.e. completely fubar,
799 * so we need to use PIPE_NOTIFY instead.
800 *
801 * However, we also need to workaround the qword write
802 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
803 * memory before requesting an interrupt.
804 */
805 ret = intel_ring_begin(ring, 32);
806 if (ret)
807 return ret;
808
809 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
810 PIPE_CONTROL_WRITE_FLUSH |
811 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
812 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
813 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
814 intel_ring_emit(ring, 0);
815 PIPE_CONTROL_FLUSH(ring, scratch_addr);
816 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
817 PIPE_CONTROL_FLUSH(ring, scratch_addr);
818 scratch_addr += 2 * CACHELINE_BYTES;
819 PIPE_CONTROL_FLUSH(ring, scratch_addr);
820 scratch_addr += 2 * CACHELINE_BYTES;
821 PIPE_CONTROL_FLUSH(ring, scratch_addr);
822 scratch_addr += 2 * CACHELINE_BYTES;
823 PIPE_CONTROL_FLUSH(ring, scratch_addr);
824 scratch_addr += 2 * CACHELINE_BYTES;
825 PIPE_CONTROL_FLUSH(ring, scratch_addr);
826
827 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
828 PIPE_CONTROL_WRITE_FLUSH |
829 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
830 PIPE_CONTROL_NOTIFY);
831 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
832 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
833 intel_ring_emit(ring, 0);
834 __intel_ring_advance(ring);
835
836 return 0;
837 }
838
839 static u32
840 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
841 {
842 /* Workaround to force correct ordering between irq and seqno writes on
843 * ivb (and maybe also on snb) by reading from a CS register (like
844 * ACTHD) before reading the status page. */
845 if (!lazy_coherency) {
846 struct drm_i915_private *dev_priv = ring->dev->dev_private;
847 POSTING_READ(RING_ACTHD(ring->mmio_base));
848 }
849
850 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
851 }
852
853 static u32
854 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
855 {
856 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
857 }
858
859 static void
860 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
861 {
862 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
863 }
864
865 static u32
866 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
867 {
868 return ring->scratch.cpu_page[0];
869 }
870
871 static void
872 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
873 {
874 ring->scratch.cpu_page[0] = seqno;
875 }
876
877 static bool
878 gen5_ring_get_irq(struct intel_ring_buffer *ring)
879 {
880 struct drm_device *dev = ring->dev;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 unsigned long flags;
883
884 if (!dev->irq_enabled)
885 return false;
886
887 spin_lock_irqsave(&dev_priv->irq_lock, flags);
888 if (ring->irq_refcount++ == 0)
889 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
890 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
891
892 return true;
893 }
894
895 static void
896 gen5_ring_put_irq(struct intel_ring_buffer *ring)
897 {
898 struct drm_device *dev = ring->dev;
899 struct drm_i915_private *dev_priv = dev->dev_private;
900 unsigned long flags;
901
902 spin_lock_irqsave(&dev_priv->irq_lock, flags);
903 if (--ring->irq_refcount == 0)
904 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
905 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
906 }
907
908 static bool
909 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
910 {
911 struct drm_device *dev = ring->dev;
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 unsigned long flags;
914
915 if (!dev->irq_enabled)
916 return false;
917
918 spin_lock_irqsave(&dev_priv->irq_lock, flags);
919 if (ring->irq_refcount++ == 0) {
920 dev_priv->irq_mask &= ~ring->irq_enable_mask;
921 I915_WRITE(IMR, dev_priv->irq_mask);
922 POSTING_READ(IMR);
923 }
924 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
925
926 return true;
927 }
928
929 static void
930 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
931 {
932 struct drm_device *dev = ring->dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 unsigned long flags;
935
936 spin_lock_irqsave(&dev_priv->irq_lock, flags);
937 if (--ring->irq_refcount == 0) {
938 dev_priv->irq_mask |= ring->irq_enable_mask;
939 I915_WRITE(IMR, dev_priv->irq_mask);
940 POSTING_READ(IMR);
941 }
942 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
943 }
944
945 static bool
946 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
947 {
948 struct drm_device *dev = ring->dev;
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 unsigned long flags;
951
952 if (!dev->irq_enabled)
953 return false;
954
955 spin_lock_irqsave(&dev_priv->irq_lock, flags);
956 if (ring->irq_refcount++ == 0) {
957 dev_priv->irq_mask &= ~ring->irq_enable_mask;
958 I915_WRITE16(IMR, dev_priv->irq_mask);
959 POSTING_READ16(IMR);
960 }
961 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
962
963 return true;
964 }
965
966 static void
967 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
968 {
969 struct drm_device *dev = ring->dev;
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 unsigned long flags;
972
973 spin_lock_irqsave(&dev_priv->irq_lock, flags);
974 if (--ring->irq_refcount == 0) {
975 dev_priv->irq_mask |= ring->irq_enable_mask;
976 I915_WRITE16(IMR, dev_priv->irq_mask);
977 POSTING_READ16(IMR);
978 }
979 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
980 }
981
982 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
983 {
984 struct drm_device *dev = ring->dev;
985 struct drm_i915_private *dev_priv = ring->dev->dev_private;
986 u32 mmio = 0;
987
988 /* The ring status page addresses are no longer next to the rest of
989 * the ring registers as of gen7.
990 */
991 if (IS_GEN7(dev)) {
992 switch (ring->id) {
993 case RCS:
994 mmio = RENDER_HWS_PGA_GEN7;
995 break;
996 case BCS:
997 mmio = BLT_HWS_PGA_GEN7;
998 break;
999 /*
1000 * VCS2 actually doesn't exist on Gen7. Only shut up
1001 * gcc switch check warning
1002 */
1003 case VCS2:
1004 case VCS:
1005 mmio = BSD_HWS_PGA_GEN7;
1006 break;
1007 case VECS:
1008 mmio = VEBOX_HWS_PGA_GEN7;
1009 break;
1010 }
1011 } else if (IS_GEN6(ring->dev)) {
1012 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1013 } else {
1014 /* XXX: gen8 returns to sanity */
1015 mmio = RING_HWS_PGA(ring->mmio_base);
1016 }
1017
1018 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1019 POSTING_READ(mmio);
1020
1021 /*
1022 * Flush the TLB for this page
1023 *
1024 * FIXME: These two bits have disappeared on gen8, so a question
1025 * arises: do we still need this and if so how should we go about
1026 * invalidating the TLB?
1027 */
1028 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1029 u32 reg = RING_INSTPM(ring->mmio_base);
1030
1031 /* ring should be idle before issuing a sync flush*/
1032 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1033
1034 I915_WRITE(reg,
1035 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1036 INSTPM_SYNC_FLUSH));
1037 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1038 1000))
1039 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1040 ring->name);
1041 }
1042 }
1043
1044 static int
1045 bsd_ring_flush(struct intel_ring_buffer *ring,
1046 u32 invalidate_domains,
1047 u32 flush_domains)
1048 {
1049 int ret;
1050
1051 ret = intel_ring_begin(ring, 2);
1052 if (ret)
1053 return ret;
1054
1055 intel_ring_emit(ring, MI_FLUSH);
1056 intel_ring_emit(ring, MI_NOOP);
1057 intel_ring_advance(ring);
1058 return 0;
1059 }
1060
1061 static int
1062 i9xx_add_request(struct intel_ring_buffer *ring)
1063 {
1064 int ret;
1065
1066 ret = intel_ring_begin(ring, 4);
1067 if (ret)
1068 return ret;
1069
1070 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1071 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1072 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1073 intel_ring_emit(ring, MI_USER_INTERRUPT);
1074 __intel_ring_advance(ring);
1075
1076 return 0;
1077 }
1078
1079 static bool
1080 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1081 {
1082 struct drm_device *dev = ring->dev;
1083 struct drm_i915_private *dev_priv = dev->dev_private;
1084 unsigned long flags;
1085
1086 if (!dev->irq_enabled)
1087 return false;
1088
1089 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1090 if (ring->irq_refcount++ == 0) {
1091 if (HAS_L3_DPF(dev) && ring->id == RCS)
1092 I915_WRITE_IMR(ring,
1093 ~(ring->irq_enable_mask |
1094 GT_PARITY_ERROR(dev)));
1095 else
1096 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1097 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1098 }
1099 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1100
1101 return true;
1102 }
1103
1104 static void
1105 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1106 {
1107 struct drm_device *dev = ring->dev;
1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109 unsigned long flags;
1110
1111 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1112 if (--ring->irq_refcount == 0) {
1113 if (HAS_L3_DPF(dev) && ring->id == RCS)
1114 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1115 else
1116 I915_WRITE_IMR(ring, ~0);
1117 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1118 }
1119 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1120 }
1121
1122 static bool
1123 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1124 {
1125 struct drm_device *dev = ring->dev;
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127 unsigned long flags;
1128
1129 if (!dev->irq_enabled)
1130 return false;
1131
1132 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1133 if (ring->irq_refcount++ == 0) {
1134 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1135 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1136 }
1137 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1138
1139 return true;
1140 }
1141
1142 static void
1143 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1144 {
1145 struct drm_device *dev = ring->dev;
1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 unsigned long flags;
1148
1149 if (!dev->irq_enabled)
1150 return;
1151
1152 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1153 if (--ring->irq_refcount == 0) {
1154 I915_WRITE_IMR(ring, ~0);
1155 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1156 }
1157 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1158 }
1159
1160 static bool
1161 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1162 {
1163 struct drm_device *dev = ring->dev;
1164 struct drm_i915_private *dev_priv = dev->dev_private;
1165 unsigned long flags;
1166
1167 if (!dev->irq_enabled)
1168 return false;
1169
1170 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1171 if (ring->irq_refcount++ == 0) {
1172 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1173 I915_WRITE_IMR(ring,
1174 ~(ring->irq_enable_mask |
1175 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1176 } else {
1177 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1178 }
1179 POSTING_READ(RING_IMR(ring->mmio_base));
1180 }
1181 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1182
1183 return true;
1184 }
1185
1186 static void
1187 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1188 {
1189 struct drm_device *dev = ring->dev;
1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 unsigned long flags;
1192
1193 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1194 if (--ring->irq_refcount == 0) {
1195 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1196 I915_WRITE_IMR(ring,
1197 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1198 } else {
1199 I915_WRITE_IMR(ring, ~0);
1200 }
1201 POSTING_READ(RING_IMR(ring->mmio_base));
1202 }
1203 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1204 }
1205
1206 static int
1207 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1208 u32 offset, u32 length,
1209 unsigned flags)
1210 {
1211 int ret;
1212
1213 ret = intel_ring_begin(ring, 2);
1214 if (ret)
1215 return ret;
1216
1217 intel_ring_emit(ring,
1218 MI_BATCH_BUFFER_START |
1219 MI_BATCH_GTT |
1220 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1221 intel_ring_emit(ring, offset);
1222 intel_ring_advance(ring);
1223
1224 return 0;
1225 }
1226
1227 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1228 #define I830_BATCH_LIMIT (256*1024)
1229 static int
1230 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1231 u32 offset, u32 len,
1232 unsigned flags)
1233 {
1234 int ret;
1235
1236 if (flags & I915_DISPATCH_PINNED) {
1237 ret = intel_ring_begin(ring, 4);
1238 if (ret)
1239 return ret;
1240
1241 intel_ring_emit(ring, MI_BATCH_BUFFER);
1242 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1243 intel_ring_emit(ring, offset + len - 8);
1244 intel_ring_emit(ring, MI_NOOP);
1245 intel_ring_advance(ring);
1246 } else {
1247 u32 cs_offset = ring->scratch.gtt_offset;
1248
1249 if (len > I830_BATCH_LIMIT)
1250 return -ENOSPC;
1251
1252 ret = intel_ring_begin(ring, 9+3);
1253 if (ret)
1254 return ret;
1255 /* Blit the batch (which has now all relocs applied) to the stable batch
1256 * scratch bo area (so that the CS never stumbles over its tlb
1257 * invalidation bug) ... */
1258 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1259 XY_SRC_COPY_BLT_WRITE_ALPHA |
1260 XY_SRC_COPY_BLT_WRITE_RGB);
1261 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1262 intel_ring_emit(ring, 0);
1263 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1264 intel_ring_emit(ring, cs_offset);
1265 intel_ring_emit(ring, 0);
1266 intel_ring_emit(ring, 4096);
1267 intel_ring_emit(ring, offset);
1268 intel_ring_emit(ring, MI_FLUSH);
1269
1270 /* ... and execute it. */
1271 intel_ring_emit(ring, MI_BATCH_BUFFER);
1272 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1273 intel_ring_emit(ring, cs_offset + len - 8);
1274 intel_ring_advance(ring);
1275 }
1276
1277 return 0;
1278 }
1279
1280 static int
1281 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1282 u32 offset, u32 len,
1283 unsigned flags)
1284 {
1285 int ret;
1286
1287 ret = intel_ring_begin(ring, 2);
1288 if (ret)
1289 return ret;
1290
1291 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1292 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1293 intel_ring_advance(ring);
1294
1295 return 0;
1296 }
1297
1298 static void cleanup_status_page(struct intel_ring_buffer *ring)
1299 {
1300 struct drm_i915_gem_object *obj;
1301
1302 obj = ring->status_page.obj;
1303 if (obj == NULL)
1304 return;
1305
1306 kunmap(sg_page(obj->pages->sgl));
1307 i915_gem_object_ggtt_unpin(obj);
1308 drm_gem_object_unreference(&obj->base);
1309 ring->status_page.obj = NULL;
1310 }
1311
1312 static int init_status_page(struct intel_ring_buffer *ring)
1313 {
1314 struct drm_i915_gem_object *obj;
1315
1316 if ((obj = ring->status_page.obj) == NULL) {
1317 int ret;
1318
1319 obj = i915_gem_alloc_object(ring->dev, 4096);
1320 if (obj == NULL) {
1321 DRM_ERROR("Failed to allocate status page\n");
1322 return -ENOMEM;
1323 }
1324
1325 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1326 if (ret)
1327 goto err_unref;
1328
1329 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1330 if (ret) {
1331 err_unref:
1332 drm_gem_object_unreference(&obj->base);
1333 return ret;
1334 }
1335
1336 ring->status_page.obj = obj;
1337 }
1338
1339 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1340 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1341 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1342
1343 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1344 ring->name, ring->status_page.gfx_addr);
1345
1346 return 0;
1347 }
1348
1349 static int init_phys_status_page(struct intel_ring_buffer *ring)
1350 {
1351 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1352
1353 if (!dev_priv->status_page_dmah) {
1354 dev_priv->status_page_dmah =
1355 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1356 if (!dev_priv->status_page_dmah)
1357 return -ENOMEM;
1358 }
1359
1360 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1361 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1362
1363 return 0;
1364 }
1365
1366 static int allocate_ring_buffer(struct intel_ring_buffer *ring)
1367 {
1368 struct drm_device *dev = ring->dev;
1369 struct drm_i915_private *dev_priv = to_i915(dev);
1370 struct drm_i915_gem_object *obj;
1371 int ret;
1372
1373 if (ring->obj)
1374 return 0;
1375
1376 obj = NULL;
1377 if (!HAS_LLC(dev))
1378 obj = i915_gem_object_create_stolen(dev, ring->size);
1379 if (obj == NULL)
1380 obj = i915_gem_alloc_object(dev, ring->size);
1381 if (obj == NULL)
1382 return -ENOMEM;
1383
1384 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1385 if (ret)
1386 goto err_unref;
1387
1388 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1389 if (ret)
1390 goto err_unpin;
1391
1392 ring->virtual_start =
1393 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1394 ring->size);
1395 if (ring->virtual_start == NULL) {
1396 ret = -EINVAL;
1397 goto err_unpin;
1398 }
1399
1400 ring->obj = obj;
1401 return 0;
1402
1403 err_unpin:
1404 i915_gem_object_ggtt_unpin(obj);
1405 err_unref:
1406 drm_gem_object_unreference(&obj->base);
1407 return ret;
1408 }
1409
1410 static int intel_init_ring_buffer(struct drm_device *dev,
1411 struct intel_ring_buffer *ring)
1412 {
1413 int ret;
1414
1415 ring->dev = dev;
1416 INIT_LIST_HEAD(&ring->active_list);
1417 INIT_LIST_HEAD(&ring->request_list);
1418 ring->size = 32 * PAGE_SIZE;
1419 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1420
1421 init_waitqueue_head(&ring->irq_queue);
1422
1423 if (I915_NEED_GFX_HWS(dev)) {
1424 ret = init_status_page(ring);
1425 if (ret)
1426 return ret;
1427 } else {
1428 BUG_ON(ring->id != RCS);
1429 ret = init_phys_status_page(ring);
1430 if (ret)
1431 return ret;
1432 }
1433
1434 ret = allocate_ring_buffer(ring);
1435 if (ret) {
1436 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1437 return ret;
1438 }
1439
1440 /* Workaround an erratum on the i830 which causes a hang if
1441 * the TAIL pointer points to within the last 2 cachelines
1442 * of the buffer.
1443 */
1444 ring->effective_size = ring->size;
1445 if (IS_I830(dev) || IS_845G(dev))
1446 ring->effective_size -= 2 * CACHELINE_BYTES;
1447
1448 i915_cmd_parser_init_ring(ring);
1449
1450 return ring->init(ring);
1451 }
1452
1453 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1454 {
1455 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1456
1457 if (ring->obj == NULL)
1458 return;
1459
1460 intel_stop_ring_buffer(ring);
1461 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1462
1463 iounmap(ring->virtual_start);
1464
1465 i915_gem_object_ggtt_unpin(ring->obj);
1466 drm_gem_object_unreference(&ring->obj->base);
1467 ring->obj = NULL;
1468 ring->preallocated_lazy_request = NULL;
1469 ring->outstanding_lazy_seqno = 0;
1470
1471 if (ring->cleanup)
1472 ring->cleanup(ring);
1473
1474 cleanup_status_page(ring);
1475 }
1476
1477 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1478 {
1479 struct drm_i915_gem_request *request;
1480 u32 seqno = 0, tail;
1481 int ret;
1482
1483 if (ring->last_retired_head != -1) {
1484 ring->head = ring->last_retired_head;
1485 ring->last_retired_head = -1;
1486
1487 ring->space = ring_space(ring);
1488 if (ring->space >= n)
1489 return 0;
1490 }
1491
1492 list_for_each_entry(request, &ring->request_list, list) {
1493 int space;
1494
1495 if (request->tail == -1)
1496 continue;
1497
1498 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1499 if (space < 0)
1500 space += ring->size;
1501 if (space >= n) {
1502 seqno = request->seqno;
1503 tail = request->tail;
1504 break;
1505 }
1506
1507 /* Consume this request in case we need more space than
1508 * is available and so need to prevent a race between
1509 * updating last_retired_head and direct reads of
1510 * I915_RING_HEAD. It also provides a nice sanity check.
1511 */
1512 request->tail = -1;
1513 }
1514
1515 if (seqno == 0)
1516 return -ENOSPC;
1517
1518 ret = i915_wait_seqno(ring, seqno);
1519 if (ret)
1520 return ret;
1521
1522 ring->head = tail;
1523 ring->space = ring_space(ring);
1524 if (WARN_ON(ring->space < n))
1525 return -ENOSPC;
1526
1527 return 0;
1528 }
1529
1530 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1531 {
1532 struct drm_device *dev = ring->dev;
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 unsigned long end;
1535 int ret;
1536
1537 ret = intel_ring_wait_request(ring, n);
1538 if (ret != -ENOSPC)
1539 return ret;
1540
1541 /* force the tail write in case we have been skipping them */
1542 __intel_ring_advance(ring);
1543
1544 trace_i915_ring_wait_begin(ring);
1545 /* With GEM the hangcheck timer should kick us out of the loop,
1546 * leaving it early runs the risk of corrupting GEM state (due
1547 * to running on almost untested codepaths). But on resume
1548 * timers don't work yet, so prevent a complete hang in that
1549 * case by choosing an insanely large timeout. */
1550 end = jiffies + 60 * HZ;
1551
1552 do {
1553 ring->head = I915_READ_HEAD(ring);
1554 ring->space = ring_space(ring);
1555 if (ring->space >= n) {
1556 trace_i915_ring_wait_end(ring);
1557 return 0;
1558 }
1559
1560 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1561 dev->primary->master) {
1562 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1563 if (master_priv->sarea_priv)
1564 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1565 }
1566
1567 msleep(1);
1568
1569 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1570 dev_priv->mm.interruptible);
1571 if (ret)
1572 return ret;
1573 } while (!time_after(jiffies, end));
1574 trace_i915_ring_wait_end(ring);
1575 return -EBUSY;
1576 }
1577
1578 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1579 {
1580 uint32_t __iomem *virt;
1581 int rem = ring->size - ring->tail;
1582
1583 if (ring->space < rem) {
1584 int ret = ring_wait_for_space(ring, rem);
1585 if (ret)
1586 return ret;
1587 }
1588
1589 virt = ring->virtual_start + ring->tail;
1590 rem /= 4;
1591 while (rem--)
1592 iowrite32(MI_NOOP, virt++);
1593
1594 ring->tail = 0;
1595 ring->space = ring_space(ring);
1596
1597 return 0;
1598 }
1599
1600 int intel_ring_idle(struct intel_ring_buffer *ring)
1601 {
1602 u32 seqno;
1603 int ret;
1604
1605 /* We need to add any requests required to flush the objects and ring */
1606 if (ring->outstanding_lazy_seqno) {
1607 ret = i915_add_request(ring, NULL);
1608 if (ret)
1609 return ret;
1610 }
1611
1612 /* Wait upon the last request to be completed */
1613 if (list_empty(&ring->request_list))
1614 return 0;
1615
1616 seqno = list_entry(ring->request_list.prev,
1617 struct drm_i915_gem_request,
1618 list)->seqno;
1619
1620 return i915_wait_seqno(ring, seqno);
1621 }
1622
1623 static int
1624 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1625 {
1626 if (ring->outstanding_lazy_seqno)
1627 return 0;
1628
1629 if (ring->preallocated_lazy_request == NULL) {
1630 struct drm_i915_gem_request *request;
1631
1632 request = kmalloc(sizeof(*request), GFP_KERNEL);
1633 if (request == NULL)
1634 return -ENOMEM;
1635
1636 ring->preallocated_lazy_request = request;
1637 }
1638
1639 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1640 }
1641
1642 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1643 int bytes)
1644 {
1645 int ret;
1646
1647 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1648 ret = intel_wrap_ring_buffer(ring);
1649 if (unlikely(ret))
1650 return ret;
1651 }
1652
1653 if (unlikely(ring->space < bytes)) {
1654 ret = ring_wait_for_space(ring, bytes);
1655 if (unlikely(ret))
1656 return ret;
1657 }
1658
1659 return 0;
1660 }
1661
1662 int intel_ring_begin(struct intel_ring_buffer *ring,
1663 int num_dwords)
1664 {
1665 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1666 int ret;
1667
1668 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1669 dev_priv->mm.interruptible);
1670 if (ret)
1671 return ret;
1672
1673 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1674 if (ret)
1675 return ret;
1676
1677 /* Preallocate the olr before touching the ring */
1678 ret = intel_ring_alloc_seqno(ring);
1679 if (ret)
1680 return ret;
1681
1682 ring->space -= num_dwords * sizeof(uint32_t);
1683 return 0;
1684 }
1685
1686 /* Align the ring tail to a cacheline boundary */
1687 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1688 {
1689 int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
1690 int ret;
1691
1692 if (num_dwords == 0)
1693 return 0;
1694
1695 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
1696 ret = intel_ring_begin(ring, num_dwords);
1697 if (ret)
1698 return ret;
1699
1700 while (num_dwords--)
1701 intel_ring_emit(ring, MI_NOOP);
1702
1703 intel_ring_advance(ring);
1704
1705 return 0;
1706 }
1707
1708 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1709 {
1710 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1711
1712 BUG_ON(ring->outstanding_lazy_seqno);
1713
1714 if (INTEL_INFO(ring->dev)->gen >= 6) {
1715 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1716 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1717 if (HAS_VEBOX(ring->dev))
1718 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1719 }
1720
1721 ring->set_seqno(ring, seqno);
1722 ring->hangcheck.seqno = seqno;
1723 }
1724
1725 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1726 u32 value)
1727 {
1728 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1729
1730 /* Every tail move must follow the sequence below */
1731
1732 /* Disable notification that the ring is IDLE. The GT
1733 * will then assume that it is busy and bring it out of rc6.
1734 */
1735 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1736 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1737
1738 /* Clear the context id. Here be magic! */
1739 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1740
1741 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1742 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1743 GEN6_BSD_SLEEP_INDICATOR) == 0,
1744 50))
1745 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1746
1747 /* Now that the ring is fully powered up, update the tail */
1748 I915_WRITE_TAIL(ring, value);
1749 POSTING_READ(RING_TAIL(ring->mmio_base));
1750
1751 /* Let the ring send IDLE messages to the GT again,
1752 * and so let it sleep to conserve power when idle.
1753 */
1754 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1755 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1756 }
1757
1758 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1759 u32 invalidate, u32 flush)
1760 {
1761 uint32_t cmd;
1762 int ret;
1763
1764 ret = intel_ring_begin(ring, 4);
1765 if (ret)
1766 return ret;
1767
1768 cmd = MI_FLUSH_DW;
1769 if (INTEL_INFO(ring->dev)->gen >= 8)
1770 cmd += 1;
1771 /*
1772 * Bspec vol 1c.5 - video engine command streamer:
1773 * "If ENABLED, all TLBs will be invalidated once the flush
1774 * operation is complete. This bit is only valid when the
1775 * Post-Sync Operation field is a value of 1h or 3h."
1776 */
1777 if (invalidate & I915_GEM_GPU_DOMAINS)
1778 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1779 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1780 intel_ring_emit(ring, cmd);
1781 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1782 if (INTEL_INFO(ring->dev)->gen >= 8) {
1783 intel_ring_emit(ring, 0); /* upper addr */
1784 intel_ring_emit(ring, 0); /* value */
1785 } else {
1786 intel_ring_emit(ring, 0);
1787 intel_ring_emit(ring, MI_NOOP);
1788 }
1789 intel_ring_advance(ring);
1790 return 0;
1791 }
1792
1793 static int
1794 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1795 u32 offset, u32 len,
1796 unsigned flags)
1797 {
1798 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1799 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1800 !(flags & I915_DISPATCH_SECURE);
1801 int ret;
1802
1803 ret = intel_ring_begin(ring, 4);
1804 if (ret)
1805 return ret;
1806
1807 /* FIXME(BDW): Address space and security selectors. */
1808 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1809 intel_ring_emit(ring, offset);
1810 intel_ring_emit(ring, 0);
1811 intel_ring_emit(ring, MI_NOOP);
1812 intel_ring_advance(ring);
1813
1814 return 0;
1815 }
1816
1817 static int
1818 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1819 u32 offset, u32 len,
1820 unsigned flags)
1821 {
1822 int ret;
1823
1824 ret = intel_ring_begin(ring, 2);
1825 if (ret)
1826 return ret;
1827
1828 intel_ring_emit(ring,
1829 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1830 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1831 /* bit0-7 is the length on GEN6+ */
1832 intel_ring_emit(ring, offset);
1833 intel_ring_advance(ring);
1834
1835 return 0;
1836 }
1837
1838 static int
1839 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1840 u32 offset, u32 len,
1841 unsigned flags)
1842 {
1843 int ret;
1844
1845 ret = intel_ring_begin(ring, 2);
1846 if (ret)
1847 return ret;
1848
1849 intel_ring_emit(ring,
1850 MI_BATCH_BUFFER_START |
1851 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1852 /* bit0-7 is the length on GEN6+ */
1853 intel_ring_emit(ring, offset);
1854 intel_ring_advance(ring);
1855
1856 return 0;
1857 }
1858
1859 /* Blitter support (SandyBridge+) */
1860
1861 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1862 u32 invalidate, u32 flush)
1863 {
1864 struct drm_device *dev = ring->dev;
1865 uint32_t cmd;
1866 int ret;
1867
1868 ret = intel_ring_begin(ring, 4);
1869 if (ret)
1870 return ret;
1871
1872 cmd = MI_FLUSH_DW;
1873 if (INTEL_INFO(ring->dev)->gen >= 8)
1874 cmd += 1;
1875 /*
1876 * Bspec vol 1c.3 - blitter engine command streamer:
1877 * "If ENABLED, all TLBs will be invalidated once the flush
1878 * operation is complete. This bit is only valid when the
1879 * Post-Sync Operation field is a value of 1h or 3h."
1880 */
1881 if (invalidate & I915_GEM_DOMAIN_RENDER)
1882 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1883 MI_FLUSH_DW_OP_STOREDW;
1884 intel_ring_emit(ring, cmd);
1885 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1886 if (INTEL_INFO(ring->dev)->gen >= 8) {
1887 intel_ring_emit(ring, 0); /* upper addr */
1888 intel_ring_emit(ring, 0); /* value */
1889 } else {
1890 intel_ring_emit(ring, 0);
1891 intel_ring_emit(ring, MI_NOOP);
1892 }
1893 intel_ring_advance(ring);
1894
1895 if (IS_GEN7(dev) && !invalidate && flush)
1896 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1897
1898 return 0;
1899 }
1900
1901 int intel_init_render_ring_buffer(struct drm_device *dev)
1902 {
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1905
1906 ring->name = "render ring";
1907 ring->id = RCS;
1908 ring->mmio_base = RENDER_RING_BASE;
1909
1910 if (INTEL_INFO(dev)->gen >= 6) {
1911 ring->add_request = gen6_add_request;
1912 ring->flush = gen7_render_ring_flush;
1913 if (INTEL_INFO(dev)->gen == 6)
1914 ring->flush = gen6_render_ring_flush;
1915 if (INTEL_INFO(dev)->gen >= 8) {
1916 ring->flush = gen8_render_ring_flush;
1917 ring->irq_get = gen8_ring_get_irq;
1918 ring->irq_put = gen8_ring_put_irq;
1919 } else {
1920 ring->irq_get = gen6_ring_get_irq;
1921 ring->irq_put = gen6_ring_put_irq;
1922 }
1923 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1924 ring->get_seqno = gen6_ring_get_seqno;
1925 ring->set_seqno = ring_set_seqno;
1926 ring->semaphore.sync_to = gen6_ring_sync;
1927 ring->semaphore.signal = gen6_signal;
1928 /*
1929 * The current semaphore is only applied on pre-gen8 platform.
1930 * And there is no VCS2 ring on the pre-gen8 platform. So the
1931 * semaphore between RCS and VCS2 is initialized as INVALID.
1932 * Gen8 will initialize the sema between VCS2 and RCS later.
1933 */
1934 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1935 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
1936 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
1937 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
1938 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
1939 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
1940 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
1941 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
1942 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
1943 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
1944 } else if (IS_GEN5(dev)) {
1945 ring->add_request = pc_render_add_request;
1946 ring->flush = gen4_render_ring_flush;
1947 ring->get_seqno = pc_render_get_seqno;
1948 ring->set_seqno = pc_render_set_seqno;
1949 ring->irq_get = gen5_ring_get_irq;
1950 ring->irq_put = gen5_ring_put_irq;
1951 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1952 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1953 } else {
1954 ring->add_request = i9xx_add_request;
1955 if (INTEL_INFO(dev)->gen < 4)
1956 ring->flush = gen2_render_ring_flush;
1957 else
1958 ring->flush = gen4_render_ring_flush;
1959 ring->get_seqno = ring_get_seqno;
1960 ring->set_seqno = ring_set_seqno;
1961 if (IS_GEN2(dev)) {
1962 ring->irq_get = i8xx_ring_get_irq;
1963 ring->irq_put = i8xx_ring_put_irq;
1964 } else {
1965 ring->irq_get = i9xx_ring_get_irq;
1966 ring->irq_put = i9xx_ring_put_irq;
1967 }
1968 ring->irq_enable_mask = I915_USER_INTERRUPT;
1969 }
1970 ring->write_tail = ring_write_tail;
1971 if (IS_HASWELL(dev))
1972 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1973 else if (IS_GEN8(dev))
1974 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1975 else if (INTEL_INFO(dev)->gen >= 6)
1976 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1977 else if (INTEL_INFO(dev)->gen >= 4)
1978 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1979 else if (IS_I830(dev) || IS_845G(dev))
1980 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1981 else
1982 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1983 ring->init = init_render_ring;
1984 ring->cleanup = render_ring_cleanup;
1985
1986 /* Workaround batchbuffer to combat CS tlb bug. */
1987 if (HAS_BROKEN_CS_TLB(dev)) {
1988 struct drm_i915_gem_object *obj;
1989 int ret;
1990
1991 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1992 if (obj == NULL) {
1993 DRM_ERROR("Failed to allocate batch bo\n");
1994 return -ENOMEM;
1995 }
1996
1997 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1998 if (ret != 0) {
1999 drm_gem_object_unreference(&obj->base);
2000 DRM_ERROR("Failed to ping batch bo\n");
2001 return ret;
2002 }
2003
2004 ring->scratch.obj = obj;
2005 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2006 }
2007
2008 return intel_init_ring_buffer(dev, ring);
2009 }
2010
2011 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2012 {
2013 struct drm_i915_private *dev_priv = dev->dev_private;
2014 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2015 int ret;
2016
2017 ring->name = "render ring";
2018 ring->id = RCS;
2019 ring->mmio_base = RENDER_RING_BASE;
2020
2021 if (INTEL_INFO(dev)->gen >= 6) {
2022 /* non-kms not supported on gen6+ */
2023 return -ENODEV;
2024 }
2025
2026 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2027 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2028 * the special gen5 functions. */
2029 ring->add_request = i9xx_add_request;
2030 if (INTEL_INFO(dev)->gen < 4)
2031 ring->flush = gen2_render_ring_flush;
2032 else
2033 ring->flush = gen4_render_ring_flush;
2034 ring->get_seqno = ring_get_seqno;
2035 ring->set_seqno = ring_set_seqno;
2036 if (IS_GEN2(dev)) {
2037 ring->irq_get = i8xx_ring_get_irq;
2038 ring->irq_put = i8xx_ring_put_irq;
2039 } else {
2040 ring->irq_get = i9xx_ring_get_irq;
2041 ring->irq_put = i9xx_ring_put_irq;
2042 }
2043 ring->irq_enable_mask = I915_USER_INTERRUPT;
2044 ring->write_tail = ring_write_tail;
2045 if (INTEL_INFO(dev)->gen >= 4)
2046 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2047 else if (IS_I830(dev) || IS_845G(dev))
2048 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2049 else
2050 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2051 ring->init = init_render_ring;
2052 ring->cleanup = render_ring_cleanup;
2053
2054 ring->dev = dev;
2055 INIT_LIST_HEAD(&ring->active_list);
2056 INIT_LIST_HEAD(&ring->request_list);
2057
2058 ring->size = size;
2059 ring->effective_size = ring->size;
2060 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2061 ring->effective_size -= 2 * CACHELINE_BYTES;
2062
2063 ring->virtual_start = ioremap_wc(start, size);
2064 if (ring->virtual_start == NULL) {
2065 DRM_ERROR("can not ioremap virtual address for"
2066 " ring buffer\n");
2067 return -ENOMEM;
2068 }
2069
2070 if (!I915_NEED_GFX_HWS(dev)) {
2071 ret = init_phys_status_page(ring);
2072 if (ret)
2073 return ret;
2074 }
2075
2076 return 0;
2077 }
2078
2079 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2080 {
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2083
2084 ring->name = "bsd ring";
2085 ring->id = VCS;
2086
2087 ring->write_tail = ring_write_tail;
2088 if (INTEL_INFO(dev)->gen >= 6) {
2089 ring->mmio_base = GEN6_BSD_RING_BASE;
2090 /* gen6 bsd needs a special wa for tail updates */
2091 if (IS_GEN6(dev))
2092 ring->write_tail = gen6_bsd_ring_write_tail;
2093 ring->flush = gen6_bsd_ring_flush;
2094 ring->add_request = gen6_add_request;
2095 ring->get_seqno = gen6_ring_get_seqno;
2096 ring->set_seqno = ring_set_seqno;
2097 if (INTEL_INFO(dev)->gen >= 8) {
2098 ring->irq_enable_mask =
2099 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2100 ring->irq_get = gen8_ring_get_irq;
2101 ring->irq_put = gen8_ring_put_irq;
2102 ring->dispatch_execbuffer =
2103 gen8_ring_dispatch_execbuffer;
2104 } else {
2105 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2106 ring->irq_get = gen6_ring_get_irq;
2107 ring->irq_put = gen6_ring_put_irq;
2108 ring->dispatch_execbuffer =
2109 gen6_ring_dispatch_execbuffer;
2110 }
2111 ring->semaphore.sync_to = gen6_ring_sync;
2112 ring->semaphore.signal = gen6_signal;
2113 /*
2114 * The current semaphore is only applied on pre-gen8 platform.
2115 * And there is no VCS2 ring on the pre-gen8 platform. So the
2116 * semaphore between VCS and VCS2 is initialized as INVALID.
2117 * Gen8 will initialize the sema between VCS2 and VCS later.
2118 */
2119 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2120 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2121 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2122 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2123 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2124 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2125 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2126 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2127 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2128 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2129 } else {
2130 ring->mmio_base = BSD_RING_BASE;
2131 ring->flush = bsd_ring_flush;
2132 ring->add_request = i9xx_add_request;
2133 ring->get_seqno = ring_get_seqno;
2134 ring->set_seqno = ring_set_seqno;
2135 if (IS_GEN5(dev)) {
2136 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2137 ring->irq_get = gen5_ring_get_irq;
2138 ring->irq_put = gen5_ring_put_irq;
2139 } else {
2140 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2141 ring->irq_get = i9xx_ring_get_irq;
2142 ring->irq_put = i9xx_ring_put_irq;
2143 }
2144 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2145 }
2146 ring->init = init_ring_common;
2147
2148 return intel_init_ring_buffer(dev, ring);
2149 }
2150
2151 /**
2152 * Initialize the second BSD ring for Broadwell GT3.
2153 * It is noted that this only exists on Broadwell GT3.
2154 */
2155 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2156 {
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 struct intel_ring_buffer *ring = &dev_priv->ring[VCS2];
2159
2160 if ((INTEL_INFO(dev)->gen != 8)) {
2161 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2162 return -EINVAL;
2163 }
2164
2165 ring->name = "bds2_ring";
2166 ring->id = VCS2;
2167
2168 ring->write_tail = ring_write_tail;
2169 ring->mmio_base = GEN8_BSD2_RING_BASE;
2170 ring->flush = gen6_bsd_ring_flush;
2171 ring->add_request = gen6_add_request;
2172 ring->get_seqno = gen6_ring_get_seqno;
2173 ring->set_seqno = ring_set_seqno;
2174 ring->irq_enable_mask =
2175 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2176 ring->irq_get = gen8_ring_get_irq;
2177 ring->irq_put = gen8_ring_put_irq;
2178 ring->dispatch_execbuffer =
2179 gen8_ring_dispatch_execbuffer;
2180 ring->semaphore.sync_to = gen6_ring_sync;
2181 /*
2182 * The current semaphore is only applied on the pre-gen8. And there
2183 * is no bsd2 ring on the pre-gen8. So now the semaphore_register
2184 * between VCS2 and other ring is initialized as invalid.
2185 * Gen8 will initialize the sema between VCS2 and other ring later.
2186 */
2187 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2188 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2189 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2190 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2191 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2192 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2193 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2194 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2195 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2196 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2197
2198 ring->init = init_ring_common;
2199
2200 return intel_init_ring_buffer(dev, ring);
2201 }
2202
2203 int intel_init_blt_ring_buffer(struct drm_device *dev)
2204 {
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2207
2208 ring->name = "blitter ring";
2209 ring->id = BCS;
2210
2211 ring->mmio_base = BLT_RING_BASE;
2212 ring->write_tail = ring_write_tail;
2213 ring->flush = gen6_ring_flush;
2214 ring->add_request = gen6_add_request;
2215 ring->get_seqno = gen6_ring_get_seqno;
2216 ring->set_seqno = ring_set_seqno;
2217 if (INTEL_INFO(dev)->gen >= 8) {
2218 ring->irq_enable_mask =
2219 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2220 ring->irq_get = gen8_ring_get_irq;
2221 ring->irq_put = gen8_ring_put_irq;
2222 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2223 } else {
2224 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2225 ring->irq_get = gen6_ring_get_irq;
2226 ring->irq_put = gen6_ring_put_irq;
2227 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2228 }
2229 ring->semaphore.sync_to = gen6_ring_sync;
2230 ring->semaphore.signal = gen6_signal;
2231 /*
2232 * The current semaphore is only applied on pre-gen8 platform. And
2233 * there is no VCS2 ring on the pre-gen8 platform. So the semaphore
2234 * between BCS and VCS2 is initialized as INVALID.
2235 * Gen8 will initialize the sema between BCS and VCS2 later.
2236 */
2237 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2238 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2239 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2240 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2241 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2242 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2243 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2244 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2245 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2246 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2247 ring->init = init_ring_common;
2248
2249 return intel_init_ring_buffer(dev, ring);
2250 }
2251
2252 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2253 {
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2256
2257 ring->name = "video enhancement ring";
2258 ring->id = VECS;
2259
2260 ring->mmio_base = VEBOX_RING_BASE;
2261 ring->write_tail = ring_write_tail;
2262 ring->flush = gen6_ring_flush;
2263 ring->add_request = gen6_add_request;
2264 ring->get_seqno = gen6_ring_get_seqno;
2265 ring->set_seqno = ring_set_seqno;
2266
2267 if (INTEL_INFO(dev)->gen >= 8) {
2268 ring->irq_enable_mask =
2269 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2270 ring->irq_get = gen8_ring_get_irq;
2271 ring->irq_put = gen8_ring_put_irq;
2272 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2273 } else {
2274 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2275 ring->irq_get = hsw_vebox_get_irq;
2276 ring->irq_put = hsw_vebox_put_irq;
2277 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2278 }
2279 ring->semaphore.sync_to = gen6_ring_sync;
2280 ring->semaphore.signal = gen6_signal;
2281 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2282 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2283 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2284 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2285 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2286 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2287 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2288 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2289 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2290 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2291 ring->init = init_ring_common;
2292
2293 return intel_init_ring_buffer(dev, ring);
2294 }
2295
2296 int
2297 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2298 {
2299 int ret;
2300
2301 if (!ring->gpu_caches_dirty)
2302 return 0;
2303
2304 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2305 if (ret)
2306 return ret;
2307
2308 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2309
2310 ring->gpu_caches_dirty = false;
2311 return 0;
2312 }
2313
2314 int
2315 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2316 {
2317 uint32_t flush_domains;
2318 int ret;
2319
2320 flush_domains = 0;
2321 if (ring->gpu_caches_dirty)
2322 flush_domains = I915_GEM_GPU_DOMAINS;
2323
2324 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2325 if (ret)
2326 return ret;
2327
2328 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2329
2330 ring->gpu_caches_dirty = false;
2331 return 0;
2332 }
2333
2334 void
2335 intel_stop_ring_buffer(struct intel_ring_buffer *ring)
2336 {
2337 int ret;
2338
2339 if (!intel_ring_initialized(ring))
2340 return;
2341
2342 ret = intel_ring_idle(ring);
2343 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2344 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2345 ring->name, ret);
2346
2347 stop_ring(ring);
2348 }
Linux kernel - Deliverables
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