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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_TLB_INVALIDATE;
230 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
232 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
233 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
235 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
236
237 ret = intel_ring_begin(ring, 6);
238 if (ret)
239 return ret;
240
241 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
242 intel_ring_emit(ring, flags);
243 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
244 intel_ring_emit(ring, 0); /* lower dword */
245 intel_ring_emit(ring, 0); /* uppwer dword */
246 intel_ring_emit(ring, MI_NOOP);
247 intel_ring_advance(ring);
248
249 return 0;
250 }
251
252 static void ring_write_tail(struct intel_ring_buffer *ring,
253 u32 value)
254 {
255 drm_i915_private_t *dev_priv = ring->dev->dev_private;
256 I915_WRITE_TAIL(ring, value);
257 }
258
259 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
260 {
261 drm_i915_private_t *dev_priv = ring->dev->dev_private;
262 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
263 RING_ACTHD(ring->mmio_base) : ACTHD;
264
265 return I915_READ(acthd_reg);
266 }
267
268 static int init_ring_common(struct intel_ring_buffer *ring)
269 {
270 struct drm_device *dev = ring->dev;
271 drm_i915_private_t *dev_priv = dev->dev_private;
272 struct drm_i915_gem_object *obj = ring->obj;
273 int ret = 0;
274 u32 head;
275
276 if (HAS_FORCE_WAKE(dev))
277 gen6_gt_force_wake_get(dev_priv);
278
279 /* Stop the ring if it's running. */
280 I915_WRITE_CTL(ring, 0);
281 I915_WRITE_HEAD(ring, 0);
282 ring->write_tail(ring, 0);
283
284 /* Initialize the ring. */
285 I915_WRITE_START(ring, obj->gtt_offset);
286 head = I915_READ_HEAD(ring) & HEAD_ADDR;
287
288 /* G45 ring initialization fails to reset head to zero */
289 if (head != 0) {
290 DRM_DEBUG_KMS("%s head not reset to zero "
291 "ctl %08x head %08x tail %08x start %08x\n",
292 ring->name,
293 I915_READ_CTL(ring),
294 I915_READ_HEAD(ring),
295 I915_READ_TAIL(ring),
296 I915_READ_START(ring));
297
298 I915_WRITE_HEAD(ring, 0);
299
300 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
301 DRM_ERROR("failed to set %s head to zero "
302 "ctl %08x head %08x tail %08x start %08x\n",
303 ring->name,
304 I915_READ_CTL(ring),
305 I915_READ_HEAD(ring),
306 I915_READ_TAIL(ring),
307 I915_READ_START(ring));
308 }
309 }
310
311 I915_WRITE_CTL(ring,
312 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
313 | RING_VALID);
314
315 /* If the head is still not zero, the ring is dead */
316 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
317 I915_READ_START(ring) == obj->gtt_offset &&
318 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
319 DRM_ERROR("%s initialization failed "
320 "ctl %08x head %08x tail %08x start %08x\n",
321 ring->name,
322 I915_READ_CTL(ring),
323 I915_READ_HEAD(ring),
324 I915_READ_TAIL(ring),
325 I915_READ_START(ring));
326 ret = -EIO;
327 goto out;
328 }
329
330 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
331 i915_kernel_lost_context(ring->dev);
332 else {
333 ring->head = I915_READ_HEAD(ring);
334 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
335 ring->space = ring_space(ring);
336 ring->last_retired_head = -1;
337 }
338
339 out:
340 if (HAS_FORCE_WAKE(dev))
341 gen6_gt_force_wake_put(dev_priv);
342
343 return ret;
344 }
345
346 static int
347 init_pipe_control(struct intel_ring_buffer *ring)
348 {
349 struct pipe_control *pc;
350 struct drm_i915_gem_object *obj;
351 int ret;
352
353 if (ring->private)
354 return 0;
355
356 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
357 if (!pc)
358 return -ENOMEM;
359
360 obj = i915_gem_alloc_object(ring->dev, 4096);
361 if (obj == NULL) {
362 DRM_ERROR("Failed to allocate seqno page\n");
363 ret = -ENOMEM;
364 goto err;
365 }
366
367 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
368
369 ret = i915_gem_object_pin(obj, 4096, true);
370 if (ret)
371 goto err_unref;
372
373 pc->gtt_offset = obj->gtt_offset;
374 pc->cpu_page = kmap(obj->pages[0]);
375 if (pc->cpu_page == NULL)
376 goto err_unpin;
377
378 pc->obj = obj;
379 ring->private = pc;
380 return 0;
381
382 err_unpin:
383 i915_gem_object_unpin(obj);
384 err_unref:
385 drm_gem_object_unreference(&obj->base);
386 err:
387 kfree(pc);
388 return ret;
389 }
390
391 static void
392 cleanup_pipe_control(struct intel_ring_buffer *ring)
393 {
394 struct pipe_control *pc = ring->private;
395 struct drm_i915_gem_object *obj;
396
397 if (!ring->private)
398 return;
399
400 obj = pc->obj;
401 kunmap(obj->pages[0]);
402 i915_gem_object_unpin(obj);
403 drm_gem_object_unreference(&obj->base);
404
405 kfree(pc);
406 ring->private = NULL;
407 }
408
409 static int init_render_ring(struct intel_ring_buffer *ring)
410 {
411 struct drm_device *dev = ring->dev;
412 struct drm_i915_private *dev_priv = dev->dev_private;
413 int ret = init_ring_common(ring);
414
415 if (INTEL_INFO(dev)->gen > 3) {
416 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
417 if (IS_GEN7(dev))
418 I915_WRITE(GFX_MODE_GEN7,
419 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
420 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
421 }
422
423 if (INTEL_INFO(dev)->gen >= 5) {
424 ret = init_pipe_control(ring);
425 if (ret)
426 return ret;
427 }
428
429 if (IS_GEN6(dev)) {
430 /* From the Sandybridge PRM, volume 1 part 3, page 24:
431 * "If this bit is set, STCunit will have LRA as replacement
432 * policy. [...] This bit must be reset. LRA replacement
433 * policy is not supported."
434 */
435 I915_WRITE(CACHE_MODE_0,
436 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
437
438 /* This is not explicitly set for GEN6, so read the register.
439 * see intel_ring_mi_set_context() for why we care.
440 * TODO: consider explicitly setting the bit for GEN5
441 */
442 ring->itlb_before_ctx_switch =
443 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
444 }
445
446 if (INTEL_INFO(dev)->gen >= 6)
447 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
448
449 if (IS_IVYBRIDGE(dev))
450 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
451
452 return ret;
453 }
454
455 static void render_ring_cleanup(struct intel_ring_buffer *ring)
456 {
457 if (!ring->private)
458 return;
459
460 cleanup_pipe_control(ring);
461 }
462
463 static void
464 update_mboxes(struct intel_ring_buffer *ring,
465 u32 seqno,
466 u32 mmio_offset)
467 {
468 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
469 MI_SEMAPHORE_GLOBAL_GTT |
470 MI_SEMAPHORE_REGISTER |
471 MI_SEMAPHORE_UPDATE);
472 intel_ring_emit(ring, seqno);
473 intel_ring_emit(ring, mmio_offset);
474 }
475
476 /**
477 * gen6_add_request - Update the semaphore mailbox registers
478 *
479 * @ring - ring that is adding a request
480 * @seqno - return seqno stuck into the ring
481 *
482 * Update the mailbox registers in the *other* rings with the current seqno.
483 * This acts like a signal in the canonical semaphore.
484 */
485 static int
486 gen6_add_request(struct intel_ring_buffer *ring,
487 u32 *seqno)
488 {
489 u32 mbox1_reg;
490 u32 mbox2_reg;
491 int ret;
492
493 ret = intel_ring_begin(ring, 10);
494 if (ret)
495 return ret;
496
497 mbox1_reg = ring->signal_mbox[0];
498 mbox2_reg = ring->signal_mbox[1];
499
500 *seqno = i915_gem_next_request_seqno(ring);
501
502 update_mboxes(ring, *seqno, mbox1_reg);
503 update_mboxes(ring, *seqno, mbox2_reg);
504 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
505 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
506 intel_ring_emit(ring, *seqno);
507 intel_ring_emit(ring, MI_USER_INTERRUPT);
508 intel_ring_advance(ring);
509
510 return 0;
511 }
512
513 /**
514 * intel_ring_sync - sync the waiter to the signaller on seqno
515 *
516 * @waiter - ring that is waiting
517 * @signaller - ring which has, or will signal
518 * @seqno - seqno which the waiter will block on
519 */
520 static int
521 gen6_ring_sync(struct intel_ring_buffer *waiter,
522 struct intel_ring_buffer *signaller,
523 u32 seqno)
524 {
525 int ret;
526 u32 dw1 = MI_SEMAPHORE_MBOX |
527 MI_SEMAPHORE_COMPARE |
528 MI_SEMAPHORE_REGISTER;
529
530 /* Throughout all of the GEM code, seqno passed implies our current
531 * seqno is >= the last seqno executed. However for hardware the
532 * comparison is strictly greater than.
533 */
534 seqno -= 1;
535
536 WARN_ON(signaller->semaphore_register[waiter->id] ==
537 MI_SEMAPHORE_SYNC_INVALID);
538
539 ret = intel_ring_begin(waiter, 4);
540 if (ret)
541 return ret;
542
543 intel_ring_emit(waiter,
544 dw1 | signaller->semaphore_register[waiter->id]);
545 intel_ring_emit(waiter, seqno);
546 intel_ring_emit(waiter, 0);
547 intel_ring_emit(waiter, MI_NOOP);
548 intel_ring_advance(waiter);
549
550 return 0;
551 }
552
553 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
554 do { \
555 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
556 PIPE_CONTROL_DEPTH_STALL); \
557 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
558 intel_ring_emit(ring__, 0); \
559 intel_ring_emit(ring__, 0); \
560 } while (0)
561
562 static int
563 pc_render_add_request(struct intel_ring_buffer *ring,
564 u32 *result)
565 {
566 u32 seqno = i915_gem_next_request_seqno(ring);
567 struct pipe_control *pc = ring->private;
568 u32 scratch_addr = pc->gtt_offset + 128;
569 int ret;
570
571 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
572 * incoherent with writes to memory, i.e. completely fubar,
573 * so we need to use PIPE_NOTIFY instead.
574 *
575 * However, we also need to workaround the qword write
576 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
577 * memory before requesting an interrupt.
578 */
579 ret = intel_ring_begin(ring, 32);
580 if (ret)
581 return ret;
582
583 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
584 PIPE_CONTROL_WRITE_FLUSH |
585 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
586 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
587 intel_ring_emit(ring, seqno);
588 intel_ring_emit(ring, 0);
589 PIPE_CONTROL_FLUSH(ring, scratch_addr);
590 scratch_addr += 128; /* write to separate cachelines */
591 PIPE_CONTROL_FLUSH(ring, scratch_addr);
592 scratch_addr += 128;
593 PIPE_CONTROL_FLUSH(ring, scratch_addr);
594 scratch_addr += 128;
595 PIPE_CONTROL_FLUSH(ring, scratch_addr);
596 scratch_addr += 128;
597 PIPE_CONTROL_FLUSH(ring, scratch_addr);
598 scratch_addr += 128;
599 PIPE_CONTROL_FLUSH(ring, scratch_addr);
600
601 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
602 PIPE_CONTROL_WRITE_FLUSH |
603 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
604 PIPE_CONTROL_NOTIFY);
605 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
606 intel_ring_emit(ring, seqno);
607 intel_ring_emit(ring, 0);
608 intel_ring_advance(ring);
609
610 *result = seqno;
611 return 0;
612 }
613
614 static u32
615 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
616 {
617 struct drm_device *dev = ring->dev;
618
619 /* Workaround to force correct ordering between irq and seqno writes on
620 * ivb (and maybe also on snb) by reading from a CS register (like
621 * ACTHD) before reading the status page. */
622 if (IS_GEN6(dev) || IS_GEN7(dev))
623 intel_ring_get_active_head(ring);
624 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
625 }
626
627 static u32
628 ring_get_seqno(struct intel_ring_buffer *ring)
629 {
630 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
631 }
632
633 static u32
634 pc_render_get_seqno(struct intel_ring_buffer *ring)
635 {
636 struct pipe_control *pc = ring->private;
637 return pc->cpu_page[0];
638 }
639
640 static bool
641 gen5_ring_get_irq(struct intel_ring_buffer *ring)
642 {
643 struct drm_device *dev = ring->dev;
644 drm_i915_private_t *dev_priv = dev->dev_private;
645 unsigned long flags;
646
647 if (!dev->irq_enabled)
648 return false;
649
650 spin_lock_irqsave(&dev_priv->irq_lock, flags);
651 if (ring->irq_refcount++ == 0) {
652 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
653 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
654 POSTING_READ(GTIMR);
655 }
656 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
657
658 return true;
659 }
660
661 static void
662 gen5_ring_put_irq(struct intel_ring_buffer *ring)
663 {
664 struct drm_device *dev = ring->dev;
665 drm_i915_private_t *dev_priv = dev->dev_private;
666 unsigned long flags;
667
668 spin_lock_irqsave(&dev_priv->irq_lock, flags);
669 if (--ring->irq_refcount == 0) {
670 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
671 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
672 POSTING_READ(GTIMR);
673 }
674 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
675 }
676
677 static bool
678 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
679 {
680 struct drm_device *dev = ring->dev;
681 drm_i915_private_t *dev_priv = dev->dev_private;
682 unsigned long flags;
683
684 if (!dev->irq_enabled)
685 return false;
686
687 spin_lock_irqsave(&dev_priv->irq_lock, flags);
688 if (ring->irq_refcount++ == 0) {
689 dev_priv->irq_mask &= ~ring->irq_enable_mask;
690 I915_WRITE(IMR, dev_priv->irq_mask);
691 POSTING_READ(IMR);
692 }
693 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
694
695 return true;
696 }
697
698 static void
699 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
700 {
701 struct drm_device *dev = ring->dev;
702 drm_i915_private_t *dev_priv = dev->dev_private;
703 unsigned long flags;
704
705 spin_lock_irqsave(&dev_priv->irq_lock, flags);
706 if (--ring->irq_refcount == 0) {
707 dev_priv->irq_mask |= ring->irq_enable_mask;
708 I915_WRITE(IMR, dev_priv->irq_mask);
709 POSTING_READ(IMR);
710 }
711 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
712 }
713
714 static bool
715 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
716 {
717 struct drm_device *dev = ring->dev;
718 drm_i915_private_t *dev_priv = dev->dev_private;
719 unsigned long flags;
720
721 if (!dev->irq_enabled)
722 return false;
723
724 spin_lock_irqsave(&dev_priv->irq_lock, flags);
725 if (ring->irq_refcount++ == 0) {
726 dev_priv->irq_mask &= ~ring->irq_enable_mask;
727 I915_WRITE16(IMR, dev_priv->irq_mask);
728 POSTING_READ16(IMR);
729 }
730 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
731
732 return true;
733 }
734
735 static void
736 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
737 {
738 struct drm_device *dev = ring->dev;
739 drm_i915_private_t *dev_priv = dev->dev_private;
740 unsigned long flags;
741
742 spin_lock_irqsave(&dev_priv->irq_lock, flags);
743 if (--ring->irq_refcount == 0) {
744 dev_priv->irq_mask |= ring->irq_enable_mask;
745 I915_WRITE16(IMR, dev_priv->irq_mask);
746 POSTING_READ16(IMR);
747 }
748 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
749 }
750
751 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
752 {
753 struct drm_device *dev = ring->dev;
754 drm_i915_private_t *dev_priv = ring->dev->dev_private;
755 u32 mmio = 0;
756
757 /* The ring status page addresses are no longer next to the rest of
758 * the ring registers as of gen7.
759 */
760 if (IS_GEN7(dev)) {
761 switch (ring->id) {
762 case RCS:
763 mmio = RENDER_HWS_PGA_GEN7;
764 break;
765 case BCS:
766 mmio = BLT_HWS_PGA_GEN7;
767 break;
768 case VCS:
769 mmio = BSD_HWS_PGA_GEN7;
770 break;
771 }
772 } else if (IS_GEN6(ring->dev)) {
773 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
774 } else {
775 mmio = RING_HWS_PGA(ring->mmio_base);
776 }
777
778 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
779 POSTING_READ(mmio);
780 }
781
782 static int
783 bsd_ring_flush(struct intel_ring_buffer *ring,
784 u32 invalidate_domains,
785 u32 flush_domains)
786 {
787 int ret;
788
789 ret = intel_ring_begin(ring, 2);
790 if (ret)
791 return ret;
792
793 intel_ring_emit(ring, MI_FLUSH);
794 intel_ring_emit(ring, MI_NOOP);
795 intel_ring_advance(ring);
796 return 0;
797 }
798
799 static int
800 i9xx_add_request(struct intel_ring_buffer *ring,
801 u32 *result)
802 {
803 u32 seqno;
804 int ret;
805
806 ret = intel_ring_begin(ring, 4);
807 if (ret)
808 return ret;
809
810 seqno = i915_gem_next_request_seqno(ring);
811
812 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
813 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
814 intel_ring_emit(ring, seqno);
815 intel_ring_emit(ring, MI_USER_INTERRUPT);
816 intel_ring_advance(ring);
817
818 *result = seqno;
819 return 0;
820 }
821
822 static bool
823 gen6_ring_get_irq(struct intel_ring_buffer *ring)
824 {
825 struct drm_device *dev = ring->dev;
826 drm_i915_private_t *dev_priv = dev->dev_private;
827 unsigned long flags;
828
829 if (!dev->irq_enabled)
830 return false;
831
832 /* It looks like we need to prevent the gt from suspending while waiting
833 * for an notifiy irq, otherwise irqs seem to get lost on at least the
834 * blt/bsd rings on ivb. */
835 gen6_gt_force_wake_get(dev_priv);
836
837 spin_lock_irqsave(&dev_priv->irq_lock, flags);
838 if (ring->irq_refcount++ == 0) {
839 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
840 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
841 GEN6_RENDER_L3_PARITY_ERROR));
842 else
843 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
844 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
845 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
846 POSTING_READ(GTIMR);
847 }
848 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
849
850 return true;
851 }
852
853 static void
854 gen6_ring_put_irq(struct intel_ring_buffer *ring)
855 {
856 struct drm_device *dev = ring->dev;
857 drm_i915_private_t *dev_priv = dev->dev_private;
858 unsigned long flags;
859
860 spin_lock_irqsave(&dev_priv->irq_lock, flags);
861 if (--ring->irq_refcount == 0) {
862 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
863 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
864 else
865 I915_WRITE_IMR(ring, ~0);
866 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
867 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
868 POSTING_READ(GTIMR);
869 }
870 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
871
872 gen6_gt_force_wake_put(dev_priv);
873 }
874
875 static int
876 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
877 {
878 int ret;
879
880 ret = intel_ring_begin(ring, 2);
881 if (ret)
882 return ret;
883
884 intel_ring_emit(ring,
885 MI_BATCH_BUFFER_START |
886 MI_BATCH_GTT |
887 MI_BATCH_NON_SECURE_I965);
888 intel_ring_emit(ring, offset);
889 intel_ring_advance(ring);
890
891 return 0;
892 }
893
894 static int
895 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
896 u32 offset, u32 len)
897 {
898 int ret;
899
900 ret = intel_ring_begin(ring, 4);
901 if (ret)
902 return ret;
903
904 intel_ring_emit(ring, MI_BATCH_BUFFER);
905 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
906 intel_ring_emit(ring, offset + len - 8);
907 intel_ring_emit(ring, 0);
908 intel_ring_advance(ring);
909
910 return 0;
911 }
912
913 static int
914 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
915 u32 offset, u32 len)
916 {
917 int ret;
918
919 ret = intel_ring_begin(ring, 2);
920 if (ret)
921 return ret;
922
923 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
924 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
925 intel_ring_advance(ring);
926
927 return 0;
928 }
929
930 static void cleanup_status_page(struct intel_ring_buffer *ring)
931 {
932 struct drm_i915_gem_object *obj;
933
934 obj = ring->status_page.obj;
935 if (obj == NULL)
936 return;
937
938 kunmap(obj->pages[0]);
939 i915_gem_object_unpin(obj);
940 drm_gem_object_unreference(&obj->base);
941 ring->status_page.obj = NULL;
942 }
943
944 static int init_status_page(struct intel_ring_buffer *ring)
945 {
946 struct drm_device *dev = ring->dev;
947 struct drm_i915_gem_object *obj;
948 int ret;
949
950 obj = i915_gem_alloc_object(dev, 4096);
951 if (obj == NULL) {
952 DRM_ERROR("Failed to allocate status page\n");
953 ret = -ENOMEM;
954 goto err;
955 }
956
957 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
958
959 ret = i915_gem_object_pin(obj, 4096, true);
960 if (ret != 0) {
961 goto err_unref;
962 }
963
964 ring->status_page.gfx_addr = obj->gtt_offset;
965 ring->status_page.page_addr = kmap(obj->pages[0]);
966 if (ring->status_page.page_addr == NULL) {
967 goto err_unpin;
968 }
969 ring->status_page.obj = obj;
970 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
971
972 intel_ring_setup_status_page(ring);
973 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
974 ring->name, ring->status_page.gfx_addr);
975
976 return 0;
977
978 err_unpin:
979 i915_gem_object_unpin(obj);
980 err_unref:
981 drm_gem_object_unreference(&obj->base);
982 err:
983 return ret;
984 }
985
986 static int intel_init_ring_buffer(struct drm_device *dev,
987 struct intel_ring_buffer *ring)
988 {
989 struct drm_i915_gem_object *obj;
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 int ret;
992
993 ring->dev = dev;
994 INIT_LIST_HEAD(&ring->active_list);
995 INIT_LIST_HEAD(&ring->request_list);
996 INIT_LIST_HEAD(&ring->gpu_write_list);
997 ring->size = 32 * PAGE_SIZE;
998
999 init_waitqueue_head(&ring->irq_queue);
1000
1001 if (I915_NEED_GFX_HWS(dev)) {
1002 ret = init_status_page(ring);
1003 if (ret)
1004 return ret;
1005 }
1006
1007 obj = i915_gem_alloc_object(dev, ring->size);
1008 if (obj == NULL) {
1009 DRM_ERROR("Failed to allocate ringbuffer\n");
1010 ret = -ENOMEM;
1011 goto err_hws;
1012 }
1013
1014 ring->obj = obj;
1015
1016 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1017 if (ret)
1018 goto err_unref;
1019
1020 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1021 if (ret)
1022 goto err_unpin;
1023
1024 ring->virtual_start =
1025 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1026 ring->size);
1027 if (ring->virtual_start == NULL) {
1028 DRM_ERROR("Failed to map ringbuffer.\n");
1029 ret = -EINVAL;
1030 goto err_unpin;
1031 }
1032
1033 ret = ring->init(ring);
1034 if (ret)
1035 goto err_unmap;
1036
1037 /* Workaround an erratum on the i830 which causes a hang if
1038 * the TAIL pointer points to within the last 2 cachelines
1039 * of the buffer.
1040 */
1041 ring->effective_size = ring->size;
1042 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1043 ring->effective_size -= 128;
1044
1045 return 0;
1046
1047 err_unmap:
1048 iounmap(ring->virtual_start);
1049 err_unpin:
1050 i915_gem_object_unpin(obj);
1051 err_unref:
1052 drm_gem_object_unreference(&obj->base);
1053 ring->obj = NULL;
1054 err_hws:
1055 cleanup_status_page(ring);
1056 return ret;
1057 }
1058
1059 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1060 {
1061 struct drm_i915_private *dev_priv;
1062 int ret;
1063
1064 if (ring->obj == NULL)
1065 return;
1066
1067 /* Disable the ring buffer. The ring must be idle at this point */
1068 dev_priv = ring->dev->dev_private;
1069 ret = intel_wait_ring_idle(ring);
1070 if (ret)
1071 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1072 ring->name, ret);
1073
1074 I915_WRITE_CTL(ring, 0);
1075
1076 iounmap(ring->virtual_start);
1077
1078 i915_gem_object_unpin(ring->obj);
1079 drm_gem_object_unreference(&ring->obj->base);
1080 ring->obj = NULL;
1081
1082 if (ring->cleanup)
1083 ring->cleanup(ring);
1084
1085 cleanup_status_page(ring);
1086 }
1087
1088 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1089 {
1090 uint32_t __iomem *virt;
1091 int rem = ring->size - ring->tail;
1092
1093 if (ring->space < rem) {
1094 int ret = intel_wait_ring_buffer(ring, rem);
1095 if (ret)
1096 return ret;
1097 }
1098
1099 virt = ring->virtual_start + ring->tail;
1100 rem /= 4;
1101 while (rem--)
1102 iowrite32(MI_NOOP, virt++);
1103
1104 ring->tail = 0;
1105 ring->space = ring_space(ring);
1106
1107 return 0;
1108 }
1109
1110 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1111 {
1112 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1113 bool was_interruptible;
1114 int ret;
1115
1116 /* XXX As we have not yet audited all the paths to check that
1117 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1118 * allow us to be interruptible by a signal.
1119 */
1120 was_interruptible = dev_priv->mm.interruptible;
1121 dev_priv->mm.interruptible = false;
1122
1123 ret = i915_wait_seqno(ring, seqno);
1124
1125 dev_priv->mm.interruptible = was_interruptible;
1126 if (!ret)
1127 i915_gem_retire_requests_ring(ring);
1128
1129 return ret;
1130 }
1131
1132 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1133 {
1134 struct drm_i915_gem_request *request;
1135 u32 seqno = 0;
1136 int ret;
1137
1138 i915_gem_retire_requests_ring(ring);
1139
1140 if (ring->last_retired_head != -1) {
1141 ring->head = ring->last_retired_head;
1142 ring->last_retired_head = -1;
1143 ring->space = ring_space(ring);
1144 if (ring->space >= n)
1145 return 0;
1146 }
1147
1148 list_for_each_entry(request, &ring->request_list, list) {
1149 int space;
1150
1151 if (request->tail == -1)
1152 continue;
1153
1154 space = request->tail - (ring->tail + 8);
1155 if (space < 0)
1156 space += ring->size;
1157 if (space >= n) {
1158 seqno = request->seqno;
1159 break;
1160 }
1161
1162 /* Consume this request in case we need more space than
1163 * is available and so need to prevent a race between
1164 * updating last_retired_head and direct reads of
1165 * I915_RING_HEAD. It also provides a nice sanity check.
1166 */
1167 request->tail = -1;
1168 }
1169
1170 if (seqno == 0)
1171 return -ENOSPC;
1172
1173 ret = intel_ring_wait_seqno(ring, seqno);
1174 if (ret)
1175 return ret;
1176
1177 if (WARN_ON(ring->last_retired_head == -1))
1178 return -ENOSPC;
1179
1180 ring->head = ring->last_retired_head;
1181 ring->last_retired_head = -1;
1182 ring->space = ring_space(ring);
1183 if (WARN_ON(ring->space < n))
1184 return -ENOSPC;
1185
1186 return 0;
1187 }
1188
1189 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1190 {
1191 struct drm_device *dev = ring->dev;
1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 unsigned long end;
1194 int ret;
1195
1196 ret = intel_ring_wait_request(ring, n);
1197 if (ret != -ENOSPC)
1198 return ret;
1199
1200 trace_i915_ring_wait_begin(ring);
1201 /* With GEM the hangcheck timer should kick us out of the loop,
1202 * leaving it early runs the risk of corrupting GEM state (due
1203 * to running on almost untested codepaths). But on resume
1204 * timers don't work yet, so prevent a complete hang in that
1205 * case by choosing an insanely large timeout. */
1206 end = jiffies + 60 * HZ;
1207
1208 do {
1209 ring->head = I915_READ_HEAD(ring);
1210 ring->space = ring_space(ring);
1211 if (ring->space >= n) {
1212 trace_i915_ring_wait_end(ring);
1213 return 0;
1214 }
1215
1216 if (dev->primary->master) {
1217 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1218 if (master_priv->sarea_priv)
1219 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1220 }
1221
1222 msleep(1);
1223 if (atomic_read(&dev_priv->mm.wedged))
1224 return -EAGAIN;
1225 } while (!time_after(jiffies, end));
1226 trace_i915_ring_wait_end(ring);
1227 return -EBUSY;
1228 }
1229
1230 int intel_ring_begin(struct intel_ring_buffer *ring,
1231 int num_dwords)
1232 {
1233 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1234 int n = 4*num_dwords;
1235 int ret;
1236
1237 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1238 return -EIO;
1239
1240 if (unlikely(ring->tail + n > ring->effective_size)) {
1241 ret = intel_wrap_ring_buffer(ring);
1242 if (unlikely(ret))
1243 return ret;
1244 }
1245
1246 if (unlikely(ring->space < n)) {
1247 ret = intel_wait_ring_buffer(ring, n);
1248 if (unlikely(ret))
1249 return ret;
1250 }
1251
1252 ring->space -= n;
1253 return 0;
1254 }
1255
1256 void intel_ring_advance(struct intel_ring_buffer *ring)
1257 {
1258 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1259
1260 ring->tail &= ring->size - 1;
1261 if (dev_priv->stop_rings & intel_ring_flag(ring))
1262 return;
1263 ring->write_tail(ring, ring->tail);
1264 }
1265
1266
1267 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1268 u32 value)
1269 {
1270 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1271
1272 /* Every tail move must follow the sequence below */
1273 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1274 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1275 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1276 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1277
1278 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1279 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1280 50))
1281 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1282
1283 I915_WRITE_TAIL(ring, value);
1284 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1285 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1286 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1287 }
1288
1289 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1290 u32 invalidate, u32 flush)
1291 {
1292 uint32_t cmd;
1293 int ret;
1294
1295 ret = intel_ring_begin(ring, 4);
1296 if (ret)
1297 return ret;
1298
1299 cmd = MI_FLUSH_DW;
1300 if (invalidate & I915_GEM_GPU_DOMAINS)
1301 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1302 intel_ring_emit(ring, cmd);
1303 intel_ring_emit(ring, 0);
1304 intel_ring_emit(ring, 0);
1305 intel_ring_emit(ring, MI_NOOP);
1306 intel_ring_advance(ring);
1307 return 0;
1308 }
1309
1310 static int
1311 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1312 u32 offset, u32 len)
1313 {
1314 int ret;
1315
1316 ret = intel_ring_begin(ring, 2);
1317 if (ret)
1318 return ret;
1319
1320 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1321 /* bit0-7 is the length on GEN6+ */
1322 intel_ring_emit(ring, offset);
1323 intel_ring_advance(ring);
1324
1325 return 0;
1326 }
1327
1328 /* Blitter support (SandyBridge+) */
1329
1330 static int blt_ring_flush(struct intel_ring_buffer *ring,
1331 u32 invalidate, u32 flush)
1332 {
1333 uint32_t cmd;
1334 int ret;
1335
1336 ret = intel_ring_begin(ring, 4);
1337 if (ret)
1338 return ret;
1339
1340 cmd = MI_FLUSH_DW;
1341 if (invalidate & I915_GEM_DOMAIN_RENDER)
1342 cmd |= MI_INVALIDATE_TLB;
1343 intel_ring_emit(ring, cmd);
1344 intel_ring_emit(ring, 0);
1345 intel_ring_emit(ring, 0);
1346 intel_ring_emit(ring, MI_NOOP);
1347 intel_ring_advance(ring);
1348 return 0;
1349 }
1350
1351 int intel_init_render_ring_buffer(struct drm_device *dev)
1352 {
1353 drm_i915_private_t *dev_priv = dev->dev_private;
1354 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1355
1356 ring->name = "render ring";
1357 ring->id = RCS;
1358 ring->mmio_base = RENDER_RING_BASE;
1359
1360 if (INTEL_INFO(dev)->gen >= 6) {
1361 ring->add_request = gen6_add_request;
1362 ring->flush = gen6_render_ring_flush;
1363 ring->irq_get = gen6_ring_get_irq;
1364 ring->irq_put = gen6_ring_put_irq;
1365 ring->irq_enable_mask = GT_USER_INTERRUPT;
1366 ring->get_seqno = gen6_ring_get_seqno;
1367 ring->sync_to = gen6_ring_sync;
1368 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1369 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1370 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1371 ring->signal_mbox[0] = GEN6_VRSYNC;
1372 ring->signal_mbox[1] = GEN6_BRSYNC;
1373 } else if (IS_GEN5(dev)) {
1374 ring->add_request = pc_render_add_request;
1375 ring->flush = gen4_render_ring_flush;
1376 ring->get_seqno = pc_render_get_seqno;
1377 ring->irq_get = gen5_ring_get_irq;
1378 ring->irq_put = gen5_ring_put_irq;
1379 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1380 } else {
1381 ring->add_request = i9xx_add_request;
1382 if (INTEL_INFO(dev)->gen < 4)
1383 ring->flush = gen2_render_ring_flush;
1384 else
1385 ring->flush = gen4_render_ring_flush;
1386 ring->get_seqno = ring_get_seqno;
1387 if (IS_GEN2(dev)) {
1388 ring->irq_get = i8xx_ring_get_irq;
1389 ring->irq_put = i8xx_ring_put_irq;
1390 } else {
1391 ring->irq_get = i9xx_ring_get_irq;
1392 ring->irq_put = i9xx_ring_put_irq;
1393 }
1394 ring->irq_enable_mask = I915_USER_INTERRUPT;
1395 }
1396 ring->write_tail = ring_write_tail;
1397 if (INTEL_INFO(dev)->gen >= 6)
1398 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1399 else if (INTEL_INFO(dev)->gen >= 4)
1400 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1401 else if (IS_I830(dev) || IS_845G(dev))
1402 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1403 else
1404 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1405 ring->init = init_render_ring;
1406 ring->cleanup = render_ring_cleanup;
1407
1408
1409 if (!I915_NEED_GFX_HWS(dev)) {
1410 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1411 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1412 }
1413
1414 return intel_init_ring_buffer(dev, ring);
1415 }
1416
1417 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1418 {
1419 drm_i915_private_t *dev_priv = dev->dev_private;
1420 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1421
1422 ring->name = "render ring";
1423 ring->id = RCS;
1424 ring->mmio_base = RENDER_RING_BASE;
1425
1426 if (INTEL_INFO(dev)->gen >= 6) {
1427 /* non-kms not supported on gen6+ */
1428 return -ENODEV;
1429 }
1430
1431 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1432 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1433 * the special gen5 functions. */
1434 ring->add_request = i9xx_add_request;
1435 if (INTEL_INFO(dev)->gen < 4)
1436 ring->flush = gen2_render_ring_flush;
1437 else
1438 ring->flush = gen4_render_ring_flush;
1439 ring->get_seqno = ring_get_seqno;
1440 if (IS_GEN2(dev)) {
1441 ring->irq_get = i8xx_ring_get_irq;
1442 ring->irq_put = i8xx_ring_put_irq;
1443 } else {
1444 ring->irq_get = i9xx_ring_get_irq;
1445 ring->irq_put = i9xx_ring_put_irq;
1446 }
1447 ring->irq_enable_mask = I915_USER_INTERRUPT;
1448 ring->write_tail = ring_write_tail;
1449 if (INTEL_INFO(dev)->gen >= 4)
1450 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1451 else if (IS_I830(dev) || IS_845G(dev))
1452 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1453 else
1454 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1455 ring->init = init_render_ring;
1456 ring->cleanup = render_ring_cleanup;
1457
1458 if (!I915_NEED_GFX_HWS(dev))
1459 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1460
1461 ring->dev = dev;
1462 INIT_LIST_HEAD(&ring->active_list);
1463 INIT_LIST_HEAD(&ring->request_list);
1464 INIT_LIST_HEAD(&ring->gpu_write_list);
1465
1466 ring->size = size;
1467 ring->effective_size = ring->size;
1468 if (IS_I830(ring->dev))
1469 ring->effective_size -= 128;
1470
1471 ring->virtual_start = ioremap_wc(start, size);
1472 if (ring->virtual_start == NULL) {
1473 DRM_ERROR("can not ioremap virtual address for"
1474 " ring buffer\n");
1475 return -ENOMEM;
1476 }
1477
1478 return 0;
1479 }
1480
1481 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1482 {
1483 drm_i915_private_t *dev_priv = dev->dev_private;
1484 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1485
1486 ring->name = "bsd ring";
1487 ring->id = VCS;
1488
1489 ring->write_tail = ring_write_tail;
1490 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1491 ring->mmio_base = GEN6_BSD_RING_BASE;
1492 /* gen6 bsd needs a special wa for tail updates */
1493 if (IS_GEN6(dev))
1494 ring->write_tail = gen6_bsd_ring_write_tail;
1495 ring->flush = gen6_ring_flush;
1496 ring->add_request = gen6_add_request;
1497 ring->get_seqno = gen6_ring_get_seqno;
1498 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1499 ring->irq_get = gen6_ring_get_irq;
1500 ring->irq_put = gen6_ring_put_irq;
1501 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1502 ring->sync_to = gen6_ring_sync;
1503 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1504 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1505 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1506 ring->signal_mbox[0] = GEN6_RVSYNC;
1507 ring->signal_mbox[1] = GEN6_BVSYNC;
1508 } else {
1509 ring->mmio_base = BSD_RING_BASE;
1510 ring->flush = bsd_ring_flush;
1511 ring->add_request = i9xx_add_request;
1512 ring->get_seqno = ring_get_seqno;
1513 if (IS_GEN5(dev)) {
1514 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1515 ring->irq_get = gen5_ring_get_irq;
1516 ring->irq_put = gen5_ring_put_irq;
1517 } else {
1518 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1519 ring->irq_get = i9xx_ring_get_irq;
1520 ring->irq_put = i9xx_ring_put_irq;
1521 }
1522 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1523 }
1524 ring->init = init_ring_common;
1525
1526
1527 return intel_init_ring_buffer(dev, ring);
1528 }
1529
1530 int intel_init_blt_ring_buffer(struct drm_device *dev)
1531 {
1532 drm_i915_private_t *dev_priv = dev->dev_private;
1533 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1534
1535 ring->name = "blitter ring";
1536 ring->id = BCS;
1537
1538 ring->mmio_base = BLT_RING_BASE;
1539 ring->write_tail = ring_write_tail;
1540 ring->flush = blt_ring_flush;
1541 ring->add_request = gen6_add_request;
1542 ring->get_seqno = gen6_ring_get_seqno;
1543 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1544 ring->irq_get = gen6_ring_get_irq;
1545 ring->irq_put = gen6_ring_put_irq;
1546 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1547 ring->sync_to = gen6_ring_sync;
1548 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1549 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1550 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1551 ring->signal_mbox[0] = GEN6_RBSYNC;
1552 ring->signal_mbox[1] = GEN6_VBSYNC;
1553 ring->init = init_ring_common;
1554
1555 return intel_init_ring_buffer(dev, ring);
1556 }
Linux kernel - Deliverables
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