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drm/i915: dynamically set up the render ring functions and params
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 struct drm_device *dev = ring->dev;
61 u32 cmd;
62 int ret;
63
64 /*
65 * read/write caches:
66 *
67 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
69 * also flushed at 2d versus 3d pipeline switches.
70 *
71 * read-only caches:
72 *
73 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74 * MI_READ_FLUSH is set, and is always flushed on 965.
75 *
76 * I915_GEM_DOMAIN_COMMAND may not exist?
77 *
78 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79 * invalidated when MI_EXE_FLUSH is set.
80 *
81 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82 * invalidated with every MI_FLUSH.
83 *
84 * TLBs:
85 *
86 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89 * are flushed at any MI_FLUSH.
90 */
91
92 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
93 if ((invalidate_domains|flush_domains) &
94 I915_GEM_DOMAIN_RENDER)
95 cmd &= ~MI_NO_WRITE_FLUSH;
96 if (INTEL_INFO(dev)->gen < 4) {
97 /*
98 * On the 965, the sampler cache always gets flushed
99 * and this bit is reserved.
100 */
101 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
102 cmd |= MI_READ_FLUSH;
103 }
104 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
105 cmd |= MI_EXE_FLUSH;
106
107 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
108 (IS_G4X(dev) || IS_GEN5(dev)))
109 cmd |= MI_INVALIDATE_ISP;
110
111 ret = intel_ring_begin(ring, 2);
112 if (ret)
113 return ret;
114
115 intel_ring_emit(ring, cmd);
116 intel_ring_emit(ring, MI_NOOP);
117 intel_ring_advance(ring);
118
119 return 0;
120 }
121
122 /**
123 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124 * implementing two workarounds on gen6. From section 1.4.7.1
125 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
126 *
127 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128 * produced by non-pipelined state commands), software needs to first
129 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
130 * 0.
131 *
132 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
134 *
135 * And the workaround for these two requires this workaround first:
136 *
137 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138 * BEFORE the pipe-control with a post-sync op and no write-cache
139 * flushes.
140 *
141 * And this last workaround is tricky because of the requirements on
142 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
143 * volume 2 part 1:
144 *
145 * "1 of the following must also be set:
146 * - Render Target Cache Flush Enable ([12] of DW1)
147 * - Depth Cache Flush Enable ([0] of DW1)
148 * - Stall at Pixel Scoreboard ([1] of DW1)
149 * - Depth Stall ([13] of DW1)
150 * - Post-Sync Operation ([13] of DW1)
151 * - Notify Enable ([8] of DW1)"
152 *
153 * The cache flushes require the workaround flush that triggered this
154 * one, so we can't use it. Depth stall would trigger the same.
155 * Post-sync nonzero is what triggered this second workaround, so we
156 * can't use that one either. Notify enable is IRQs, which aren't
157 * really our business. That leaves only stall at scoreboard.
158 */
159 static int
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
161 {
162 struct pipe_control *pc = ring->private;
163 u32 scratch_addr = pc->gtt_offset + 128;
164 int ret;
165
166
167 ret = intel_ring_begin(ring, 6);
168 if (ret)
169 return ret;
170
171 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
172 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
173 PIPE_CONTROL_STALL_AT_SCOREBOARD);
174 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
175 intel_ring_emit(ring, 0); /* low dword */
176 intel_ring_emit(ring, 0); /* high dword */
177 intel_ring_emit(ring, MI_NOOP);
178 intel_ring_advance(ring);
179
180 ret = intel_ring_begin(ring, 6);
181 if (ret)
182 return ret;
183
184 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
185 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
186 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
187 intel_ring_emit(ring, 0);
188 intel_ring_emit(ring, 0);
189 intel_ring_emit(ring, MI_NOOP);
190 intel_ring_advance(ring);
191
192 return 0;
193 }
194
195 static int
196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
197 u32 invalidate_domains, u32 flush_domains)
198 {
199 u32 flags = 0;
200 struct pipe_control *pc = ring->private;
201 u32 scratch_addr = pc->gtt_offset + 128;
202 int ret;
203
204 /* Force SNB workarounds for PIPE_CONTROL flushes */
205 intel_emit_post_sync_nonzero_flush(ring);
206
207 /* Just flush everything. Experiments have shown that reducing the
208 * number of bits based on the write domains has little performance
209 * impact.
210 */
211 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
212 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
213 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
214 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
215 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
216 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
217 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
218
219 ret = intel_ring_begin(ring, 6);
220 if (ret)
221 return ret;
222
223 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
224 intel_ring_emit(ring, flags);
225 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
226 intel_ring_emit(ring, 0); /* lower dword */
227 intel_ring_emit(ring, 0); /* uppwer dword */
228 intel_ring_emit(ring, MI_NOOP);
229 intel_ring_advance(ring);
230
231 return 0;
232 }
233
234 static void ring_write_tail(struct intel_ring_buffer *ring,
235 u32 value)
236 {
237 drm_i915_private_t *dev_priv = ring->dev->dev_private;
238 I915_WRITE_TAIL(ring, value);
239 }
240
241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
242 {
243 drm_i915_private_t *dev_priv = ring->dev->dev_private;
244 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
245 RING_ACTHD(ring->mmio_base) : ACTHD;
246
247 return I915_READ(acthd_reg);
248 }
249
250 static int init_ring_common(struct intel_ring_buffer *ring)
251 {
252 drm_i915_private_t *dev_priv = ring->dev->dev_private;
253 struct drm_i915_gem_object *obj = ring->obj;
254 u32 head;
255
256 /* Stop the ring if it's running. */
257 I915_WRITE_CTL(ring, 0);
258 I915_WRITE_HEAD(ring, 0);
259 ring->write_tail(ring, 0);
260
261 /* Initialize the ring. */
262 I915_WRITE_START(ring, obj->gtt_offset);
263 head = I915_READ_HEAD(ring) & HEAD_ADDR;
264
265 /* G45 ring initialization fails to reset head to zero */
266 if (head != 0) {
267 DRM_DEBUG_KMS("%s head not reset to zero "
268 "ctl %08x head %08x tail %08x start %08x\n",
269 ring->name,
270 I915_READ_CTL(ring),
271 I915_READ_HEAD(ring),
272 I915_READ_TAIL(ring),
273 I915_READ_START(ring));
274
275 I915_WRITE_HEAD(ring, 0);
276
277 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
278 DRM_ERROR("failed to set %s head to zero "
279 "ctl %08x head %08x tail %08x start %08x\n",
280 ring->name,
281 I915_READ_CTL(ring),
282 I915_READ_HEAD(ring),
283 I915_READ_TAIL(ring),
284 I915_READ_START(ring));
285 }
286 }
287
288 I915_WRITE_CTL(ring,
289 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
290 | RING_VALID);
291
292 /* If the head is still not zero, the ring is dead */
293 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
294 I915_READ_START(ring) == obj->gtt_offset &&
295 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
296 DRM_ERROR("%s initialization failed "
297 "ctl %08x head %08x tail %08x start %08x\n",
298 ring->name,
299 I915_READ_CTL(ring),
300 I915_READ_HEAD(ring),
301 I915_READ_TAIL(ring),
302 I915_READ_START(ring));
303 return -EIO;
304 }
305
306 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
307 i915_kernel_lost_context(ring->dev);
308 else {
309 ring->head = I915_READ_HEAD(ring);
310 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
311 ring->space = ring_space(ring);
312 }
313
314 return 0;
315 }
316
317 static int
318 init_pipe_control(struct intel_ring_buffer *ring)
319 {
320 struct pipe_control *pc;
321 struct drm_i915_gem_object *obj;
322 int ret;
323
324 if (ring->private)
325 return 0;
326
327 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
328 if (!pc)
329 return -ENOMEM;
330
331 obj = i915_gem_alloc_object(ring->dev, 4096);
332 if (obj == NULL) {
333 DRM_ERROR("Failed to allocate seqno page\n");
334 ret = -ENOMEM;
335 goto err;
336 }
337
338 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
339
340 ret = i915_gem_object_pin(obj, 4096, true);
341 if (ret)
342 goto err_unref;
343
344 pc->gtt_offset = obj->gtt_offset;
345 pc->cpu_page = kmap(obj->pages[0]);
346 if (pc->cpu_page == NULL)
347 goto err_unpin;
348
349 pc->obj = obj;
350 ring->private = pc;
351 return 0;
352
353 err_unpin:
354 i915_gem_object_unpin(obj);
355 err_unref:
356 drm_gem_object_unreference(&obj->base);
357 err:
358 kfree(pc);
359 return ret;
360 }
361
362 static void
363 cleanup_pipe_control(struct intel_ring_buffer *ring)
364 {
365 struct pipe_control *pc = ring->private;
366 struct drm_i915_gem_object *obj;
367
368 if (!ring->private)
369 return;
370
371 obj = pc->obj;
372 kunmap(obj->pages[0]);
373 i915_gem_object_unpin(obj);
374 drm_gem_object_unreference(&obj->base);
375
376 kfree(pc);
377 ring->private = NULL;
378 }
379
380 static int init_render_ring(struct intel_ring_buffer *ring)
381 {
382 struct drm_device *dev = ring->dev;
383 struct drm_i915_private *dev_priv = dev->dev_private;
384 int ret = init_ring_common(ring);
385
386 if (INTEL_INFO(dev)->gen > 3) {
387 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
388 I915_WRITE(MI_MODE, mode);
389 if (IS_GEN7(dev))
390 I915_WRITE(GFX_MODE_GEN7,
391 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
392 GFX_MODE_ENABLE(GFX_REPLAY_MODE));
393 }
394
395 if (INTEL_INFO(dev)->gen >= 5) {
396 ret = init_pipe_control(ring);
397 if (ret)
398 return ret;
399 }
400
401 if (INTEL_INFO(dev)->gen >= 6) {
402 I915_WRITE(INSTPM,
403 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
404 }
405
406 return ret;
407 }
408
409 static void render_ring_cleanup(struct intel_ring_buffer *ring)
410 {
411 if (!ring->private)
412 return;
413
414 cleanup_pipe_control(ring);
415 }
416
417 static void
418 update_mboxes(struct intel_ring_buffer *ring,
419 u32 seqno,
420 u32 mmio_offset)
421 {
422 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
423 MI_SEMAPHORE_GLOBAL_GTT |
424 MI_SEMAPHORE_REGISTER |
425 MI_SEMAPHORE_UPDATE);
426 intel_ring_emit(ring, seqno);
427 intel_ring_emit(ring, mmio_offset);
428 }
429
430 /**
431 * gen6_add_request - Update the semaphore mailbox registers
432 *
433 * @ring - ring that is adding a request
434 * @seqno - return seqno stuck into the ring
435 *
436 * Update the mailbox registers in the *other* rings with the current seqno.
437 * This acts like a signal in the canonical semaphore.
438 */
439 static int
440 gen6_add_request(struct intel_ring_buffer *ring,
441 u32 *seqno)
442 {
443 u32 mbox1_reg;
444 u32 mbox2_reg;
445 int ret;
446
447 ret = intel_ring_begin(ring, 10);
448 if (ret)
449 return ret;
450
451 mbox1_reg = ring->signal_mbox[0];
452 mbox2_reg = ring->signal_mbox[1];
453
454 *seqno = i915_gem_next_request_seqno(ring);
455
456 update_mboxes(ring, *seqno, mbox1_reg);
457 update_mboxes(ring, *seqno, mbox2_reg);
458 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
459 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
460 intel_ring_emit(ring, *seqno);
461 intel_ring_emit(ring, MI_USER_INTERRUPT);
462 intel_ring_advance(ring);
463
464 return 0;
465 }
466
467 /**
468 * intel_ring_sync - sync the waiter to the signaller on seqno
469 *
470 * @waiter - ring that is waiting
471 * @signaller - ring which has, or will signal
472 * @seqno - seqno which the waiter will block on
473 */
474 static int
475 intel_ring_sync(struct intel_ring_buffer *waiter,
476 struct intel_ring_buffer *signaller,
477 int ring,
478 u32 seqno)
479 {
480 int ret;
481 u32 dw1 = MI_SEMAPHORE_MBOX |
482 MI_SEMAPHORE_COMPARE |
483 MI_SEMAPHORE_REGISTER;
484
485 /* Throughout all of the GEM code, seqno passed implies our current
486 * seqno is >= the last seqno executed. However for hardware the
487 * comparison is strictly greater than.
488 */
489 seqno -= 1;
490
491 ret = intel_ring_begin(waiter, 4);
492 if (ret)
493 return ret;
494
495 intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
496 intel_ring_emit(waiter, seqno);
497 intel_ring_emit(waiter, 0);
498 intel_ring_emit(waiter, MI_NOOP);
499 intel_ring_advance(waiter);
500
501 return 0;
502 }
503
504 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
505 int
506 render_ring_sync_to(struct intel_ring_buffer *waiter,
507 struct intel_ring_buffer *signaller,
508 u32 seqno)
509 {
510 WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
511 return intel_ring_sync(waiter,
512 signaller,
513 RCS,
514 seqno);
515 }
516
517 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
518 int
519 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
520 struct intel_ring_buffer *signaller,
521 u32 seqno)
522 {
523 WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
524 return intel_ring_sync(waiter,
525 signaller,
526 VCS,
527 seqno);
528 }
529
530 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
531 int
532 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
533 struct intel_ring_buffer *signaller,
534 u32 seqno)
535 {
536 WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
537 return intel_ring_sync(waiter,
538 signaller,
539 BCS,
540 seqno);
541 }
542
543
544
545 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
546 do { \
547 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
548 PIPE_CONTROL_DEPTH_STALL); \
549 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
550 intel_ring_emit(ring__, 0); \
551 intel_ring_emit(ring__, 0); \
552 } while (0)
553
554 static int
555 pc_render_add_request(struct intel_ring_buffer *ring,
556 u32 *result)
557 {
558 u32 seqno = i915_gem_next_request_seqno(ring);
559 struct pipe_control *pc = ring->private;
560 u32 scratch_addr = pc->gtt_offset + 128;
561 int ret;
562
563 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
564 * incoherent with writes to memory, i.e. completely fubar,
565 * so we need to use PIPE_NOTIFY instead.
566 *
567 * However, we also need to workaround the qword write
568 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
569 * memory before requesting an interrupt.
570 */
571 ret = intel_ring_begin(ring, 32);
572 if (ret)
573 return ret;
574
575 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
576 PIPE_CONTROL_WRITE_FLUSH |
577 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
578 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
579 intel_ring_emit(ring, seqno);
580 intel_ring_emit(ring, 0);
581 PIPE_CONTROL_FLUSH(ring, scratch_addr);
582 scratch_addr += 128; /* write to separate cachelines */
583 PIPE_CONTROL_FLUSH(ring, scratch_addr);
584 scratch_addr += 128;
585 PIPE_CONTROL_FLUSH(ring, scratch_addr);
586 scratch_addr += 128;
587 PIPE_CONTROL_FLUSH(ring, scratch_addr);
588 scratch_addr += 128;
589 PIPE_CONTROL_FLUSH(ring, scratch_addr);
590 scratch_addr += 128;
591 PIPE_CONTROL_FLUSH(ring, scratch_addr);
592
593 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
594 PIPE_CONTROL_WRITE_FLUSH |
595 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
596 PIPE_CONTROL_NOTIFY);
597 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
598 intel_ring_emit(ring, seqno);
599 intel_ring_emit(ring, 0);
600 intel_ring_advance(ring);
601
602 *result = seqno;
603 return 0;
604 }
605
606 static int
607 render_ring_add_request(struct intel_ring_buffer *ring,
608 u32 *result)
609 {
610 u32 seqno = i915_gem_next_request_seqno(ring);
611 int ret;
612
613 ret = intel_ring_begin(ring, 4);
614 if (ret)
615 return ret;
616
617 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
618 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
619 intel_ring_emit(ring, seqno);
620 intel_ring_emit(ring, MI_USER_INTERRUPT);
621 intel_ring_advance(ring);
622
623 *result = seqno;
624 return 0;
625 }
626
627 static u32
628 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
629 {
630 struct drm_device *dev = ring->dev;
631
632 /* Workaround to force correct ordering between irq and seqno writes on
633 * ivb (and maybe also on snb) by reading from a CS register (like
634 * ACTHD) before reading the status page. */
635 if (IS_GEN6(dev) || IS_GEN7(dev))
636 intel_ring_get_active_head(ring);
637 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
638 }
639
640 static u32
641 ring_get_seqno(struct intel_ring_buffer *ring)
642 {
643 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
644 }
645
646 static u32
647 pc_render_get_seqno(struct intel_ring_buffer *ring)
648 {
649 struct pipe_control *pc = ring->private;
650 return pc->cpu_page[0];
651 }
652
653 static void
654 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
655 {
656 dev_priv->gt_irq_mask &= ~mask;
657 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
658 POSTING_READ(GTIMR);
659 }
660
661 static void
662 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
663 {
664 dev_priv->gt_irq_mask |= mask;
665 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
666 POSTING_READ(GTIMR);
667 }
668
669 static void
670 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
671 {
672 dev_priv->irq_mask &= ~mask;
673 I915_WRITE(IMR, dev_priv->irq_mask);
674 POSTING_READ(IMR);
675 }
676
677 static void
678 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
679 {
680 dev_priv->irq_mask |= mask;
681 I915_WRITE(IMR, dev_priv->irq_mask);
682 POSTING_READ(IMR);
683 }
684
685 static bool
686 render_ring_get_irq(struct intel_ring_buffer *ring)
687 {
688 struct drm_device *dev = ring->dev;
689 drm_i915_private_t *dev_priv = dev->dev_private;
690
691 if (!dev->irq_enabled)
692 return false;
693
694 spin_lock(&ring->irq_lock);
695 if (ring->irq_refcount++ == 0) {
696 if (INTEL_INFO(dev)->gen >= 5)
697 ironlake_enable_irq(dev_priv,
698 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
699 else
700 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
701 }
702 spin_unlock(&ring->irq_lock);
703
704 return true;
705 }
706
707 static void
708 render_ring_put_irq(struct intel_ring_buffer *ring)
709 {
710 struct drm_device *dev = ring->dev;
711 drm_i915_private_t *dev_priv = dev->dev_private;
712
713 spin_lock(&ring->irq_lock);
714 if (--ring->irq_refcount == 0) {
715 if (INTEL_INFO(dev)->gen >= 5)
716 ironlake_disable_irq(dev_priv,
717 GT_USER_INTERRUPT |
718 GT_PIPE_NOTIFY);
719 else
720 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
721 }
722 spin_unlock(&ring->irq_lock);
723 }
724
725 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
726 {
727 struct drm_device *dev = ring->dev;
728 drm_i915_private_t *dev_priv = ring->dev->dev_private;
729 u32 mmio = 0;
730
731 /* The ring status page addresses are no longer next to the rest of
732 * the ring registers as of gen7.
733 */
734 if (IS_GEN7(dev)) {
735 switch (ring->id) {
736 case RCS:
737 mmio = RENDER_HWS_PGA_GEN7;
738 break;
739 case BCS:
740 mmio = BLT_HWS_PGA_GEN7;
741 break;
742 case VCS:
743 mmio = BSD_HWS_PGA_GEN7;
744 break;
745 }
746 } else if (IS_GEN6(ring->dev)) {
747 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
748 } else {
749 mmio = RING_HWS_PGA(ring->mmio_base);
750 }
751
752 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
753 POSTING_READ(mmio);
754 }
755
756 static int
757 bsd_ring_flush(struct intel_ring_buffer *ring,
758 u32 invalidate_domains,
759 u32 flush_domains)
760 {
761 int ret;
762
763 ret = intel_ring_begin(ring, 2);
764 if (ret)
765 return ret;
766
767 intel_ring_emit(ring, MI_FLUSH);
768 intel_ring_emit(ring, MI_NOOP);
769 intel_ring_advance(ring);
770 return 0;
771 }
772
773 static int
774 ring_add_request(struct intel_ring_buffer *ring,
775 u32 *result)
776 {
777 u32 seqno;
778 int ret;
779
780 ret = intel_ring_begin(ring, 4);
781 if (ret)
782 return ret;
783
784 seqno = i915_gem_next_request_seqno(ring);
785
786 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
787 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
788 intel_ring_emit(ring, seqno);
789 intel_ring_emit(ring, MI_USER_INTERRUPT);
790 intel_ring_advance(ring);
791
792 *result = seqno;
793 return 0;
794 }
795
796 static bool
797 gen6_ring_get_irq(struct intel_ring_buffer *ring)
798 {
799 struct drm_device *dev = ring->dev;
800 drm_i915_private_t *dev_priv = dev->dev_private;
801
802 if (!dev->irq_enabled)
803 return false;
804
805 /* It looks like we need to prevent the gt from suspending while waiting
806 * for an notifiy irq, otherwise irqs seem to get lost on at least the
807 * blt/bsd rings on ivb. */
808 gen6_gt_force_wake_get(dev_priv);
809
810 spin_lock(&ring->irq_lock);
811 if (ring->irq_refcount++ == 0) {
812 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
813 ironlake_enable_irq(dev_priv, ring->irq_enable_mask);
814 }
815 spin_unlock(&ring->irq_lock);
816
817 return true;
818 }
819
820 static void
821 gen6_ring_put_irq(struct intel_ring_buffer *ring)
822 {
823 struct drm_device *dev = ring->dev;
824 drm_i915_private_t *dev_priv = dev->dev_private;
825
826 spin_lock(&ring->irq_lock);
827 if (--ring->irq_refcount == 0) {
828 I915_WRITE_IMR(ring, ~0);
829 ironlake_disable_irq(dev_priv, ring->irq_enable_mask);
830 }
831 spin_unlock(&ring->irq_lock);
832
833 gen6_gt_force_wake_put(dev_priv);
834 }
835
836 static bool
837 bsd_ring_get_irq(struct intel_ring_buffer *ring)
838 {
839 struct drm_device *dev = ring->dev;
840 drm_i915_private_t *dev_priv = dev->dev_private;
841
842 if (!dev->irq_enabled)
843 return false;
844
845 spin_lock(&ring->irq_lock);
846 if (ring->irq_refcount++ == 0) {
847 if (IS_G4X(dev))
848 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
849 else
850 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
851 }
852 spin_unlock(&ring->irq_lock);
853
854 return true;
855 }
856 static void
857 bsd_ring_put_irq(struct intel_ring_buffer *ring)
858 {
859 struct drm_device *dev = ring->dev;
860 drm_i915_private_t *dev_priv = dev->dev_private;
861
862 spin_lock(&ring->irq_lock);
863 if (--ring->irq_refcount == 0) {
864 if (IS_G4X(dev))
865 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
866 else
867 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
868 }
869 spin_unlock(&ring->irq_lock);
870 }
871
872 static int
873 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
874 {
875 int ret;
876
877 ret = intel_ring_begin(ring, 2);
878 if (ret)
879 return ret;
880
881 intel_ring_emit(ring,
882 MI_BATCH_BUFFER_START | (2 << 6) |
883 MI_BATCH_NON_SECURE_I965);
884 intel_ring_emit(ring, offset);
885 intel_ring_advance(ring);
886
887 return 0;
888 }
889
890 static int
891 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
892 u32 offset, u32 len)
893 {
894 struct drm_device *dev = ring->dev;
895 int ret;
896
897 if (IS_I830(dev) || IS_845G(dev)) {
898 ret = intel_ring_begin(ring, 4);
899 if (ret)
900 return ret;
901
902 intel_ring_emit(ring, MI_BATCH_BUFFER);
903 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
904 intel_ring_emit(ring, offset + len - 8);
905 intel_ring_emit(ring, 0);
906 } else {
907 ret = intel_ring_begin(ring, 2);
908 if (ret)
909 return ret;
910
911 if (INTEL_INFO(dev)->gen >= 4) {
912 intel_ring_emit(ring,
913 MI_BATCH_BUFFER_START | (2 << 6) |
914 MI_BATCH_NON_SECURE_I965);
915 intel_ring_emit(ring, offset);
916 } else {
917 intel_ring_emit(ring,
918 MI_BATCH_BUFFER_START | (2 << 6));
919 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
920 }
921 }
922 intel_ring_advance(ring);
923
924 return 0;
925 }
926
927 static void cleanup_status_page(struct intel_ring_buffer *ring)
928 {
929 drm_i915_private_t *dev_priv = ring->dev->dev_private;
930 struct drm_i915_gem_object *obj;
931
932 obj = ring->status_page.obj;
933 if (obj == NULL)
934 return;
935
936 kunmap(obj->pages[0]);
937 i915_gem_object_unpin(obj);
938 drm_gem_object_unreference(&obj->base);
939 ring->status_page.obj = NULL;
940
941 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
942 }
943
944 static int init_status_page(struct intel_ring_buffer *ring)
945 {
946 struct drm_device *dev = ring->dev;
947 drm_i915_private_t *dev_priv = dev->dev_private;
948 struct drm_i915_gem_object *obj;
949 int ret;
950
951 obj = i915_gem_alloc_object(dev, 4096);
952 if (obj == NULL) {
953 DRM_ERROR("Failed to allocate status page\n");
954 ret = -ENOMEM;
955 goto err;
956 }
957
958 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
959
960 ret = i915_gem_object_pin(obj, 4096, true);
961 if (ret != 0) {
962 goto err_unref;
963 }
964
965 ring->status_page.gfx_addr = obj->gtt_offset;
966 ring->status_page.page_addr = kmap(obj->pages[0]);
967 if (ring->status_page.page_addr == NULL) {
968 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
969 goto err_unpin;
970 }
971 ring->status_page.obj = obj;
972 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
973
974 intel_ring_setup_status_page(ring);
975 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
976 ring->name, ring->status_page.gfx_addr);
977
978 return 0;
979
980 err_unpin:
981 i915_gem_object_unpin(obj);
982 err_unref:
983 drm_gem_object_unreference(&obj->base);
984 err:
985 return ret;
986 }
987
988 int intel_init_ring_buffer(struct drm_device *dev,
989 struct intel_ring_buffer *ring)
990 {
991 struct drm_i915_gem_object *obj;
992 int ret;
993
994 ring->dev = dev;
995 INIT_LIST_HEAD(&ring->active_list);
996 INIT_LIST_HEAD(&ring->request_list);
997 INIT_LIST_HEAD(&ring->gpu_write_list);
998 ring->size = 32 * PAGE_SIZE;
999
1000 init_waitqueue_head(&ring->irq_queue);
1001 spin_lock_init(&ring->irq_lock);
1002
1003 if (I915_NEED_GFX_HWS(dev)) {
1004 ret = init_status_page(ring);
1005 if (ret)
1006 return ret;
1007 }
1008
1009 obj = i915_gem_alloc_object(dev, ring->size);
1010 if (obj == NULL) {
1011 DRM_ERROR("Failed to allocate ringbuffer\n");
1012 ret = -ENOMEM;
1013 goto err_hws;
1014 }
1015
1016 ring->obj = obj;
1017
1018 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1019 if (ret)
1020 goto err_unref;
1021
1022 ring->map.size = ring->size;
1023 ring->map.offset = dev->agp->base + obj->gtt_offset;
1024 ring->map.type = 0;
1025 ring->map.flags = 0;
1026 ring->map.mtrr = 0;
1027
1028 drm_core_ioremap_wc(&ring->map, dev);
1029 if (ring->map.handle == NULL) {
1030 DRM_ERROR("Failed to map ringbuffer.\n");
1031 ret = -EINVAL;
1032 goto err_unpin;
1033 }
1034
1035 ring->virtual_start = ring->map.handle;
1036 ret = ring->init(ring);
1037 if (ret)
1038 goto err_unmap;
1039
1040 /* Workaround an erratum on the i830 which causes a hang if
1041 * the TAIL pointer points to within the last 2 cachelines
1042 * of the buffer.
1043 */
1044 ring->effective_size = ring->size;
1045 if (IS_I830(ring->dev))
1046 ring->effective_size -= 128;
1047
1048 return 0;
1049
1050 err_unmap:
1051 drm_core_ioremapfree(&ring->map, dev);
1052 err_unpin:
1053 i915_gem_object_unpin(obj);
1054 err_unref:
1055 drm_gem_object_unreference(&obj->base);
1056 ring->obj = NULL;
1057 err_hws:
1058 cleanup_status_page(ring);
1059 return ret;
1060 }
1061
1062 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1063 {
1064 struct drm_i915_private *dev_priv;
1065 int ret;
1066
1067 if (ring->obj == NULL)
1068 return;
1069
1070 /* Disable the ring buffer. The ring must be idle at this point */
1071 dev_priv = ring->dev->dev_private;
1072 ret = intel_wait_ring_idle(ring);
1073 if (ret)
1074 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1075 ring->name, ret);
1076
1077 I915_WRITE_CTL(ring, 0);
1078
1079 drm_core_ioremapfree(&ring->map, ring->dev);
1080
1081 i915_gem_object_unpin(ring->obj);
1082 drm_gem_object_unreference(&ring->obj->base);
1083 ring->obj = NULL;
1084
1085 if (ring->cleanup)
1086 ring->cleanup(ring);
1087
1088 cleanup_status_page(ring);
1089 }
1090
1091 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1092 {
1093 unsigned int *virt;
1094 int rem = ring->size - ring->tail;
1095
1096 if (ring->space < rem) {
1097 int ret = intel_wait_ring_buffer(ring, rem);
1098 if (ret)
1099 return ret;
1100 }
1101
1102 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1103 rem /= 8;
1104 while (rem--) {
1105 *virt++ = MI_NOOP;
1106 *virt++ = MI_NOOP;
1107 }
1108
1109 ring->tail = 0;
1110 ring->space = ring_space(ring);
1111
1112 return 0;
1113 }
1114
1115 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1116 {
1117 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1118 bool was_interruptible;
1119 int ret;
1120
1121 /* XXX As we have not yet audited all the paths to check that
1122 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1123 * allow us to be interruptible by a signal.
1124 */
1125 was_interruptible = dev_priv->mm.interruptible;
1126 dev_priv->mm.interruptible = false;
1127
1128 ret = i915_wait_request(ring, seqno, true);
1129
1130 dev_priv->mm.interruptible = was_interruptible;
1131
1132 return ret;
1133 }
1134
1135 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1136 {
1137 struct drm_i915_gem_request *request;
1138 u32 seqno = 0;
1139 int ret;
1140
1141 i915_gem_retire_requests_ring(ring);
1142
1143 if (ring->last_retired_head != -1) {
1144 ring->head = ring->last_retired_head;
1145 ring->last_retired_head = -1;
1146 ring->space = ring_space(ring);
1147 if (ring->space >= n)
1148 return 0;
1149 }
1150
1151 list_for_each_entry(request, &ring->request_list, list) {
1152 int space;
1153
1154 if (request->tail == -1)
1155 continue;
1156
1157 space = request->tail - (ring->tail + 8);
1158 if (space < 0)
1159 space += ring->size;
1160 if (space >= n) {
1161 seqno = request->seqno;
1162 break;
1163 }
1164
1165 /* Consume this request in case we need more space than
1166 * is available and so need to prevent a race between
1167 * updating last_retired_head and direct reads of
1168 * I915_RING_HEAD. It also provides a nice sanity check.
1169 */
1170 request->tail = -1;
1171 }
1172
1173 if (seqno == 0)
1174 return -ENOSPC;
1175
1176 ret = intel_ring_wait_seqno(ring, seqno);
1177 if (ret)
1178 return ret;
1179
1180 if (WARN_ON(ring->last_retired_head == -1))
1181 return -ENOSPC;
1182
1183 ring->head = ring->last_retired_head;
1184 ring->last_retired_head = -1;
1185 ring->space = ring_space(ring);
1186 if (WARN_ON(ring->space < n))
1187 return -ENOSPC;
1188
1189 return 0;
1190 }
1191
1192 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1193 {
1194 struct drm_device *dev = ring->dev;
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 unsigned long end;
1197 int ret;
1198
1199 ret = intel_ring_wait_request(ring, n);
1200 if (ret != -ENOSPC)
1201 return ret;
1202
1203 trace_i915_ring_wait_begin(ring);
1204 if (drm_core_check_feature(dev, DRIVER_GEM))
1205 /* With GEM the hangcheck timer should kick us out of the loop,
1206 * leaving it early runs the risk of corrupting GEM state (due
1207 * to running on almost untested codepaths). But on resume
1208 * timers don't work yet, so prevent a complete hang in that
1209 * case by choosing an insanely large timeout. */
1210 end = jiffies + 60 * HZ;
1211 else
1212 end = jiffies + 3 * HZ;
1213
1214 do {
1215 ring->head = I915_READ_HEAD(ring);
1216 ring->space = ring_space(ring);
1217 if (ring->space >= n) {
1218 trace_i915_ring_wait_end(ring);
1219 return 0;
1220 }
1221
1222 if (dev->primary->master) {
1223 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1224 if (master_priv->sarea_priv)
1225 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1226 }
1227
1228 msleep(1);
1229 if (atomic_read(&dev_priv->mm.wedged))
1230 return -EAGAIN;
1231 } while (!time_after(jiffies, end));
1232 trace_i915_ring_wait_end(ring);
1233 return -EBUSY;
1234 }
1235
1236 int intel_ring_begin(struct intel_ring_buffer *ring,
1237 int num_dwords)
1238 {
1239 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1240 int n = 4*num_dwords;
1241 int ret;
1242
1243 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1244 return -EIO;
1245
1246 if (unlikely(ring->tail + n > ring->effective_size)) {
1247 ret = intel_wrap_ring_buffer(ring);
1248 if (unlikely(ret))
1249 return ret;
1250 }
1251
1252 if (unlikely(ring->space < n)) {
1253 ret = intel_wait_ring_buffer(ring, n);
1254 if (unlikely(ret))
1255 return ret;
1256 }
1257
1258 ring->space -= n;
1259 return 0;
1260 }
1261
1262 void intel_ring_advance(struct intel_ring_buffer *ring)
1263 {
1264 ring->tail &= ring->size - 1;
1265 ring->write_tail(ring, ring->tail);
1266 }
1267
1268 /* ring buffer for bit-stream decoder */
1269
1270 static const struct intel_ring_buffer bsd_ring = {
1271 .name = "bsd ring",
1272 .id = VCS,
1273 .mmio_base = BSD_RING_BASE,
1274 .init = init_ring_common,
1275 .write_tail = ring_write_tail,
1276 .flush = bsd_ring_flush,
1277 .add_request = ring_add_request,
1278 .get_seqno = ring_get_seqno,
1279 .irq_get = bsd_ring_get_irq,
1280 .irq_put = bsd_ring_put_irq,
1281 .dispatch_execbuffer = ring_dispatch_execbuffer,
1282 };
1283
1284
1285 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1286 u32 value)
1287 {
1288 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1289
1290 /* Every tail move must follow the sequence below */
1291 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1292 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1293 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1294 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1295
1296 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1297 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1298 50))
1299 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1300
1301 I915_WRITE_TAIL(ring, value);
1302 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1303 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1304 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1305 }
1306
1307 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1308 u32 invalidate, u32 flush)
1309 {
1310 uint32_t cmd;
1311 int ret;
1312
1313 ret = intel_ring_begin(ring, 4);
1314 if (ret)
1315 return ret;
1316
1317 cmd = MI_FLUSH_DW;
1318 if (invalidate & I915_GEM_GPU_DOMAINS)
1319 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1320 intel_ring_emit(ring, cmd);
1321 intel_ring_emit(ring, 0);
1322 intel_ring_emit(ring, 0);
1323 intel_ring_emit(ring, MI_NOOP);
1324 intel_ring_advance(ring);
1325 return 0;
1326 }
1327
1328 static int
1329 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1330 u32 offset, u32 len)
1331 {
1332 int ret;
1333
1334 ret = intel_ring_begin(ring, 2);
1335 if (ret)
1336 return ret;
1337
1338 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1339 /* bit0-7 is the length on GEN6+ */
1340 intel_ring_emit(ring, offset);
1341 intel_ring_advance(ring);
1342
1343 return 0;
1344 }
1345
1346 /* ring buffer for Video Codec for Gen6+ */
1347 static const struct intel_ring_buffer gen6_bsd_ring = {
1348 .name = "gen6 bsd ring",
1349 .id = VCS,
1350 .mmio_base = GEN6_BSD_RING_BASE,
1351 .init = init_ring_common,
1352 .write_tail = gen6_bsd_ring_write_tail,
1353 .flush = gen6_ring_flush,
1354 .add_request = gen6_add_request,
1355 .get_seqno = gen6_ring_get_seqno,
1356 .irq_enable_mask = GEN6_BSD_USER_INTERRUPT,
1357 .irq_get = gen6_ring_get_irq,
1358 .irq_put = gen6_ring_put_irq,
1359 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1360 .sync_to = gen6_bsd_ring_sync_to,
1361 .semaphore_register = {MI_SEMAPHORE_SYNC_VR,
1362 MI_SEMAPHORE_SYNC_INVALID,
1363 MI_SEMAPHORE_SYNC_VB},
1364 .signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
1365 };
1366
1367 /* Blitter support (SandyBridge+) */
1368
1369 static int blt_ring_flush(struct intel_ring_buffer *ring,
1370 u32 invalidate, u32 flush)
1371 {
1372 uint32_t cmd;
1373 int ret;
1374
1375 ret = intel_ring_begin(ring, 4);
1376 if (ret)
1377 return ret;
1378
1379 cmd = MI_FLUSH_DW;
1380 if (invalidate & I915_GEM_DOMAIN_RENDER)
1381 cmd |= MI_INVALIDATE_TLB;
1382 intel_ring_emit(ring, cmd);
1383 intel_ring_emit(ring, 0);
1384 intel_ring_emit(ring, 0);
1385 intel_ring_emit(ring, MI_NOOP);
1386 intel_ring_advance(ring);
1387 return 0;
1388 }
1389
1390 static const struct intel_ring_buffer gen6_blt_ring = {
1391 .name = "blt ring",
1392 .id = BCS,
1393 .mmio_base = BLT_RING_BASE,
1394 .init = init_ring_common,
1395 .write_tail = ring_write_tail,
1396 .flush = blt_ring_flush,
1397 .add_request = gen6_add_request,
1398 .get_seqno = gen6_ring_get_seqno,
1399 .irq_get = gen6_ring_get_irq,
1400 .irq_put = gen6_ring_put_irq,
1401 .irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT,
1402 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1403 .sync_to = gen6_blt_ring_sync_to,
1404 .semaphore_register = {MI_SEMAPHORE_SYNC_BR,
1405 MI_SEMAPHORE_SYNC_BV,
1406 MI_SEMAPHORE_SYNC_INVALID},
1407 .signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
1408 };
1409
1410 int intel_init_render_ring_buffer(struct drm_device *dev)
1411 {
1412 drm_i915_private_t *dev_priv = dev->dev_private;
1413 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1414
1415 ring->name = "render ring";
1416 ring->id = RCS;
1417 ring->mmio_base = RENDER_RING_BASE;
1418
1419 if (INTEL_INFO(dev)->gen >= 6) {
1420 ring->add_request = gen6_add_request;
1421 ring->flush = gen6_render_ring_flush;
1422 ring->irq_get = gen6_ring_get_irq;
1423 ring->irq_put = gen6_ring_put_irq;
1424 ring->irq_enable_mask = GT_USER_INTERRUPT;
1425 ring->get_seqno = gen6_ring_get_seqno;
1426 ring->sync_to = render_ring_sync_to;
1427 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1428 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1429 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1430 ring->signal_mbox[0] = GEN6_VRSYNC;
1431 ring->signal_mbox[1] = GEN6_BRSYNC;
1432 } else if (IS_GEN5(dev)) {
1433 ring->add_request = pc_render_add_request;
1434 ring->flush = render_ring_flush;
1435 ring->get_seqno = pc_render_get_seqno;
1436 ring->irq_get = render_ring_get_irq;
1437 ring->irq_put = render_ring_put_irq;
1438 } else {
1439 ring->add_request = render_ring_add_request;
1440 ring->flush = render_ring_flush;
1441 ring->get_seqno = ring_get_seqno;
1442 ring->irq_get = render_ring_get_irq;
1443 ring->irq_put = render_ring_put_irq;
1444 }
1445 ring->write_tail = ring_write_tail;
1446 ring->dispatch_execbuffer = render_ring_dispatch_execbuffer;
1447 ring->init = init_render_ring;
1448 ring->cleanup = render_ring_cleanup;
1449
1450
1451 if (!I915_NEED_GFX_HWS(dev)) {
1452 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1453 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1454 }
1455
1456 return intel_init_ring_buffer(dev, ring);
1457 }
1458
1459 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1460 {
1461 drm_i915_private_t *dev_priv = dev->dev_private;
1462 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1463
1464 ring->name = "render ring";
1465 ring->id = RCS;
1466 ring->mmio_base = RENDER_RING_BASE;
1467
1468 if (INTEL_INFO(dev)->gen >= 6) {
1469 ring->add_request = gen6_add_request;
1470 ring->flush = gen6_render_ring_flush;
1471 ring->irq_get = gen6_ring_get_irq;
1472 ring->irq_put = gen6_ring_put_irq;
1473 ring->irq_enable_mask = GT_USER_INTERRUPT;
1474 ring->get_seqno = gen6_ring_get_seqno;
1475 ring->sync_to = render_ring_sync_to;
1476 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1477 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1478 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1479 ring->signal_mbox[0] = GEN6_VRSYNC;
1480 ring->signal_mbox[1] = GEN6_BRSYNC;
1481 } else if (IS_GEN5(dev)) {
1482 ring->add_request = pc_render_add_request;
1483 ring->flush = render_ring_flush;
1484 ring->get_seqno = pc_render_get_seqno;
1485 ring->irq_get = render_ring_get_irq;
1486 ring->irq_put = render_ring_put_irq;
1487 } else {
1488 ring->add_request = render_ring_add_request;
1489 ring->flush = render_ring_flush;
1490 ring->get_seqno = ring_get_seqno;
1491 ring->irq_get = render_ring_get_irq;
1492 ring->irq_put = render_ring_put_irq;
1493 }
1494 ring->write_tail = ring_write_tail;
1495 ring->dispatch_execbuffer = render_ring_dispatch_execbuffer;
1496 ring->init = init_render_ring;
1497 ring->cleanup = render_ring_cleanup;
1498
1499 if (!I915_NEED_GFX_HWS(dev))
1500 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1501
1502 ring->dev = dev;
1503 INIT_LIST_HEAD(&ring->active_list);
1504 INIT_LIST_HEAD(&ring->request_list);
1505 INIT_LIST_HEAD(&ring->gpu_write_list);
1506
1507 ring->size = size;
1508 ring->effective_size = ring->size;
1509 if (IS_I830(ring->dev))
1510 ring->effective_size -= 128;
1511
1512 ring->map.offset = start;
1513 ring->map.size = size;
1514 ring->map.type = 0;
1515 ring->map.flags = 0;
1516 ring->map.mtrr = 0;
1517
1518 drm_core_ioremap_wc(&ring->map, dev);
1519 if (ring->map.handle == NULL) {
1520 DRM_ERROR("can not ioremap virtual address for"
1521 " ring buffer\n");
1522 return -ENOMEM;
1523 }
1524
1525 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1526 return 0;
1527 }
1528
1529 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1530 {
1531 drm_i915_private_t *dev_priv = dev->dev_private;
1532 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1533
1534 if (IS_GEN6(dev) || IS_GEN7(dev))
1535 *ring = gen6_bsd_ring;
1536 else
1537 *ring = bsd_ring;
1538
1539 return intel_init_ring_buffer(dev, ring);
1540 }
1541
1542 int intel_init_blt_ring_buffer(struct drm_device *dev)
1543 {
1544 drm_i915_private_t *dev_priv = dev->dev_private;
1545 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1546
1547 *ring = gen6_blt_ring;
1548
1549 return intel_init_ring_buffer(dev, ring);
1550 }
Linux kernel - Deliverables
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