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drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
286 {
287 u32 flags = 0;
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
290 int ret;
291
292 /*
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
295 *
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
299 */
300 flags |= PIPE_CONTROL_CS_STALL;
301
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
304 * impact.
305 */
306 if (flush_domains) {
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
309 }
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
317 /*
318 * TLB invalidate requires a post-sync write.
319 */
320 flags |= PIPE_CONTROL_QW_WRITE;
321
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring);
326 }
327
328 ret = intel_ring_begin(ring, 4);
329 if (ret)
330 return ret;
331
332 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring, flags);
334 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
335 intel_ring_emit(ring, 0);
336 intel_ring_advance(ring);
337
338 return 0;
339 }
340
341 static void ring_write_tail(struct intel_ring_buffer *ring,
342 u32 value)
343 {
344 drm_i915_private_t *dev_priv = ring->dev->dev_private;
345 I915_WRITE_TAIL(ring, value);
346 }
347
348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
349 {
350 drm_i915_private_t *dev_priv = ring->dev->dev_private;
351 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
352 RING_ACTHD(ring->mmio_base) : ACTHD;
353
354 return I915_READ(acthd_reg);
355 }
356
357 static int init_ring_common(struct intel_ring_buffer *ring)
358 {
359 struct drm_device *dev = ring->dev;
360 drm_i915_private_t *dev_priv = dev->dev_private;
361 struct drm_i915_gem_object *obj = ring->obj;
362 int ret = 0;
363 u32 head;
364
365 if (HAS_FORCE_WAKE(dev))
366 gen6_gt_force_wake_get(dev_priv);
367
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring, 0);
370 I915_WRITE_HEAD(ring, 0);
371 ring->write_tail(ring, 0);
372
373 head = I915_READ_HEAD(ring) & HEAD_ADDR;
374
375 /* G45 ring initialization fails to reset head to zero */
376 if (head != 0) {
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
379 ring->name,
380 I915_READ_CTL(ring),
381 I915_READ_HEAD(ring),
382 I915_READ_TAIL(ring),
383 I915_READ_START(ring));
384
385 I915_WRITE_HEAD(ring, 0);
386
387 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
390 ring->name,
391 I915_READ_CTL(ring),
392 I915_READ_HEAD(ring),
393 I915_READ_TAIL(ring),
394 I915_READ_START(ring));
395 }
396 }
397
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring, obj->gtt_offset);
403 I915_WRITE_CTL(ring,
404 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
405 | RING_VALID);
406
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
409 I915_READ_START(ring) == obj->gtt_offset &&
410 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
413 ring->name,
414 I915_READ_CTL(ring),
415 I915_READ_HEAD(ring),
416 I915_READ_TAIL(ring),
417 I915_READ_START(ring));
418 ret = -EIO;
419 goto out;
420 }
421
422 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
423 i915_kernel_lost_context(ring->dev);
424 else {
425 ring->head = I915_READ_HEAD(ring);
426 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
427 ring->space = ring_space(ring);
428 ring->last_retired_head = -1;
429 }
430
431 out:
432 if (HAS_FORCE_WAKE(dev))
433 gen6_gt_force_wake_put(dev_priv);
434
435 return ret;
436 }
437
438 static int
439 init_pipe_control(struct intel_ring_buffer *ring)
440 {
441 struct pipe_control *pc;
442 struct drm_i915_gem_object *obj;
443 int ret;
444
445 if (ring->private)
446 return 0;
447
448 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
449 if (!pc)
450 return -ENOMEM;
451
452 obj = i915_gem_alloc_object(ring->dev, 4096);
453 if (obj == NULL) {
454 DRM_ERROR("Failed to allocate seqno page\n");
455 ret = -ENOMEM;
456 goto err;
457 }
458
459 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
460
461 ret = i915_gem_object_pin(obj, 4096, true, false);
462 if (ret)
463 goto err_unref;
464
465 pc->gtt_offset = obj->gtt_offset;
466 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
467 if (pc->cpu_page == NULL)
468 goto err_unpin;
469
470 pc->obj = obj;
471 ring->private = pc;
472 return 0;
473
474 err_unpin:
475 i915_gem_object_unpin(obj);
476 err_unref:
477 drm_gem_object_unreference(&obj->base);
478 err:
479 kfree(pc);
480 return ret;
481 }
482
483 static void
484 cleanup_pipe_control(struct intel_ring_buffer *ring)
485 {
486 struct pipe_control *pc = ring->private;
487 struct drm_i915_gem_object *obj;
488
489 if (!ring->private)
490 return;
491
492 obj = pc->obj;
493
494 kunmap(sg_page(obj->pages->sgl));
495 i915_gem_object_unpin(obj);
496 drm_gem_object_unreference(&obj->base);
497
498 kfree(pc);
499 ring->private = NULL;
500 }
501
502 static int init_render_ring(struct intel_ring_buffer *ring)
503 {
504 struct drm_device *dev = ring->dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring);
507
508 if (INTEL_INFO(dev)->gen > 3) {
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
510 if (IS_GEN7(dev))
511 I915_WRITE(GFX_MODE_GEN7,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
514 }
515
516 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring);
518 if (ret)
519 return ret;
520 }
521
522 if (IS_GEN6(dev)) {
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
527 */
528 I915_WRITE(CACHE_MODE_0,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
530
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
534 */
535 ring->itlb_before_ctx_switch =
536 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
537 }
538
539 if (INTEL_INFO(dev)->gen >= 6)
540 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
541
542 if (HAS_L3_GPU_CACHE(dev))
543 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
544
545 return ret;
546 }
547
548 static void render_ring_cleanup(struct intel_ring_buffer *ring)
549 {
550 if (!ring->private)
551 return;
552
553 cleanup_pipe_control(ring);
554 }
555
556 static void
557 update_mboxes(struct intel_ring_buffer *ring,
558 u32 seqno,
559 u32 mmio_offset)
560 {
561 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
562 MI_SEMAPHORE_GLOBAL_GTT |
563 MI_SEMAPHORE_REGISTER |
564 MI_SEMAPHORE_UPDATE);
565 intel_ring_emit(ring, seqno);
566 intel_ring_emit(ring, mmio_offset);
567 }
568
569 /**
570 * gen6_add_request - Update the semaphore mailbox registers
571 *
572 * @ring - ring that is adding a request
573 * @seqno - return seqno stuck into the ring
574 *
575 * Update the mailbox registers in the *other* rings with the current seqno.
576 * This acts like a signal in the canonical semaphore.
577 */
578 static int
579 gen6_add_request(struct intel_ring_buffer *ring,
580 u32 *seqno)
581 {
582 u32 mbox1_reg;
583 u32 mbox2_reg;
584 int ret;
585
586 ret = intel_ring_begin(ring, 10);
587 if (ret)
588 return ret;
589
590 mbox1_reg = ring->signal_mbox[0];
591 mbox2_reg = ring->signal_mbox[1];
592
593 *seqno = i915_gem_next_request_seqno(ring);
594
595 update_mboxes(ring, *seqno, mbox1_reg);
596 update_mboxes(ring, *seqno, mbox2_reg);
597 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
598 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
599 intel_ring_emit(ring, *seqno);
600 intel_ring_emit(ring, MI_USER_INTERRUPT);
601 intel_ring_advance(ring);
602
603 return 0;
604 }
605
606 /**
607 * intel_ring_sync - sync the waiter to the signaller on seqno
608 *
609 * @waiter - ring that is waiting
610 * @signaller - ring which has, or will signal
611 * @seqno - seqno which the waiter will block on
612 */
613 static int
614 gen6_ring_sync(struct intel_ring_buffer *waiter,
615 struct intel_ring_buffer *signaller,
616 u32 seqno)
617 {
618 int ret;
619 u32 dw1 = MI_SEMAPHORE_MBOX |
620 MI_SEMAPHORE_COMPARE |
621 MI_SEMAPHORE_REGISTER;
622
623 /* Throughout all of the GEM code, seqno passed implies our current
624 * seqno is >= the last seqno executed. However for hardware the
625 * comparison is strictly greater than.
626 */
627 seqno -= 1;
628
629 WARN_ON(signaller->semaphore_register[waiter->id] ==
630 MI_SEMAPHORE_SYNC_INVALID);
631
632 ret = intel_ring_begin(waiter, 4);
633 if (ret)
634 return ret;
635
636 intel_ring_emit(waiter,
637 dw1 | signaller->semaphore_register[waiter->id]);
638 intel_ring_emit(waiter, seqno);
639 intel_ring_emit(waiter, 0);
640 intel_ring_emit(waiter, MI_NOOP);
641 intel_ring_advance(waiter);
642
643 return 0;
644 }
645
646 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
647 do { \
648 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
649 PIPE_CONTROL_DEPTH_STALL); \
650 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
651 intel_ring_emit(ring__, 0); \
652 intel_ring_emit(ring__, 0); \
653 } while (0)
654
655 static int
656 pc_render_add_request(struct intel_ring_buffer *ring,
657 u32 *result)
658 {
659 u32 seqno = i915_gem_next_request_seqno(ring);
660 struct pipe_control *pc = ring->private;
661 u32 scratch_addr = pc->gtt_offset + 128;
662 int ret;
663
664 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
665 * incoherent with writes to memory, i.e. completely fubar,
666 * so we need to use PIPE_NOTIFY instead.
667 *
668 * However, we also need to workaround the qword write
669 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
670 * memory before requesting an interrupt.
671 */
672 ret = intel_ring_begin(ring, 32);
673 if (ret)
674 return ret;
675
676 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
677 PIPE_CONTROL_WRITE_FLUSH |
678 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
679 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
680 intel_ring_emit(ring, seqno);
681 intel_ring_emit(ring, 0);
682 PIPE_CONTROL_FLUSH(ring, scratch_addr);
683 scratch_addr += 128; /* write to separate cachelines */
684 PIPE_CONTROL_FLUSH(ring, scratch_addr);
685 scratch_addr += 128;
686 PIPE_CONTROL_FLUSH(ring, scratch_addr);
687 scratch_addr += 128;
688 PIPE_CONTROL_FLUSH(ring, scratch_addr);
689 scratch_addr += 128;
690 PIPE_CONTROL_FLUSH(ring, scratch_addr);
691 scratch_addr += 128;
692 PIPE_CONTROL_FLUSH(ring, scratch_addr);
693
694 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
695 PIPE_CONTROL_WRITE_FLUSH |
696 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
697 PIPE_CONTROL_NOTIFY);
698 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
699 intel_ring_emit(ring, seqno);
700 intel_ring_emit(ring, 0);
701 intel_ring_advance(ring);
702
703 *result = seqno;
704 return 0;
705 }
706
707 static u32
708 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
709 {
710 /* Workaround to force correct ordering between irq and seqno writes on
711 * ivb (and maybe also on snb) by reading from a CS register (like
712 * ACTHD) before reading the status page. */
713 if (!lazy_coherency)
714 intel_ring_get_active_head(ring);
715 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
716 }
717
718 static u32
719 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
720 {
721 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
722 }
723
724 static u32
725 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
726 {
727 struct pipe_control *pc = ring->private;
728 return pc->cpu_page[0];
729 }
730
731 static bool
732 gen5_ring_get_irq(struct intel_ring_buffer *ring)
733 {
734 struct drm_device *dev = ring->dev;
735 drm_i915_private_t *dev_priv = dev->dev_private;
736 unsigned long flags;
737
738 if (!dev->irq_enabled)
739 return false;
740
741 spin_lock_irqsave(&dev_priv->irq_lock, flags);
742 if (ring->irq_refcount++ == 0) {
743 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
744 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
745 POSTING_READ(GTIMR);
746 }
747 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
748
749 return true;
750 }
751
752 static void
753 gen5_ring_put_irq(struct intel_ring_buffer *ring)
754 {
755 struct drm_device *dev = ring->dev;
756 drm_i915_private_t *dev_priv = dev->dev_private;
757 unsigned long flags;
758
759 spin_lock_irqsave(&dev_priv->irq_lock, flags);
760 if (--ring->irq_refcount == 0) {
761 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
762 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
763 POSTING_READ(GTIMR);
764 }
765 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
766 }
767
768 static bool
769 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
770 {
771 struct drm_device *dev = ring->dev;
772 drm_i915_private_t *dev_priv = dev->dev_private;
773 unsigned long flags;
774
775 if (!dev->irq_enabled)
776 return false;
777
778 spin_lock_irqsave(&dev_priv->irq_lock, flags);
779 if (ring->irq_refcount++ == 0) {
780 dev_priv->irq_mask &= ~ring->irq_enable_mask;
781 I915_WRITE(IMR, dev_priv->irq_mask);
782 POSTING_READ(IMR);
783 }
784 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
785
786 return true;
787 }
788
789 static void
790 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
791 {
792 struct drm_device *dev = ring->dev;
793 drm_i915_private_t *dev_priv = dev->dev_private;
794 unsigned long flags;
795
796 spin_lock_irqsave(&dev_priv->irq_lock, flags);
797 if (--ring->irq_refcount == 0) {
798 dev_priv->irq_mask |= ring->irq_enable_mask;
799 I915_WRITE(IMR, dev_priv->irq_mask);
800 POSTING_READ(IMR);
801 }
802 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
803 }
804
805 static bool
806 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
807 {
808 struct drm_device *dev = ring->dev;
809 drm_i915_private_t *dev_priv = dev->dev_private;
810 unsigned long flags;
811
812 if (!dev->irq_enabled)
813 return false;
814
815 spin_lock_irqsave(&dev_priv->irq_lock, flags);
816 if (ring->irq_refcount++ == 0) {
817 dev_priv->irq_mask &= ~ring->irq_enable_mask;
818 I915_WRITE16(IMR, dev_priv->irq_mask);
819 POSTING_READ16(IMR);
820 }
821 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
822
823 return true;
824 }
825
826 static void
827 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
828 {
829 struct drm_device *dev = ring->dev;
830 drm_i915_private_t *dev_priv = dev->dev_private;
831 unsigned long flags;
832
833 spin_lock_irqsave(&dev_priv->irq_lock, flags);
834 if (--ring->irq_refcount == 0) {
835 dev_priv->irq_mask |= ring->irq_enable_mask;
836 I915_WRITE16(IMR, dev_priv->irq_mask);
837 POSTING_READ16(IMR);
838 }
839 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
840 }
841
842 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
843 {
844 struct drm_device *dev = ring->dev;
845 drm_i915_private_t *dev_priv = ring->dev->dev_private;
846 u32 mmio = 0;
847
848 /* The ring status page addresses are no longer next to the rest of
849 * the ring registers as of gen7.
850 */
851 if (IS_GEN7(dev)) {
852 switch (ring->id) {
853 case RCS:
854 mmio = RENDER_HWS_PGA_GEN7;
855 break;
856 case BCS:
857 mmio = BLT_HWS_PGA_GEN7;
858 break;
859 case VCS:
860 mmio = BSD_HWS_PGA_GEN7;
861 break;
862 }
863 } else if (IS_GEN6(ring->dev)) {
864 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
865 } else {
866 mmio = RING_HWS_PGA(ring->mmio_base);
867 }
868
869 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
870 POSTING_READ(mmio);
871 }
872
873 static int
874 bsd_ring_flush(struct intel_ring_buffer *ring,
875 u32 invalidate_domains,
876 u32 flush_domains)
877 {
878 int ret;
879
880 ret = intel_ring_begin(ring, 2);
881 if (ret)
882 return ret;
883
884 intel_ring_emit(ring, MI_FLUSH);
885 intel_ring_emit(ring, MI_NOOP);
886 intel_ring_advance(ring);
887 return 0;
888 }
889
890 static int
891 i9xx_add_request(struct intel_ring_buffer *ring,
892 u32 *result)
893 {
894 u32 seqno;
895 int ret;
896
897 ret = intel_ring_begin(ring, 4);
898 if (ret)
899 return ret;
900
901 seqno = i915_gem_next_request_seqno(ring);
902
903 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
904 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
905 intel_ring_emit(ring, seqno);
906 intel_ring_emit(ring, MI_USER_INTERRUPT);
907 intel_ring_advance(ring);
908
909 *result = seqno;
910 return 0;
911 }
912
913 static bool
914 gen6_ring_get_irq(struct intel_ring_buffer *ring)
915 {
916 struct drm_device *dev = ring->dev;
917 drm_i915_private_t *dev_priv = dev->dev_private;
918 unsigned long flags;
919
920 if (!dev->irq_enabled)
921 return false;
922
923 /* It looks like we need to prevent the gt from suspending while waiting
924 * for an notifiy irq, otherwise irqs seem to get lost on at least the
925 * blt/bsd rings on ivb. */
926 gen6_gt_force_wake_get(dev_priv);
927
928 spin_lock_irqsave(&dev_priv->irq_lock, flags);
929 if (ring->irq_refcount++ == 0) {
930 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
931 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
932 GEN6_RENDER_L3_PARITY_ERROR));
933 else
934 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
935 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
936 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
937 POSTING_READ(GTIMR);
938 }
939 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
940
941 return true;
942 }
943
944 static void
945 gen6_ring_put_irq(struct intel_ring_buffer *ring)
946 {
947 struct drm_device *dev = ring->dev;
948 drm_i915_private_t *dev_priv = dev->dev_private;
949 unsigned long flags;
950
951 spin_lock_irqsave(&dev_priv->irq_lock, flags);
952 if (--ring->irq_refcount == 0) {
953 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
954 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
955 else
956 I915_WRITE_IMR(ring, ~0);
957 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
958 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
959 POSTING_READ(GTIMR);
960 }
961 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
962
963 gen6_gt_force_wake_put(dev_priv);
964 }
965
966 static int
967 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
968 u32 offset, u32 length,
969 unsigned flags)
970 {
971 int ret;
972
973 ret = intel_ring_begin(ring, 2);
974 if (ret)
975 return ret;
976
977 intel_ring_emit(ring,
978 MI_BATCH_BUFFER_START |
979 MI_BATCH_GTT |
980 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
981 intel_ring_emit(ring, offset);
982 intel_ring_advance(ring);
983
984 return 0;
985 }
986
987 static int
988 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
989 u32 offset, u32 len,
990 unsigned flags)
991 {
992 int ret;
993
994 ret = intel_ring_begin(ring, 4);
995 if (ret)
996 return ret;
997
998 intel_ring_emit(ring, MI_BATCH_BUFFER);
999 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1000 intel_ring_emit(ring, offset + len - 8);
1001 intel_ring_emit(ring, 0);
1002 intel_ring_advance(ring);
1003
1004 return 0;
1005 }
1006
1007 static int
1008 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1009 u32 offset, u32 len,
1010 unsigned flags)
1011 {
1012 int ret;
1013
1014 ret = intel_ring_begin(ring, 2);
1015 if (ret)
1016 return ret;
1017
1018 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1019 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1020 intel_ring_advance(ring);
1021
1022 return 0;
1023 }
1024
1025 static void cleanup_status_page(struct intel_ring_buffer *ring)
1026 {
1027 struct drm_i915_gem_object *obj;
1028
1029 obj = ring->status_page.obj;
1030 if (obj == NULL)
1031 return;
1032
1033 kunmap(sg_page(obj->pages->sgl));
1034 i915_gem_object_unpin(obj);
1035 drm_gem_object_unreference(&obj->base);
1036 ring->status_page.obj = NULL;
1037 }
1038
1039 static int init_status_page(struct intel_ring_buffer *ring)
1040 {
1041 struct drm_device *dev = ring->dev;
1042 struct drm_i915_gem_object *obj;
1043 int ret;
1044
1045 obj = i915_gem_alloc_object(dev, 4096);
1046 if (obj == NULL) {
1047 DRM_ERROR("Failed to allocate status page\n");
1048 ret = -ENOMEM;
1049 goto err;
1050 }
1051
1052 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1053
1054 ret = i915_gem_object_pin(obj, 4096, true, false);
1055 if (ret != 0) {
1056 goto err_unref;
1057 }
1058
1059 ring->status_page.gfx_addr = obj->gtt_offset;
1060 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1061 if (ring->status_page.page_addr == NULL) {
1062 ret = -ENOMEM;
1063 goto err_unpin;
1064 }
1065 ring->status_page.obj = obj;
1066 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1067
1068 intel_ring_setup_status_page(ring);
1069 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1070 ring->name, ring->status_page.gfx_addr);
1071
1072 return 0;
1073
1074 err_unpin:
1075 i915_gem_object_unpin(obj);
1076 err_unref:
1077 drm_gem_object_unreference(&obj->base);
1078 err:
1079 return ret;
1080 }
1081
1082 static int intel_init_ring_buffer(struct drm_device *dev,
1083 struct intel_ring_buffer *ring)
1084 {
1085 struct drm_i915_gem_object *obj;
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1087 int ret;
1088
1089 ring->dev = dev;
1090 INIT_LIST_HEAD(&ring->active_list);
1091 INIT_LIST_HEAD(&ring->request_list);
1092 ring->size = 32 * PAGE_SIZE;
1093
1094 init_waitqueue_head(&ring->irq_queue);
1095
1096 if (I915_NEED_GFX_HWS(dev)) {
1097 ret = init_status_page(ring);
1098 if (ret)
1099 return ret;
1100 }
1101
1102 obj = i915_gem_alloc_object(dev, ring->size);
1103 if (obj == NULL) {
1104 DRM_ERROR("Failed to allocate ringbuffer\n");
1105 ret = -ENOMEM;
1106 goto err_hws;
1107 }
1108
1109 ring->obj = obj;
1110
1111 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1112 if (ret)
1113 goto err_unref;
1114
1115 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1116 if (ret)
1117 goto err_unpin;
1118
1119 ring->virtual_start =
1120 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1121 ring->size);
1122 if (ring->virtual_start == NULL) {
1123 DRM_ERROR("Failed to map ringbuffer.\n");
1124 ret = -EINVAL;
1125 goto err_unpin;
1126 }
1127
1128 ret = ring->init(ring);
1129 if (ret)
1130 goto err_unmap;
1131
1132 /* Workaround an erratum on the i830 which causes a hang if
1133 * the TAIL pointer points to within the last 2 cachelines
1134 * of the buffer.
1135 */
1136 ring->effective_size = ring->size;
1137 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1138 ring->effective_size -= 128;
1139
1140 return 0;
1141
1142 err_unmap:
1143 iounmap(ring->virtual_start);
1144 err_unpin:
1145 i915_gem_object_unpin(obj);
1146 err_unref:
1147 drm_gem_object_unreference(&obj->base);
1148 ring->obj = NULL;
1149 err_hws:
1150 cleanup_status_page(ring);
1151 return ret;
1152 }
1153
1154 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1155 {
1156 struct drm_i915_private *dev_priv;
1157 int ret;
1158
1159 if (ring->obj == NULL)
1160 return;
1161
1162 /* Disable the ring buffer. The ring must be idle at this point */
1163 dev_priv = ring->dev->dev_private;
1164 ret = intel_wait_ring_idle(ring);
1165 if (ret)
1166 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1167 ring->name, ret);
1168
1169 I915_WRITE_CTL(ring, 0);
1170
1171 iounmap(ring->virtual_start);
1172
1173 i915_gem_object_unpin(ring->obj);
1174 drm_gem_object_unreference(&ring->obj->base);
1175 ring->obj = NULL;
1176
1177 if (ring->cleanup)
1178 ring->cleanup(ring);
1179
1180 cleanup_status_page(ring);
1181 }
1182
1183 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1184 {
1185 uint32_t __iomem *virt;
1186 int rem = ring->size - ring->tail;
1187
1188 if (ring->space < rem) {
1189 int ret = intel_wait_ring_buffer(ring, rem);
1190 if (ret)
1191 return ret;
1192 }
1193
1194 virt = ring->virtual_start + ring->tail;
1195 rem /= 4;
1196 while (rem--)
1197 iowrite32(MI_NOOP, virt++);
1198
1199 ring->tail = 0;
1200 ring->space = ring_space(ring);
1201
1202 return 0;
1203 }
1204
1205 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1206 {
1207 int ret;
1208
1209 ret = i915_wait_seqno(ring, seqno);
1210 if (!ret)
1211 i915_gem_retire_requests_ring(ring);
1212
1213 return ret;
1214 }
1215
1216 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1217 {
1218 struct drm_i915_gem_request *request;
1219 u32 seqno = 0;
1220 int ret;
1221
1222 i915_gem_retire_requests_ring(ring);
1223
1224 if (ring->last_retired_head != -1) {
1225 ring->head = ring->last_retired_head;
1226 ring->last_retired_head = -1;
1227 ring->space = ring_space(ring);
1228 if (ring->space >= n)
1229 return 0;
1230 }
1231
1232 list_for_each_entry(request, &ring->request_list, list) {
1233 int space;
1234
1235 if (request->tail == -1)
1236 continue;
1237
1238 space = request->tail - (ring->tail + 8);
1239 if (space < 0)
1240 space += ring->size;
1241 if (space >= n) {
1242 seqno = request->seqno;
1243 break;
1244 }
1245
1246 /* Consume this request in case we need more space than
1247 * is available and so need to prevent a race between
1248 * updating last_retired_head and direct reads of
1249 * I915_RING_HEAD. It also provides a nice sanity check.
1250 */
1251 request->tail = -1;
1252 }
1253
1254 if (seqno == 0)
1255 return -ENOSPC;
1256
1257 ret = intel_ring_wait_seqno(ring, seqno);
1258 if (ret)
1259 return ret;
1260
1261 if (WARN_ON(ring->last_retired_head == -1))
1262 return -ENOSPC;
1263
1264 ring->head = ring->last_retired_head;
1265 ring->last_retired_head = -1;
1266 ring->space = ring_space(ring);
1267 if (WARN_ON(ring->space < n))
1268 return -ENOSPC;
1269
1270 return 0;
1271 }
1272
1273 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1274 {
1275 struct drm_device *dev = ring->dev;
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 unsigned long end;
1278 int ret;
1279
1280 ret = intel_ring_wait_request(ring, n);
1281 if (ret != -ENOSPC)
1282 return ret;
1283
1284 trace_i915_ring_wait_begin(ring);
1285 /* With GEM the hangcheck timer should kick us out of the loop,
1286 * leaving it early runs the risk of corrupting GEM state (due
1287 * to running on almost untested codepaths). But on resume
1288 * timers don't work yet, so prevent a complete hang in that
1289 * case by choosing an insanely large timeout. */
1290 end = jiffies + 60 * HZ;
1291
1292 do {
1293 ring->head = I915_READ_HEAD(ring);
1294 ring->space = ring_space(ring);
1295 if (ring->space >= n) {
1296 trace_i915_ring_wait_end(ring);
1297 return 0;
1298 }
1299
1300 if (dev->primary->master) {
1301 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1302 if (master_priv->sarea_priv)
1303 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1304 }
1305
1306 msleep(1);
1307
1308 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1309 if (ret)
1310 return ret;
1311 } while (!time_after(jiffies, end));
1312 trace_i915_ring_wait_end(ring);
1313 return -EBUSY;
1314 }
1315
1316 int intel_ring_begin(struct intel_ring_buffer *ring,
1317 int num_dwords)
1318 {
1319 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1320 int n = 4*num_dwords;
1321 int ret;
1322
1323 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1324 if (ret)
1325 return ret;
1326
1327 if (unlikely(ring->tail + n > ring->effective_size)) {
1328 ret = intel_wrap_ring_buffer(ring);
1329 if (unlikely(ret))
1330 return ret;
1331 }
1332
1333 if (unlikely(ring->space < n)) {
1334 ret = intel_wait_ring_buffer(ring, n);
1335 if (unlikely(ret))
1336 return ret;
1337 }
1338
1339 ring->space -= n;
1340 return 0;
1341 }
1342
1343 void intel_ring_advance(struct intel_ring_buffer *ring)
1344 {
1345 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1346
1347 ring->tail &= ring->size - 1;
1348 if (dev_priv->stop_rings & intel_ring_flag(ring))
1349 return;
1350 ring->write_tail(ring, ring->tail);
1351 }
1352
1353
1354 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1355 u32 value)
1356 {
1357 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1358
1359 /* Every tail move must follow the sequence below */
1360
1361 /* Disable notification that the ring is IDLE. The GT
1362 * will then assume that it is busy and bring it out of rc6.
1363 */
1364 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1365 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1366
1367 /* Clear the context id. Here be magic! */
1368 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1369
1370 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1371 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1372 GEN6_BSD_SLEEP_INDICATOR) == 0,
1373 50))
1374 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1375
1376 /* Now that the ring is fully powered up, update the tail */
1377 I915_WRITE_TAIL(ring, value);
1378 POSTING_READ(RING_TAIL(ring->mmio_base));
1379
1380 /* Let the ring send IDLE messages to the GT again,
1381 * and so let it sleep to conserve power when idle.
1382 */
1383 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1384 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1385 }
1386
1387 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1388 u32 invalidate, u32 flush)
1389 {
1390 uint32_t cmd;
1391 int ret;
1392
1393 ret = intel_ring_begin(ring, 4);
1394 if (ret)
1395 return ret;
1396
1397 cmd = MI_FLUSH_DW;
1398 /*
1399 * Bspec vol 1c.5 - video engine command streamer:
1400 * "If ENABLED, all TLBs will be invalidated once the flush
1401 * operation is complete. This bit is only valid when the
1402 * Post-Sync Operation field is a value of 1h or 3h."
1403 */
1404 if (invalidate & I915_GEM_GPU_DOMAINS)
1405 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1406 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1407 intel_ring_emit(ring, cmd);
1408 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1409 intel_ring_emit(ring, 0);
1410 intel_ring_emit(ring, MI_NOOP);
1411 intel_ring_advance(ring);
1412 return 0;
1413 }
1414
1415 static int
1416 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1417 u32 offset, u32 len,
1418 unsigned flags)
1419 {
1420 int ret;
1421
1422 ret = intel_ring_begin(ring, 2);
1423 if (ret)
1424 return ret;
1425
1426 intel_ring_emit(ring,
1427 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1428 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1429 /* bit0-7 is the length on GEN6+ */
1430 intel_ring_emit(ring, offset);
1431 intel_ring_advance(ring);
1432
1433 return 0;
1434 }
1435
1436 static int
1437 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1438 u32 offset, u32 len,
1439 unsigned flags)
1440 {
1441 int ret;
1442
1443 ret = intel_ring_begin(ring, 2);
1444 if (ret)
1445 return ret;
1446
1447 intel_ring_emit(ring,
1448 MI_BATCH_BUFFER_START |
1449 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1450 /* bit0-7 is the length on GEN6+ */
1451 intel_ring_emit(ring, offset);
1452 intel_ring_advance(ring);
1453
1454 return 0;
1455 }
1456
1457 /* Blitter support (SandyBridge+) */
1458
1459 static int blt_ring_flush(struct intel_ring_buffer *ring,
1460 u32 invalidate, u32 flush)
1461 {
1462 uint32_t cmd;
1463 int ret;
1464
1465 ret = intel_ring_begin(ring, 4);
1466 if (ret)
1467 return ret;
1468
1469 cmd = MI_FLUSH_DW;
1470 /*
1471 * Bspec vol 1c.3 - blitter engine command streamer:
1472 * "If ENABLED, all TLBs will be invalidated once the flush
1473 * operation is complete. This bit is only valid when the
1474 * Post-Sync Operation field is a value of 1h or 3h."
1475 */
1476 if (invalidate & I915_GEM_DOMAIN_RENDER)
1477 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1478 MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_OP_STOREDW;
1479 intel_ring_emit(ring, cmd);
1480 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1481 intel_ring_emit(ring, 0);
1482 intel_ring_emit(ring, MI_NOOP);
1483 intel_ring_advance(ring);
1484 return 0;
1485 }
1486
1487 int intel_init_render_ring_buffer(struct drm_device *dev)
1488 {
1489 drm_i915_private_t *dev_priv = dev->dev_private;
1490 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1491
1492 ring->name = "render ring";
1493 ring->id = RCS;
1494 ring->mmio_base = RENDER_RING_BASE;
1495
1496 if (INTEL_INFO(dev)->gen >= 6) {
1497 ring->add_request = gen6_add_request;
1498 ring->flush = gen7_render_ring_flush;
1499 if (INTEL_INFO(dev)->gen == 6)
1500 ring->flush = gen6_render_ring_flush;
1501 ring->irq_get = gen6_ring_get_irq;
1502 ring->irq_put = gen6_ring_put_irq;
1503 ring->irq_enable_mask = GT_USER_INTERRUPT;
1504 ring->get_seqno = gen6_ring_get_seqno;
1505 ring->sync_to = gen6_ring_sync;
1506 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1507 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1508 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1509 ring->signal_mbox[0] = GEN6_VRSYNC;
1510 ring->signal_mbox[1] = GEN6_BRSYNC;
1511 } else if (IS_GEN5(dev)) {
1512 ring->add_request = pc_render_add_request;
1513 ring->flush = gen4_render_ring_flush;
1514 ring->get_seqno = pc_render_get_seqno;
1515 ring->irq_get = gen5_ring_get_irq;
1516 ring->irq_put = gen5_ring_put_irq;
1517 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1518 } else {
1519 ring->add_request = i9xx_add_request;
1520 if (INTEL_INFO(dev)->gen < 4)
1521 ring->flush = gen2_render_ring_flush;
1522 else
1523 ring->flush = gen4_render_ring_flush;
1524 ring->get_seqno = ring_get_seqno;
1525 if (IS_GEN2(dev)) {
1526 ring->irq_get = i8xx_ring_get_irq;
1527 ring->irq_put = i8xx_ring_put_irq;
1528 } else {
1529 ring->irq_get = i9xx_ring_get_irq;
1530 ring->irq_put = i9xx_ring_put_irq;
1531 }
1532 ring->irq_enable_mask = I915_USER_INTERRUPT;
1533 }
1534 ring->write_tail = ring_write_tail;
1535 if (IS_HASWELL(dev))
1536 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1537 else if (INTEL_INFO(dev)->gen >= 6)
1538 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1539 else if (INTEL_INFO(dev)->gen >= 4)
1540 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1541 else if (IS_I830(dev) || IS_845G(dev))
1542 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1543 else
1544 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1545 ring->init = init_render_ring;
1546 ring->cleanup = render_ring_cleanup;
1547
1548
1549 if (!I915_NEED_GFX_HWS(dev)) {
1550 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1551 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1552 }
1553
1554 return intel_init_ring_buffer(dev, ring);
1555 }
1556
1557 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1558 {
1559 drm_i915_private_t *dev_priv = dev->dev_private;
1560 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1561
1562 ring->name = "render ring";
1563 ring->id = RCS;
1564 ring->mmio_base = RENDER_RING_BASE;
1565
1566 if (INTEL_INFO(dev)->gen >= 6) {
1567 /* non-kms not supported on gen6+ */
1568 return -ENODEV;
1569 }
1570
1571 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1572 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1573 * the special gen5 functions. */
1574 ring->add_request = i9xx_add_request;
1575 if (INTEL_INFO(dev)->gen < 4)
1576 ring->flush = gen2_render_ring_flush;
1577 else
1578 ring->flush = gen4_render_ring_flush;
1579 ring->get_seqno = ring_get_seqno;
1580 if (IS_GEN2(dev)) {
1581 ring->irq_get = i8xx_ring_get_irq;
1582 ring->irq_put = i8xx_ring_put_irq;
1583 } else {
1584 ring->irq_get = i9xx_ring_get_irq;
1585 ring->irq_put = i9xx_ring_put_irq;
1586 }
1587 ring->irq_enable_mask = I915_USER_INTERRUPT;
1588 ring->write_tail = ring_write_tail;
1589 if (INTEL_INFO(dev)->gen >= 4)
1590 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1591 else if (IS_I830(dev) || IS_845G(dev))
1592 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1593 else
1594 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1595 ring->init = init_render_ring;
1596 ring->cleanup = render_ring_cleanup;
1597
1598 if (!I915_NEED_GFX_HWS(dev))
1599 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1600
1601 ring->dev = dev;
1602 INIT_LIST_HEAD(&ring->active_list);
1603 INIT_LIST_HEAD(&ring->request_list);
1604
1605 ring->size = size;
1606 ring->effective_size = ring->size;
1607 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1608 ring->effective_size -= 128;
1609
1610 ring->virtual_start = ioremap_wc(start, size);
1611 if (ring->virtual_start == NULL) {
1612 DRM_ERROR("can not ioremap virtual address for"
1613 " ring buffer\n");
1614 return -ENOMEM;
1615 }
1616
1617 return 0;
1618 }
1619
1620 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1621 {
1622 drm_i915_private_t *dev_priv = dev->dev_private;
1623 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1624
1625 ring->name = "bsd ring";
1626 ring->id = VCS;
1627
1628 ring->write_tail = ring_write_tail;
1629 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1630 ring->mmio_base = GEN6_BSD_RING_BASE;
1631 /* gen6 bsd needs a special wa for tail updates */
1632 if (IS_GEN6(dev))
1633 ring->write_tail = gen6_bsd_ring_write_tail;
1634 ring->flush = gen6_ring_flush;
1635 ring->add_request = gen6_add_request;
1636 ring->get_seqno = gen6_ring_get_seqno;
1637 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1638 ring->irq_get = gen6_ring_get_irq;
1639 ring->irq_put = gen6_ring_put_irq;
1640 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1641 ring->sync_to = gen6_ring_sync;
1642 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1643 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1644 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1645 ring->signal_mbox[0] = GEN6_RVSYNC;
1646 ring->signal_mbox[1] = GEN6_BVSYNC;
1647 } else {
1648 ring->mmio_base = BSD_RING_BASE;
1649 ring->flush = bsd_ring_flush;
1650 ring->add_request = i9xx_add_request;
1651 ring->get_seqno = ring_get_seqno;
1652 if (IS_GEN5(dev)) {
1653 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1654 ring->irq_get = gen5_ring_get_irq;
1655 ring->irq_put = gen5_ring_put_irq;
1656 } else {
1657 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1658 ring->irq_get = i9xx_ring_get_irq;
1659 ring->irq_put = i9xx_ring_put_irq;
1660 }
1661 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1662 }
1663 ring->init = init_ring_common;
1664
1665
1666 return intel_init_ring_buffer(dev, ring);
1667 }
1668
1669 int intel_init_blt_ring_buffer(struct drm_device *dev)
1670 {
1671 drm_i915_private_t *dev_priv = dev->dev_private;
1672 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1673
1674 ring->name = "blitter ring";
1675 ring->id = BCS;
1676
1677 ring->mmio_base = BLT_RING_BASE;
1678 ring->write_tail = ring_write_tail;
1679 ring->flush = blt_ring_flush;
1680 ring->add_request = gen6_add_request;
1681 ring->get_seqno = gen6_ring_get_seqno;
1682 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1683 ring->irq_get = gen6_ring_get_irq;
1684 ring->irq_put = gen6_ring_put_irq;
1685 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1686 ring->sync_to = gen6_ring_sync;
1687 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1688 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1689 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1690 ring->signal_mbox[0] = GEN6_RBSYNC;
1691 ring->signal_mbox[1] = GEN6_VBSYNC;
1692 ring->init = init_ring_common;
1693
1694 return intel_init_ring_buffer(dev, ring);
1695 }
1696
1697 int
1698 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1699 {
1700 int ret;
1701
1702 if (!ring->gpu_caches_dirty)
1703 return 0;
1704
1705 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1706 if (ret)
1707 return ret;
1708
1709 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1710
1711 ring->gpu_caches_dirty = false;
1712 return 0;
1713 }
1714
1715 int
1716 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1717 {
1718 uint32_t flush_domains;
1719 int ret;
1720
1721 flush_domains = 0;
1722 if (ring->gpu_caches_dirty)
1723 flush_domains = I915_GEM_GPU_DOMAINS;
1724
1725 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1726 if (ret)
1727 return ret;
1728
1729 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1730
1731 ring->gpu_caches_dirty = false;
1732 return 0;
1733 }
Linux kernel - Deliverables
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