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drm/i915: release cursor when crtc is destroyed
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
286 {
287 u32 flags = 0;
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
290 int ret;
291
292 /*
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
295 *
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
299 */
300 flags |= PIPE_CONTROL_CS_STALL;
301
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
304 * impact.
305 */
306 if (flush_domains) {
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
309 }
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
317 /*
318 * TLB invalidate requires a post-sync write.
319 */
320 flags |= PIPE_CONTROL_QW_WRITE;
321 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
322
323 /* Workaround: we must issue a pipe_control with CS-stall bit
324 * set before a pipe_control command that has the state cache
325 * invalidate bit set. */
326 gen7_render_ring_cs_stall_wa(ring);
327 }
328
329 ret = intel_ring_begin(ring, 4);
330 if (ret)
331 return ret;
332
333 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
334 intel_ring_emit(ring, flags);
335 intel_ring_emit(ring, scratch_addr);
336 intel_ring_emit(ring, 0);
337 intel_ring_advance(ring);
338
339 return 0;
340 }
341
342 static void ring_write_tail(struct intel_ring_buffer *ring,
343 u32 value)
344 {
345 drm_i915_private_t *dev_priv = ring->dev->dev_private;
346 I915_WRITE_TAIL(ring, value);
347 }
348
349 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
350 {
351 drm_i915_private_t *dev_priv = ring->dev->dev_private;
352 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
353 RING_ACTHD(ring->mmio_base) : ACTHD;
354
355 return I915_READ(acthd_reg);
356 }
357
358 static int init_ring_common(struct intel_ring_buffer *ring)
359 {
360 struct drm_device *dev = ring->dev;
361 drm_i915_private_t *dev_priv = dev->dev_private;
362 struct drm_i915_gem_object *obj = ring->obj;
363 int ret = 0;
364 u32 head;
365
366 if (HAS_FORCE_WAKE(dev))
367 gen6_gt_force_wake_get(dev_priv);
368
369 /* Stop the ring if it's running. */
370 I915_WRITE_CTL(ring, 0);
371 I915_WRITE_HEAD(ring, 0);
372 ring->write_tail(ring, 0);
373
374 head = I915_READ_HEAD(ring) & HEAD_ADDR;
375
376 /* G45 ring initialization fails to reset head to zero */
377 if (head != 0) {
378 DRM_DEBUG_KMS("%s head not reset to zero "
379 "ctl %08x head %08x tail %08x start %08x\n",
380 ring->name,
381 I915_READ_CTL(ring),
382 I915_READ_HEAD(ring),
383 I915_READ_TAIL(ring),
384 I915_READ_START(ring));
385
386 I915_WRITE_HEAD(ring, 0);
387
388 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
389 DRM_ERROR("failed to set %s head to zero "
390 "ctl %08x head %08x tail %08x start %08x\n",
391 ring->name,
392 I915_READ_CTL(ring),
393 I915_READ_HEAD(ring),
394 I915_READ_TAIL(ring),
395 I915_READ_START(ring));
396 }
397 }
398
399 /* Initialize the ring. This must happen _after_ we've cleared the ring
400 * registers with the above sequence (the readback of the HEAD registers
401 * also enforces ordering), otherwise the hw might lose the new ring
402 * register values. */
403 I915_WRITE_START(ring, obj->gtt_offset);
404 I915_WRITE_CTL(ring,
405 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
406 | RING_VALID);
407
408 /* If the head is still not zero, the ring is dead */
409 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
410 I915_READ_START(ring) == obj->gtt_offset &&
411 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
412 DRM_ERROR("%s initialization failed "
413 "ctl %08x head %08x tail %08x start %08x\n",
414 ring->name,
415 I915_READ_CTL(ring),
416 I915_READ_HEAD(ring),
417 I915_READ_TAIL(ring),
418 I915_READ_START(ring));
419 ret = -EIO;
420 goto out;
421 }
422
423 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
424 i915_kernel_lost_context(ring->dev);
425 else {
426 ring->head = I915_READ_HEAD(ring);
427 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
428 ring->space = ring_space(ring);
429 ring->last_retired_head = -1;
430 }
431
432 out:
433 if (HAS_FORCE_WAKE(dev))
434 gen6_gt_force_wake_put(dev_priv);
435
436 return ret;
437 }
438
439 static int
440 init_pipe_control(struct intel_ring_buffer *ring)
441 {
442 struct pipe_control *pc;
443 struct drm_i915_gem_object *obj;
444 int ret;
445
446 if (ring->private)
447 return 0;
448
449 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
450 if (!pc)
451 return -ENOMEM;
452
453 obj = i915_gem_alloc_object(ring->dev, 4096);
454 if (obj == NULL) {
455 DRM_ERROR("Failed to allocate seqno page\n");
456 ret = -ENOMEM;
457 goto err;
458 }
459
460 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
461
462 ret = i915_gem_object_pin(obj, 4096, true, false);
463 if (ret)
464 goto err_unref;
465
466 pc->gtt_offset = obj->gtt_offset;
467 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
468 if (pc->cpu_page == NULL) {
469 ret = -ENOMEM;
470 goto err_unpin;
471 }
472
473 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
474 ring->name, pc->gtt_offset);
475
476 pc->obj = obj;
477 ring->private = pc;
478 return 0;
479
480 err_unpin:
481 i915_gem_object_unpin(obj);
482 err_unref:
483 drm_gem_object_unreference(&obj->base);
484 err:
485 kfree(pc);
486 return ret;
487 }
488
489 static void
490 cleanup_pipe_control(struct intel_ring_buffer *ring)
491 {
492 struct pipe_control *pc = ring->private;
493 struct drm_i915_gem_object *obj;
494
495 if (!ring->private)
496 return;
497
498 obj = pc->obj;
499
500 kunmap(sg_page(obj->pages->sgl));
501 i915_gem_object_unpin(obj);
502 drm_gem_object_unreference(&obj->base);
503
504 kfree(pc);
505 ring->private = NULL;
506 }
507
508 static int init_render_ring(struct intel_ring_buffer *ring)
509 {
510 struct drm_device *dev = ring->dev;
511 struct drm_i915_private *dev_priv = dev->dev_private;
512 int ret = init_ring_common(ring);
513
514 if (INTEL_INFO(dev)->gen > 3)
515 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
516
517 /* We need to disable the AsyncFlip performance optimisations in order
518 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
519 * programmed to '1' on all products.
520 *
521 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
522 */
523 if (INTEL_INFO(dev)->gen >= 6)
524 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
525
526 /* Required for the hardware to program scanline values for waiting */
527 if (INTEL_INFO(dev)->gen == 6)
528 I915_WRITE(GFX_MODE,
529 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
530
531 if (IS_GEN7(dev))
532 I915_WRITE(GFX_MODE_GEN7,
533 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
534 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
535
536 if (INTEL_INFO(dev)->gen >= 5) {
537 ret = init_pipe_control(ring);
538 if (ret)
539 return ret;
540 }
541
542 if (IS_GEN6(dev)) {
543 /* From the Sandybridge PRM, volume 1 part 3, page 24:
544 * "If this bit is set, STCunit will have LRA as replacement
545 * policy. [...] This bit must be reset. LRA replacement
546 * policy is not supported."
547 */
548 I915_WRITE(CACHE_MODE_0,
549 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
550
551 /* This is not explicitly set for GEN6, so read the register.
552 * see intel_ring_mi_set_context() for why we care.
553 * TODO: consider explicitly setting the bit for GEN5
554 */
555 ring->itlb_before_ctx_switch =
556 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
557 }
558
559 if (INTEL_INFO(dev)->gen >= 6)
560 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
561
562 if (HAS_L3_GPU_CACHE(dev))
563 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
564
565 return ret;
566 }
567
568 static void render_ring_cleanup(struct intel_ring_buffer *ring)
569 {
570 struct drm_device *dev = ring->dev;
571
572 if (!ring->private)
573 return;
574
575 if (HAS_BROKEN_CS_TLB(dev))
576 drm_gem_object_unreference(to_gem_object(ring->private));
577
578 cleanup_pipe_control(ring);
579 }
580
581 static void
582 update_mboxes(struct intel_ring_buffer *ring,
583 u32 mmio_offset)
584 {
585 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
586 intel_ring_emit(ring, mmio_offset);
587 intel_ring_emit(ring, ring->outstanding_lazy_request);
588 }
589
590 /**
591 * gen6_add_request - Update the semaphore mailbox registers
592 *
593 * @ring - ring that is adding a request
594 * @seqno - return seqno stuck into the ring
595 *
596 * Update the mailbox registers in the *other* rings with the current seqno.
597 * This acts like a signal in the canonical semaphore.
598 */
599 static int
600 gen6_add_request(struct intel_ring_buffer *ring)
601 {
602 u32 mbox1_reg;
603 u32 mbox2_reg;
604 int ret;
605
606 ret = intel_ring_begin(ring, 10);
607 if (ret)
608 return ret;
609
610 mbox1_reg = ring->signal_mbox[0];
611 mbox2_reg = ring->signal_mbox[1];
612
613 update_mboxes(ring, mbox1_reg);
614 update_mboxes(ring, mbox2_reg);
615 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
616 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
617 intel_ring_emit(ring, ring->outstanding_lazy_request);
618 intel_ring_emit(ring, MI_USER_INTERRUPT);
619 intel_ring_advance(ring);
620
621 return 0;
622 }
623
624 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
625 u32 seqno)
626 {
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 return dev_priv->last_seqno < seqno;
629 }
630
631 /**
632 * intel_ring_sync - sync the waiter to the signaller on seqno
633 *
634 * @waiter - ring that is waiting
635 * @signaller - ring which has, or will signal
636 * @seqno - seqno which the waiter will block on
637 */
638 static int
639 gen6_ring_sync(struct intel_ring_buffer *waiter,
640 struct intel_ring_buffer *signaller,
641 u32 seqno)
642 {
643 int ret;
644 u32 dw1 = MI_SEMAPHORE_MBOX |
645 MI_SEMAPHORE_COMPARE |
646 MI_SEMAPHORE_REGISTER;
647
648 /* Throughout all of the GEM code, seqno passed implies our current
649 * seqno is >= the last seqno executed. However for hardware the
650 * comparison is strictly greater than.
651 */
652 seqno -= 1;
653
654 WARN_ON(signaller->semaphore_register[waiter->id] ==
655 MI_SEMAPHORE_SYNC_INVALID);
656
657 ret = intel_ring_begin(waiter, 4);
658 if (ret)
659 return ret;
660
661 /* If seqno wrap happened, omit the wait with no-ops */
662 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
663 intel_ring_emit(waiter,
664 dw1 |
665 signaller->semaphore_register[waiter->id]);
666 intel_ring_emit(waiter, seqno);
667 intel_ring_emit(waiter, 0);
668 intel_ring_emit(waiter, MI_NOOP);
669 } else {
670 intel_ring_emit(waiter, MI_NOOP);
671 intel_ring_emit(waiter, MI_NOOP);
672 intel_ring_emit(waiter, MI_NOOP);
673 intel_ring_emit(waiter, MI_NOOP);
674 }
675 intel_ring_advance(waiter);
676
677 return 0;
678 }
679
680 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
681 do { \
682 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
683 PIPE_CONTROL_DEPTH_STALL); \
684 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
685 intel_ring_emit(ring__, 0); \
686 intel_ring_emit(ring__, 0); \
687 } while (0)
688
689 static int
690 pc_render_add_request(struct intel_ring_buffer *ring)
691 {
692 struct pipe_control *pc = ring->private;
693 u32 scratch_addr = pc->gtt_offset + 128;
694 int ret;
695
696 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
697 * incoherent with writes to memory, i.e. completely fubar,
698 * so we need to use PIPE_NOTIFY instead.
699 *
700 * However, we also need to workaround the qword write
701 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
702 * memory before requesting an interrupt.
703 */
704 ret = intel_ring_begin(ring, 32);
705 if (ret)
706 return ret;
707
708 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
709 PIPE_CONTROL_WRITE_FLUSH |
710 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
711 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
712 intel_ring_emit(ring, ring->outstanding_lazy_request);
713 intel_ring_emit(ring, 0);
714 PIPE_CONTROL_FLUSH(ring, scratch_addr);
715 scratch_addr += 128; /* write to separate cachelines */
716 PIPE_CONTROL_FLUSH(ring, scratch_addr);
717 scratch_addr += 128;
718 PIPE_CONTROL_FLUSH(ring, scratch_addr);
719 scratch_addr += 128;
720 PIPE_CONTROL_FLUSH(ring, scratch_addr);
721 scratch_addr += 128;
722 PIPE_CONTROL_FLUSH(ring, scratch_addr);
723 scratch_addr += 128;
724 PIPE_CONTROL_FLUSH(ring, scratch_addr);
725
726 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
727 PIPE_CONTROL_WRITE_FLUSH |
728 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
729 PIPE_CONTROL_NOTIFY);
730 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
731 intel_ring_emit(ring, ring->outstanding_lazy_request);
732 intel_ring_emit(ring, 0);
733 intel_ring_advance(ring);
734
735 return 0;
736 }
737
738 static u32
739 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
740 {
741 /* Workaround to force correct ordering between irq and seqno writes on
742 * ivb (and maybe also on snb) by reading from a CS register (like
743 * ACTHD) before reading the status page. */
744 if (!lazy_coherency)
745 intel_ring_get_active_head(ring);
746 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
747 }
748
749 static u32
750 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
751 {
752 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
753 }
754
755 static void
756 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
757 {
758 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
759 }
760
761 static u32
762 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
763 {
764 struct pipe_control *pc = ring->private;
765 return pc->cpu_page[0];
766 }
767
768 static void
769 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
770 {
771 struct pipe_control *pc = ring->private;
772 pc->cpu_page[0] = seqno;
773 }
774
775 static bool
776 gen5_ring_get_irq(struct intel_ring_buffer *ring)
777 {
778 struct drm_device *dev = ring->dev;
779 drm_i915_private_t *dev_priv = dev->dev_private;
780 unsigned long flags;
781
782 if (!dev->irq_enabled)
783 return false;
784
785 spin_lock_irqsave(&dev_priv->irq_lock, flags);
786 if (ring->irq_refcount++ == 0) {
787 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
788 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
789 POSTING_READ(GTIMR);
790 }
791 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
792
793 return true;
794 }
795
796 static void
797 gen5_ring_put_irq(struct intel_ring_buffer *ring)
798 {
799 struct drm_device *dev = ring->dev;
800 drm_i915_private_t *dev_priv = dev->dev_private;
801 unsigned long flags;
802
803 spin_lock_irqsave(&dev_priv->irq_lock, flags);
804 if (--ring->irq_refcount == 0) {
805 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
806 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
807 POSTING_READ(GTIMR);
808 }
809 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
810 }
811
812 static bool
813 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
814 {
815 struct drm_device *dev = ring->dev;
816 drm_i915_private_t *dev_priv = dev->dev_private;
817 unsigned long flags;
818
819 if (!dev->irq_enabled)
820 return false;
821
822 spin_lock_irqsave(&dev_priv->irq_lock, flags);
823 if (ring->irq_refcount++ == 0) {
824 dev_priv->irq_mask &= ~ring->irq_enable_mask;
825 I915_WRITE(IMR, dev_priv->irq_mask);
826 POSTING_READ(IMR);
827 }
828 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
829
830 return true;
831 }
832
833 static void
834 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
835 {
836 struct drm_device *dev = ring->dev;
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 unsigned long flags;
839
840 spin_lock_irqsave(&dev_priv->irq_lock, flags);
841 if (--ring->irq_refcount == 0) {
842 dev_priv->irq_mask |= ring->irq_enable_mask;
843 I915_WRITE(IMR, dev_priv->irq_mask);
844 POSTING_READ(IMR);
845 }
846 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
847 }
848
849 static bool
850 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
851 {
852 struct drm_device *dev = ring->dev;
853 drm_i915_private_t *dev_priv = dev->dev_private;
854 unsigned long flags;
855
856 if (!dev->irq_enabled)
857 return false;
858
859 spin_lock_irqsave(&dev_priv->irq_lock, flags);
860 if (ring->irq_refcount++ == 0) {
861 dev_priv->irq_mask &= ~ring->irq_enable_mask;
862 I915_WRITE16(IMR, dev_priv->irq_mask);
863 POSTING_READ16(IMR);
864 }
865 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
866
867 return true;
868 }
869
870 static void
871 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
872 {
873 struct drm_device *dev = ring->dev;
874 drm_i915_private_t *dev_priv = dev->dev_private;
875 unsigned long flags;
876
877 spin_lock_irqsave(&dev_priv->irq_lock, flags);
878 if (--ring->irq_refcount == 0) {
879 dev_priv->irq_mask |= ring->irq_enable_mask;
880 I915_WRITE16(IMR, dev_priv->irq_mask);
881 POSTING_READ16(IMR);
882 }
883 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
884 }
885
886 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
887 {
888 struct drm_device *dev = ring->dev;
889 drm_i915_private_t *dev_priv = ring->dev->dev_private;
890 u32 mmio = 0;
891
892 /* The ring status page addresses are no longer next to the rest of
893 * the ring registers as of gen7.
894 */
895 if (IS_GEN7(dev)) {
896 switch (ring->id) {
897 case RCS:
898 mmio = RENDER_HWS_PGA_GEN7;
899 break;
900 case BCS:
901 mmio = BLT_HWS_PGA_GEN7;
902 break;
903 case VCS:
904 mmio = BSD_HWS_PGA_GEN7;
905 break;
906 }
907 } else if (IS_GEN6(ring->dev)) {
908 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
909 } else {
910 mmio = RING_HWS_PGA(ring->mmio_base);
911 }
912
913 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
914 POSTING_READ(mmio);
915 }
916
917 static int
918 bsd_ring_flush(struct intel_ring_buffer *ring,
919 u32 invalidate_domains,
920 u32 flush_domains)
921 {
922 int ret;
923
924 ret = intel_ring_begin(ring, 2);
925 if (ret)
926 return ret;
927
928 intel_ring_emit(ring, MI_FLUSH);
929 intel_ring_emit(ring, MI_NOOP);
930 intel_ring_advance(ring);
931 return 0;
932 }
933
934 static int
935 i9xx_add_request(struct intel_ring_buffer *ring)
936 {
937 int ret;
938
939 ret = intel_ring_begin(ring, 4);
940 if (ret)
941 return ret;
942
943 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
944 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
945 intel_ring_emit(ring, ring->outstanding_lazy_request);
946 intel_ring_emit(ring, MI_USER_INTERRUPT);
947 intel_ring_advance(ring);
948
949 return 0;
950 }
951
952 static bool
953 gen6_ring_get_irq(struct intel_ring_buffer *ring)
954 {
955 struct drm_device *dev = ring->dev;
956 drm_i915_private_t *dev_priv = dev->dev_private;
957 unsigned long flags;
958
959 if (!dev->irq_enabled)
960 return false;
961
962 /* It looks like we need to prevent the gt from suspending while waiting
963 * for an notifiy irq, otherwise irqs seem to get lost on at least the
964 * blt/bsd rings on ivb. */
965 gen6_gt_force_wake_get(dev_priv);
966
967 spin_lock_irqsave(&dev_priv->irq_lock, flags);
968 if (ring->irq_refcount++ == 0) {
969 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
970 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
971 GEN6_RENDER_L3_PARITY_ERROR));
972 else
973 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
974 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
975 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
976 POSTING_READ(GTIMR);
977 }
978 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
979
980 return true;
981 }
982
983 static void
984 gen6_ring_put_irq(struct intel_ring_buffer *ring)
985 {
986 struct drm_device *dev = ring->dev;
987 drm_i915_private_t *dev_priv = dev->dev_private;
988 unsigned long flags;
989
990 spin_lock_irqsave(&dev_priv->irq_lock, flags);
991 if (--ring->irq_refcount == 0) {
992 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
993 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
994 else
995 I915_WRITE_IMR(ring, ~0);
996 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
997 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
998 POSTING_READ(GTIMR);
999 }
1000 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1001
1002 gen6_gt_force_wake_put(dev_priv);
1003 }
1004
1005 static int
1006 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1007 u32 offset, u32 length,
1008 unsigned flags)
1009 {
1010 int ret;
1011
1012 ret = intel_ring_begin(ring, 2);
1013 if (ret)
1014 return ret;
1015
1016 intel_ring_emit(ring,
1017 MI_BATCH_BUFFER_START |
1018 MI_BATCH_GTT |
1019 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1020 intel_ring_emit(ring, offset);
1021 intel_ring_advance(ring);
1022
1023 return 0;
1024 }
1025
1026 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1027 #define I830_BATCH_LIMIT (256*1024)
1028 static int
1029 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1030 u32 offset, u32 len,
1031 unsigned flags)
1032 {
1033 int ret;
1034
1035 if (flags & I915_DISPATCH_PINNED) {
1036 ret = intel_ring_begin(ring, 4);
1037 if (ret)
1038 return ret;
1039
1040 intel_ring_emit(ring, MI_BATCH_BUFFER);
1041 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1042 intel_ring_emit(ring, offset + len - 8);
1043 intel_ring_emit(ring, MI_NOOP);
1044 intel_ring_advance(ring);
1045 } else {
1046 struct drm_i915_gem_object *obj = ring->private;
1047 u32 cs_offset = obj->gtt_offset;
1048
1049 if (len > I830_BATCH_LIMIT)
1050 return -ENOSPC;
1051
1052 ret = intel_ring_begin(ring, 9+3);
1053 if (ret)
1054 return ret;
1055 /* Blit the batch (which has now all relocs applied) to the stable batch
1056 * scratch bo area (so that the CS never stumbles over its tlb
1057 * invalidation bug) ... */
1058 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1059 XY_SRC_COPY_BLT_WRITE_ALPHA |
1060 XY_SRC_COPY_BLT_WRITE_RGB);
1061 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1062 intel_ring_emit(ring, 0);
1063 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1064 intel_ring_emit(ring, cs_offset);
1065 intel_ring_emit(ring, 0);
1066 intel_ring_emit(ring, 4096);
1067 intel_ring_emit(ring, offset);
1068 intel_ring_emit(ring, MI_FLUSH);
1069
1070 /* ... and execute it. */
1071 intel_ring_emit(ring, MI_BATCH_BUFFER);
1072 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1073 intel_ring_emit(ring, cs_offset + len - 8);
1074 intel_ring_advance(ring);
1075 }
1076
1077 return 0;
1078 }
1079
1080 static int
1081 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1082 u32 offset, u32 len,
1083 unsigned flags)
1084 {
1085 int ret;
1086
1087 ret = intel_ring_begin(ring, 2);
1088 if (ret)
1089 return ret;
1090
1091 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1092 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1093 intel_ring_advance(ring);
1094
1095 return 0;
1096 }
1097
1098 static void cleanup_status_page(struct intel_ring_buffer *ring)
1099 {
1100 struct drm_i915_gem_object *obj;
1101
1102 obj = ring->status_page.obj;
1103 if (obj == NULL)
1104 return;
1105
1106 kunmap(sg_page(obj->pages->sgl));
1107 i915_gem_object_unpin(obj);
1108 drm_gem_object_unreference(&obj->base);
1109 ring->status_page.obj = NULL;
1110 }
1111
1112 static int init_status_page(struct intel_ring_buffer *ring)
1113 {
1114 struct drm_device *dev = ring->dev;
1115 struct drm_i915_gem_object *obj;
1116 int ret;
1117
1118 obj = i915_gem_alloc_object(dev, 4096);
1119 if (obj == NULL) {
1120 DRM_ERROR("Failed to allocate status page\n");
1121 ret = -ENOMEM;
1122 goto err;
1123 }
1124
1125 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1126
1127 ret = i915_gem_object_pin(obj, 4096, true, false);
1128 if (ret != 0) {
1129 goto err_unref;
1130 }
1131
1132 ring->status_page.gfx_addr = obj->gtt_offset;
1133 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1134 if (ring->status_page.page_addr == NULL) {
1135 ret = -ENOMEM;
1136 goto err_unpin;
1137 }
1138 ring->status_page.obj = obj;
1139 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1140
1141 intel_ring_setup_status_page(ring);
1142 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1143 ring->name, ring->status_page.gfx_addr);
1144
1145 return 0;
1146
1147 err_unpin:
1148 i915_gem_object_unpin(obj);
1149 err_unref:
1150 drm_gem_object_unreference(&obj->base);
1151 err:
1152 return ret;
1153 }
1154
1155 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1156 {
1157 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1158 u32 addr;
1159
1160 if (!dev_priv->status_page_dmah) {
1161 dev_priv->status_page_dmah =
1162 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1163 if (!dev_priv->status_page_dmah)
1164 return -ENOMEM;
1165 }
1166
1167 addr = dev_priv->status_page_dmah->busaddr;
1168 if (INTEL_INFO(ring->dev)->gen >= 4)
1169 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1170 I915_WRITE(HWS_PGA, addr);
1171
1172 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1173 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1174
1175 return 0;
1176 }
1177
1178 static int intel_init_ring_buffer(struct drm_device *dev,
1179 struct intel_ring_buffer *ring)
1180 {
1181 struct drm_i915_gem_object *obj;
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 int ret;
1184
1185 ring->dev = dev;
1186 INIT_LIST_HEAD(&ring->active_list);
1187 INIT_LIST_HEAD(&ring->request_list);
1188 ring->size = 32 * PAGE_SIZE;
1189 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1190
1191 init_waitqueue_head(&ring->irq_queue);
1192
1193 if (I915_NEED_GFX_HWS(dev)) {
1194 ret = init_status_page(ring);
1195 if (ret)
1196 return ret;
1197 } else {
1198 BUG_ON(ring->id != RCS);
1199 ret = init_phys_hws_pga(ring);
1200 if (ret)
1201 return ret;
1202 }
1203
1204 obj = NULL;
1205 if (!HAS_LLC(dev))
1206 obj = i915_gem_object_create_stolen(dev, ring->size);
1207 if (obj == NULL)
1208 obj = i915_gem_alloc_object(dev, ring->size);
1209 if (obj == NULL) {
1210 DRM_ERROR("Failed to allocate ringbuffer\n");
1211 ret = -ENOMEM;
1212 goto err_hws;
1213 }
1214
1215 ring->obj = obj;
1216
1217 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1218 if (ret)
1219 goto err_unref;
1220
1221 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1222 if (ret)
1223 goto err_unpin;
1224
1225 ring->virtual_start =
1226 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1227 ring->size);
1228 if (ring->virtual_start == NULL) {
1229 DRM_ERROR("Failed to map ringbuffer.\n");
1230 ret = -EINVAL;
1231 goto err_unpin;
1232 }
1233
1234 ret = ring->init(ring);
1235 if (ret)
1236 goto err_unmap;
1237
1238 /* Workaround an erratum on the i830 which causes a hang if
1239 * the TAIL pointer points to within the last 2 cachelines
1240 * of the buffer.
1241 */
1242 ring->effective_size = ring->size;
1243 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1244 ring->effective_size -= 128;
1245
1246 return 0;
1247
1248 err_unmap:
1249 iounmap(ring->virtual_start);
1250 err_unpin:
1251 i915_gem_object_unpin(obj);
1252 err_unref:
1253 drm_gem_object_unreference(&obj->base);
1254 ring->obj = NULL;
1255 err_hws:
1256 cleanup_status_page(ring);
1257 return ret;
1258 }
1259
1260 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1261 {
1262 struct drm_i915_private *dev_priv;
1263 int ret;
1264
1265 if (ring->obj == NULL)
1266 return;
1267
1268 /* Disable the ring buffer. The ring must be idle at this point */
1269 dev_priv = ring->dev->dev_private;
1270 ret = intel_ring_idle(ring);
1271 if (ret)
1272 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1273 ring->name, ret);
1274
1275 I915_WRITE_CTL(ring, 0);
1276
1277 iounmap(ring->virtual_start);
1278
1279 i915_gem_object_unpin(ring->obj);
1280 drm_gem_object_unreference(&ring->obj->base);
1281 ring->obj = NULL;
1282
1283 if (ring->cleanup)
1284 ring->cleanup(ring);
1285
1286 cleanup_status_page(ring);
1287 }
1288
1289 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1290 {
1291 int ret;
1292
1293 ret = i915_wait_seqno(ring, seqno);
1294 if (!ret)
1295 i915_gem_retire_requests_ring(ring);
1296
1297 return ret;
1298 }
1299
1300 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1301 {
1302 struct drm_i915_gem_request *request;
1303 u32 seqno = 0;
1304 int ret;
1305
1306 i915_gem_retire_requests_ring(ring);
1307
1308 if (ring->last_retired_head != -1) {
1309 ring->head = ring->last_retired_head;
1310 ring->last_retired_head = -1;
1311 ring->space = ring_space(ring);
1312 if (ring->space >= n)
1313 return 0;
1314 }
1315
1316 list_for_each_entry(request, &ring->request_list, list) {
1317 int space;
1318
1319 if (request->tail == -1)
1320 continue;
1321
1322 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1323 if (space < 0)
1324 space += ring->size;
1325 if (space >= n) {
1326 seqno = request->seqno;
1327 break;
1328 }
1329
1330 /* Consume this request in case we need more space than
1331 * is available and so need to prevent a race between
1332 * updating last_retired_head and direct reads of
1333 * I915_RING_HEAD. It also provides a nice sanity check.
1334 */
1335 request->tail = -1;
1336 }
1337
1338 if (seqno == 0)
1339 return -ENOSPC;
1340
1341 ret = intel_ring_wait_seqno(ring, seqno);
1342 if (ret)
1343 return ret;
1344
1345 if (WARN_ON(ring->last_retired_head == -1))
1346 return -ENOSPC;
1347
1348 ring->head = ring->last_retired_head;
1349 ring->last_retired_head = -1;
1350 ring->space = ring_space(ring);
1351 if (WARN_ON(ring->space < n))
1352 return -ENOSPC;
1353
1354 return 0;
1355 }
1356
1357 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1358 {
1359 struct drm_device *dev = ring->dev;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 unsigned long end;
1362 int ret;
1363
1364 ret = intel_ring_wait_request(ring, n);
1365 if (ret != -ENOSPC)
1366 return ret;
1367
1368 trace_i915_ring_wait_begin(ring);
1369 /* With GEM the hangcheck timer should kick us out of the loop,
1370 * leaving it early runs the risk of corrupting GEM state (due
1371 * to running on almost untested codepaths). But on resume
1372 * timers don't work yet, so prevent a complete hang in that
1373 * case by choosing an insanely large timeout. */
1374 end = jiffies + 60 * HZ;
1375
1376 do {
1377 ring->head = I915_READ_HEAD(ring);
1378 ring->space = ring_space(ring);
1379 if (ring->space >= n) {
1380 trace_i915_ring_wait_end(ring);
1381 return 0;
1382 }
1383
1384 if (dev->primary->master) {
1385 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1386 if (master_priv->sarea_priv)
1387 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1388 }
1389
1390 msleep(1);
1391
1392 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1393 dev_priv->mm.interruptible);
1394 if (ret)
1395 return ret;
1396 } while (!time_after(jiffies, end));
1397 trace_i915_ring_wait_end(ring);
1398 return -EBUSY;
1399 }
1400
1401 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1402 {
1403 uint32_t __iomem *virt;
1404 int rem = ring->size - ring->tail;
1405
1406 if (ring->space < rem) {
1407 int ret = ring_wait_for_space(ring, rem);
1408 if (ret)
1409 return ret;
1410 }
1411
1412 virt = ring->virtual_start + ring->tail;
1413 rem /= 4;
1414 while (rem--)
1415 iowrite32(MI_NOOP, virt++);
1416
1417 ring->tail = 0;
1418 ring->space = ring_space(ring);
1419
1420 return 0;
1421 }
1422
1423 int intel_ring_idle(struct intel_ring_buffer *ring)
1424 {
1425 u32 seqno;
1426 int ret;
1427
1428 /* We need to add any requests required to flush the objects and ring */
1429 if (ring->outstanding_lazy_request) {
1430 ret = i915_add_request(ring, NULL, NULL);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 /* Wait upon the last request to be completed */
1436 if (list_empty(&ring->request_list))
1437 return 0;
1438
1439 seqno = list_entry(ring->request_list.prev,
1440 struct drm_i915_gem_request,
1441 list)->seqno;
1442
1443 return i915_wait_seqno(ring, seqno);
1444 }
1445
1446 static int
1447 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1448 {
1449 if (ring->outstanding_lazy_request)
1450 return 0;
1451
1452 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1453 }
1454
1455 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1456 int bytes)
1457 {
1458 int ret;
1459
1460 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1461 ret = intel_wrap_ring_buffer(ring);
1462 if (unlikely(ret))
1463 return ret;
1464 }
1465
1466 if (unlikely(ring->space < bytes)) {
1467 ret = ring_wait_for_space(ring, bytes);
1468 if (unlikely(ret))
1469 return ret;
1470 }
1471
1472 ring->space -= bytes;
1473 return 0;
1474 }
1475
1476 int intel_ring_begin(struct intel_ring_buffer *ring,
1477 int num_dwords)
1478 {
1479 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1480 int ret;
1481
1482 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1483 dev_priv->mm.interruptible);
1484 if (ret)
1485 return ret;
1486
1487 /* Preallocate the olr before touching the ring */
1488 ret = intel_ring_alloc_seqno(ring);
1489 if (ret)
1490 return ret;
1491
1492 return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1493 }
1494
1495 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1496 {
1497 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1498
1499 BUG_ON(ring->outstanding_lazy_request);
1500
1501 if (INTEL_INFO(ring->dev)->gen >= 6) {
1502 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1503 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1504 }
1505
1506 ring->set_seqno(ring, seqno);
1507 ring->hangcheck.seqno = seqno;
1508 }
1509
1510 void intel_ring_advance(struct intel_ring_buffer *ring)
1511 {
1512 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1513
1514 ring->tail &= ring->size - 1;
1515 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1516 return;
1517 ring->write_tail(ring, ring->tail);
1518 }
1519
1520
1521 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1522 u32 value)
1523 {
1524 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1525
1526 /* Every tail move must follow the sequence below */
1527
1528 /* Disable notification that the ring is IDLE. The GT
1529 * will then assume that it is busy and bring it out of rc6.
1530 */
1531 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1532 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1533
1534 /* Clear the context id. Here be magic! */
1535 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1536
1537 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1538 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1539 GEN6_BSD_SLEEP_INDICATOR) == 0,
1540 50))
1541 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1542
1543 /* Now that the ring is fully powered up, update the tail */
1544 I915_WRITE_TAIL(ring, value);
1545 POSTING_READ(RING_TAIL(ring->mmio_base));
1546
1547 /* Let the ring send IDLE messages to the GT again,
1548 * and so let it sleep to conserve power when idle.
1549 */
1550 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1551 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1552 }
1553
1554 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1555 u32 invalidate, u32 flush)
1556 {
1557 uint32_t cmd;
1558 int ret;
1559
1560 ret = intel_ring_begin(ring, 4);
1561 if (ret)
1562 return ret;
1563
1564 cmd = MI_FLUSH_DW;
1565 /*
1566 * Bspec vol 1c.5 - video engine command streamer:
1567 * "If ENABLED, all TLBs will be invalidated once the flush
1568 * operation is complete. This bit is only valid when the
1569 * Post-Sync Operation field is a value of 1h or 3h."
1570 */
1571 if (invalidate & I915_GEM_GPU_DOMAINS)
1572 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1573 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1574 intel_ring_emit(ring, cmd);
1575 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1576 intel_ring_emit(ring, 0);
1577 intel_ring_emit(ring, MI_NOOP);
1578 intel_ring_advance(ring);
1579 return 0;
1580 }
1581
1582 static int
1583 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1584 u32 offset, u32 len,
1585 unsigned flags)
1586 {
1587 int ret;
1588
1589 ret = intel_ring_begin(ring, 2);
1590 if (ret)
1591 return ret;
1592
1593 intel_ring_emit(ring,
1594 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1595 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1596 /* bit0-7 is the length on GEN6+ */
1597 intel_ring_emit(ring, offset);
1598 intel_ring_advance(ring);
1599
1600 return 0;
1601 }
1602
1603 static int
1604 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1605 u32 offset, u32 len,
1606 unsigned flags)
1607 {
1608 int ret;
1609
1610 ret = intel_ring_begin(ring, 2);
1611 if (ret)
1612 return ret;
1613
1614 intel_ring_emit(ring,
1615 MI_BATCH_BUFFER_START |
1616 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1617 /* bit0-7 is the length on GEN6+ */
1618 intel_ring_emit(ring, offset);
1619 intel_ring_advance(ring);
1620
1621 return 0;
1622 }
1623
1624 /* Blitter support (SandyBridge+) */
1625
1626 static int blt_ring_flush(struct intel_ring_buffer *ring,
1627 u32 invalidate, u32 flush)
1628 {
1629 uint32_t cmd;
1630 int ret;
1631
1632 ret = intel_ring_begin(ring, 4);
1633 if (ret)
1634 return ret;
1635
1636 cmd = MI_FLUSH_DW;
1637 /*
1638 * Bspec vol 1c.3 - blitter engine command streamer:
1639 * "If ENABLED, all TLBs will be invalidated once the flush
1640 * operation is complete. This bit is only valid when the
1641 * Post-Sync Operation field is a value of 1h or 3h."
1642 */
1643 if (invalidate & I915_GEM_DOMAIN_RENDER)
1644 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1645 MI_FLUSH_DW_OP_STOREDW;
1646 intel_ring_emit(ring, cmd);
1647 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1648 intel_ring_emit(ring, 0);
1649 intel_ring_emit(ring, MI_NOOP);
1650 intel_ring_advance(ring);
1651 return 0;
1652 }
1653
1654 int intel_init_render_ring_buffer(struct drm_device *dev)
1655 {
1656 drm_i915_private_t *dev_priv = dev->dev_private;
1657 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1658
1659 ring->name = "render ring";
1660 ring->id = RCS;
1661 ring->mmio_base = RENDER_RING_BASE;
1662
1663 if (INTEL_INFO(dev)->gen >= 6) {
1664 ring->add_request = gen6_add_request;
1665 ring->flush = gen7_render_ring_flush;
1666 if (INTEL_INFO(dev)->gen == 6)
1667 ring->flush = gen6_render_ring_flush;
1668 ring->irq_get = gen6_ring_get_irq;
1669 ring->irq_put = gen6_ring_put_irq;
1670 ring->irq_enable_mask = GT_USER_INTERRUPT;
1671 ring->get_seqno = gen6_ring_get_seqno;
1672 ring->set_seqno = ring_set_seqno;
1673 ring->sync_to = gen6_ring_sync;
1674 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1675 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1676 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1677 ring->signal_mbox[0] = GEN6_VRSYNC;
1678 ring->signal_mbox[1] = GEN6_BRSYNC;
1679 } else if (IS_GEN5(dev)) {
1680 ring->add_request = pc_render_add_request;
1681 ring->flush = gen4_render_ring_flush;
1682 ring->get_seqno = pc_render_get_seqno;
1683 ring->set_seqno = pc_render_set_seqno;
1684 ring->irq_get = gen5_ring_get_irq;
1685 ring->irq_put = gen5_ring_put_irq;
1686 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1687 } else {
1688 ring->add_request = i9xx_add_request;
1689 if (INTEL_INFO(dev)->gen < 4)
1690 ring->flush = gen2_render_ring_flush;
1691 else
1692 ring->flush = gen4_render_ring_flush;
1693 ring->get_seqno = ring_get_seqno;
1694 ring->set_seqno = ring_set_seqno;
1695 if (IS_GEN2(dev)) {
1696 ring->irq_get = i8xx_ring_get_irq;
1697 ring->irq_put = i8xx_ring_put_irq;
1698 } else {
1699 ring->irq_get = i9xx_ring_get_irq;
1700 ring->irq_put = i9xx_ring_put_irq;
1701 }
1702 ring->irq_enable_mask = I915_USER_INTERRUPT;
1703 }
1704 ring->write_tail = ring_write_tail;
1705 if (IS_HASWELL(dev))
1706 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1707 else if (INTEL_INFO(dev)->gen >= 6)
1708 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1709 else if (INTEL_INFO(dev)->gen >= 4)
1710 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1711 else if (IS_I830(dev) || IS_845G(dev))
1712 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1713 else
1714 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1715 ring->init = init_render_ring;
1716 ring->cleanup = render_ring_cleanup;
1717
1718 /* Workaround batchbuffer to combat CS tlb bug. */
1719 if (HAS_BROKEN_CS_TLB(dev)) {
1720 struct drm_i915_gem_object *obj;
1721 int ret;
1722
1723 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1724 if (obj == NULL) {
1725 DRM_ERROR("Failed to allocate batch bo\n");
1726 return -ENOMEM;
1727 }
1728
1729 ret = i915_gem_object_pin(obj, 0, true, false);
1730 if (ret != 0) {
1731 drm_gem_object_unreference(&obj->base);
1732 DRM_ERROR("Failed to ping batch bo\n");
1733 return ret;
1734 }
1735
1736 ring->private = obj;
1737 }
1738
1739 return intel_init_ring_buffer(dev, ring);
1740 }
1741
1742 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1743 {
1744 drm_i915_private_t *dev_priv = dev->dev_private;
1745 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1746 int ret;
1747
1748 ring->name = "render ring";
1749 ring->id = RCS;
1750 ring->mmio_base = RENDER_RING_BASE;
1751
1752 if (INTEL_INFO(dev)->gen >= 6) {
1753 /* non-kms not supported on gen6+ */
1754 return -ENODEV;
1755 }
1756
1757 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1758 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1759 * the special gen5 functions. */
1760 ring->add_request = i9xx_add_request;
1761 if (INTEL_INFO(dev)->gen < 4)
1762 ring->flush = gen2_render_ring_flush;
1763 else
1764 ring->flush = gen4_render_ring_flush;
1765 ring->get_seqno = ring_get_seqno;
1766 ring->set_seqno = ring_set_seqno;
1767 if (IS_GEN2(dev)) {
1768 ring->irq_get = i8xx_ring_get_irq;
1769 ring->irq_put = i8xx_ring_put_irq;
1770 } else {
1771 ring->irq_get = i9xx_ring_get_irq;
1772 ring->irq_put = i9xx_ring_put_irq;
1773 }
1774 ring->irq_enable_mask = I915_USER_INTERRUPT;
1775 ring->write_tail = ring_write_tail;
1776 if (INTEL_INFO(dev)->gen >= 4)
1777 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1778 else if (IS_I830(dev) || IS_845G(dev))
1779 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1780 else
1781 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1782 ring->init = init_render_ring;
1783 ring->cleanup = render_ring_cleanup;
1784
1785 ring->dev = dev;
1786 INIT_LIST_HEAD(&ring->active_list);
1787 INIT_LIST_HEAD(&ring->request_list);
1788
1789 ring->size = size;
1790 ring->effective_size = ring->size;
1791 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1792 ring->effective_size -= 128;
1793
1794 ring->virtual_start = ioremap_wc(start, size);
1795 if (ring->virtual_start == NULL) {
1796 DRM_ERROR("can not ioremap virtual address for"
1797 " ring buffer\n");
1798 return -ENOMEM;
1799 }
1800
1801 if (!I915_NEED_GFX_HWS(dev)) {
1802 ret = init_phys_hws_pga(ring);
1803 if (ret)
1804 return ret;
1805 }
1806
1807 return 0;
1808 }
1809
1810 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1811 {
1812 drm_i915_private_t *dev_priv = dev->dev_private;
1813 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1814
1815 ring->name = "bsd ring";
1816 ring->id = VCS;
1817
1818 ring->write_tail = ring_write_tail;
1819 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1820 ring->mmio_base = GEN6_BSD_RING_BASE;
1821 /* gen6 bsd needs a special wa for tail updates */
1822 if (IS_GEN6(dev))
1823 ring->write_tail = gen6_bsd_ring_write_tail;
1824 ring->flush = gen6_ring_flush;
1825 ring->add_request = gen6_add_request;
1826 ring->get_seqno = gen6_ring_get_seqno;
1827 ring->set_seqno = ring_set_seqno;
1828 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1829 ring->irq_get = gen6_ring_get_irq;
1830 ring->irq_put = gen6_ring_put_irq;
1831 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1832 ring->sync_to = gen6_ring_sync;
1833 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1834 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1835 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1836 ring->signal_mbox[0] = GEN6_RVSYNC;
1837 ring->signal_mbox[1] = GEN6_BVSYNC;
1838 } else {
1839 ring->mmio_base = BSD_RING_BASE;
1840 ring->flush = bsd_ring_flush;
1841 ring->add_request = i9xx_add_request;
1842 ring->get_seqno = ring_get_seqno;
1843 ring->set_seqno = ring_set_seqno;
1844 if (IS_GEN5(dev)) {
1845 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1846 ring->irq_get = gen5_ring_get_irq;
1847 ring->irq_put = gen5_ring_put_irq;
1848 } else {
1849 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1850 ring->irq_get = i9xx_ring_get_irq;
1851 ring->irq_put = i9xx_ring_put_irq;
1852 }
1853 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1854 }
1855 ring->init = init_ring_common;
1856
1857 return intel_init_ring_buffer(dev, ring);
1858 }
1859
1860 int intel_init_blt_ring_buffer(struct drm_device *dev)
1861 {
1862 drm_i915_private_t *dev_priv = dev->dev_private;
1863 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1864
1865 ring->name = "blitter ring";
1866 ring->id = BCS;
1867
1868 ring->mmio_base = BLT_RING_BASE;
1869 ring->write_tail = ring_write_tail;
1870 ring->flush = blt_ring_flush;
1871 ring->add_request = gen6_add_request;
1872 ring->get_seqno = gen6_ring_get_seqno;
1873 ring->set_seqno = ring_set_seqno;
1874 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1875 ring->irq_get = gen6_ring_get_irq;
1876 ring->irq_put = gen6_ring_put_irq;
1877 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1878 ring->sync_to = gen6_ring_sync;
1879 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1880 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1881 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1882 ring->signal_mbox[0] = GEN6_RBSYNC;
1883 ring->signal_mbox[1] = GEN6_VBSYNC;
1884 ring->init = init_ring_common;
1885
1886 return intel_init_ring_buffer(dev, ring);
1887 }
1888
1889 int
1890 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1891 {
1892 int ret;
1893
1894 if (!ring->gpu_caches_dirty)
1895 return 0;
1896
1897 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1898 if (ret)
1899 return ret;
1900
1901 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1902
1903 ring->gpu_caches_dirty = false;
1904 return 0;
1905 }
1906
1907 int
1908 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1909 {
1910 uint32_t flush_domains;
1911 int ret;
1912
1913 flush_domains = 0;
1914 if (ring->gpu_caches_dirty)
1915 flush_domains = I915_GEM_GPU_DOMAINS;
1916
1917 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1918 if (ret)
1919 return ret;
1920
1921 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1922
1923 ring->gpu_caches_dirty = false;
1924 return 0;
1925 }
Linux kernel - Deliverables
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