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drm/i915: add gen7_render_ring_flush
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Just flush everything. Experiments have shown that reducing the
222 * number of bits based on the write domains has little performance
223 * impact.
224 */
225 if (flush_domains) {
226 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
227 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
228 /*
229 * Ensure that any following seqno writes only happen
230 * when the render cache is indeed flushed.
231 */
232 flags |= PIPE_CONTROL_CS_STALL;
233 }
234 if (invalidate_domains) {
235 flags |= PIPE_CONTROL_TLB_INVALIDATE;
236 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
237 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
238 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
241 /*
242 * TLB invalidate requires a post-sync write.
243 */
244 flags |= PIPE_CONTROL_QW_WRITE;
245 }
246
247 ret = intel_ring_begin(ring, 4);
248 if (ret)
249 return ret;
250
251 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
252 intel_ring_emit(ring, flags);
253 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
254 intel_ring_emit(ring, 0);
255 intel_ring_advance(ring);
256
257 return 0;
258 }
259
260 static int
261 gen7_render_ring_flush(struct intel_ring_buffer *ring,
262 u32 invalidate_domains, u32 flush_domains)
263 {
264 u32 flags = 0;
265 struct pipe_control *pc = ring->private;
266 u32 scratch_addr = pc->gtt_offset + 128;
267 int ret;
268
269 /* Just flush everything. Experiments have shown that reducing the
270 * number of bits based on the write domains has little performance
271 * impact.
272 */
273 if (flush_domains) {
274 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
275 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
276 /*
277 * Ensure that any following seqno writes only happen
278 * when the render cache is indeed flushed.
279 */
280 flags |= PIPE_CONTROL_CS_STALL;
281 }
282 if (invalidate_domains) {
283 flags |= PIPE_CONTROL_TLB_INVALIDATE;
284 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
285 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
286 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
287 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
288 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
289 /*
290 * TLB invalidate requires a post-sync write.
291 */
292 flags |= PIPE_CONTROL_QW_WRITE;
293 }
294
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring, flags);
301 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
302 intel_ring_emit(ring, 0);
303 intel_ring_advance(ring);
304
305 return 0;
306 }
307
308 static int
309 gen6_render_ring_flush__wa(struct intel_ring_buffer *ring,
310 u32 invalidate_domains, u32 flush_domains)
311 {
312 int ret;
313
314 /* Force SNB workarounds for PIPE_CONTROL flushes */
315 ret = intel_emit_post_sync_nonzero_flush(ring);
316 if (ret)
317 return ret;
318
319 return gen6_render_ring_flush(ring, invalidate_domains, flush_domains);
320 }
321
322 static void ring_write_tail(struct intel_ring_buffer *ring,
323 u32 value)
324 {
325 drm_i915_private_t *dev_priv = ring->dev->dev_private;
326 I915_WRITE_TAIL(ring, value);
327 }
328
329 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
330 {
331 drm_i915_private_t *dev_priv = ring->dev->dev_private;
332 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
333 RING_ACTHD(ring->mmio_base) : ACTHD;
334
335 return I915_READ(acthd_reg);
336 }
337
338 static int init_ring_common(struct intel_ring_buffer *ring)
339 {
340 struct drm_device *dev = ring->dev;
341 drm_i915_private_t *dev_priv = dev->dev_private;
342 struct drm_i915_gem_object *obj = ring->obj;
343 int ret = 0;
344 u32 head;
345
346 if (HAS_FORCE_WAKE(dev))
347 gen6_gt_force_wake_get(dev_priv);
348
349 /* Stop the ring if it's running. */
350 I915_WRITE_CTL(ring, 0);
351 I915_WRITE_HEAD(ring, 0);
352 ring->write_tail(ring, 0);
353
354 head = I915_READ_HEAD(ring) & HEAD_ADDR;
355
356 /* G45 ring initialization fails to reset head to zero */
357 if (head != 0) {
358 DRM_DEBUG_KMS("%s head not reset to zero "
359 "ctl %08x head %08x tail %08x start %08x\n",
360 ring->name,
361 I915_READ_CTL(ring),
362 I915_READ_HEAD(ring),
363 I915_READ_TAIL(ring),
364 I915_READ_START(ring));
365
366 I915_WRITE_HEAD(ring, 0);
367
368 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
369 DRM_ERROR("failed to set %s head to zero "
370 "ctl %08x head %08x tail %08x start %08x\n",
371 ring->name,
372 I915_READ_CTL(ring),
373 I915_READ_HEAD(ring),
374 I915_READ_TAIL(ring),
375 I915_READ_START(ring));
376 }
377 }
378
379 /* Initialize the ring. This must happen _after_ we've cleared the ring
380 * registers with the above sequence (the readback of the HEAD registers
381 * also enforces ordering), otherwise the hw might lose the new ring
382 * register values. */
383 I915_WRITE_START(ring, obj->gtt_offset);
384 I915_WRITE_CTL(ring,
385 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
386 | RING_VALID);
387
388 /* If the head is still not zero, the ring is dead */
389 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
390 I915_READ_START(ring) == obj->gtt_offset &&
391 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
392 DRM_ERROR("%s initialization failed "
393 "ctl %08x head %08x tail %08x start %08x\n",
394 ring->name,
395 I915_READ_CTL(ring),
396 I915_READ_HEAD(ring),
397 I915_READ_TAIL(ring),
398 I915_READ_START(ring));
399 ret = -EIO;
400 goto out;
401 }
402
403 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
404 i915_kernel_lost_context(ring->dev);
405 else {
406 ring->head = I915_READ_HEAD(ring);
407 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
408 ring->space = ring_space(ring);
409 ring->last_retired_head = -1;
410 }
411
412 out:
413 if (HAS_FORCE_WAKE(dev))
414 gen6_gt_force_wake_put(dev_priv);
415
416 return ret;
417 }
418
419 static int
420 init_pipe_control(struct intel_ring_buffer *ring)
421 {
422 struct pipe_control *pc;
423 struct drm_i915_gem_object *obj;
424 int ret;
425
426 if (ring->private)
427 return 0;
428
429 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
430 if (!pc)
431 return -ENOMEM;
432
433 obj = i915_gem_alloc_object(ring->dev, 4096);
434 if (obj == NULL) {
435 DRM_ERROR("Failed to allocate seqno page\n");
436 ret = -ENOMEM;
437 goto err;
438 }
439
440 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
441
442 ret = i915_gem_object_pin(obj, 4096, true, false);
443 if (ret)
444 goto err_unref;
445
446 pc->gtt_offset = obj->gtt_offset;
447 pc->cpu_page = kmap(obj->pages[0]);
448 if (pc->cpu_page == NULL)
449 goto err_unpin;
450
451 pc->obj = obj;
452 ring->private = pc;
453 return 0;
454
455 err_unpin:
456 i915_gem_object_unpin(obj);
457 err_unref:
458 drm_gem_object_unreference(&obj->base);
459 err:
460 kfree(pc);
461 return ret;
462 }
463
464 static void
465 cleanup_pipe_control(struct intel_ring_buffer *ring)
466 {
467 struct pipe_control *pc = ring->private;
468 struct drm_i915_gem_object *obj;
469
470 if (!ring->private)
471 return;
472
473 obj = pc->obj;
474 kunmap(obj->pages[0]);
475 i915_gem_object_unpin(obj);
476 drm_gem_object_unreference(&obj->base);
477
478 kfree(pc);
479 ring->private = NULL;
480 }
481
482 static int init_render_ring(struct intel_ring_buffer *ring)
483 {
484 struct drm_device *dev = ring->dev;
485 struct drm_i915_private *dev_priv = dev->dev_private;
486 int ret = init_ring_common(ring);
487
488 if (INTEL_INFO(dev)->gen > 3) {
489 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
490 if (IS_GEN7(dev))
491 I915_WRITE(GFX_MODE_GEN7,
492 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
493 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
494 }
495
496 if (INTEL_INFO(dev)->gen >= 5) {
497 ret = init_pipe_control(ring);
498 if (ret)
499 return ret;
500 }
501
502 if (IS_GEN6(dev)) {
503 /* From the Sandybridge PRM, volume 1 part 3, page 24:
504 * "If this bit is set, STCunit will have LRA as replacement
505 * policy. [...] This bit must be reset. LRA replacement
506 * policy is not supported."
507 */
508 I915_WRITE(CACHE_MODE_0,
509 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
510
511 /* This is not explicitly set for GEN6, so read the register.
512 * see intel_ring_mi_set_context() for why we care.
513 * TODO: consider explicitly setting the bit for GEN5
514 */
515 ring->itlb_before_ctx_switch =
516 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
517 }
518
519 if (INTEL_INFO(dev)->gen >= 6)
520 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
521
522 if (HAS_L3_GPU_CACHE(dev))
523 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
524
525 return ret;
526 }
527
528 static void render_ring_cleanup(struct intel_ring_buffer *ring)
529 {
530 if (!ring->private)
531 return;
532
533 cleanup_pipe_control(ring);
534 }
535
536 static void
537 update_mboxes(struct intel_ring_buffer *ring,
538 u32 seqno,
539 u32 mmio_offset)
540 {
541 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
542 MI_SEMAPHORE_GLOBAL_GTT |
543 MI_SEMAPHORE_REGISTER |
544 MI_SEMAPHORE_UPDATE);
545 intel_ring_emit(ring, seqno);
546 intel_ring_emit(ring, mmio_offset);
547 }
548
549 /**
550 * gen6_add_request - Update the semaphore mailbox registers
551 *
552 * @ring - ring that is adding a request
553 * @seqno - return seqno stuck into the ring
554 *
555 * Update the mailbox registers in the *other* rings with the current seqno.
556 * This acts like a signal in the canonical semaphore.
557 */
558 static int
559 gen6_add_request(struct intel_ring_buffer *ring,
560 u32 *seqno)
561 {
562 u32 mbox1_reg;
563 u32 mbox2_reg;
564 int ret;
565
566 ret = intel_ring_begin(ring, 10);
567 if (ret)
568 return ret;
569
570 mbox1_reg = ring->signal_mbox[0];
571 mbox2_reg = ring->signal_mbox[1];
572
573 *seqno = i915_gem_next_request_seqno(ring);
574
575 update_mboxes(ring, *seqno, mbox1_reg);
576 update_mboxes(ring, *seqno, mbox2_reg);
577 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
578 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
579 intel_ring_emit(ring, *seqno);
580 intel_ring_emit(ring, MI_USER_INTERRUPT);
581 intel_ring_advance(ring);
582
583 return 0;
584 }
585
586 /**
587 * intel_ring_sync - sync the waiter to the signaller on seqno
588 *
589 * @waiter - ring that is waiting
590 * @signaller - ring which has, or will signal
591 * @seqno - seqno which the waiter will block on
592 */
593 static int
594 gen6_ring_sync(struct intel_ring_buffer *waiter,
595 struct intel_ring_buffer *signaller,
596 u32 seqno)
597 {
598 int ret;
599 u32 dw1 = MI_SEMAPHORE_MBOX |
600 MI_SEMAPHORE_COMPARE |
601 MI_SEMAPHORE_REGISTER;
602
603 /* Throughout all of the GEM code, seqno passed implies our current
604 * seqno is >= the last seqno executed. However for hardware the
605 * comparison is strictly greater than.
606 */
607 seqno -= 1;
608
609 WARN_ON(signaller->semaphore_register[waiter->id] ==
610 MI_SEMAPHORE_SYNC_INVALID);
611
612 ret = intel_ring_begin(waiter, 4);
613 if (ret)
614 return ret;
615
616 intel_ring_emit(waiter,
617 dw1 | signaller->semaphore_register[waiter->id]);
618 intel_ring_emit(waiter, seqno);
619 intel_ring_emit(waiter, 0);
620 intel_ring_emit(waiter, MI_NOOP);
621 intel_ring_advance(waiter);
622
623 return 0;
624 }
625
626 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
627 do { \
628 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
629 PIPE_CONTROL_DEPTH_STALL); \
630 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
631 intel_ring_emit(ring__, 0); \
632 intel_ring_emit(ring__, 0); \
633 } while (0)
634
635 static int
636 pc_render_add_request(struct intel_ring_buffer *ring,
637 u32 *result)
638 {
639 u32 seqno = i915_gem_next_request_seqno(ring);
640 struct pipe_control *pc = ring->private;
641 u32 scratch_addr = pc->gtt_offset + 128;
642 int ret;
643
644 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
645 * incoherent with writes to memory, i.e. completely fubar,
646 * so we need to use PIPE_NOTIFY instead.
647 *
648 * However, we also need to workaround the qword write
649 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
650 * memory before requesting an interrupt.
651 */
652 ret = intel_ring_begin(ring, 32);
653 if (ret)
654 return ret;
655
656 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
657 PIPE_CONTROL_WRITE_FLUSH |
658 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
659 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
660 intel_ring_emit(ring, seqno);
661 intel_ring_emit(ring, 0);
662 PIPE_CONTROL_FLUSH(ring, scratch_addr);
663 scratch_addr += 128; /* write to separate cachelines */
664 PIPE_CONTROL_FLUSH(ring, scratch_addr);
665 scratch_addr += 128;
666 PIPE_CONTROL_FLUSH(ring, scratch_addr);
667 scratch_addr += 128;
668 PIPE_CONTROL_FLUSH(ring, scratch_addr);
669 scratch_addr += 128;
670 PIPE_CONTROL_FLUSH(ring, scratch_addr);
671 scratch_addr += 128;
672 PIPE_CONTROL_FLUSH(ring, scratch_addr);
673
674 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
675 PIPE_CONTROL_WRITE_FLUSH |
676 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
677 PIPE_CONTROL_NOTIFY);
678 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
679 intel_ring_emit(ring, seqno);
680 intel_ring_emit(ring, 0);
681 intel_ring_advance(ring);
682
683 *result = seqno;
684 return 0;
685 }
686
687 static u32
688 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
689 {
690 /* Workaround to force correct ordering between irq and seqno writes on
691 * ivb (and maybe also on snb) by reading from a CS register (like
692 * ACTHD) before reading the status page. */
693 if (!lazy_coherency)
694 intel_ring_get_active_head(ring);
695 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
696 }
697
698 static u32
699 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
700 {
701 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
702 }
703
704 static u32
705 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
706 {
707 struct pipe_control *pc = ring->private;
708 return pc->cpu_page[0];
709 }
710
711 static bool
712 gen5_ring_get_irq(struct intel_ring_buffer *ring)
713 {
714 struct drm_device *dev = ring->dev;
715 drm_i915_private_t *dev_priv = dev->dev_private;
716 unsigned long flags;
717
718 if (!dev->irq_enabled)
719 return false;
720
721 spin_lock_irqsave(&dev_priv->irq_lock, flags);
722 if (ring->irq_refcount++ == 0) {
723 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
724 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
725 POSTING_READ(GTIMR);
726 }
727 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
728
729 return true;
730 }
731
732 static void
733 gen5_ring_put_irq(struct intel_ring_buffer *ring)
734 {
735 struct drm_device *dev = ring->dev;
736 drm_i915_private_t *dev_priv = dev->dev_private;
737 unsigned long flags;
738
739 spin_lock_irqsave(&dev_priv->irq_lock, flags);
740 if (--ring->irq_refcount == 0) {
741 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
742 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
743 POSTING_READ(GTIMR);
744 }
745 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
746 }
747
748 static bool
749 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
750 {
751 struct drm_device *dev = ring->dev;
752 drm_i915_private_t *dev_priv = dev->dev_private;
753 unsigned long flags;
754
755 if (!dev->irq_enabled)
756 return false;
757
758 spin_lock_irqsave(&dev_priv->irq_lock, flags);
759 if (ring->irq_refcount++ == 0) {
760 dev_priv->irq_mask &= ~ring->irq_enable_mask;
761 I915_WRITE(IMR, dev_priv->irq_mask);
762 POSTING_READ(IMR);
763 }
764 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
765
766 return true;
767 }
768
769 static void
770 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
771 {
772 struct drm_device *dev = ring->dev;
773 drm_i915_private_t *dev_priv = dev->dev_private;
774 unsigned long flags;
775
776 spin_lock_irqsave(&dev_priv->irq_lock, flags);
777 if (--ring->irq_refcount == 0) {
778 dev_priv->irq_mask |= ring->irq_enable_mask;
779 I915_WRITE(IMR, dev_priv->irq_mask);
780 POSTING_READ(IMR);
781 }
782 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
783 }
784
785 static bool
786 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
787 {
788 struct drm_device *dev = ring->dev;
789 drm_i915_private_t *dev_priv = dev->dev_private;
790 unsigned long flags;
791
792 if (!dev->irq_enabled)
793 return false;
794
795 spin_lock_irqsave(&dev_priv->irq_lock, flags);
796 if (ring->irq_refcount++ == 0) {
797 dev_priv->irq_mask &= ~ring->irq_enable_mask;
798 I915_WRITE16(IMR, dev_priv->irq_mask);
799 POSTING_READ16(IMR);
800 }
801 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
802
803 return true;
804 }
805
806 static void
807 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
808 {
809 struct drm_device *dev = ring->dev;
810 drm_i915_private_t *dev_priv = dev->dev_private;
811 unsigned long flags;
812
813 spin_lock_irqsave(&dev_priv->irq_lock, flags);
814 if (--ring->irq_refcount == 0) {
815 dev_priv->irq_mask |= ring->irq_enable_mask;
816 I915_WRITE16(IMR, dev_priv->irq_mask);
817 POSTING_READ16(IMR);
818 }
819 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
820 }
821
822 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
823 {
824 struct drm_device *dev = ring->dev;
825 drm_i915_private_t *dev_priv = ring->dev->dev_private;
826 u32 mmio = 0;
827
828 /* The ring status page addresses are no longer next to the rest of
829 * the ring registers as of gen7.
830 */
831 if (IS_GEN7(dev)) {
832 switch (ring->id) {
833 case RCS:
834 mmio = RENDER_HWS_PGA_GEN7;
835 break;
836 case BCS:
837 mmio = BLT_HWS_PGA_GEN7;
838 break;
839 case VCS:
840 mmio = BSD_HWS_PGA_GEN7;
841 break;
842 }
843 } else if (IS_GEN6(ring->dev)) {
844 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
845 } else {
846 mmio = RING_HWS_PGA(ring->mmio_base);
847 }
848
849 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
850 POSTING_READ(mmio);
851 }
852
853 static int
854 bsd_ring_flush(struct intel_ring_buffer *ring,
855 u32 invalidate_domains,
856 u32 flush_domains)
857 {
858 int ret;
859
860 ret = intel_ring_begin(ring, 2);
861 if (ret)
862 return ret;
863
864 intel_ring_emit(ring, MI_FLUSH);
865 intel_ring_emit(ring, MI_NOOP);
866 intel_ring_advance(ring);
867 return 0;
868 }
869
870 static int
871 i9xx_add_request(struct intel_ring_buffer *ring,
872 u32 *result)
873 {
874 u32 seqno;
875 int ret;
876
877 ret = intel_ring_begin(ring, 4);
878 if (ret)
879 return ret;
880
881 seqno = i915_gem_next_request_seqno(ring);
882
883 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
884 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
885 intel_ring_emit(ring, seqno);
886 intel_ring_emit(ring, MI_USER_INTERRUPT);
887 intel_ring_advance(ring);
888
889 *result = seqno;
890 return 0;
891 }
892
893 static bool
894 gen6_ring_get_irq(struct intel_ring_buffer *ring)
895 {
896 struct drm_device *dev = ring->dev;
897 drm_i915_private_t *dev_priv = dev->dev_private;
898 unsigned long flags;
899
900 if (!dev->irq_enabled)
901 return false;
902
903 /* It looks like we need to prevent the gt from suspending while waiting
904 * for an notifiy irq, otherwise irqs seem to get lost on at least the
905 * blt/bsd rings on ivb. */
906 gen6_gt_force_wake_get(dev_priv);
907
908 spin_lock_irqsave(&dev_priv->irq_lock, flags);
909 if (ring->irq_refcount++ == 0) {
910 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
911 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
912 GEN6_RENDER_L3_PARITY_ERROR));
913 else
914 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
915 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
916 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
917 POSTING_READ(GTIMR);
918 }
919 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
920
921 return true;
922 }
923
924 static void
925 gen6_ring_put_irq(struct intel_ring_buffer *ring)
926 {
927 struct drm_device *dev = ring->dev;
928 drm_i915_private_t *dev_priv = dev->dev_private;
929 unsigned long flags;
930
931 spin_lock_irqsave(&dev_priv->irq_lock, flags);
932 if (--ring->irq_refcount == 0) {
933 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
934 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
935 else
936 I915_WRITE_IMR(ring, ~0);
937 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
938 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
939 POSTING_READ(GTIMR);
940 }
941 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
942
943 gen6_gt_force_wake_put(dev_priv);
944 }
945
946 static int
947 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
948 {
949 int ret;
950
951 ret = intel_ring_begin(ring, 2);
952 if (ret)
953 return ret;
954
955 intel_ring_emit(ring,
956 MI_BATCH_BUFFER_START |
957 MI_BATCH_GTT |
958 MI_BATCH_NON_SECURE_I965);
959 intel_ring_emit(ring, offset);
960 intel_ring_advance(ring);
961
962 return 0;
963 }
964
965 static int
966 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
967 u32 offset, u32 len)
968 {
969 int ret;
970
971 ret = intel_ring_begin(ring, 4);
972 if (ret)
973 return ret;
974
975 intel_ring_emit(ring, MI_BATCH_BUFFER);
976 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
977 intel_ring_emit(ring, offset + len - 8);
978 intel_ring_emit(ring, 0);
979 intel_ring_advance(ring);
980
981 return 0;
982 }
983
984 static int
985 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
986 u32 offset, u32 len)
987 {
988 int ret;
989
990 ret = intel_ring_begin(ring, 2);
991 if (ret)
992 return ret;
993
994 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
995 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
996 intel_ring_advance(ring);
997
998 return 0;
999 }
1000
1001 static void cleanup_status_page(struct intel_ring_buffer *ring)
1002 {
1003 struct drm_i915_gem_object *obj;
1004
1005 obj = ring->status_page.obj;
1006 if (obj == NULL)
1007 return;
1008
1009 kunmap(obj->pages[0]);
1010 i915_gem_object_unpin(obj);
1011 drm_gem_object_unreference(&obj->base);
1012 ring->status_page.obj = NULL;
1013 }
1014
1015 static int init_status_page(struct intel_ring_buffer *ring)
1016 {
1017 struct drm_device *dev = ring->dev;
1018 struct drm_i915_gem_object *obj;
1019 int ret;
1020
1021 obj = i915_gem_alloc_object(dev, 4096);
1022 if (obj == NULL) {
1023 DRM_ERROR("Failed to allocate status page\n");
1024 ret = -ENOMEM;
1025 goto err;
1026 }
1027
1028 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1029
1030 ret = i915_gem_object_pin(obj, 4096, true, false);
1031 if (ret != 0) {
1032 goto err_unref;
1033 }
1034
1035 ring->status_page.gfx_addr = obj->gtt_offset;
1036 ring->status_page.page_addr = kmap(obj->pages[0]);
1037 if (ring->status_page.page_addr == NULL) {
1038 ret = -ENOMEM;
1039 goto err_unpin;
1040 }
1041 ring->status_page.obj = obj;
1042 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1043
1044 intel_ring_setup_status_page(ring);
1045 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1046 ring->name, ring->status_page.gfx_addr);
1047
1048 return 0;
1049
1050 err_unpin:
1051 i915_gem_object_unpin(obj);
1052 err_unref:
1053 drm_gem_object_unreference(&obj->base);
1054 err:
1055 return ret;
1056 }
1057
1058 static int intel_init_ring_buffer(struct drm_device *dev,
1059 struct intel_ring_buffer *ring)
1060 {
1061 struct drm_i915_gem_object *obj;
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 int ret;
1064
1065 ring->dev = dev;
1066 INIT_LIST_HEAD(&ring->active_list);
1067 INIT_LIST_HEAD(&ring->request_list);
1068 ring->size = 32 * PAGE_SIZE;
1069
1070 init_waitqueue_head(&ring->irq_queue);
1071
1072 if (I915_NEED_GFX_HWS(dev)) {
1073 ret = init_status_page(ring);
1074 if (ret)
1075 return ret;
1076 }
1077
1078 obj = i915_gem_alloc_object(dev, ring->size);
1079 if (obj == NULL) {
1080 DRM_ERROR("Failed to allocate ringbuffer\n");
1081 ret = -ENOMEM;
1082 goto err_hws;
1083 }
1084
1085 ring->obj = obj;
1086
1087 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1088 if (ret)
1089 goto err_unref;
1090
1091 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1092 if (ret)
1093 goto err_unpin;
1094
1095 ring->virtual_start =
1096 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1097 ring->size);
1098 if (ring->virtual_start == NULL) {
1099 DRM_ERROR("Failed to map ringbuffer.\n");
1100 ret = -EINVAL;
1101 goto err_unpin;
1102 }
1103
1104 ret = ring->init(ring);
1105 if (ret)
1106 goto err_unmap;
1107
1108 /* Workaround an erratum on the i830 which causes a hang if
1109 * the TAIL pointer points to within the last 2 cachelines
1110 * of the buffer.
1111 */
1112 ring->effective_size = ring->size;
1113 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1114 ring->effective_size -= 128;
1115
1116 return 0;
1117
1118 err_unmap:
1119 iounmap(ring->virtual_start);
1120 err_unpin:
1121 i915_gem_object_unpin(obj);
1122 err_unref:
1123 drm_gem_object_unreference(&obj->base);
1124 ring->obj = NULL;
1125 err_hws:
1126 cleanup_status_page(ring);
1127 return ret;
1128 }
1129
1130 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1131 {
1132 struct drm_i915_private *dev_priv;
1133 int ret;
1134
1135 if (ring->obj == NULL)
1136 return;
1137
1138 /* Disable the ring buffer. The ring must be idle at this point */
1139 dev_priv = ring->dev->dev_private;
1140 ret = intel_wait_ring_idle(ring);
1141 if (ret)
1142 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1143 ring->name, ret);
1144
1145 I915_WRITE_CTL(ring, 0);
1146
1147 iounmap(ring->virtual_start);
1148
1149 i915_gem_object_unpin(ring->obj);
1150 drm_gem_object_unreference(&ring->obj->base);
1151 ring->obj = NULL;
1152
1153 if (ring->cleanup)
1154 ring->cleanup(ring);
1155
1156 cleanup_status_page(ring);
1157 }
1158
1159 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1160 {
1161 uint32_t __iomem *virt;
1162 int rem = ring->size - ring->tail;
1163
1164 if (ring->space < rem) {
1165 int ret = intel_wait_ring_buffer(ring, rem);
1166 if (ret)
1167 return ret;
1168 }
1169
1170 virt = ring->virtual_start + ring->tail;
1171 rem /= 4;
1172 while (rem--)
1173 iowrite32(MI_NOOP, virt++);
1174
1175 ring->tail = 0;
1176 ring->space = ring_space(ring);
1177
1178 return 0;
1179 }
1180
1181 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1182 {
1183 int ret;
1184
1185 ret = i915_wait_seqno(ring, seqno);
1186 if (!ret)
1187 i915_gem_retire_requests_ring(ring);
1188
1189 return ret;
1190 }
1191
1192 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1193 {
1194 struct drm_i915_gem_request *request;
1195 u32 seqno = 0;
1196 int ret;
1197
1198 i915_gem_retire_requests_ring(ring);
1199
1200 if (ring->last_retired_head != -1) {
1201 ring->head = ring->last_retired_head;
1202 ring->last_retired_head = -1;
1203 ring->space = ring_space(ring);
1204 if (ring->space >= n)
1205 return 0;
1206 }
1207
1208 list_for_each_entry(request, &ring->request_list, list) {
1209 int space;
1210
1211 if (request->tail == -1)
1212 continue;
1213
1214 space = request->tail - (ring->tail + 8);
1215 if (space < 0)
1216 space += ring->size;
1217 if (space >= n) {
1218 seqno = request->seqno;
1219 break;
1220 }
1221
1222 /* Consume this request in case we need more space than
1223 * is available and so need to prevent a race between
1224 * updating last_retired_head and direct reads of
1225 * I915_RING_HEAD. It also provides a nice sanity check.
1226 */
1227 request->tail = -1;
1228 }
1229
1230 if (seqno == 0)
1231 return -ENOSPC;
1232
1233 ret = intel_ring_wait_seqno(ring, seqno);
1234 if (ret)
1235 return ret;
1236
1237 if (WARN_ON(ring->last_retired_head == -1))
1238 return -ENOSPC;
1239
1240 ring->head = ring->last_retired_head;
1241 ring->last_retired_head = -1;
1242 ring->space = ring_space(ring);
1243 if (WARN_ON(ring->space < n))
1244 return -ENOSPC;
1245
1246 return 0;
1247 }
1248
1249 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1250 {
1251 struct drm_device *dev = ring->dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253 unsigned long end;
1254 int ret;
1255
1256 ret = intel_ring_wait_request(ring, n);
1257 if (ret != -ENOSPC)
1258 return ret;
1259
1260 trace_i915_ring_wait_begin(ring);
1261 /* With GEM the hangcheck timer should kick us out of the loop,
1262 * leaving it early runs the risk of corrupting GEM state (due
1263 * to running on almost untested codepaths). But on resume
1264 * timers don't work yet, so prevent a complete hang in that
1265 * case by choosing an insanely large timeout. */
1266 end = jiffies + 60 * HZ;
1267
1268 do {
1269 ring->head = I915_READ_HEAD(ring);
1270 ring->space = ring_space(ring);
1271 if (ring->space >= n) {
1272 trace_i915_ring_wait_end(ring);
1273 return 0;
1274 }
1275
1276 if (dev->primary->master) {
1277 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1278 if (master_priv->sarea_priv)
1279 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1280 }
1281
1282 msleep(1);
1283
1284 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1285 if (ret)
1286 return ret;
1287 } while (!time_after(jiffies, end));
1288 trace_i915_ring_wait_end(ring);
1289 return -EBUSY;
1290 }
1291
1292 int intel_ring_begin(struct intel_ring_buffer *ring,
1293 int num_dwords)
1294 {
1295 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1296 int n = 4*num_dwords;
1297 int ret;
1298
1299 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1300 if (ret)
1301 return ret;
1302
1303 if (unlikely(ring->tail + n > ring->effective_size)) {
1304 ret = intel_wrap_ring_buffer(ring);
1305 if (unlikely(ret))
1306 return ret;
1307 }
1308
1309 if (unlikely(ring->space < n)) {
1310 ret = intel_wait_ring_buffer(ring, n);
1311 if (unlikely(ret))
1312 return ret;
1313 }
1314
1315 ring->space -= n;
1316 return 0;
1317 }
1318
1319 void intel_ring_advance(struct intel_ring_buffer *ring)
1320 {
1321 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1322
1323 ring->tail &= ring->size - 1;
1324 if (dev_priv->stop_rings & intel_ring_flag(ring))
1325 return;
1326 ring->write_tail(ring, ring->tail);
1327 }
1328
1329
1330 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1331 u32 value)
1332 {
1333 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1334
1335 /* Every tail move must follow the sequence below */
1336
1337 /* Disable notification that the ring is IDLE. The GT
1338 * will then assume that it is busy and bring it out of rc6.
1339 */
1340 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1341 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1342
1343 /* Clear the context id. Here be magic! */
1344 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1345
1346 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1347 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1348 GEN6_BSD_SLEEP_INDICATOR) == 0,
1349 50))
1350 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1351
1352 /* Now that the ring is fully powered up, update the tail */
1353 I915_WRITE_TAIL(ring, value);
1354 POSTING_READ(RING_TAIL(ring->mmio_base));
1355
1356 /* Let the ring send IDLE messages to the GT again,
1357 * and so let it sleep to conserve power when idle.
1358 */
1359 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1360 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1361 }
1362
1363 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1364 u32 invalidate, u32 flush)
1365 {
1366 uint32_t cmd;
1367 int ret;
1368
1369 ret = intel_ring_begin(ring, 4);
1370 if (ret)
1371 return ret;
1372
1373 cmd = MI_FLUSH_DW;
1374 if (invalidate & I915_GEM_GPU_DOMAINS)
1375 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1376 intel_ring_emit(ring, cmd);
1377 intel_ring_emit(ring, 0);
1378 intel_ring_emit(ring, 0);
1379 intel_ring_emit(ring, MI_NOOP);
1380 intel_ring_advance(ring);
1381 return 0;
1382 }
1383
1384 static int
1385 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1386 u32 offset, u32 len)
1387 {
1388 int ret;
1389
1390 ret = intel_ring_begin(ring, 2);
1391 if (ret)
1392 return ret;
1393
1394 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1395 /* bit0-7 is the length on GEN6+ */
1396 intel_ring_emit(ring, offset);
1397 intel_ring_advance(ring);
1398
1399 return 0;
1400 }
1401
1402 /* Blitter support (SandyBridge+) */
1403
1404 static int blt_ring_flush(struct intel_ring_buffer *ring,
1405 u32 invalidate, u32 flush)
1406 {
1407 uint32_t cmd;
1408 int ret;
1409
1410 ret = intel_ring_begin(ring, 4);
1411 if (ret)
1412 return ret;
1413
1414 cmd = MI_FLUSH_DW;
1415 if (invalidate & I915_GEM_DOMAIN_RENDER)
1416 cmd |= MI_INVALIDATE_TLB;
1417 intel_ring_emit(ring, cmd);
1418 intel_ring_emit(ring, 0);
1419 intel_ring_emit(ring, 0);
1420 intel_ring_emit(ring, MI_NOOP);
1421 intel_ring_advance(ring);
1422 return 0;
1423 }
1424
1425 int intel_init_render_ring_buffer(struct drm_device *dev)
1426 {
1427 drm_i915_private_t *dev_priv = dev->dev_private;
1428 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1429
1430 ring->name = "render ring";
1431 ring->id = RCS;
1432 ring->mmio_base = RENDER_RING_BASE;
1433
1434 if (INTEL_INFO(dev)->gen >= 6) {
1435 ring->add_request = gen6_add_request;
1436 ring->flush = gen7_render_ring_flush;
1437 if (INTEL_INFO(dev)->gen == 6)
1438 ring->flush = gen6_render_ring_flush__wa;
1439 ring->irq_get = gen6_ring_get_irq;
1440 ring->irq_put = gen6_ring_put_irq;
1441 ring->irq_enable_mask = GT_USER_INTERRUPT;
1442 ring->get_seqno = gen6_ring_get_seqno;
1443 ring->sync_to = gen6_ring_sync;
1444 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1445 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1446 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1447 ring->signal_mbox[0] = GEN6_VRSYNC;
1448 ring->signal_mbox[1] = GEN6_BRSYNC;
1449 } else if (IS_GEN5(dev)) {
1450 ring->add_request = pc_render_add_request;
1451 ring->flush = gen4_render_ring_flush;
1452 ring->get_seqno = pc_render_get_seqno;
1453 ring->irq_get = gen5_ring_get_irq;
1454 ring->irq_put = gen5_ring_put_irq;
1455 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1456 } else {
1457 ring->add_request = i9xx_add_request;
1458 if (INTEL_INFO(dev)->gen < 4)
1459 ring->flush = gen2_render_ring_flush;
1460 else
1461 ring->flush = gen4_render_ring_flush;
1462 ring->get_seqno = ring_get_seqno;
1463 if (IS_GEN2(dev)) {
1464 ring->irq_get = i8xx_ring_get_irq;
1465 ring->irq_put = i8xx_ring_put_irq;
1466 } else {
1467 ring->irq_get = i9xx_ring_get_irq;
1468 ring->irq_put = i9xx_ring_put_irq;
1469 }
1470 ring->irq_enable_mask = I915_USER_INTERRUPT;
1471 }
1472 ring->write_tail = ring_write_tail;
1473 if (INTEL_INFO(dev)->gen >= 6)
1474 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1475 else if (INTEL_INFO(dev)->gen >= 4)
1476 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1477 else if (IS_I830(dev) || IS_845G(dev))
1478 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1479 else
1480 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1481 ring->init = init_render_ring;
1482 ring->cleanup = render_ring_cleanup;
1483
1484
1485 if (!I915_NEED_GFX_HWS(dev)) {
1486 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1487 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1488 }
1489
1490 return intel_init_ring_buffer(dev, ring);
1491 }
1492
1493 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1494 {
1495 drm_i915_private_t *dev_priv = dev->dev_private;
1496 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1497
1498 ring->name = "render ring";
1499 ring->id = RCS;
1500 ring->mmio_base = RENDER_RING_BASE;
1501
1502 if (INTEL_INFO(dev)->gen >= 6) {
1503 /* non-kms not supported on gen6+ */
1504 return -ENODEV;
1505 }
1506
1507 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1508 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1509 * the special gen5 functions. */
1510 ring->add_request = i9xx_add_request;
1511 if (INTEL_INFO(dev)->gen < 4)
1512 ring->flush = gen2_render_ring_flush;
1513 else
1514 ring->flush = gen4_render_ring_flush;
1515 ring->get_seqno = ring_get_seqno;
1516 if (IS_GEN2(dev)) {
1517 ring->irq_get = i8xx_ring_get_irq;
1518 ring->irq_put = i8xx_ring_put_irq;
1519 } else {
1520 ring->irq_get = i9xx_ring_get_irq;
1521 ring->irq_put = i9xx_ring_put_irq;
1522 }
1523 ring->irq_enable_mask = I915_USER_INTERRUPT;
1524 ring->write_tail = ring_write_tail;
1525 if (INTEL_INFO(dev)->gen >= 4)
1526 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1527 else if (IS_I830(dev) || IS_845G(dev))
1528 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1529 else
1530 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1531 ring->init = init_render_ring;
1532 ring->cleanup = render_ring_cleanup;
1533
1534 if (!I915_NEED_GFX_HWS(dev))
1535 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1536
1537 ring->dev = dev;
1538 INIT_LIST_HEAD(&ring->active_list);
1539 INIT_LIST_HEAD(&ring->request_list);
1540
1541 ring->size = size;
1542 ring->effective_size = ring->size;
1543 if (IS_I830(ring->dev))
1544 ring->effective_size -= 128;
1545
1546 ring->virtual_start = ioremap_wc(start, size);
1547 if (ring->virtual_start == NULL) {
1548 DRM_ERROR("can not ioremap virtual address for"
1549 " ring buffer\n");
1550 return -ENOMEM;
1551 }
1552
1553 return 0;
1554 }
1555
1556 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1557 {
1558 drm_i915_private_t *dev_priv = dev->dev_private;
1559 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1560
1561 ring->name = "bsd ring";
1562 ring->id = VCS;
1563
1564 ring->write_tail = ring_write_tail;
1565 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1566 ring->mmio_base = GEN6_BSD_RING_BASE;
1567 /* gen6 bsd needs a special wa for tail updates */
1568 if (IS_GEN6(dev))
1569 ring->write_tail = gen6_bsd_ring_write_tail;
1570 ring->flush = gen6_ring_flush;
1571 ring->add_request = gen6_add_request;
1572 ring->get_seqno = gen6_ring_get_seqno;
1573 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1574 ring->irq_get = gen6_ring_get_irq;
1575 ring->irq_put = gen6_ring_put_irq;
1576 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1577 ring->sync_to = gen6_ring_sync;
1578 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1579 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1580 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1581 ring->signal_mbox[0] = GEN6_RVSYNC;
1582 ring->signal_mbox[1] = GEN6_BVSYNC;
1583 } else {
1584 ring->mmio_base = BSD_RING_BASE;
1585 ring->flush = bsd_ring_flush;
1586 ring->add_request = i9xx_add_request;
1587 ring->get_seqno = ring_get_seqno;
1588 if (IS_GEN5(dev)) {
1589 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1590 ring->irq_get = gen5_ring_get_irq;
1591 ring->irq_put = gen5_ring_put_irq;
1592 } else {
1593 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1594 ring->irq_get = i9xx_ring_get_irq;
1595 ring->irq_put = i9xx_ring_put_irq;
1596 }
1597 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1598 }
1599 ring->init = init_ring_common;
1600
1601
1602 return intel_init_ring_buffer(dev, ring);
1603 }
1604
1605 int intel_init_blt_ring_buffer(struct drm_device *dev)
1606 {
1607 drm_i915_private_t *dev_priv = dev->dev_private;
1608 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1609
1610 ring->name = "blitter ring";
1611 ring->id = BCS;
1612
1613 ring->mmio_base = BLT_RING_BASE;
1614 ring->write_tail = ring_write_tail;
1615 ring->flush = blt_ring_flush;
1616 ring->add_request = gen6_add_request;
1617 ring->get_seqno = gen6_ring_get_seqno;
1618 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1619 ring->irq_get = gen6_ring_get_irq;
1620 ring->irq_put = gen6_ring_put_irq;
1621 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1622 ring->sync_to = gen6_ring_sync;
1623 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1624 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1625 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1626 ring->signal_mbox[0] = GEN6_RBSYNC;
1627 ring->signal_mbox[1] = GEN6_VBSYNC;
1628 ring->init = init_ring_common;
1629
1630 return intel_init_ring_buffer(dev, ring);
1631 }
1632
1633 int
1634 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1635 {
1636 int ret;
1637
1638 if (!ring->gpu_caches_dirty)
1639 return 0;
1640
1641 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1642 if (ret)
1643 return ret;
1644
1645 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1646
1647 ring->gpu_caches_dirty = false;
1648 return 0;
1649 }
1650
1651 int
1652 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1653 {
1654 uint32_t flush_domains;
1655 int ret;
1656
1657 flush_domains = 0;
1658 if (ring->gpu_caches_dirty)
1659 flush_domains = I915_GEM_GPU_DOMAINS;
1660
1661 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1662 if (ret)
1663 return ret;
1664
1665 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1666
1667 ring->gpu_caches_dirty = false;
1668 return 0;
1669 }
Linux kernel - Deliverables
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