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drm/i915: Remove unused 'reg' argument to dp_pipe_enabled
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 static inline int ring_space(struct intel_ring_buffer *ring)
38 {
39 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
40 if (space < 0)
41 space += ring->size;
42 return space;
43 }
44
45 static u32 i915_gem_get_seqno(struct drm_device *dev)
46 {
47 drm_i915_private_t *dev_priv = dev->dev_private;
48 u32 seqno;
49
50 seqno = dev_priv->next_seqno;
51
52 /* reserve 0 for non-seqno */
53 if (++dev_priv->next_seqno == 0)
54 dev_priv->next_seqno = 1;
55
56 return seqno;
57 }
58
59 static int
60 render_ring_flush(struct intel_ring_buffer *ring,
61 u32 invalidate_domains,
62 u32 flush_domains)
63 {
64 struct drm_device *dev = ring->dev;
65 u32 cmd;
66 int ret;
67
68 /*
69 * read/write caches:
70 *
71 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
72 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
73 * also flushed at 2d versus 3d pipeline switches.
74 *
75 * read-only caches:
76 *
77 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
78 * MI_READ_FLUSH is set, and is always flushed on 965.
79 *
80 * I915_GEM_DOMAIN_COMMAND may not exist?
81 *
82 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
83 * invalidated when MI_EXE_FLUSH is set.
84 *
85 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
86 * invalidated with every MI_FLUSH.
87 *
88 * TLBs:
89 *
90 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
91 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
92 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
93 * are flushed at any MI_FLUSH.
94 */
95
96 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
97 if ((invalidate_domains|flush_domains) &
98 I915_GEM_DOMAIN_RENDER)
99 cmd &= ~MI_NO_WRITE_FLUSH;
100 if (INTEL_INFO(dev)->gen < 4) {
101 /*
102 * On the 965, the sampler cache always gets flushed
103 * and this bit is reserved.
104 */
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107 }
108 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
109 cmd |= MI_EXE_FLUSH;
110
111 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
112 (IS_G4X(dev) || IS_GEN5(dev)))
113 cmd |= MI_INVALIDATE_ISP;
114
115 ret = intel_ring_begin(ring, 2);
116 if (ret)
117 return ret;
118
119 intel_ring_emit(ring, cmd);
120 intel_ring_emit(ring, MI_NOOP);
121 intel_ring_advance(ring);
122
123 return 0;
124 }
125
126 static void ring_write_tail(struct intel_ring_buffer *ring,
127 u32 value)
128 {
129 drm_i915_private_t *dev_priv = ring->dev->dev_private;
130 I915_WRITE_TAIL(ring, value);
131 }
132
133 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
134 {
135 drm_i915_private_t *dev_priv = ring->dev->dev_private;
136 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
137 RING_ACTHD(ring->mmio_base) : ACTHD;
138
139 return I915_READ(acthd_reg);
140 }
141
142 static int init_ring_common(struct intel_ring_buffer *ring)
143 {
144 drm_i915_private_t *dev_priv = ring->dev->dev_private;
145 struct drm_i915_gem_object *obj = ring->obj;
146 u32 head;
147
148 /* Stop the ring if it's running. */
149 I915_WRITE_CTL(ring, 0);
150 I915_WRITE_HEAD(ring, 0);
151 ring->write_tail(ring, 0);
152
153 /* Initialize the ring. */
154 I915_WRITE_START(ring, obj->gtt_offset);
155 head = I915_READ_HEAD(ring) & HEAD_ADDR;
156
157 /* G45 ring initialization fails to reset head to zero */
158 if (head != 0) {
159 DRM_DEBUG_KMS("%s head not reset to zero "
160 "ctl %08x head %08x tail %08x start %08x\n",
161 ring->name,
162 I915_READ_CTL(ring),
163 I915_READ_HEAD(ring),
164 I915_READ_TAIL(ring),
165 I915_READ_START(ring));
166
167 I915_WRITE_HEAD(ring, 0);
168
169 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
170 DRM_ERROR("failed to set %s head to zero "
171 "ctl %08x head %08x tail %08x start %08x\n",
172 ring->name,
173 I915_READ_CTL(ring),
174 I915_READ_HEAD(ring),
175 I915_READ_TAIL(ring),
176 I915_READ_START(ring));
177 }
178 }
179
180 I915_WRITE_CTL(ring,
181 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
182 | RING_REPORT_64K | RING_VALID);
183
184 /* If the head is still not zero, the ring is dead */
185 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
186 I915_READ_START(ring) != obj->gtt_offset ||
187 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
188 DRM_ERROR("%s initialization failed "
189 "ctl %08x head %08x tail %08x start %08x\n",
190 ring->name,
191 I915_READ_CTL(ring),
192 I915_READ_HEAD(ring),
193 I915_READ_TAIL(ring),
194 I915_READ_START(ring));
195 return -EIO;
196 }
197
198 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
199 i915_kernel_lost_context(ring->dev);
200 else {
201 ring->head = I915_READ_HEAD(ring);
202 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
203 ring->space = ring_space(ring);
204 }
205
206 return 0;
207 }
208
209 /*
210 * 965+ support PIPE_CONTROL commands, which provide finer grained control
211 * over cache flushing.
212 */
213 struct pipe_control {
214 struct drm_i915_gem_object *obj;
215 volatile u32 *cpu_page;
216 u32 gtt_offset;
217 };
218
219 static int
220 init_pipe_control(struct intel_ring_buffer *ring)
221 {
222 struct pipe_control *pc;
223 struct drm_i915_gem_object *obj;
224 int ret;
225
226 if (ring->private)
227 return 0;
228
229 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
230 if (!pc)
231 return -ENOMEM;
232
233 obj = i915_gem_alloc_object(ring->dev, 4096);
234 if (obj == NULL) {
235 DRM_ERROR("Failed to allocate seqno page\n");
236 ret = -ENOMEM;
237 goto err;
238 }
239
240 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
241
242 ret = i915_gem_object_pin(obj, 4096, true);
243 if (ret)
244 goto err_unref;
245
246 pc->gtt_offset = obj->gtt_offset;
247 pc->cpu_page = kmap(obj->pages[0]);
248 if (pc->cpu_page == NULL)
249 goto err_unpin;
250
251 pc->obj = obj;
252 ring->private = pc;
253 return 0;
254
255 err_unpin:
256 i915_gem_object_unpin(obj);
257 err_unref:
258 drm_gem_object_unreference(&obj->base);
259 err:
260 kfree(pc);
261 return ret;
262 }
263
264 static void
265 cleanup_pipe_control(struct intel_ring_buffer *ring)
266 {
267 struct pipe_control *pc = ring->private;
268 struct drm_i915_gem_object *obj;
269
270 if (!ring->private)
271 return;
272
273 obj = pc->obj;
274 kunmap(obj->pages[0]);
275 i915_gem_object_unpin(obj);
276 drm_gem_object_unreference(&obj->base);
277
278 kfree(pc);
279 ring->private = NULL;
280 }
281
282 static int init_render_ring(struct intel_ring_buffer *ring)
283 {
284 struct drm_device *dev = ring->dev;
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 int ret = init_ring_common(ring);
287
288 if (INTEL_INFO(dev)->gen > 3) {
289 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
290 if (IS_GEN6(dev) || IS_GEN7(dev))
291 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
292 I915_WRITE(MI_MODE, mode);
293 }
294
295 if (INTEL_INFO(dev)->gen >= 6) {
296 } else if (IS_GEN5(dev)) {
297 ret = init_pipe_control(ring);
298 if (ret)
299 return ret;
300 }
301
302 return ret;
303 }
304
305 static void render_ring_cleanup(struct intel_ring_buffer *ring)
306 {
307 if (!ring->private)
308 return;
309
310 cleanup_pipe_control(ring);
311 }
312
313 static void
314 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
315 {
316 struct drm_device *dev = ring->dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 int id;
319
320 /*
321 * cs -> 1 = vcs, 0 = bcs
322 * vcs -> 1 = bcs, 0 = cs,
323 * bcs -> 1 = cs, 0 = vcs.
324 */
325 id = ring - dev_priv->ring;
326 id += 2 - i;
327 id %= 3;
328
329 intel_ring_emit(ring,
330 MI_SEMAPHORE_MBOX |
331 MI_SEMAPHORE_REGISTER |
332 MI_SEMAPHORE_UPDATE);
333 intel_ring_emit(ring, seqno);
334 intel_ring_emit(ring,
335 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
336 }
337
338 static int
339 gen6_add_request(struct intel_ring_buffer *ring,
340 u32 *result)
341 {
342 u32 seqno;
343 int ret;
344
345 ret = intel_ring_begin(ring, 10);
346 if (ret)
347 return ret;
348
349 seqno = i915_gem_get_seqno(ring->dev);
350 update_semaphore(ring, 0, seqno);
351 update_semaphore(ring, 1, seqno);
352
353 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
354 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
355 intel_ring_emit(ring, seqno);
356 intel_ring_emit(ring, MI_USER_INTERRUPT);
357 intel_ring_advance(ring);
358
359 *result = seqno;
360 return 0;
361 }
362
363 int
364 intel_ring_sync(struct intel_ring_buffer *ring,
365 struct intel_ring_buffer *to,
366 u32 seqno)
367 {
368 int ret;
369
370 ret = intel_ring_begin(ring, 4);
371 if (ret)
372 return ret;
373
374 intel_ring_emit(ring,
375 MI_SEMAPHORE_MBOX |
376 MI_SEMAPHORE_REGISTER |
377 intel_ring_sync_index(ring, to) << 17 |
378 MI_SEMAPHORE_COMPARE);
379 intel_ring_emit(ring, seqno);
380 intel_ring_emit(ring, 0);
381 intel_ring_emit(ring, MI_NOOP);
382 intel_ring_advance(ring);
383
384 return 0;
385 }
386
387 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
388 do { \
389 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
390 PIPE_CONTROL_DEPTH_STALL | 2); \
391 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
392 intel_ring_emit(ring__, 0); \
393 intel_ring_emit(ring__, 0); \
394 } while (0)
395
396 static int
397 pc_render_add_request(struct intel_ring_buffer *ring,
398 u32 *result)
399 {
400 struct drm_device *dev = ring->dev;
401 u32 seqno = i915_gem_get_seqno(dev);
402 struct pipe_control *pc = ring->private;
403 u32 scratch_addr = pc->gtt_offset + 128;
404 int ret;
405
406 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
407 * incoherent with writes to memory, i.e. completely fubar,
408 * so we need to use PIPE_NOTIFY instead.
409 *
410 * However, we also need to workaround the qword write
411 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
412 * memory before requesting an interrupt.
413 */
414 ret = intel_ring_begin(ring, 32);
415 if (ret)
416 return ret;
417
418 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
419 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
420 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
421 intel_ring_emit(ring, seqno);
422 intel_ring_emit(ring, 0);
423 PIPE_CONTROL_FLUSH(ring, scratch_addr);
424 scratch_addr += 128; /* write to separate cachelines */
425 PIPE_CONTROL_FLUSH(ring, scratch_addr);
426 scratch_addr += 128;
427 PIPE_CONTROL_FLUSH(ring, scratch_addr);
428 scratch_addr += 128;
429 PIPE_CONTROL_FLUSH(ring, scratch_addr);
430 scratch_addr += 128;
431 PIPE_CONTROL_FLUSH(ring, scratch_addr);
432 scratch_addr += 128;
433 PIPE_CONTROL_FLUSH(ring, scratch_addr);
434 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
435 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
436 PIPE_CONTROL_NOTIFY);
437 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
438 intel_ring_emit(ring, seqno);
439 intel_ring_emit(ring, 0);
440 intel_ring_advance(ring);
441
442 *result = seqno;
443 return 0;
444 }
445
446 static int
447 render_ring_add_request(struct intel_ring_buffer *ring,
448 u32 *result)
449 {
450 struct drm_device *dev = ring->dev;
451 u32 seqno = i915_gem_get_seqno(dev);
452 int ret;
453
454 ret = intel_ring_begin(ring, 4);
455 if (ret)
456 return ret;
457
458 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
459 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
460 intel_ring_emit(ring, seqno);
461 intel_ring_emit(ring, MI_USER_INTERRUPT);
462 intel_ring_advance(ring);
463
464 *result = seqno;
465 return 0;
466 }
467
468 static u32
469 ring_get_seqno(struct intel_ring_buffer *ring)
470 {
471 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
472 }
473
474 static u32
475 pc_render_get_seqno(struct intel_ring_buffer *ring)
476 {
477 struct pipe_control *pc = ring->private;
478 return pc->cpu_page[0];
479 }
480
481 static void
482 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
483 {
484 dev_priv->gt_irq_mask &= ~mask;
485 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
486 POSTING_READ(GTIMR);
487 }
488
489 static void
490 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
491 {
492 dev_priv->gt_irq_mask |= mask;
493 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
494 POSTING_READ(GTIMR);
495 }
496
497 static void
498 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
499 {
500 dev_priv->irq_mask &= ~mask;
501 I915_WRITE(IMR, dev_priv->irq_mask);
502 POSTING_READ(IMR);
503 }
504
505 static void
506 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
507 {
508 dev_priv->irq_mask |= mask;
509 I915_WRITE(IMR, dev_priv->irq_mask);
510 POSTING_READ(IMR);
511 }
512
513 static bool
514 render_ring_get_irq(struct intel_ring_buffer *ring)
515 {
516 struct drm_device *dev = ring->dev;
517 drm_i915_private_t *dev_priv = dev->dev_private;
518
519 if (!dev->irq_enabled)
520 return false;
521
522 spin_lock(&ring->irq_lock);
523 if (ring->irq_refcount++ == 0) {
524 if (HAS_PCH_SPLIT(dev))
525 ironlake_enable_irq(dev_priv,
526 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
527 else
528 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
529 }
530 spin_unlock(&ring->irq_lock);
531
532 return true;
533 }
534
535 static void
536 render_ring_put_irq(struct intel_ring_buffer *ring)
537 {
538 struct drm_device *dev = ring->dev;
539 drm_i915_private_t *dev_priv = dev->dev_private;
540
541 spin_lock(&ring->irq_lock);
542 if (--ring->irq_refcount == 0) {
543 if (HAS_PCH_SPLIT(dev))
544 ironlake_disable_irq(dev_priv,
545 GT_USER_INTERRUPT |
546 GT_PIPE_NOTIFY);
547 else
548 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
549 }
550 spin_unlock(&ring->irq_lock);
551 }
552
553 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
554 {
555 struct drm_device *dev = ring->dev;
556 drm_i915_private_t *dev_priv = ring->dev->dev_private;
557 u32 mmio = 0;
558
559 /* The ring status page addresses are no longer next to the rest of
560 * the ring registers as of gen7.
561 */
562 if (IS_GEN7(dev)) {
563 switch (ring->id) {
564 case RING_RENDER:
565 mmio = RENDER_HWS_PGA_GEN7;
566 break;
567 case RING_BLT:
568 mmio = BLT_HWS_PGA_GEN7;
569 break;
570 case RING_BSD:
571 mmio = BSD_HWS_PGA_GEN7;
572 break;
573 }
574 } else if (IS_GEN6(ring->dev)) {
575 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
576 } else {
577 mmio = RING_HWS_PGA(ring->mmio_base);
578 }
579
580 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
581 POSTING_READ(mmio);
582 }
583
584 static int
585 bsd_ring_flush(struct intel_ring_buffer *ring,
586 u32 invalidate_domains,
587 u32 flush_domains)
588 {
589 int ret;
590
591 ret = intel_ring_begin(ring, 2);
592 if (ret)
593 return ret;
594
595 intel_ring_emit(ring, MI_FLUSH);
596 intel_ring_emit(ring, MI_NOOP);
597 intel_ring_advance(ring);
598 return 0;
599 }
600
601 static int
602 ring_add_request(struct intel_ring_buffer *ring,
603 u32 *result)
604 {
605 u32 seqno;
606 int ret;
607
608 ret = intel_ring_begin(ring, 4);
609 if (ret)
610 return ret;
611
612 seqno = i915_gem_get_seqno(ring->dev);
613
614 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
615 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
616 intel_ring_emit(ring, seqno);
617 intel_ring_emit(ring, MI_USER_INTERRUPT);
618 intel_ring_advance(ring);
619
620 *result = seqno;
621 return 0;
622 }
623
624 static bool
625 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
626 {
627 struct drm_device *dev = ring->dev;
628 drm_i915_private_t *dev_priv = dev->dev_private;
629
630 if (!dev->irq_enabled)
631 return false;
632
633 spin_lock(&ring->irq_lock);
634 if (ring->irq_refcount++ == 0) {
635 ring->irq_mask &= ~rflag;
636 I915_WRITE_IMR(ring, ring->irq_mask);
637 ironlake_enable_irq(dev_priv, gflag);
638 }
639 spin_unlock(&ring->irq_lock);
640
641 return true;
642 }
643
644 static void
645 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
646 {
647 struct drm_device *dev = ring->dev;
648 drm_i915_private_t *dev_priv = dev->dev_private;
649
650 spin_lock(&ring->irq_lock);
651 if (--ring->irq_refcount == 0) {
652 ring->irq_mask |= rflag;
653 I915_WRITE_IMR(ring, ring->irq_mask);
654 ironlake_disable_irq(dev_priv, gflag);
655 }
656 spin_unlock(&ring->irq_lock);
657 }
658
659 static bool
660 bsd_ring_get_irq(struct intel_ring_buffer *ring)
661 {
662 struct drm_device *dev = ring->dev;
663 drm_i915_private_t *dev_priv = dev->dev_private;
664
665 if (!dev->irq_enabled)
666 return false;
667
668 spin_lock(&ring->irq_lock);
669 if (ring->irq_refcount++ == 0) {
670 if (IS_G4X(dev))
671 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
672 else
673 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
674 }
675 spin_unlock(&ring->irq_lock);
676
677 return true;
678 }
679 static void
680 bsd_ring_put_irq(struct intel_ring_buffer *ring)
681 {
682 struct drm_device *dev = ring->dev;
683 drm_i915_private_t *dev_priv = dev->dev_private;
684
685 spin_lock(&ring->irq_lock);
686 if (--ring->irq_refcount == 0) {
687 if (IS_G4X(dev))
688 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
689 else
690 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
691 }
692 spin_unlock(&ring->irq_lock);
693 }
694
695 static int
696 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
697 {
698 int ret;
699
700 ret = intel_ring_begin(ring, 2);
701 if (ret)
702 return ret;
703
704 intel_ring_emit(ring,
705 MI_BATCH_BUFFER_START | (2 << 6) |
706 MI_BATCH_NON_SECURE_I965);
707 intel_ring_emit(ring, offset);
708 intel_ring_advance(ring);
709
710 return 0;
711 }
712
713 static int
714 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
715 u32 offset, u32 len)
716 {
717 struct drm_device *dev = ring->dev;
718 int ret;
719
720 if (IS_I830(dev) || IS_845G(dev)) {
721 ret = intel_ring_begin(ring, 4);
722 if (ret)
723 return ret;
724
725 intel_ring_emit(ring, MI_BATCH_BUFFER);
726 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
727 intel_ring_emit(ring, offset + len - 8);
728 intel_ring_emit(ring, 0);
729 } else {
730 ret = intel_ring_begin(ring, 2);
731 if (ret)
732 return ret;
733
734 if (INTEL_INFO(dev)->gen >= 4) {
735 intel_ring_emit(ring,
736 MI_BATCH_BUFFER_START | (2 << 6) |
737 MI_BATCH_NON_SECURE_I965);
738 intel_ring_emit(ring, offset);
739 } else {
740 intel_ring_emit(ring,
741 MI_BATCH_BUFFER_START | (2 << 6));
742 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
743 }
744 }
745 intel_ring_advance(ring);
746
747 return 0;
748 }
749
750 static void cleanup_status_page(struct intel_ring_buffer *ring)
751 {
752 drm_i915_private_t *dev_priv = ring->dev->dev_private;
753 struct drm_i915_gem_object *obj;
754
755 obj = ring->status_page.obj;
756 if (obj == NULL)
757 return;
758
759 kunmap(obj->pages[0]);
760 i915_gem_object_unpin(obj);
761 drm_gem_object_unreference(&obj->base);
762 ring->status_page.obj = NULL;
763
764 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
765 }
766
767 static int init_status_page(struct intel_ring_buffer *ring)
768 {
769 struct drm_device *dev = ring->dev;
770 drm_i915_private_t *dev_priv = dev->dev_private;
771 struct drm_i915_gem_object *obj;
772 int ret;
773
774 obj = i915_gem_alloc_object(dev, 4096);
775 if (obj == NULL) {
776 DRM_ERROR("Failed to allocate status page\n");
777 ret = -ENOMEM;
778 goto err;
779 }
780
781 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
782
783 ret = i915_gem_object_pin(obj, 4096, true);
784 if (ret != 0) {
785 goto err_unref;
786 }
787
788 ring->status_page.gfx_addr = obj->gtt_offset;
789 ring->status_page.page_addr = kmap(obj->pages[0]);
790 if (ring->status_page.page_addr == NULL) {
791 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
792 goto err_unpin;
793 }
794 ring->status_page.obj = obj;
795 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
796
797 intel_ring_setup_status_page(ring);
798 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
799 ring->name, ring->status_page.gfx_addr);
800
801 return 0;
802
803 err_unpin:
804 i915_gem_object_unpin(obj);
805 err_unref:
806 drm_gem_object_unreference(&obj->base);
807 err:
808 return ret;
809 }
810
811 int intel_init_ring_buffer(struct drm_device *dev,
812 struct intel_ring_buffer *ring)
813 {
814 struct drm_i915_gem_object *obj;
815 int ret;
816
817 ring->dev = dev;
818 INIT_LIST_HEAD(&ring->active_list);
819 INIT_LIST_HEAD(&ring->request_list);
820 INIT_LIST_HEAD(&ring->gpu_write_list);
821
822 init_waitqueue_head(&ring->irq_queue);
823 spin_lock_init(&ring->irq_lock);
824 ring->irq_mask = ~0;
825
826 if (I915_NEED_GFX_HWS(dev)) {
827 ret = init_status_page(ring);
828 if (ret)
829 return ret;
830 }
831
832 obj = i915_gem_alloc_object(dev, ring->size);
833 if (obj == NULL) {
834 DRM_ERROR("Failed to allocate ringbuffer\n");
835 ret = -ENOMEM;
836 goto err_hws;
837 }
838
839 ring->obj = obj;
840
841 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
842 if (ret)
843 goto err_unref;
844
845 ring->map.size = ring->size;
846 ring->map.offset = dev->agp->base + obj->gtt_offset;
847 ring->map.type = 0;
848 ring->map.flags = 0;
849 ring->map.mtrr = 0;
850
851 drm_core_ioremap_wc(&ring->map, dev);
852 if (ring->map.handle == NULL) {
853 DRM_ERROR("Failed to map ringbuffer.\n");
854 ret = -EINVAL;
855 goto err_unpin;
856 }
857
858 ring->virtual_start = ring->map.handle;
859 ret = ring->init(ring);
860 if (ret)
861 goto err_unmap;
862
863 /* Workaround an erratum on the i830 which causes a hang if
864 * the TAIL pointer points to within the last 2 cachelines
865 * of the buffer.
866 */
867 ring->effective_size = ring->size;
868 if (IS_I830(ring->dev))
869 ring->effective_size -= 128;
870
871 return 0;
872
873 err_unmap:
874 drm_core_ioremapfree(&ring->map, dev);
875 err_unpin:
876 i915_gem_object_unpin(obj);
877 err_unref:
878 drm_gem_object_unreference(&obj->base);
879 ring->obj = NULL;
880 err_hws:
881 cleanup_status_page(ring);
882 return ret;
883 }
884
885 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
886 {
887 struct drm_i915_private *dev_priv;
888 int ret;
889
890 if (ring->obj == NULL)
891 return;
892
893 /* Disable the ring buffer. The ring must be idle at this point */
894 dev_priv = ring->dev->dev_private;
895 ret = intel_wait_ring_idle(ring);
896 if (ret)
897 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
898 ring->name, ret);
899
900 I915_WRITE_CTL(ring, 0);
901
902 drm_core_ioremapfree(&ring->map, ring->dev);
903
904 i915_gem_object_unpin(ring->obj);
905 drm_gem_object_unreference(&ring->obj->base);
906 ring->obj = NULL;
907
908 if (ring->cleanup)
909 ring->cleanup(ring);
910
911 cleanup_status_page(ring);
912 }
913
914 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
915 {
916 unsigned int *virt;
917 int rem = ring->size - ring->tail;
918
919 if (ring->space < rem) {
920 int ret = intel_wait_ring_buffer(ring, rem);
921 if (ret)
922 return ret;
923 }
924
925 virt = (unsigned int *)(ring->virtual_start + ring->tail);
926 rem /= 8;
927 while (rem--) {
928 *virt++ = MI_NOOP;
929 *virt++ = MI_NOOP;
930 }
931
932 ring->tail = 0;
933 ring->space = ring_space(ring);
934
935 return 0;
936 }
937
938 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
939 {
940 struct drm_device *dev = ring->dev;
941 struct drm_i915_private *dev_priv = dev->dev_private;
942 unsigned long end;
943 u32 head;
944
945 /* If the reported head position has wrapped or hasn't advanced,
946 * fallback to the slow and accurate path.
947 */
948 head = intel_read_status_page(ring, 4);
949 if (head > ring->head) {
950 ring->head = head;
951 ring->space = ring_space(ring);
952 if (ring->space >= n)
953 return 0;
954 }
955
956 trace_i915_ring_wait_begin(ring);
957 end = jiffies + 3 * HZ;
958 do {
959 ring->head = I915_READ_HEAD(ring);
960 ring->space = ring_space(ring);
961 if (ring->space >= n) {
962 trace_i915_ring_wait_end(ring);
963 return 0;
964 }
965
966 if (dev->primary->master) {
967 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
968 if (master_priv->sarea_priv)
969 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
970 }
971
972 msleep(1);
973 if (atomic_read(&dev_priv->mm.wedged))
974 return -EAGAIN;
975 } while (!time_after(jiffies, end));
976 trace_i915_ring_wait_end(ring);
977 return -EBUSY;
978 }
979
980 int intel_ring_begin(struct intel_ring_buffer *ring,
981 int num_dwords)
982 {
983 struct drm_i915_private *dev_priv = ring->dev->dev_private;
984 int n = 4*num_dwords;
985 int ret;
986
987 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
988 return -EIO;
989
990 if (unlikely(ring->tail + n > ring->effective_size)) {
991 ret = intel_wrap_ring_buffer(ring);
992 if (unlikely(ret))
993 return ret;
994 }
995
996 if (unlikely(ring->space < n)) {
997 ret = intel_wait_ring_buffer(ring, n);
998 if (unlikely(ret))
999 return ret;
1000 }
1001
1002 ring->space -= n;
1003 return 0;
1004 }
1005
1006 void intel_ring_advance(struct intel_ring_buffer *ring)
1007 {
1008 ring->tail &= ring->size - 1;
1009 ring->write_tail(ring, ring->tail);
1010 }
1011
1012 static const struct intel_ring_buffer render_ring = {
1013 .name = "render ring",
1014 .id = RING_RENDER,
1015 .mmio_base = RENDER_RING_BASE,
1016 .size = 32 * PAGE_SIZE,
1017 .init = init_render_ring,
1018 .write_tail = ring_write_tail,
1019 .flush = render_ring_flush,
1020 .add_request = render_ring_add_request,
1021 .get_seqno = ring_get_seqno,
1022 .irq_get = render_ring_get_irq,
1023 .irq_put = render_ring_put_irq,
1024 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
1025 .cleanup = render_ring_cleanup,
1026 };
1027
1028 /* ring buffer for bit-stream decoder */
1029
1030 static const struct intel_ring_buffer bsd_ring = {
1031 .name = "bsd ring",
1032 .id = RING_BSD,
1033 .mmio_base = BSD_RING_BASE,
1034 .size = 32 * PAGE_SIZE,
1035 .init = init_ring_common,
1036 .write_tail = ring_write_tail,
1037 .flush = bsd_ring_flush,
1038 .add_request = ring_add_request,
1039 .get_seqno = ring_get_seqno,
1040 .irq_get = bsd_ring_get_irq,
1041 .irq_put = bsd_ring_put_irq,
1042 .dispatch_execbuffer = ring_dispatch_execbuffer,
1043 };
1044
1045
1046 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1047 u32 value)
1048 {
1049 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1050
1051 /* Every tail move must follow the sequence below */
1052 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1053 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1054 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1055 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1056
1057 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1058 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1059 50))
1060 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1061
1062 I915_WRITE_TAIL(ring, value);
1063 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1064 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1065 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1066 }
1067
1068 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1069 u32 invalidate, u32 flush)
1070 {
1071 uint32_t cmd;
1072 int ret;
1073
1074 ret = intel_ring_begin(ring, 4);
1075 if (ret)
1076 return ret;
1077
1078 cmd = MI_FLUSH_DW;
1079 if (invalidate & I915_GEM_GPU_DOMAINS)
1080 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1081 intel_ring_emit(ring, cmd);
1082 intel_ring_emit(ring, 0);
1083 intel_ring_emit(ring, 0);
1084 intel_ring_emit(ring, MI_NOOP);
1085 intel_ring_advance(ring);
1086 return 0;
1087 }
1088
1089 static int
1090 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1091 u32 offset, u32 len)
1092 {
1093 int ret;
1094
1095 ret = intel_ring_begin(ring, 2);
1096 if (ret)
1097 return ret;
1098
1099 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1100 /* bit0-7 is the length on GEN6+ */
1101 intel_ring_emit(ring, offset);
1102 intel_ring_advance(ring);
1103
1104 return 0;
1105 }
1106
1107 static bool
1108 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1109 {
1110 return gen6_ring_get_irq(ring,
1111 GT_USER_INTERRUPT,
1112 GEN6_RENDER_USER_INTERRUPT);
1113 }
1114
1115 static void
1116 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1117 {
1118 return gen6_ring_put_irq(ring,
1119 GT_USER_INTERRUPT,
1120 GEN6_RENDER_USER_INTERRUPT);
1121 }
1122
1123 static bool
1124 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1125 {
1126 return gen6_ring_get_irq(ring,
1127 GT_GEN6_BSD_USER_INTERRUPT,
1128 GEN6_BSD_USER_INTERRUPT);
1129 }
1130
1131 static void
1132 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1133 {
1134 return gen6_ring_put_irq(ring,
1135 GT_GEN6_BSD_USER_INTERRUPT,
1136 GEN6_BSD_USER_INTERRUPT);
1137 }
1138
1139 /* ring buffer for Video Codec for Gen6+ */
1140 static const struct intel_ring_buffer gen6_bsd_ring = {
1141 .name = "gen6 bsd ring",
1142 .id = RING_BSD,
1143 .mmio_base = GEN6_BSD_RING_BASE,
1144 .size = 32 * PAGE_SIZE,
1145 .init = init_ring_common,
1146 .write_tail = gen6_bsd_ring_write_tail,
1147 .flush = gen6_ring_flush,
1148 .add_request = gen6_add_request,
1149 .get_seqno = ring_get_seqno,
1150 .irq_get = gen6_bsd_ring_get_irq,
1151 .irq_put = gen6_bsd_ring_put_irq,
1152 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1153 };
1154
1155 /* Blitter support (SandyBridge+) */
1156
1157 static bool
1158 blt_ring_get_irq(struct intel_ring_buffer *ring)
1159 {
1160 return gen6_ring_get_irq(ring,
1161 GT_BLT_USER_INTERRUPT,
1162 GEN6_BLITTER_USER_INTERRUPT);
1163 }
1164
1165 static void
1166 blt_ring_put_irq(struct intel_ring_buffer *ring)
1167 {
1168 gen6_ring_put_irq(ring,
1169 GT_BLT_USER_INTERRUPT,
1170 GEN6_BLITTER_USER_INTERRUPT);
1171 }
1172
1173
1174 /* Workaround for some stepping of SNB,
1175 * each time when BLT engine ring tail moved,
1176 * the first command in the ring to be parsed
1177 * should be MI_BATCH_BUFFER_START
1178 */
1179 #define NEED_BLT_WORKAROUND(dev) \
1180 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1181
1182 static inline struct drm_i915_gem_object *
1183 to_blt_workaround(struct intel_ring_buffer *ring)
1184 {
1185 return ring->private;
1186 }
1187
1188 static int blt_ring_init(struct intel_ring_buffer *ring)
1189 {
1190 if (NEED_BLT_WORKAROUND(ring->dev)) {
1191 struct drm_i915_gem_object *obj;
1192 u32 *ptr;
1193 int ret;
1194
1195 obj = i915_gem_alloc_object(ring->dev, 4096);
1196 if (obj == NULL)
1197 return -ENOMEM;
1198
1199 ret = i915_gem_object_pin(obj, 4096, true);
1200 if (ret) {
1201 drm_gem_object_unreference(&obj->base);
1202 return ret;
1203 }
1204
1205 ptr = kmap(obj->pages[0]);
1206 *ptr++ = MI_BATCH_BUFFER_END;
1207 *ptr++ = MI_NOOP;
1208 kunmap(obj->pages[0]);
1209
1210 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1211 if (ret) {
1212 i915_gem_object_unpin(obj);
1213 drm_gem_object_unreference(&obj->base);
1214 return ret;
1215 }
1216
1217 ring->private = obj;
1218 }
1219
1220 return init_ring_common(ring);
1221 }
1222
1223 static int blt_ring_begin(struct intel_ring_buffer *ring,
1224 int num_dwords)
1225 {
1226 if (ring->private) {
1227 int ret = intel_ring_begin(ring, num_dwords+2);
1228 if (ret)
1229 return ret;
1230
1231 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1232 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1233
1234 return 0;
1235 } else
1236 return intel_ring_begin(ring, 4);
1237 }
1238
1239 static int blt_ring_flush(struct intel_ring_buffer *ring,
1240 u32 invalidate, u32 flush)
1241 {
1242 uint32_t cmd;
1243 int ret;
1244
1245 ret = blt_ring_begin(ring, 4);
1246 if (ret)
1247 return ret;
1248
1249 cmd = MI_FLUSH_DW;
1250 if (invalidate & I915_GEM_DOMAIN_RENDER)
1251 cmd |= MI_INVALIDATE_TLB;
1252 intel_ring_emit(ring, cmd);
1253 intel_ring_emit(ring, 0);
1254 intel_ring_emit(ring, 0);
1255 intel_ring_emit(ring, MI_NOOP);
1256 intel_ring_advance(ring);
1257 return 0;
1258 }
1259
1260 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1261 {
1262 if (!ring->private)
1263 return;
1264
1265 i915_gem_object_unpin(ring->private);
1266 drm_gem_object_unreference(ring->private);
1267 ring->private = NULL;
1268 }
1269
1270 static const struct intel_ring_buffer gen6_blt_ring = {
1271 .name = "blt ring",
1272 .id = RING_BLT,
1273 .mmio_base = BLT_RING_BASE,
1274 .size = 32 * PAGE_SIZE,
1275 .init = blt_ring_init,
1276 .write_tail = ring_write_tail,
1277 .flush = blt_ring_flush,
1278 .add_request = gen6_add_request,
1279 .get_seqno = ring_get_seqno,
1280 .irq_get = blt_ring_get_irq,
1281 .irq_put = blt_ring_put_irq,
1282 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1283 .cleanup = blt_ring_cleanup,
1284 };
1285
1286 int intel_init_render_ring_buffer(struct drm_device *dev)
1287 {
1288 drm_i915_private_t *dev_priv = dev->dev_private;
1289 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1290
1291 *ring = render_ring;
1292 if (INTEL_INFO(dev)->gen >= 6) {
1293 ring->add_request = gen6_add_request;
1294 ring->irq_get = gen6_render_ring_get_irq;
1295 ring->irq_put = gen6_render_ring_put_irq;
1296 } else if (IS_GEN5(dev)) {
1297 ring->add_request = pc_render_add_request;
1298 ring->get_seqno = pc_render_get_seqno;
1299 }
1300
1301 if (!I915_NEED_GFX_HWS(dev)) {
1302 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1303 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1304 }
1305
1306 return intel_init_ring_buffer(dev, ring);
1307 }
1308
1309 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1310 {
1311 drm_i915_private_t *dev_priv = dev->dev_private;
1312 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1313
1314 *ring = render_ring;
1315 if (INTEL_INFO(dev)->gen >= 6) {
1316 ring->add_request = gen6_add_request;
1317 ring->irq_get = gen6_render_ring_get_irq;
1318 ring->irq_put = gen6_render_ring_put_irq;
1319 } else if (IS_GEN5(dev)) {
1320 ring->add_request = pc_render_add_request;
1321 ring->get_seqno = pc_render_get_seqno;
1322 }
1323
1324 if (!I915_NEED_GFX_HWS(dev))
1325 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1326
1327 ring->dev = dev;
1328 INIT_LIST_HEAD(&ring->active_list);
1329 INIT_LIST_HEAD(&ring->request_list);
1330 INIT_LIST_HEAD(&ring->gpu_write_list);
1331
1332 ring->size = size;
1333 ring->effective_size = ring->size;
1334 if (IS_I830(ring->dev))
1335 ring->effective_size -= 128;
1336
1337 ring->map.offset = start;
1338 ring->map.size = size;
1339 ring->map.type = 0;
1340 ring->map.flags = 0;
1341 ring->map.mtrr = 0;
1342
1343 drm_core_ioremap_wc(&ring->map, dev);
1344 if (ring->map.handle == NULL) {
1345 DRM_ERROR("can not ioremap virtual address for"
1346 " ring buffer\n");
1347 return -ENOMEM;
1348 }
1349
1350 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1351 return 0;
1352 }
1353
1354 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1355 {
1356 drm_i915_private_t *dev_priv = dev->dev_private;
1357 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1358
1359 if (IS_GEN6(dev) || IS_GEN7(dev))
1360 *ring = gen6_bsd_ring;
1361 else
1362 *ring = bsd_ring;
1363
1364 return intel_init_ring_buffer(dev, ring);
1365 }
1366
1367 int intel_init_blt_ring_buffer(struct drm_device *dev)
1368 {
1369 drm_i915_private_t *dev_priv = dev->dev_private;
1370 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1371
1372 *ring = gen6_blt_ring;
1373
1374 return intel_init_ring_buffer(dev, ring);
1375 }
Linux kernel - Deliverables
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