2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- tail
;
58 return space
- I915_RING_FREE_SPACE
;
61 void intel_ring_update_space(struct intel_ringbuffer
*ringbuf
)
63 if (ringbuf
->last_retired_head
!= -1) {
64 ringbuf
->head
= ringbuf
->last_retired_head
;
65 ringbuf
->last_retired_head
= -1;
68 ringbuf
->space
= __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
69 ringbuf
->tail
, ringbuf
->size
);
72 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
74 intel_ring_update_space(ringbuf
);
75 return ringbuf
->space
;
78 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
80 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
81 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
84 static void __intel_ring_advance(struct intel_engine_cs
*ring
)
86 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
87 ringbuf
->tail
&= ringbuf
->size
- 1;
88 if (intel_ring_stopped(ring
))
90 ring
->write_tail(ring
, ringbuf
->tail
);
94 gen2_render_ring_flush(struct drm_i915_gem_request
*req
,
95 u32 invalidate_domains
,
98 struct intel_engine_cs
*ring
= req
->ring
;
103 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
104 cmd
|= MI_NO_WRITE_FLUSH
;
106 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
107 cmd
|= MI_READ_FLUSH
;
109 ret
= intel_ring_begin(req
, 2);
113 intel_ring_emit(ring
, cmd
);
114 intel_ring_emit(ring
, MI_NOOP
);
115 intel_ring_advance(ring
);
121 gen4_render_ring_flush(struct drm_i915_gem_request
*req
,
122 u32 invalidate_domains
,
125 struct intel_engine_cs
*ring
= req
->ring
;
126 struct drm_device
*dev
= ring
->dev
;
133 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
134 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
135 * also flushed at 2d versus 3d pipeline switches.
139 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
140 * MI_READ_FLUSH is set, and is always flushed on 965.
142 * I915_GEM_DOMAIN_COMMAND may not exist?
144 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
145 * invalidated when MI_EXE_FLUSH is set.
147 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
148 * invalidated with every MI_FLUSH.
152 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
153 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
154 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
155 * are flushed at any MI_FLUSH.
158 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
159 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
160 cmd
&= ~MI_NO_WRITE_FLUSH
;
161 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
164 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
165 (IS_G4X(dev
) || IS_GEN5(dev
)))
166 cmd
|= MI_INVALIDATE_ISP
;
168 ret
= intel_ring_begin(req
, 2);
172 intel_ring_emit(ring
, cmd
);
173 intel_ring_emit(ring
, MI_NOOP
);
174 intel_ring_advance(ring
);
180 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
181 * implementing two workarounds on gen6. From section 1.4.7.1
182 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
184 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
185 * produced by non-pipelined state commands), software needs to first
186 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
189 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
190 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
192 * And the workaround for these two requires this workaround first:
194 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
195 * BEFORE the pipe-control with a post-sync op and no write-cache
198 * And this last workaround is tricky because of the requirements on
199 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
202 * "1 of the following must also be set:
203 * - Render Target Cache Flush Enable ([12] of DW1)
204 * - Depth Cache Flush Enable ([0] of DW1)
205 * - Stall at Pixel Scoreboard ([1] of DW1)
206 * - Depth Stall ([13] of DW1)
207 * - Post-Sync Operation ([13] of DW1)
208 * - Notify Enable ([8] of DW1)"
210 * The cache flushes require the workaround flush that triggered this
211 * one, so we can't use it. Depth stall would trigger the same.
212 * Post-sync nonzero is what triggered this second workaround, so we
213 * can't use that one either. Notify enable is IRQs, which aren't
214 * really our business. That leaves only stall at scoreboard.
217 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
219 struct intel_engine_cs
*ring
= req
->ring
;
220 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
223 ret
= intel_ring_begin(req
, 6);
227 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
229 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
230 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
231 intel_ring_emit(ring
, 0); /* low dword */
232 intel_ring_emit(ring
, 0); /* high dword */
233 intel_ring_emit(ring
, MI_NOOP
);
234 intel_ring_advance(ring
);
236 ret
= intel_ring_begin(req
, 6);
240 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
242 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
243 intel_ring_emit(ring
, 0);
244 intel_ring_emit(ring
, 0);
245 intel_ring_emit(ring
, MI_NOOP
);
246 intel_ring_advance(ring
);
252 gen6_render_ring_flush(struct drm_i915_gem_request
*req
,
253 u32 invalidate_domains
, u32 flush_domains
)
255 struct intel_engine_cs
*ring
= req
->ring
;
257 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
260 /* Force SNB workarounds for PIPE_CONTROL flushes */
261 ret
= intel_emit_post_sync_nonzero_flush(req
);
265 /* Just flush everything. Experiments have shown that reducing the
266 * number of bits based on the write domains has little performance
270 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
271 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
273 * Ensure that any following seqno writes only happen
274 * when the render cache is indeed flushed.
276 flags
|= PIPE_CONTROL_CS_STALL
;
278 if (invalidate_domains
) {
279 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
280 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
281 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
282 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
283 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
284 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
286 * TLB invalidate requires a post-sync write.
288 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
291 ret
= intel_ring_begin(req
, 4);
295 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
296 intel_ring_emit(ring
, flags
);
297 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
298 intel_ring_emit(ring
, 0);
299 intel_ring_advance(ring
);
305 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
307 struct intel_engine_cs
*ring
= req
->ring
;
310 ret
= intel_ring_begin(req
, 4);
314 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
315 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
316 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
317 intel_ring_emit(ring
, 0);
318 intel_ring_emit(ring
, 0);
319 intel_ring_advance(ring
);
325 gen7_render_ring_flush(struct drm_i915_gem_request
*req
,
326 u32 invalidate_domains
, u32 flush_domains
)
328 struct intel_engine_cs
*ring
= req
->ring
;
330 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
334 * Ensure that any following seqno writes only happen when the render
335 * cache is indeed flushed.
337 * Workaround: 4th PIPE_CONTROL command (except the ones with only
338 * read-cache invalidate bits set) must have the CS_STALL bit set. We
339 * don't try to be clever and just set it unconditionally.
341 flags
|= PIPE_CONTROL_CS_STALL
;
343 /* Just flush everything. Experiments have shown that reducing the
344 * number of bits based on the write domains has little performance
348 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
349 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
351 if (invalidate_domains
) {
352 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
353 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
354 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
355 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
356 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
357 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
358 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
360 * TLB invalidate requires a post-sync write.
362 flags
|= PIPE_CONTROL_QW_WRITE
;
363 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
365 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
367 /* Workaround: we must issue a pipe_control with CS-stall bit
368 * set before a pipe_control command that has the state cache
369 * invalidate bit set. */
370 gen7_render_ring_cs_stall_wa(req
);
373 ret
= intel_ring_begin(req
, 4);
377 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
378 intel_ring_emit(ring
, flags
);
379 intel_ring_emit(ring
, scratch_addr
);
380 intel_ring_emit(ring
, 0);
381 intel_ring_advance(ring
);
387 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
388 u32 flags
, u32 scratch_addr
)
390 struct intel_engine_cs
*ring
= req
->ring
;
393 ret
= intel_ring_begin(req
, 6);
397 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
398 intel_ring_emit(ring
, flags
);
399 intel_ring_emit(ring
, scratch_addr
);
400 intel_ring_emit(ring
, 0);
401 intel_ring_emit(ring
, 0);
402 intel_ring_emit(ring
, 0);
403 intel_ring_advance(ring
);
409 gen8_render_ring_flush(struct drm_i915_gem_request
*req
,
410 u32 invalidate_domains
, u32 flush_domains
)
413 u32 scratch_addr
= req
->ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
416 flags
|= PIPE_CONTROL_CS_STALL
;
419 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
420 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
422 if (invalidate_domains
) {
423 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
424 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
425 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
426 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
427 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
428 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
429 flags
|= PIPE_CONTROL_QW_WRITE
;
430 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
432 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
433 ret
= gen8_emit_pipe_control(req
,
434 PIPE_CONTROL_CS_STALL
|
435 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
441 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
444 static void ring_write_tail(struct intel_engine_cs
*ring
,
447 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
448 I915_WRITE_TAIL(ring
, value
);
451 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
453 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
456 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
457 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
458 RING_ACTHD_UDW(ring
->mmio_base
));
459 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
460 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
462 acthd
= I915_READ(ACTHD
);
467 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
469 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 addr
= dev_priv
->status_page_dmah
->busaddr
;
473 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
474 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
475 I915_WRITE(HWS_PGA
, addr
);
478 static void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
480 struct drm_device
*dev
= ring
->dev
;
481 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
484 /* The ring status page addresses are no longer next to the rest of
485 * the ring registers as of gen7.
490 mmio
= RENDER_HWS_PGA_GEN7
;
493 mmio
= BLT_HWS_PGA_GEN7
;
496 * VCS2 actually doesn't exist on Gen7. Only shut up
497 * gcc switch check warning
501 mmio
= BSD_HWS_PGA_GEN7
;
504 mmio
= VEBOX_HWS_PGA_GEN7
;
507 } else if (IS_GEN6(ring
->dev
)) {
508 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
510 /* XXX: gen8 returns to sanity */
511 mmio
= RING_HWS_PGA(ring
->mmio_base
);
514 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
518 * Flush the TLB for this page
520 * FIXME: These two bits have disappeared on gen8, so a question
521 * arises: do we still need this and if so how should we go about
522 * invalidating the TLB?
524 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
525 u32 reg
= RING_INSTPM(ring
->mmio_base
);
527 /* ring should be idle before issuing a sync flush*/
528 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
531 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
533 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
535 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
540 static bool stop_ring(struct intel_engine_cs
*ring
)
542 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
544 if (!IS_GEN2(ring
->dev
)) {
545 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
546 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
547 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
548 /* Sometimes we observe that the idle flag is not
549 * set even though the ring is empty. So double
550 * check before giving up.
552 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
557 I915_WRITE_CTL(ring
, 0);
558 I915_WRITE_HEAD(ring
, 0);
559 ring
->write_tail(ring
, 0);
561 if (!IS_GEN2(ring
->dev
)) {
562 (void)I915_READ_CTL(ring
);
563 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
566 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
569 static int init_ring_common(struct intel_engine_cs
*ring
)
571 struct drm_device
*dev
= ring
->dev
;
572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
573 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
574 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
577 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
579 if (!stop_ring(ring
)) {
580 /* G45 ring initialization often fails to reset head to zero */
581 DRM_DEBUG_KMS("%s head not reset to zero "
582 "ctl %08x head %08x tail %08x start %08x\n",
585 I915_READ_HEAD(ring
),
586 I915_READ_TAIL(ring
),
587 I915_READ_START(ring
));
589 if (!stop_ring(ring
)) {
590 DRM_ERROR("failed to set %s head to zero "
591 "ctl %08x head %08x tail %08x start %08x\n",
594 I915_READ_HEAD(ring
),
595 I915_READ_TAIL(ring
),
596 I915_READ_START(ring
));
602 if (I915_NEED_GFX_HWS(dev
))
603 intel_ring_setup_status_page(ring
);
605 ring_setup_phys_status_page(ring
);
607 /* Enforce ordering by reading HEAD register back */
608 I915_READ_HEAD(ring
);
610 /* Initialize the ring. This must happen _after_ we've cleared the ring
611 * registers with the above sequence (the readback of the HEAD registers
612 * also enforces ordering), otherwise the hw might lose the new ring
613 * register values. */
614 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
616 /* WaClearRingBufHeadRegAtInit:ctg,elk */
617 if (I915_READ_HEAD(ring
))
618 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
619 ring
->name
, I915_READ_HEAD(ring
));
620 I915_WRITE_HEAD(ring
, 0);
621 (void)I915_READ_HEAD(ring
);
624 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
627 /* If the head is still not zero, the ring is dead */
628 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
629 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
630 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
631 DRM_ERROR("%s initialization failed "
632 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
634 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
635 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
636 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
641 ringbuf
->last_retired_head
= -1;
642 ringbuf
->head
= I915_READ_HEAD(ring
);
643 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
644 intel_ring_update_space(ringbuf
);
646 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
649 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
655 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
657 struct drm_device
*dev
= ring
->dev
;
659 if (ring
->scratch
.obj
== NULL
)
662 if (INTEL_INFO(dev
)->gen
>= 5) {
663 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
664 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
667 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
668 ring
->scratch
.obj
= NULL
;
672 intel_init_pipe_control(struct intel_engine_cs
*ring
)
676 WARN_ON(ring
->scratch
.obj
);
678 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
679 if (ring
->scratch
.obj
== NULL
) {
680 DRM_ERROR("Failed to allocate seqno page\n");
685 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
689 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
693 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
694 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
695 if (ring
->scratch
.cpu_page
== NULL
) {
700 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
701 ring
->name
, ring
->scratch
.gtt_offset
);
705 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
707 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
712 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
715 struct intel_engine_cs
*ring
= req
->ring
;
716 struct drm_device
*dev
= ring
->dev
;
717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
718 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
720 if (WARN_ON_ONCE(w
->count
== 0))
723 ring
->gpu_caches_dirty
= true;
724 ret
= intel_ring_flush_all_caches(req
);
728 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
732 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
733 for (i
= 0; i
< w
->count
; i
++) {
734 intel_ring_emit(ring
, w
->reg
[i
].addr
);
735 intel_ring_emit(ring
, w
->reg
[i
].value
);
737 intel_ring_emit(ring
, MI_NOOP
);
739 intel_ring_advance(ring
);
741 ring
->gpu_caches_dirty
= true;
742 ret
= intel_ring_flush_all_caches(req
);
746 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
751 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
755 ret
= intel_ring_workarounds_emit(req
);
759 ret
= i915_gem_render_state_init(req
);
761 DRM_ERROR("init render state: %d\n", ret
);
766 static int wa_add(struct drm_i915_private
*dev_priv
,
767 const u32 addr
, const u32 mask
, const u32 val
)
769 const u32 idx
= dev_priv
->workarounds
.count
;
771 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
774 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
775 dev_priv
->workarounds
.reg
[idx
].value
= val
;
776 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
778 dev_priv
->workarounds
.count
++;
783 #define WA_REG(addr, mask, val) do { \
784 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
789 #define WA_SET_BIT_MASKED(addr, mask) \
790 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
792 #define WA_CLR_BIT_MASKED(addr, mask) \
793 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
795 #define WA_SET_FIELD_MASKED(addr, mask, value) \
796 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
798 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
799 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
801 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
803 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
805 struct drm_device
*dev
= ring
->dev
;
806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
808 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
810 /* WaDisableAsyncFlipPerfMode:bdw */
811 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
813 /* WaDisablePartialInstShootdown:bdw */
814 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
815 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
816 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
817 STALL_DOP_GATING_DISABLE
);
819 /* WaDisableDopClockGating:bdw */
820 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
821 DOP_CLOCK_GATING_DISABLE
);
823 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
824 GEN8_SAMPLER_POWER_BYPASS_DIS
);
826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
830 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
831 /* WaForceEnableNonCoherent:bdw */
832 HDC_FORCE_NON_COHERENT
|
833 /* WaForceContextSaveRestoreNonCoherent:bdw */
834 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
835 /* WaHdcDisableFetchWhenMasked:bdw */
836 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
837 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
838 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
840 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
841 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
842 * polygons in the same 8x4 pixel/sample area to be processed without
843 * stalling waiting for the earlier ones to write to Hierarchical Z
846 * This optimization is off by default for Broadwell; turn it on.
848 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
850 /* Wa4x4STCOptimizationDisable:bdw */
851 WA_SET_BIT_MASKED(CACHE_MODE_1
,
852 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
855 * BSpec recommends 8x4 when MSAA is used,
856 * however in practice 16x4 seems fastest.
858 * Note that PS/WM thread counts depend on the WIZ hashing
859 * disable bit, which we don't touch here, but it's good
860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
862 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
863 GEN6_WIZ_HASHING_MASK
,
864 GEN6_WIZ_HASHING_16x4
);
869 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
871 struct drm_device
*dev
= ring
->dev
;
872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
874 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
876 /* WaDisableAsyncFlipPerfMode:chv */
877 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
879 /* WaDisablePartialInstShootdown:chv */
880 /* WaDisableThreadStallDopClockGating:chv */
881 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
882 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
883 STALL_DOP_GATING_DISABLE
);
885 /* Use Force Non-Coherent whenever executing a 3D context. This is a
886 * workaround for a possible hang in the unlikely event a TLB
887 * invalidation occurs during a PSD flush.
889 /* WaForceEnableNonCoherent:chv */
890 /* WaHdcDisableFetchWhenMasked:chv */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
892 HDC_FORCE_NON_COHERENT
|
893 HDC_DONOT_FETCH_MEM_WHEN_MASKED
);
895 /* According to the CACHE_MODE_0 default value documentation, some
896 * CHV platforms disable this optimization by default. Turn it on.
898 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
900 /* Wa4x4STCOptimizationDisable:chv */
901 WA_SET_BIT_MASKED(CACHE_MODE_1
,
902 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
904 /* Improve HiZ throughput on CHV. */
905 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
908 * BSpec recommends 8x4 when MSAA is used,
909 * however in practice 16x4 seems fastest.
911 * Note that PS/WM thread counts depend on the WIZ hashing
912 * disable bit, which we don't touch here, but it's good
913 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
915 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
916 GEN6_WIZ_HASHING_MASK
,
917 GEN6_WIZ_HASHING_16x4
);
922 static int gen9_init_workarounds(struct intel_engine_cs
*ring
)
924 struct drm_device
*dev
= ring
->dev
;
925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 /* WaDisablePartialInstShootdown:skl,bxt */
929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
932 /* Syncing dependencies between camera and graphics:skl,bxt */
933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
936 if ((IS_SKYLAKE(dev
) && (INTEL_REVID(dev
) == SKL_REVID_A0
||
937 INTEL_REVID(dev
) == SKL_REVID_B0
)) ||
938 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
)) {
939 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
940 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
941 GEN9_DG_MIRROR_FIX_ENABLE
);
944 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) <= SKL_REVID_B0
) ||
945 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
)) {
946 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
947 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
948 GEN9_RHWO_OPTIMIZATION_DISABLE
);
950 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
951 * but we do that in per ctx batchbuffer as there is an issue
952 * with this register not getting restored on ctx restore
956 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) >= SKL_REVID_C0
) ||
958 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
959 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
960 GEN9_ENABLE_YV12_BUGFIX
);
963 /* Wa4x4STCOptimizationDisable:skl,bxt */
964 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
966 /* WaDisablePartialResolveInVc:skl,bxt */
967 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
);
969 /* WaCcsTlbPrefetchDisable:skl,bxt */
970 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
971 GEN9_CCS_TLB_PREFETCH_ENABLE
);
973 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
974 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) == SKL_REVID_C0
) ||
975 (IS_BROXTON(dev
) && INTEL_REVID(dev
) < BXT_REVID_B0
))
976 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
977 PIXEL_MASK_CAMMING_DISABLE
);
979 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
980 tmp
= HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
;
981 if ((IS_SKYLAKE(dev
) && INTEL_REVID(dev
) == SKL_REVID_F0
) ||
982 (IS_BROXTON(dev
) && INTEL_REVID(dev
) >= BXT_REVID_B0
))
983 tmp
|= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
;
984 WA_SET_BIT_MASKED(HDC_CHICKEN0
, tmp
);
989 static int skl_tune_iz_hashing(struct intel_engine_cs
*ring
)
991 struct drm_device
*dev
= ring
->dev
;
992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
993 u8 vals
[3] = { 0, 0, 0 };
996 for (i
= 0; i
< 3; i
++) {
1000 * Only consider slices where one, and only one, subslice has 7
1003 if (hweight8(dev_priv
->info
.subslice_7eu
[i
]) != 1)
1007 * subslice_7eu[i] != 0 (because of the check above) and
1008 * ss_max == 4 (maximum number of subslices possible per slice)
1012 ss
= ffs(dev_priv
->info
.subslice_7eu
[i
]) - 1;
1016 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
1019 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1020 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
1021 GEN9_IZ_HASHING_MASK(2) |
1022 GEN9_IZ_HASHING_MASK(1) |
1023 GEN9_IZ_HASHING_MASK(0),
1024 GEN9_IZ_HASHING(2, vals
[2]) |
1025 GEN9_IZ_HASHING(1, vals
[1]) |
1026 GEN9_IZ_HASHING(0, vals
[0]));
1032 static int skl_init_workarounds(struct intel_engine_cs
*ring
)
1034 struct drm_device
*dev
= ring
->dev
;
1035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1037 gen9_init_workarounds(ring
);
1039 /* WaDisablePowerCompilerClockGating:skl */
1040 if (INTEL_REVID(dev
) == SKL_REVID_B0
)
1041 WA_SET_BIT_MASKED(HIZ_CHICKEN
,
1042 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE
);
1044 if (INTEL_REVID(dev
) <= SKL_REVID_D0
) {
1046 *Use Force Non-Coherent whenever executing a 3D context. This
1047 * is a workaround for a possible hang in the unlikely event
1048 * a TLB invalidation occurs during a PSD flush.
1050 /* WaForceEnableNonCoherent:skl */
1051 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1052 HDC_FORCE_NON_COHERENT
);
1055 if (INTEL_REVID(dev
) == SKL_REVID_C0
||
1056 INTEL_REVID(dev
) == SKL_REVID_D0
)
1057 /* WaBarrierPerformanceFixDisable:skl */
1058 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1059 HDC_FENCE_DEST_SLM_DISABLE
|
1060 HDC_BARRIER_PERFORMANCE_DISABLE
);
1062 /* WaDisableSbeCacheDispatchPortSharing:skl */
1063 if (INTEL_REVID(dev
) <= SKL_REVID_F0
) {
1065 GEN7_HALF_SLICE_CHICKEN1
,
1066 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1069 return skl_tune_iz_hashing(ring
);
1072 static int bxt_init_workarounds(struct intel_engine_cs
*ring
)
1074 struct drm_device
*dev
= ring
->dev
;
1075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1077 gen9_init_workarounds(ring
);
1079 /* WaDisableThreadStallDopClockGating:bxt */
1080 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1081 STALL_DOP_GATING_DISABLE
);
1083 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1084 if (INTEL_REVID(dev
) <= BXT_REVID_B0
) {
1086 GEN7_HALF_SLICE_CHICKEN1
,
1087 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1093 int init_workarounds_ring(struct intel_engine_cs
*ring
)
1095 struct drm_device
*dev
= ring
->dev
;
1096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 WARN_ON(ring
->id
!= RCS
);
1100 dev_priv
->workarounds
.count
= 0;
1102 if (IS_BROADWELL(dev
))
1103 return bdw_init_workarounds(ring
);
1105 if (IS_CHERRYVIEW(dev
))
1106 return chv_init_workarounds(ring
);
1108 if (IS_SKYLAKE(dev
))
1109 return skl_init_workarounds(ring
);
1111 if (IS_BROXTON(dev
))
1112 return bxt_init_workarounds(ring
);
1117 static int init_render_ring(struct intel_engine_cs
*ring
)
1119 struct drm_device
*dev
= ring
->dev
;
1120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1121 int ret
= init_ring_common(ring
);
1125 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1126 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
1127 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1129 /* We need to disable the AsyncFlip performance optimisations in order
1130 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1131 * programmed to '1' on all products.
1133 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1135 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1136 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1138 /* Required for the hardware to program scanline values for waiting */
1139 /* WaEnableFlushTlbInvalidationMode:snb */
1140 if (INTEL_INFO(dev
)->gen
== 6)
1141 I915_WRITE(GFX_MODE
,
1142 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1144 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1146 I915_WRITE(GFX_MODE_GEN7
,
1147 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1148 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1151 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1152 * "If this bit is set, STCunit will have LRA as replacement
1153 * policy. [...] This bit must be reset. LRA replacement
1154 * policy is not supported."
1156 I915_WRITE(CACHE_MODE_0
,
1157 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1160 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8)
1161 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1163 if (HAS_L3_DPF(dev
))
1164 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1166 return init_workarounds_ring(ring
);
1169 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
1171 struct drm_device
*dev
= ring
->dev
;
1172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1174 if (dev_priv
->semaphore_obj
) {
1175 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
1176 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
1177 dev_priv
->semaphore_obj
= NULL
;
1180 intel_fini_pipe_control(ring
);
1183 static int gen8_rcs_signal(struct drm_i915_gem_request
*signaller_req
,
1184 unsigned int num_dwords
)
1186 #define MBOX_UPDATE_DWORDS 8
1187 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1188 struct drm_device
*dev
= signaller
->dev
;
1189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1190 struct intel_engine_cs
*waiter
;
1191 int i
, ret
, num_rings
;
1193 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1194 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1195 #undef MBOX_UPDATE_DWORDS
1197 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1201 for_each_ring(waiter
, dev_priv
, i
) {
1203 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1204 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1207 seqno
= i915_gem_request_get_seqno(signaller_req
);
1208 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
1209 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
1210 PIPE_CONTROL_QW_WRITE
|
1211 PIPE_CONTROL_FLUSH_ENABLE
);
1212 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
1213 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1214 intel_ring_emit(signaller
, seqno
);
1215 intel_ring_emit(signaller
, 0);
1216 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1217 MI_SEMAPHORE_TARGET(waiter
->id
));
1218 intel_ring_emit(signaller
, 0);
1224 static int gen8_xcs_signal(struct drm_i915_gem_request
*signaller_req
,
1225 unsigned int num_dwords
)
1227 #define MBOX_UPDATE_DWORDS 6
1228 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1229 struct drm_device
*dev
= signaller
->dev
;
1230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1231 struct intel_engine_cs
*waiter
;
1232 int i
, ret
, num_rings
;
1234 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1235 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
1236 #undef MBOX_UPDATE_DWORDS
1238 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1242 for_each_ring(waiter
, dev_priv
, i
) {
1244 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
1245 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1248 seqno
= i915_gem_request_get_seqno(signaller_req
);
1249 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
1250 MI_FLUSH_DW_OP_STOREDW
);
1251 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
1252 MI_FLUSH_DW_USE_GTT
);
1253 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
1254 intel_ring_emit(signaller
, seqno
);
1255 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
1256 MI_SEMAPHORE_TARGET(waiter
->id
));
1257 intel_ring_emit(signaller
, 0);
1263 static int gen6_signal(struct drm_i915_gem_request
*signaller_req
,
1264 unsigned int num_dwords
)
1266 struct intel_engine_cs
*signaller
= signaller_req
->ring
;
1267 struct drm_device
*dev
= signaller
->dev
;
1268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1269 struct intel_engine_cs
*useless
;
1270 int i
, ret
, num_rings
;
1272 #define MBOX_UPDATE_DWORDS 3
1273 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
1274 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
1275 #undef MBOX_UPDATE_DWORDS
1277 ret
= intel_ring_begin(signaller_req
, num_dwords
);
1281 for_each_ring(useless
, dev_priv
, i
) {
1282 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
1283 if (mbox_reg
!= GEN6_NOSYNC
) {
1284 u32 seqno
= i915_gem_request_get_seqno(signaller_req
);
1285 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
1286 intel_ring_emit(signaller
, mbox_reg
);
1287 intel_ring_emit(signaller
, seqno
);
1291 /* If num_dwords was rounded, make sure the tail pointer is correct */
1292 if (num_rings
% 2 == 0)
1293 intel_ring_emit(signaller
, MI_NOOP
);
1299 * gen6_add_request - Update the semaphore mailbox registers
1301 * @request - request to write to the ring
1303 * Update the mailbox registers in the *other* rings with the current seqno.
1304 * This acts like a signal in the canonical semaphore.
1307 gen6_add_request(struct drm_i915_gem_request
*req
)
1309 struct intel_engine_cs
*ring
= req
->ring
;
1312 if (ring
->semaphore
.signal
)
1313 ret
= ring
->semaphore
.signal(req
, 4);
1315 ret
= intel_ring_begin(req
, 4);
1320 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1321 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1322 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1323 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1324 __intel_ring_advance(ring
);
1329 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1333 return dev_priv
->last_seqno
< seqno
;
1337 * intel_ring_sync - sync the waiter to the signaller on seqno
1339 * @waiter - ring that is waiting
1340 * @signaller - ring which has, or will signal
1341 * @seqno - seqno which the waiter will block on
1345 gen8_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1346 struct intel_engine_cs
*signaller
,
1349 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1350 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1353 ret
= intel_ring_begin(waiter_req
, 4);
1357 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1358 MI_SEMAPHORE_GLOBAL_GTT
|
1360 MI_SEMAPHORE_SAD_GTE_SDD
);
1361 intel_ring_emit(waiter
, seqno
);
1362 intel_ring_emit(waiter
,
1363 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1364 intel_ring_emit(waiter
,
1365 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1366 intel_ring_advance(waiter
);
1371 gen6_ring_sync(struct drm_i915_gem_request
*waiter_req
,
1372 struct intel_engine_cs
*signaller
,
1375 struct intel_engine_cs
*waiter
= waiter_req
->ring
;
1376 u32 dw1
= MI_SEMAPHORE_MBOX
|
1377 MI_SEMAPHORE_COMPARE
|
1378 MI_SEMAPHORE_REGISTER
;
1379 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1382 /* Throughout all of the GEM code, seqno passed implies our current
1383 * seqno is >= the last seqno executed. However for hardware the
1384 * comparison is strictly greater than.
1388 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1390 ret
= intel_ring_begin(waiter_req
, 4);
1394 /* If seqno wrap happened, omit the wait with no-ops */
1395 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1396 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1397 intel_ring_emit(waiter
, seqno
);
1398 intel_ring_emit(waiter
, 0);
1399 intel_ring_emit(waiter
, MI_NOOP
);
1401 intel_ring_emit(waiter
, MI_NOOP
);
1402 intel_ring_emit(waiter
, MI_NOOP
);
1403 intel_ring_emit(waiter
, MI_NOOP
);
1404 intel_ring_emit(waiter
, MI_NOOP
);
1406 intel_ring_advance(waiter
);
1411 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1413 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1414 PIPE_CONTROL_DEPTH_STALL); \
1415 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1416 intel_ring_emit(ring__, 0); \
1417 intel_ring_emit(ring__, 0); \
1421 pc_render_add_request(struct drm_i915_gem_request
*req
)
1423 struct intel_engine_cs
*ring
= req
->ring
;
1424 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1427 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1428 * incoherent with writes to memory, i.e. completely fubar,
1429 * so we need to use PIPE_NOTIFY instead.
1431 * However, we also need to workaround the qword write
1432 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1433 * memory before requesting an interrupt.
1435 ret
= intel_ring_begin(req
, 32);
1439 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1440 PIPE_CONTROL_WRITE_FLUSH
|
1441 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1442 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1443 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1444 intel_ring_emit(ring
, 0);
1445 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1446 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1447 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1448 scratch_addr
+= 2 * CACHELINE_BYTES
;
1449 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1450 scratch_addr
+= 2 * CACHELINE_BYTES
;
1451 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1452 scratch_addr
+= 2 * CACHELINE_BYTES
;
1453 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1454 scratch_addr
+= 2 * CACHELINE_BYTES
;
1455 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1457 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1458 PIPE_CONTROL_WRITE_FLUSH
|
1459 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1460 PIPE_CONTROL_NOTIFY
);
1461 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1462 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1463 intel_ring_emit(ring
, 0);
1464 __intel_ring_advance(ring
);
1470 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1472 /* Workaround to force correct ordering between irq and seqno writes on
1473 * ivb (and maybe also on snb) by reading from a CS register (like
1474 * ACTHD) before reading the status page. */
1475 if (!lazy_coherency
) {
1476 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1477 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1480 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1484 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1486 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1490 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1492 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1496 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1498 return ring
->scratch
.cpu_page
[0];
1502 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1504 ring
->scratch
.cpu_page
[0] = seqno
;
1508 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1510 struct drm_device
*dev
= ring
->dev
;
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 unsigned long flags
;
1514 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1517 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1518 if (ring
->irq_refcount
++ == 0)
1519 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1520 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1526 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1528 struct drm_device
*dev
= ring
->dev
;
1529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1530 unsigned long flags
;
1532 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1533 if (--ring
->irq_refcount
== 0)
1534 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1535 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1539 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1541 struct drm_device
*dev
= ring
->dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 unsigned long flags
;
1545 if (!intel_irqs_enabled(dev_priv
))
1548 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1549 if (ring
->irq_refcount
++ == 0) {
1550 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1551 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1554 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1560 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1562 struct drm_device
*dev
= ring
->dev
;
1563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1564 unsigned long flags
;
1566 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1567 if (--ring
->irq_refcount
== 0) {
1568 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1569 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1572 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1576 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1578 struct drm_device
*dev
= ring
->dev
;
1579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1580 unsigned long flags
;
1582 if (!intel_irqs_enabled(dev_priv
))
1585 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1586 if (ring
->irq_refcount
++ == 0) {
1587 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1588 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1589 POSTING_READ16(IMR
);
1591 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1597 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1599 struct drm_device
*dev
= ring
->dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 unsigned long flags
;
1603 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1604 if (--ring
->irq_refcount
== 0) {
1605 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1606 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1607 POSTING_READ16(IMR
);
1609 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1613 bsd_ring_flush(struct drm_i915_gem_request
*req
,
1614 u32 invalidate_domains
,
1617 struct intel_engine_cs
*ring
= req
->ring
;
1620 ret
= intel_ring_begin(req
, 2);
1624 intel_ring_emit(ring
, MI_FLUSH
);
1625 intel_ring_emit(ring
, MI_NOOP
);
1626 intel_ring_advance(ring
);
1631 i9xx_add_request(struct drm_i915_gem_request
*req
)
1633 struct intel_engine_cs
*ring
= req
->ring
;
1636 ret
= intel_ring_begin(req
, 4);
1640 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1641 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1642 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1643 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1644 __intel_ring_advance(ring
);
1650 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1652 struct drm_device
*dev
= ring
->dev
;
1653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1654 unsigned long flags
;
1656 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1659 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1660 if (ring
->irq_refcount
++ == 0) {
1661 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1662 I915_WRITE_IMR(ring
,
1663 ~(ring
->irq_enable_mask
|
1664 GT_PARITY_ERROR(dev
)));
1666 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1667 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1669 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1675 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1677 struct drm_device
*dev
= ring
->dev
;
1678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1679 unsigned long flags
;
1681 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1682 if (--ring
->irq_refcount
== 0) {
1683 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1684 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1686 I915_WRITE_IMR(ring
, ~0);
1687 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1689 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1693 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1695 struct drm_device
*dev
= ring
->dev
;
1696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1697 unsigned long flags
;
1699 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1702 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1703 if (ring
->irq_refcount
++ == 0) {
1704 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1705 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1707 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1713 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1715 struct drm_device
*dev
= ring
->dev
;
1716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1717 unsigned long flags
;
1719 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1720 if (--ring
->irq_refcount
== 0) {
1721 I915_WRITE_IMR(ring
, ~0);
1722 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1724 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1728 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1730 struct drm_device
*dev
= ring
->dev
;
1731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1732 unsigned long flags
;
1734 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1737 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1738 if (ring
->irq_refcount
++ == 0) {
1739 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1740 I915_WRITE_IMR(ring
,
1741 ~(ring
->irq_enable_mask
|
1742 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1744 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1746 POSTING_READ(RING_IMR(ring
->mmio_base
));
1748 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1754 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1756 struct drm_device
*dev
= ring
->dev
;
1757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1758 unsigned long flags
;
1760 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1761 if (--ring
->irq_refcount
== 0) {
1762 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1763 I915_WRITE_IMR(ring
,
1764 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1766 I915_WRITE_IMR(ring
, ~0);
1768 POSTING_READ(RING_IMR(ring
->mmio_base
));
1770 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1774 i965_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1775 u64 offset
, u32 length
,
1776 unsigned dispatch_flags
)
1778 struct intel_engine_cs
*ring
= req
->ring
;
1781 ret
= intel_ring_begin(req
, 2);
1785 intel_ring_emit(ring
,
1786 MI_BATCH_BUFFER_START
|
1788 (dispatch_flags
& I915_DISPATCH_SECURE
?
1789 0 : MI_BATCH_NON_SECURE_I965
));
1790 intel_ring_emit(ring
, offset
);
1791 intel_ring_advance(ring
);
1796 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1797 #define I830_BATCH_LIMIT (256*1024)
1798 #define I830_TLB_ENTRIES (2)
1799 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1801 i830_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1802 u64 offset
, u32 len
,
1803 unsigned dispatch_flags
)
1805 struct intel_engine_cs
*ring
= req
->ring
;
1806 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1809 ret
= intel_ring_begin(req
, 6);
1813 /* Evict the invalid PTE TLBs */
1814 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1815 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1816 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1817 intel_ring_emit(ring
, cs_offset
);
1818 intel_ring_emit(ring
, 0xdeadbeef);
1819 intel_ring_emit(ring
, MI_NOOP
);
1820 intel_ring_advance(ring
);
1822 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1823 if (len
> I830_BATCH_LIMIT
)
1826 ret
= intel_ring_begin(req
, 6 + 2);
1830 /* Blit the batch (which has now all relocs applied) to the
1831 * stable batch scratch bo area (so that the CS never
1832 * stumbles over its tlb invalidation bug) ...
1834 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1835 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1836 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1837 intel_ring_emit(ring
, cs_offset
);
1838 intel_ring_emit(ring
, 4096);
1839 intel_ring_emit(ring
, offset
);
1841 intel_ring_emit(ring
, MI_FLUSH
);
1842 intel_ring_emit(ring
, MI_NOOP
);
1843 intel_ring_advance(ring
);
1845 /* ... and execute it. */
1849 ret
= intel_ring_begin(req
, 4);
1853 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1854 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1855 0 : MI_BATCH_NON_SECURE
));
1856 intel_ring_emit(ring
, offset
+ len
- 8);
1857 intel_ring_emit(ring
, MI_NOOP
);
1858 intel_ring_advance(ring
);
1864 i915_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
1865 u64 offset
, u32 len
,
1866 unsigned dispatch_flags
)
1868 struct intel_engine_cs
*ring
= req
->ring
;
1871 ret
= intel_ring_begin(req
, 2);
1875 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1876 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1877 0 : MI_BATCH_NON_SECURE
));
1878 intel_ring_advance(ring
);
1883 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1885 struct drm_i915_gem_object
*obj
;
1887 obj
= ring
->status_page
.obj
;
1891 kunmap(sg_page(obj
->pages
->sgl
));
1892 i915_gem_object_ggtt_unpin(obj
);
1893 drm_gem_object_unreference(&obj
->base
);
1894 ring
->status_page
.obj
= NULL
;
1897 static int init_status_page(struct intel_engine_cs
*ring
)
1899 struct drm_i915_gem_object
*obj
;
1901 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1905 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1907 DRM_ERROR("Failed to allocate status page\n");
1911 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1916 if (!HAS_LLC(ring
->dev
))
1917 /* On g33, we cannot place HWS above 256MiB, so
1918 * restrict its pinning to the low mappable arena.
1919 * Though this restriction is not documented for
1920 * gen4, gen5, or byt, they also behave similarly
1921 * and hang if the HWS is placed at the top of the
1922 * GTT. To generalise, it appears that all !llc
1923 * platforms have issues with us placing the HWS
1924 * above the mappable region (even though we never
1927 flags
|= PIN_MAPPABLE
;
1928 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1931 drm_gem_object_unreference(&obj
->base
);
1935 ring
->status_page
.obj
= obj
;
1938 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1939 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1940 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1942 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1943 ring
->name
, ring
->status_page
.gfx_addr
);
1948 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1950 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1952 if (!dev_priv
->status_page_dmah
) {
1953 dev_priv
->status_page_dmah
=
1954 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1955 if (!dev_priv
->status_page_dmah
)
1959 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1960 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1965 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1967 iounmap(ringbuf
->virtual_start
);
1968 ringbuf
->virtual_start
= NULL
;
1969 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1972 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
1973 struct intel_ringbuffer
*ringbuf
)
1975 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1976 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
1979 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1983 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1985 i915_gem_object_ggtt_unpin(obj
);
1989 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
1990 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
1991 if (ringbuf
->virtual_start
== NULL
) {
1992 i915_gem_object_ggtt_unpin(obj
);
1999 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
2001 drm_gem_object_unreference(&ringbuf
->obj
->base
);
2002 ringbuf
->obj
= NULL
;
2005 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
2006 struct intel_ringbuffer
*ringbuf
)
2008 struct drm_i915_gem_object
*obj
;
2012 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
2014 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
2018 /* mark ring buffers as read-only from GPU side by default */
2026 static int intel_init_ring_buffer(struct drm_device
*dev
,
2027 struct intel_engine_cs
*ring
)
2029 struct intel_ringbuffer
*ringbuf
;
2032 WARN_ON(ring
->buffer
);
2034 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
2037 ring
->buffer
= ringbuf
;
2040 INIT_LIST_HEAD(&ring
->active_list
);
2041 INIT_LIST_HEAD(&ring
->request_list
);
2042 INIT_LIST_HEAD(&ring
->execlist_queue
);
2043 i915_gem_batch_pool_init(dev
, &ring
->batch_pool
);
2044 ringbuf
->size
= 32 * PAGE_SIZE
;
2045 ringbuf
->ring
= ring
;
2046 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
2048 init_waitqueue_head(&ring
->irq_queue
);
2050 if (I915_NEED_GFX_HWS(dev
)) {
2051 ret
= init_status_page(ring
);
2055 BUG_ON(ring
->id
!= RCS
);
2056 ret
= init_phys_status_page(ring
);
2061 WARN_ON(ringbuf
->obj
);
2063 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
2065 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2070 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
2072 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2074 intel_destroy_ringbuffer_obj(ringbuf
);
2078 /* Workaround an erratum on the i830 which causes a hang if
2079 * the TAIL pointer points to within the last 2 cachelines
2082 ringbuf
->effective_size
= ringbuf
->size
;
2083 if (IS_I830(dev
) || IS_845G(dev
))
2084 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
2086 ret
= i915_cmd_parser_init_ring(ring
);
2094 ring
->buffer
= NULL
;
2098 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
2100 struct drm_i915_private
*dev_priv
;
2101 struct intel_ringbuffer
*ringbuf
;
2103 if (!intel_ring_initialized(ring
))
2106 dev_priv
= to_i915(ring
->dev
);
2107 ringbuf
= ring
->buffer
;
2109 intel_stop_ring_buffer(ring
);
2110 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
2112 intel_unpin_ringbuffer_obj(ringbuf
);
2113 intel_destroy_ringbuffer_obj(ringbuf
);
2116 ring
->cleanup(ring
);
2118 cleanup_status_page(ring
);
2120 i915_cmd_parser_fini_ring(ring
);
2121 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2124 ring
->buffer
= NULL
;
2127 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
2129 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2130 struct drm_i915_gem_request
*request
;
2134 if (intel_ring_space(ringbuf
) >= n
)
2137 /* The whole point of reserving space is to not wait! */
2138 WARN_ON(ringbuf
->reserved_in_use
);
2140 list_for_each_entry(request
, &ring
->request_list
, list
) {
2141 space
= __intel_ring_space(request
->postfix
, ringbuf
->tail
,
2147 if (WARN_ON(&request
->list
== &ring
->request_list
))
2150 ret
= i915_wait_request(request
);
2154 ringbuf
->space
= space
;
2158 static void __wrap_ring_buffer(struct intel_ringbuffer
*ringbuf
)
2160 uint32_t __iomem
*virt
;
2161 int rem
= ringbuf
->size
- ringbuf
->tail
;
2163 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2166 iowrite32(MI_NOOP
, virt
++);
2169 intel_ring_update_space(ringbuf
);
2172 int intel_ring_idle(struct intel_engine_cs
*ring
)
2174 struct drm_i915_gem_request
*req
;
2176 /* Wait upon the last request to be completed */
2177 if (list_empty(&ring
->request_list
))
2180 req
= list_entry(ring
->request_list
.prev
,
2181 struct drm_i915_gem_request
,
2184 /* Make sure we do not trigger any retires */
2185 return __i915_wait_request(req
,
2186 atomic_read(&to_i915(ring
->dev
)->gpu_error
.reset_counter
),
2187 to_i915(ring
->dev
)->mm
.interruptible
,
2191 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2193 request
->ringbuf
= request
->ring
->buffer
;
2197 int intel_ring_reserve_space(struct drm_i915_gem_request
*request
)
2200 * The first call merely notes the reserve request and is common for
2201 * all back ends. The subsequent localised _begin() call actually
2202 * ensures that the reservation is available. Without the begin, if
2203 * the request creator immediately submitted the request without
2204 * adding any commands to it then there might not actually be
2205 * sufficient room for the submission commands.
2207 intel_ring_reserved_space_reserve(request
->ringbuf
, MIN_SPACE_FOR_ADD_REQUEST
);
2209 return intel_ring_begin(request
, 0);
2212 void intel_ring_reserved_space_reserve(struct intel_ringbuffer
*ringbuf
, int size
)
2214 WARN_ON(ringbuf
->reserved_size
);
2215 WARN_ON(ringbuf
->reserved_in_use
);
2217 ringbuf
->reserved_size
= size
;
2220 void intel_ring_reserved_space_cancel(struct intel_ringbuffer
*ringbuf
)
2222 WARN_ON(ringbuf
->reserved_in_use
);
2224 ringbuf
->reserved_size
= 0;
2225 ringbuf
->reserved_in_use
= false;
2228 void intel_ring_reserved_space_use(struct intel_ringbuffer
*ringbuf
)
2230 WARN_ON(ringbuf
->reserved_in_use
);
2232 ringbuf
->reserved_in_use
= true;
2233 ringbuf
->reserved_tail
= ringbuf
->tail
;
2236 void intel_ring_reserved_space_end(struct intel_ringbuffer
*ringbuf
)
2238 WARN_ON(!ringbuf
->reserved_in_use
);
2239 if (ringbuf
->tail
> ringbuf
->reserved_tail
) {
2240 WARN(ringbuf
->tail
> ringbuf
->reserved_tail
+ ringbuf
->reserved_size
,
2241 "request reserved size too small: %d vs %d!\n",
2242 ringbuf
->tail
- ringbuf
->reserved_tail
, ringbuf
->reserved_size
);
2245 * The ring was wrapped while the reserved space was in use.
2246 * That means that some unknown amount of the ring tail was
2247 * no-op filled and skipped. Thus simply adding the ring size
2248 * to the tail and doing the above space check will not work.
2249 * Rather than attempt to track how much tail was skipped,
2250 * it is much simpler to say that also skipping the sanity
2251 * check every once in a while is not a big issue.
2255 ringbuf
->reserved_size
= 0;
2256 ringbuf
->reserved_in_use
= false;
2259 static int __intel_ring_prepare(struct intel_engine_cs
*ring
, int bytes
)
2261 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2262 int remain_usable
= ringbuf
->effective_size
- ringbuf
->tail
;
2263 int remain_actual
= ringbuf
->size
- ringbuf
->tail
;
2264 int ret
, total_bytes
, wait_bytes
= 0;
2265 bool need_wrap
= false;
2267 if (ringbuf
->reserved_in_use
)
2268 total_bytes
= bytes
;
2270 total_bytes
= bytes
+ ringbuf
->reserved_size
;
2272 if (unlikely(bytes
> remain_usable
)) {
2274 * Not enough space for the basic request. So need to flush
2275 * out the remainder and then wait for base + reserved.
2277 wait_bytes
= remain_actual
+ total_bytes
;
2280 if (unlikely(total_bytes
> remain_usable
)) {
2282 * The base request will fit but the reserved space
2283 * falls off the end. So only need to to wait for the
2284 * reserved size after flushing out the remainder.
2286 wait_bytes
= remain_actual
+ ringbuf
->reserved_size
;
2288 } else if (total_bytes
> ringbuf
->space
) {
2289 /* No wrapping required, just waiting. */
2290 wait_bytes
= total_bytes
;
2295 ret
= ring_wait_for_space(ring
, wait_bytes
);
2300 __wrap_ring_buffer(ringbuf
);
2306 int intel_ring_begin(struct drm_i915_gem_request
*req
,
2309 struct intel_engine_cs
*ring
;
2310 struct drm_i915_private
*dev_priv
;
2313 WARN_ON(req
== NULL
);
2315 dev_priv
= ring
->dev
->dev_private
;
2317 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2318 dev_priv
->mm
.interruptible
);
2322 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2326 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2330 /* Align the ring tail to a cacheline boundary */
2331 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2333 struct intel_engine_cs
*ring
= req
->ring
;
2334 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2337 if (num_dwords
== 0)
2340 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2341 ret
= intel_ring_begin(req
, num_dwords
);
2345 while (num_dwords
--)
2346 intel_ring_emit(ring
, MI_NOOP
);
2348 intel_ring_advance(ring
);
2353 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2355 struct drm_device
*dev
= ring
->dev
;
2356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2358 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2359 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2360 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2362 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2365 ring
->set_seqno(ring
, seqno
);
2366 ring
->hangcheck
.seqno
= seqno
;
2369 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2372 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2374 /* Every tail move must follow the sequence below */
2376 /* Disable notification that the ring is IDLE. The GT
2377 * will then assume that it is busy and bring it out of rc6.
2379 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2380 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2382 /* Clear the context id. Here be magic! */
2383 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2385 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2386 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2387 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2389 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2391 /* Now that the ring is fully powered up, update the tail */
2392 I915_WRITE_TAIL(ring
, value
);
2393 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2395 /* Let the ring send IDLE messages to the GT again,
2396 * and so let it sleep to conserve power when idle.
2398 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2399 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2402 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
,
2403 u32 invalidate
, u32 flush
)
2405 struct intel_engine_cs
*ring
= req
->ring
;
2409 ret
= intel_ring_begin(req
, 4);
2414 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2417 /* We always require a command barrier so that subsequent
2418 * commands, such as breadcrumb interrupts, are strictly ordered
2419 * wrt the contents of the write cache being flushed to memory
2420 * (and thus being coherent from the CPU).
2422 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2425 * Bspec vol 1c.5 - video engine command streamer:
2426 * "If ENABLED, all TLBs will be invalidated once the flush
2427 * operation is complete. This bit is only valid when the
2428 * Post-Sync Operation field is a value of 1h or 3h."
2430 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2431 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2433 intel_ring_emit(ring
, cmd
);
2434 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2435 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2436 intel_ring_emit(ring
, 0); /* upper addr */
2437 intel_ring_emit(ring
, 0); /* value */
2439 intel_ring_emit(ring
, 0);
2440 intel_ring_emit(ring
, MI_NOOP
);
2442 intel_ring_advance(ring
);
2447 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2448 u64 offset
, u32 len
,
2449 unsigned dispatch_flags
)
2451 struct intel_engine_cs
*ring
= req
->ring
;
2452 bool ppgtt
= USES_PPGTT(ring
->dev
) &&
2453 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2456 ret
= intel_ring_begin(req
, 4);
2460 /* FIXME(BDW): Address space and security selectors. */
2461 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2462 (dispatch_flags
& I915_DISPATCH_RS
?
2463 MI_BATCH_RESOURCE_STREAMER
: 0));
2464 intel_ring_emit(ring
, lower_32_bits(offset
));
2465 intel_ring_emit(ring
, upper_32_bits(offset
));
2466 intel_ring_emit(ring
, MI_NOOP
);
2467 intel_ring_advance(ring
);
2473 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2474 u64 offset
, u32 len
,
2475 unsigned dispatch_flags
)
2477 struct intel_engine_cs
*ring
= req
->ring
;
2480 ret
= intel_ring_begin(req
, 2);
2484 intel_ring_emit(ring
,
2485 MI_BATCH_BUFFER_START
|
2486 (dispatch_flags
& I915_DISPATCH_SECURE
?
2487 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2488 (dispatch_flags
& I915_DISPATCH_RS
?
2489 MI_BATCH_RESOURCE_STREAMER
: 0));
2490 /* bit0-7 is the length on GEN6+ */
2491 intel_ring_emit(ring
, offset
);
2492 intel_ring_advance(ring
);
2498 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request
*req
,
2499 u64 offset
, u32 len
,
2500 unsigned dispatch_flags
)
2502 struct intel_engine_cs
*ring
= req
->ring
;
2505 ret
= intel_ring_begin(req
, 2);
2509 intel_ring_emit(ring
,
2510 MI_BATCH_BUFFER_START
|
2511 (dispatch_flags
& I915_DISPATCH_SECURE
?
2512 0 : MI_BATCH_NON_SECURE_I965
));
2513 /* bit0-7 is the length on GEN6+ */
2514 intel_ring_emit(ring
, offset
);
2515 intel_ring_advance(ring
);
2520 /* Blitter support (SandyBridge+) */
2522 static int gen6_ring_flush(struct drm_i915_gem_request
*req
,
2523 u32 invalidate
, u32 flush
)
2525 struct intel_engine_cs
*ring
= req
->ring
;
2526 struct drm_device
*dev
= ring
->dev
;
2530 ret
= intel_ring_begin(req
, 4);
2535 if (INTEL_INFO(dev
)->gen
>= 8)
2538 /* We always require a command barrier so that subsequent
2539 * commands, such as breadcrumb interrupts, are strictly ordered
2540 * wrt the contents of the write cache being flushed to memory
2541 * (and thus being coherent from the CPU).
2543 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2546 * Bspec vol 1c.3 - blitter engine command streamer:
2547 * "If ENABLED, all TLBs will be invalidated once the flush
2548 * operation is complete. This bit is only valid when the
2549 * Post-Sync Operation field is a value of 1h or 3h."
2551 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2552 cmd
|= MI_INVALIDATE_TLB
;
2553 intel_ring_emit(ring
, cmd
);
2554 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2555 if (INTEL_INFO(dev
)->gen
>= 8) {
2556 intel_ring_emit(ring
, 0); /* upper addr */
2557 intel_ring_emit(ring
, 0); /* value */
2559 intel_ring_emit(ring
, 0);
2560 intel_ring_emit(ring
, MI_NOOP
);
2562 intel_ring_advance(ring
);
2567 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2570 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2571 struct drm_i915_gem_object
*obj
;
2574 ring
->name
= "render ring";
2576 ring
->mmio_base
= RENDER_RING_BASE
;
2578 if (INTEL_INFO(dev
)->gen
>= 8) {
2579 if (i915_semaphore_is_enabled(dev
)) {
2580 obj
= i915_gem_alloc_object(dev
, 4096);
2582 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2583 i915
.semaphores
= 0;
2585 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2586 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2588 drm_gem_object_unreference(&obj
->base
);
2589 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2590 i915
.semaphores
= 0;
2592 dev_priv
->semaphore_obj
= obj
;
2596 ring
->init_context
= intel_rcs_ctx_init
;
2597 ring
->add_request
= gen6_add_request
;
2598 ring
->flush
= gen8_render_ring_flush
;
2599 ring
->irq_get
= gen8_ring_get_irq
;
2600 ring
->irq_put
= gen8_ring_put_irq
;
2601 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2602 ring
->get_seqno
= gen6_ring_get_seqno
;
2603 ring
->set_seqno
= ring_set_seqno
;
2604 if (i915_semaphore_is_enabled(dev
)) {
2605 WARN_ON(!dev_priv
->semaphore_obj
);
2606 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2607 ring
->semaphore
.signal
= gen8_rcs_signal
;
2608 GEN8_RING_SEMAPHORE_INIT
;
2610 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2611 ring
->add_request
= gen6_add_request
;
2612 ring
->flush
= gen7_render_ring_flush
;
2613 if (INTEL_INFO(dev
)->gen
== 6)
2614 ring
->flush
= gen6_render_ring_flush
;
2615 ring
->irq_get
= gen6_ring_get_irq
;
2616 ring
->irq_put
= gen6_ring_put_irq
;
2617 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2618 ring
->get_seqno
= gen6_ring_get_seqno
;
2619 ring
->set_seqno
= ring_set_seqno
;
2620 if (i915_semaphore_is_enabled(dev
)) {
2621 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2622 ring
->semaphore
.signal
= gen6_signal
;
2624 * The current semaphore is only applied on pre-gen8
2625 * platform. And there is no VCS2 ring on the pre-gen8
2626 * platform. So the semaphore between RCS and VCS2 is
2627 * initialized as INVALID. Gen8 will initialize the
2628 * sema between VCS2 and RCS later.
2630 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2631 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2632 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2633 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2634 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2635 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2636 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2637 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2638 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2639 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2641 } else if (IS_GEN5(dev
)) {
2642 ring
->add_request
= pc_render_add_request
;
2643 ring
->flush
= gen4_render_ring_flush
;
2644 ring
->get_seqno
= pc_render_get_seqno
;
2645 ring
->set_seqno
= pc_render_set_seqno
;
2646 ring
->irq_get
= gen5_ring_get_irq
;
2647 ring
->irq_put
= gen5_ring_put_irq
;
2648 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2649 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2651 ring
->add_request
= i9xx_add_request
;
2652 if (INTEL_INFO(dev
)->gen
< 4)
2653 ring
->flush
= gen2_render_ring_flush
;
2655 ring
->flush
= gen4_render_ring_flush
;
2656 ring
->get_seqno
= ring_get_seqno
;
2657 ring
->set_seqno
= ring_set_seqno
;
2659 ring
->irq_get
= i8xx_ring_get_irq
;
2660 ring
->irq_put
= i8xx_ring_put_irq
;
2662 ring
->irq_get
= i9xx_ring_get_irq
;
2663 ring
->irq_put
= i9xx_ring_put_irq
;
2665 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2667 ring
->write_tail
= ring_write_tail
;
2669 if (IS_HASWELL(dev
))
2670 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2671 else if (IS_GEN8(dev
))
2672 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2673 else if (INTEL_INFO(dev
)->gen
>= 6)
2674 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2675 else if (INTEL_INFO(dev
)->gen
>= 4)
2676 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2677 else if (IS_I830(dev
) || IS_845G(dev
))
2678 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2680 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2681 ring
->init_hw
= init_render_ring
;
2682 ring
->cleanup
= render_ring_cleanup
;
2684 /* Workaround batchbuffer to combat CS tlb bug. */
2685 if (HAS_BROKEN_CS_TLB(dev
)) {
2686 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2688 DRM_ERROR("Failed to allocate batch bo\n");
2692 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2694 drm_gem_object_unreference(&obj
->base
);
2695 DRM_ERROR("Failed to ping batch bo\n");
2699 ring
->scratch
.obj
= obj
;
2700 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2703 ret
= intel_init_ring_buffer(dev
, ring
);
2707 if (INTEL_INFO(dev
)->gen
>= 5) {
2708 ret
= intel_init_pipe_control(ring
);
2716 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2719 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2721 ring
->name
= "bsd ring";
2724 ring
->write_tail
= ring_write_tail
;
2725 if (INTEL_INFO(dev
)->gen
>= 6) {
2726 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2727 /* gen6 bsd needs a special wa for tail updates */
2729 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2730 ring
->flush
= gen6_bsd_ring_flush
;
2731 ring
->add_request
= gen6_add_request
;
2732 ring
->get_seqno
= gen6_ring_get_seqno
;
2733 ring
->set_seqno
= ring_set_seqno
;
2734 if (INTEL_INFO(dev
)->gen
>= 8) {
2735 ring
->irq_enable_mask
=
2736 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2737 ring
->irq_get
= gen8_ring_get_irq
;
2738 ring
->irq_put
= gen8_ring_put_irq
;
2739 ring
->dispatch_execbuffer
=
2740 gen8_ring_dispatch_execbuffer
;
2741 if (i915_semaphore_is_enabled(dev
)) {
2742 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2743 ring
->semaphore
.signal
= gen8_xcs_signal
;
2744 GEN8_RING_SEMAPHORE_INIT
;
2747 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2748 ring
->irq_get
= gen6_ring_get_irq
;
2749 ring
->irq_put
= gen6_ring_put_irq
;
2750 ring
->dispatch_execbuffer
=
2751 gen6_ring_dispatch_execbuffer
;
2752 if (i915_semaphore_is_enabled(dev
)) {
2753 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2754 ring
->semaphore
.signal
= gen6_signal
;
2755 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2756 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2757 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2758 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2759 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2760 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2761 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2762 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2763 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2764 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2768 ring
->mmio_base
= BSD_RING_BASE
;
2769 ring
->flush
= bsd_ring_flush
;
2770 ring
->add_request
= i9xx_add_request
;
2771 ring
->get_seqno
= ring_get_seqno
;
2772 ring
->set_seqno
= ring_set_seqno
;
2774 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2775 ring
->irq_get
= gen5_ring_get_irq
;
2776 ring
->irq_put
= gen5_ring_put_irq
;
2778 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2779 ring
->irq_get
= i9xx_ring_get_irq
;
2780 ring
->irq_put
= i9xx_ring_put_irq
;
2782 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2784 ring
->init_hw
= init_ring_common
;
2786 return intel_init_ring_buffer(dev
, ring
);
2790 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2792 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2795 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2797 ring
->name
= "bsd2 ring";
2800 ring
->write_tail
= ring_write_tail
;
2801 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2802 ring
->flush
= gen6_bsd_ring_flush
;
2803 ring
->add_request
= gen6_add_request
;
2804 ring
->get_seqno
= gen6_ring_get_seqno
;
2805 ring
->set_seqno
= ring_set_seqno
;
2806 ring
->irq_enable_mask
=
2807 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2808 ring
->irq_get
= gen8_ring_get_irq
;
2809 ring
->irq_put
= gen8_ring_put_irq
;
2810 ring
->dispatch_execbuffer
=
2811 gen8_ring_dispatch_execbuffer
;
2812 if (i915_semaphore_is_enabled(dev
)) {
2813 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2814 ring
->semaphore
.signal
= gen8_xcs_signal
;
2815 GEN8_RING_SEMAPHORE_INIT
;
2817 ring
->init_hw
= init_ring_common
;
2819 return intel_init_ring_buffer(dev
, ring
);
2822 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2825 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2827 ring
->name
= "blitter ring";
2830 ring
->mmio_base
= BLT_RING_BASE
;
2831 ring
->write_tail
= ring_write_tail
;
2832 ring
->flush
= gen6_ring_flush
;
2833 ring
->add_request
= gen6_add_request
;
2834 ring
->get_seqno
= gen6_ring_get_seqno
;
2835 ring
->set_seqno
= ring_set_seqno
;
2836 if (INTEL_INFO(dev
)->gen
>= 8) {
2837 ring
->irq_enable_mask
=
2838 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2839 ring
->irq_get
= gen8_ring_get_irq
;
2840 ring
->irq_put
= gen8_ring_put_irq
;
2841 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2842 if (i915_semaphore_is_enabled(dev
)) {
2843 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2844 ring
->semaphore
.signal
= gen8_xcs_signal
;
2845 GEN8_RING_SEMAPHORE_INIT
;
2848 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2849 ring
->irq_get
= gen6_ring_get_irq
;
2850 ring
->irq_put
= gen6_ring_put_irq
;
2851 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2852 if (i915_semaphore_is_enabled(dev
)) {
2853 ring
->semaphore
.signal
= gen6_signal
;
2854 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2856 * The current semaphore is only applied on pre-gen8
2857 * platform. And there is no VCS2 ring on the pre-gen8
2858 * platform. So the semaphore between BCS and VCS2 is
2859 * initialized as INVALID. Gen8 will initialize the
2860 * sema between BCS and VCS2 later.
2862 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2863 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2864 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2865 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2866 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2867 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2868 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2869 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2870 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2871 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2874 ring
->init_hw
= init_ring_common
;
2876 return intel_init_ring_buffer(dev
, ring
);
2879 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2882 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2884 ring
->name
= "video enhancement ring";
2887 ring
->mmio_base
= VEBOX_RING_BASE
;
2888 ring
->write_tail
= ring_write_tail
;
2889 ring
->flush
= gen6_ring_flush
;
2890 ring
->add_request
= gen6_add_request
;
2891 ring
->get_seqno
= gen6_ring_get_seqno
;
2892 ring
->set_seqno
= ring_set_seqno
;
2894 if (INTEL_INFO(dev
)->gen
>= 8) {
2895 ring
->irq_enable_mask
=
2896 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2897 ring
->irq_get
= gen8_ring_get_irq
;
2898 ring
->irq_put
= gen8_ring_put_irq
;
2899 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2900 if (i915_semaphore_is_enabled(dev
)) {
2901 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2902 ring
->semaphore
.signal
= gen8_xcs_signal
;
2903 GEN8_RING_SEMAPHORE_INIT
;
2906 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2907 ring
->irq_get
= hsw_vebox_get_irq
;
2908 ring
->irq_put
= hsw_vebox_put_irq
;
2909 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2910 if (i915_semaphore_is_enabled(dev
)) {
2911 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2912 ring
->semaphore
.signal
= gen6_signal
;
2913 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2914 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2915 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2916 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2917 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2918 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2919 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2920 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2921 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2922 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2925 ring
->init_hw
= init_ring_common
;
2927 return intel_init_ring_buffer(dev
, ring
);
2931 intel_ring_flush_all_caches(struct drm_i915_gem_request
*req
)
2933 struct intel_engine_cs
*ring
= req
->ring
;
2936 if (!ring
->gpu_caches_dirty
)
2939 ret
= ring
->flush(req
, 0, I915_GEM_GPU_DOMAINS
);
2943 trace_i915_gem_ring_flush(req
, 0, I915_GEM_GPU_DOMAINS
);
2945 ring
->gpu_caches_dirty
= false;
2950 intel_ring_invalidate_all_caches(struct drm_i915_gem_request
*req
)
2952 struct intel_engine_cs
*ring
= req
->ring
;
2953 uint32_t flush_domains
;
2957 if (ring
->gpu_caches_dirty
)
2958 flush_domains
= I915_GEM_GPU_DOMAINS
;
2960 ret
= ring
->flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2964 trace_i915_gem_ring_flush(req
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2966 ring
->gpu_caches_dirty
= false;
2971 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2975 if (!intel_ring_initialized(ring
))
2978 ret
= intel_ring_idle(ring
);
2979 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2980 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",