2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object
*obj
;
43 volatile u32
*cpu_page
;
47 static inline int ring_space(struct intel_ring_buffer
*ring
)
49 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ 8);
56 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
57 u32 invalidate_domains
,
64 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
65 cmd
|= MI_NO_WRITE_FLUSH
;
67 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
70 ret
= intel_ring_begin(ring
, 2);
74 intel_ring_emit(ring
, cmd
);
75 intel_ring_emit(ring
, MI_NOOP
);
76 intel_ring_advance(ring
);
82 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
83 u32 invalidate_domains
,
86 struct drm_device
*dev
= ring
->dev
;
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
102 * I915_GEM_DOMAIN_COMMAND may not exist?
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
118 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
119 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
120 cmd
&= ~MI_NO_WRITE_FLUSH
;
121 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
124 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
125 (IS_G4X(dev
) || IS_GEN5(dev
)))
126 cmd
|= MI_INVALIDATE_ISP
;
128 ret
= intel_ring_begin(ring
, 2);
132 intel_ring_emit(ring
, cmd
);
133 intel_ring_emit(ring
, MI_NOOP
);
134 intel_ring_advance(ring
);
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
152 * And the workaround for these two requires this workaround first:
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
179 struct pipe_control
*pc
= ring
->private;
180 u32 scratch_addr
= pc
->gtt_offset
+ 128;
184 ret
= intel_ring_begin(ring
, 6);
188 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
190 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
191 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
192 intel_ring_emit(ring
, 0); /* low dword */
193 intel_ring_emit(ring
, 0); /* high dword */
194 intel_ring_emit(ring
, MI_NOOP
);
195 intel_ring_advance(ring
);
197 ret
= intel_ring_begin(ring
, 6);
201 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
203 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, 0);
206 intel_ring_emit(ring
, MI_NOOP
);
207 intel_ring_advance(ring
);
213 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
214 u32 invalidate_domains
, u32 flush_domains
)
217 struct pipe_control
*pc
= ring
->private;
218 u32 scratch_addr
= pc
->gtt_offset
+ 128;
221 /* Just flush everything. Experiments have shown that reducing the
222 * number of bits based on the write domains has little performance
226 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
227 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
229 * Ensure that any following seqno writes only happen
230 * when the render cache is indeed flushed.
232 flags
|= PIPE_CONTROL_CS_STALL
;
234 if (invalidate_domains
) {
235 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
236 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
237 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
238 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
239 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
240 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
242 * TLB invalidate requires a post-sync write.
244 flags
|= PIPE_CONTROL_QW_WRITE
;
247 ret
= intel_ring_begin(ring
, 4);
251 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
252 intel_ring_emit(ring
, flags
);
253 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
254 intel_ring_emit(ring
, 0);
255 intel_ring_advance(ring
);
261 gen6_render_ring_flush__wa(struct intel_ring_buffer
*ring
,
262 u32 invalidate_domains
, u32 flush_domains
)
266 /* Force SNB workarounds for PIPE_CONTROL flushes */
267 ret
= intel_emit_post_sync_nonzero_flush(ring
);
271 return gen6_render_ring_flush(ring
, invalidate_domains
, flush_domains
);
274 static void ring_write_tail(struct intel_ring_buffer
*ring
,
277 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
278 I915_WRITE_TAIL(ring
, value
);
281 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
283 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
284 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
285 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
287 return I915_READ(acthd_reg
);
290 static int init_ring_common(struct intel_ring_buffer
*ring
)
292 struct drm_device
*dev
= ring
->dev
;
293 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
294 struct drm_i915_gem_object
*obj
= ring
->obj
;
298 if (HAS_FORCE_WAKE(dev
))
299 gen6_gt_force_wake_get(dev_priv
);
301 /* Stop the ring if it's running. */
302 I915_WRITE_CTL(ring
, 0);
303 I915_WRITE_HEAD(ring
, 0);
304 ring
->write_tail(ring
, 0);
306 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
308 /* G45 ring initialization fails to reset head to zero */
310 DRM_DEBUG_KMS("%s head not reset to zero "
311 "ctl %08x head %08x tail %08x start %08x\n",
314 I915_READ_HEAD(ring
),
315 I915_READ_TAIL(ring
),
316 I915_READ_START(ring
));
318 I915_WRITE_HEAD(ring
, 0);
320 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
321 DRM_ERROR("failed to set %s head to zero "
322 "ctl %08x head %08x tail %08x start %08x\n",
325 I915_READ_HEAD(ring
),
326 I915_READ_TAIL(ring
),
327 I915_READ_START(ring
));
331 /* Initialize the ring. This must happen _after_ we've cleared the ring
332 * registers with the above sequence (the readback of the HEAD registers
333 * also enforces ordering), otherwise the hw might lose the new ring
334 * register values. */
335 I915_WRITE_START(ring
, obj
->gtt_offset
);
337 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
340 /* If the head is still not zero, the ring is dead */
341 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
342 I915_READ_START(ring
) == obj
->gtt_offset
&&
343 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
344 DRM_ERROR("%s initialization failed "
345 "ctl %08x head %08x tail %08x start %08x\n",
348 I915_READ_HEAD(ring
),
349 I915_READ_TAIL(ring
),
350 I915_READ_START(ring
));
355 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
356 i915_kernel_lost_context(ring
->dev
);
358 ring
->head
= I915_READ_HEAD(ring
);
359 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
360 ring
->space
= ring_space(ring
);
361 ring
->last_retired_head
= -1;
365 if (HAS_FORCE_WAKE(dev
))
366 gen6_gt_force_wake_put(dev_priv
);
372 init_pipe_control(struct intel_ring_buffer
*ring
)
374 struct pipe_control
*pc
;
375 struct drm_i915_gem_object
*obj
;
381 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
385 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
387 DRM_ERROR("Failed to allocate seqno page\n");
392 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
394 ret
= i915_gem_object_pin(obj
, 4096, true, false);
398 pc
->gtt_offset
= obj
->gtt_offset
;
399 pc
->cpu_page
= kmap(obj
->pages
[0]);
400 if (pc
->cpu_page
== NULL
)
408 i915_gem_object_unpin(obj
);
410 drm_gem_object_unreference(&obj
->base
);
417 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
419 struct pipe_control
*pc
= ring
->private;
420 struct drm_i915_gem_object
*obj
;
426 kunmap(obj
->pages
[0]);
427 i915_gem_object_unpin(obj
);
428 drm_gem_object_unreference(&obj
->base
);
431 ring
->private = NULL
;
434 static int init_render_ring(struct intel_ring_buffer
*ring
)
436 struct drm_device
*dev
= ring
->dev
;
437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
438 int ret
= init_ring_common(ring
);
440 if (INTEL_INFO(dev
)->gen
> 3) {
441 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
443 I915_WRITE(GFX_MODE_GEN7
,
444 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
445 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
448 if (INTEL_INFO(dev
)->gen
>= 5) {
449 ret
= init_pipe_control(ring
);
455 /* From the Sandybridge PRM, volume 1 part 3, page 24:
456 * "If this bit is set, STCunit will have LRA as replacement
457 * policy. [...] This bit must be reset. LRA replacement
458 * policy is not supported."
460 I915_WRITE(CACHE_MODE_0
,
461 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
463 /* This is not explicitly set for GEN6, so read the register.
464 * see intel_ring_mi_set_context() for why we care.
465 * TODO: consider explicitly setting the bit for GEN5
467 ring
->itlb_before_ctx_switch
=
468 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
471 if (INTEL_INFO(dev
)->gen
>= 6)
472 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
474 if (HAS_L3_GPU_CACHE(dev
))
475 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
480 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
485 cleanup_pipe_control(ring
);
489 update_mboxes(struct intel_ring_buffer
*ring
,
493 intel_ring_emit(ring
, MI_SEMAPHORE_MBOX
|
494 MI_SEMAPHORE_GLOBAL_GTT
|
495 MI_SEMAPHORE_REGISTER
|
496 MI_SEMAPHORE_UPDATE
);
497 intel_ring_emit(ring
, seqno
);
498 intel_ring_emit(ring
, mmio_offset
);
502 * gen6_add_request - Update the semaphore mailbox registers
504 * @ring - ring that is adding a request
505 * @seqno - return seqno stuck into the ring
507 * Update the mailbox registers in the *other* rings with the current seqno.
508 * This acts like a signal in the canonical semaphore.
511 gen6_add_request(struct intel_ring_buffer
*ring
,
518 ret
= intel_ring_begin(ring
, 10);
522 mbox1_reg
= ring
->signal_mbox
[0];
523 mbox2_reg
= ring
->signal_mbox
[1];
525 *seqno
= i915_gem_next_request_seqno(ring
);
527 update_mboxes(ring
, *seqno
, mbox1_reg
);
528 update_mboxes(ring
, *seqno
, mbox2_reg
);
529 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
530 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
531 intel_ring_emit(ring
, *seqno
);
532 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
533 intel_ring_advance(ring
);
539 * intel_ring_sync - sync the waiter to the signaller on seqno
541 * @waiter - ring that is waiting
542 * @signaller - ring which has, or will signal
543 * @seqno - seqno which the waiter will block on
546 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
547 struct intel_ring_buffer
*signaller
,
551 u32 dw1
= MI_SEMAPHORE_MBOX
|
552 MI_SEMAPHORE_COMPARE
|
553 MI_SEMAPHORE_REGISTER
;
555 /* Throughout all of the GEM code, seqno passed implies our current
556 * seqno is >= the last seqno executed. However for hardware the
557 * comparison is strictly greater than.
561 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
562 MI_SEMAPHORE_SYNC_INVALID
);
564 ret
= intel_ring_begin(waiter
, 4);
568 intel_ring_emit(waiter
,
569 dw1
| signaller
->semaphore_register
[waiter
->id
]);
570 intel_ring_emit(waiter
, seqno
);
571 intel_ring_emit(waiter
, 0);
572 intel_ring_emit(waiter
, MI_NOOP
);
573 intel_ring_advance(waiter
);
578 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
580 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
581 PIPE_CONTROL_DEPTH_STALL); \
582 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
583 intel_ring_emit(ring__, 0); \
584 intel_ring_emit(ring__, 0); \
588 pc_render_add_request(struct intel_ring_buffer
*ring
,
591 u32 seqno
= i915_gem_next_request_seqno(ring
);
592 struct pipe_control
*pc
= ring
->private;
593 u32 scratch_addr
= pc
->gtt_offset
+ 128;
596 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
597 * incoherent with writes to memory, i.e. completely fubar,
598 * so we need to use PIPE_NOTIFY instead.
600 * However, we also need to workaround the qword write
601 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
602 * memory before requesting an interrupt.
604 ret
= intel_ring_begin(ring
, 32);
608 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
609 PIPE_CONTROL_WRITE_FLUSH
|
610 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
611 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
612 intel_ring_emit(ring
, seqno
);
613 intel_ring_emit(ring
, 0);
614 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
615 scratch_addr
+= 128; /* write to separate cachelines */
616 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
618 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
620 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
622 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
624 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
626 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
627 PIPE_CONTROL_WRITE_FLUSH
|
628 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
629 PIPE_CONTROL_NOTIFY
);
630 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
631 intel_ring_emit(ring
, seqno
);
632 intel_ring_emit(ring
, 0);
633 intel_ring_advance(ring
);
640 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
642 /* Workaround to force correct ordering between irq and seqno writes on
643 * ivb (and maybe also on snb) by reading from a CS register (like
644 * ACTHD) before reading the status page. */
646 intel_ring_get_active_head(ring
);
647 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
651 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
653 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
657 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
659 struct pipe_control
*pc
= ring
->private;
660 return pc
->cpu_page
[0];
664 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
666 struct drm_device
*dev
= ring
->dev
;
667 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
670 if (!dev
->irq_enabled
)
673 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
674 if (ring
->irq_refcount
++ == 0) {
675 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
676 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
679 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
685 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
687 struct drm_device
*dev
= ring
->dev
;
688 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
691 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
692 if (--ring
->irq_refcount
== 0) {
693 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
694 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
697 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
701 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
703 struct drm_device
*dev
= ring
->dev
;
704 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
707 if (!dev
->irq_enabled
)
710 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
711 if (ring
->irq_refcount
++ == 0) {
712 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
713 I915_WRITE(IMR
, dev_priv
->irq_mask
);
716 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
722 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
724 struct drm_device
*dev
= ring
->dev
;
725 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
728 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
729 if (--ring
->irq_refcount
== 0) {
730 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
731 I915_WRITE(IMR
, dev_priv
->irq_mask
);
734 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
738 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
740 struct drm_device
*dev
= ring
->dev
;
741 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
744 if (!dev
->irq_enabled
)
747 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
748 if (ring
->irq_refcount
++ == 0) {
749 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
750 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
753 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
759 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
761 struct drm_device
*dev
= ring
->dev
;
762 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
765 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
766 if (--ring
->irq_refcount
== 0) {
767 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
768 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
771 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
774 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
776 struct drm_device
*dev
= ring
->dev
;
777 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
780 /* The ring status page addresses are no longer next to the rest of
781 * the ring registers as of gen7.
786 mmio
= RENDER_HWS_PGA_GEN7
;
789 mmio
= BLT_HWS_PGA_GEN7
;
792 mmio
= BSD_HWS_PGA_GEN7
;
795 } else if (IS_GEN6(ring
->dev
)) {
796 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
798 mmio
= RING_HWS_PGA(ring
->mmio_base
);
801 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
806 bsd_ring_flush(struct intel_ring_buffer
*ring
,
807 u32 invalidate_domains
,
812 ret
= intel_ring_begin(ring
, 2);
816 intel_ring_emit(ring
, MI_FLUSH
);
817 intel_ring_emit(ring
, MI_NOOP
);
818 intel_ring_advance(ring
);
823 i9xx_add_request(struct intel_ring_buffer
*ring
,
829 ret
= intel_ring_begin(ring
, 4);
833 seqno
= i915_gem_next_request_seqno(ring
);
835 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
836 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
837 intel_ring_emit(ring
, seqno
);
838 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
839 intel_ring_advance(ring
);
846 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
848 struct drm_device
*dev
= ring
->dev
;
849 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
852 if (!dev
->irq_enabled
)
855 /* It looks like we need to prevent the gt from suspending while waiting
856 * for an notifiy irq, otherwise irqs seem to get lost on at least the
857 * blt/bsd rings on ivb. */
858 gen6_gt_force_wake_get(dev_priv
);
860 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
861 if (ring
->irq_refcount
++ == 0) {
862 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
863 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
|
864 GEN6_RENDER_L3_PARITY_ERROR
));
866 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
867 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
868 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
871 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
877 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
879 struct drm_device
*dev
= ring
->dev
;
880 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
883 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
884 if (--ring
->irq_refcount
== 0) {
885 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
886 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
888 I915_WRITE_IMR(ring
, ~0);
889 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
890 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
893 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
895 gen6_gt_force_wake_put(dev_priv
);
899 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
, u32 offset
, u32 length
)
903 ret
= intel_ring_begin(ring
, 2);
907 intel_ring_emit(ring
,
908 MI_BATCH_BUFFER_START
|
910 MI_BATCH_NON_SECURE_I965
);
911 intel_ring_emit(ring
, offset
);
912 intel_ring_advance(ring
);
918 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
923 ret
= intel_ring_begin(ring
, 4);
927 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
928 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
929 intel_ring_emit(ring
, offset
+ len
- 8);
930 intel_ring_emit(ring
, 0);
931 intel_ring_advance(ring
);
937 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
942 ret
= intel_ring_begin(ring
, 2);
946 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
947 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
948 intel_ring_advance(ring
);
953 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
955 struct drm_i915_gem_object
*obj
;
957 obj
= ring
->status_page
.obj
;
961 kunmap(obj
->pages
[0]);
962 i915_gem_object_unpin(obj
);
963 drm_gem_object_unreference(&obj
->base
);
964 ring
->status_page
.obj
= NULL
;
967 static int init_status_page(struct intel_ring_buffer
*ring
)
969 struct drm_device
*dev
= ring
->dev
;
970 struct drm_i915_gem_object
*obj
;
973 obj
= i915_gem_alloc_object(dev
, 4096);
975 DRM_ERROR("Failed to allocate status page\n");
980 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
982 ret
= i915_gem_object_pin(obj
, 4096, true, false);
987 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
988 ring
->status_page
.page_addr
= kmap(obj
->pages
[0]);
989 if (ring
->status_page
.page_addr
== NULL
) {
993 ring
->status_page
.obj
= obj
;
994 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
996 intel_ring_setup_status_page(ring
);
997 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
998 ring
->name
, ring
->status_page
.gfx_addr
);
1003 i915_gem_object_unpin(obj
);
1005 drm_gem_object_unreference(&obj
->base
);
1010 static int intel_init_ring_buffer(struct drm_device
*dev
,
1011 struct intel_ring_buffer
*ring
)
1013 struct drm_i915_gem_object
*obj
;
1014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1018 INIT_LIST_HEAD(&ring
->active_list
);
1019 INIT_LIST_HEAD(&ring
->request_list
);
1020 ring
->size
= 32 * PAGE_SIZE
;
1022 init_waitqueue_head(&ring
->irq_queue
);
1024 if (I915_NEED_GFX_HWS(dev
)) {
1025 ret
= init_status_page(ring
);
1030 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1032 DRM_ERROR("Failed to allocate ringbuffer\n");
1039 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true, false);
1043 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1047 ring
->virtual_start
=
1048 ioremap_wc(dev_priv
->mm
.gtt
->gma_bus_addr
+ obj
->gtt_offset
,
1050 if (ring
->virtual_start
== NULL
) {
1051 DRM_ERROR("Failed to map ringbuffer.\n");
1056 ret
= ring
->init(ring
);
1060 /* Workaround an erratum on the i830 which causes a hang if
1061 * the TAIL pointer points to within the last 2 cachelines
1064 ring
->effective_size
= ring
->size
;
1065 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1066 ring
->effective_size
-= 128;
1071 iounmap(ring
->virtual_start
);
1073 i915_gem_object_unpin(obj
);
1075 drm_gem_object_unreference(&obj
->base
);
1078 cleanup_status_page(ring
);
1082 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1084 struct drm_i915_private
*dev_priv
;
1087 if (ring
->obj
== NULL
)
1090 /* Disable the ring buffer. The ring must be idle at this point */
1091 dev_priv
= ring
->dev
->dev_private
;
1092 ret
= intel_wait_ring_idle(ring
);
1094 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1097 I915_WRITE_CTL(ring
, 0);
1099 iounmap(ring
->virtual_start
);
1101 i915_gem_object_unpin(ring
->obj
);
1102 drm_gem_object_unreference(&ring
->obj
->base
);
1106 ring
->cleanup(ring
);
1108 cleanup_status_page(ring
);
1111 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1113 uint32_t __iomem
*virt
;
1114 int rem
= ring
->size
- ring
->tail
;
1116 if (ring
->space
< rem
) {
1117 int ret
= intel_wait_ring_buffer(ring
, rem
);
1122 virt
= ring
->virtual_start
+ ring
->tail
;
1125 iowrite32(MI_NOOP
, virt
++);
1128 ring
->space
= ring_space(ring
);
1133 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1137 ret
= i915_wait_seqno(ring
, seqno
);
1139 i915_gem_retire_requests_ring(ring
);
1144 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1146 struct drm_i915_gem_request
*request
;
1150 i915_gem_retire_requests_ring(ring
);
1152 if (ring
->last_retired_head
!= -1) {
1153 ring
->head
= ring
->last_retired_head
;
1154 ring
->last_retired_head
= -1;
1155 ring
->space
= ring_space(ring
);
1156 if (ring
->space
>= n
)
1160 list_for_each_entry(request
, &ring
->request_list
, list
) {
1163 if (request
->tail
== -1)
1166 space
= request
->tail
- (ring
->tail
+ 8);
1168 space
+= ring
->size
;
1170 seqno
= request
->seqno
;
1174 /* Consume this request in case we need more space than
1175 * is available and so need to prevent a race between
1176 * updating last_retired_head and direct reads of
1177 * I915_RING_HEAD. It also provides a nice sanity check.
1185 ret
= intel_ring_wait_seqno(ring
, seqno
);
1189 if (WARN_ON(ring
->last_retired_head
== -1))
1192 ring
->head
= ring
->last_retired_head
;
1193 ring
->last_retired_head
= -1;
1194 ring
->space
= ring_space(ring
);
1195 if (WARN_ON(ring
->space
< n
))
1201 int intel_wait_ring_buffer(struct intel_ring_buffer
*ring
, int n
)
1203 struct drm_device
*dev
= ring
->dev
;
1204 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1208 ret
= intel_ring_wait_request(ring
, n
);
1212 trace_i915_ring_wait_begin(ring
);
1213 /* With GEM the hangcheck timer should kick us out of the loop,
1214 * leaving it early runs the risk of corrupting GEM state (due
1215 * to running on almost untested codepaths). But on resume
1216 * timers don't work yet, so prevent a complete hang in that
1217 * case by choosing an insanely large timeout. */
1218 end
= jiffies
+ 60 * HZ
;
1221 ring
->head
= I915_READ_HEAD(ring
);
1222 ring
->space
= ring_space(ring
);
1223 if (ring
->space
>= n
) {
1224 trace_i915_ring_wait_end(ring
);
1228 if (dev
->primary
->master
) {
1229 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1230 if (master_priv
->sarea_priv
)
1231 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1236 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1239 } while (!time_after(jiffies
, end
));
1240 trace_i915_ring_wait_end(ring
);
1244 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1247 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1248 int n
= 4*num_dwords
;
1251 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1255 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1256 ret
= intel_wrap_ring_buffer(ring
);
1261 if (unlikely(ring
->space
< n
)) {
1262 ret
= intel_wait_ring_buffer(ring
, n
);
1271 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1273 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1275 ring
->tail
&= ring
->size
- 1;
1276 if (dev_priv
->stop_rings
& intel_ring_flag(ring
))
1278 ring
->write_tail(ring
, ring
->tail
);
1282 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1285 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1287 /* Every tail move must follow the sequence below */
1289 /* Disable notification that the ring is IDLE. The GT
1290 * will then assume that it is busy and bring it out of rc6.
1292 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1293 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1295 /* Clear the context id. Here be magic! */
1296 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1298 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1299 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1300 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1302 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1304 /* Now that the ring is fully powered up, update the tail */
1305 I915_WRITE_TAIL(ring
, value
);
1306 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1308 /* Let the ring send IDLE messages to the GT again,
1309 * and so let it sleep to conserve power when idle.
1311 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1312 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1315 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1316 u32 invalidate
, u32 flush
)
1321 ret
= intel_ring_begin(ring
, 4);
1326 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1327 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
1328 intel_ring_emit(ring
, cmd
);
1329 intel_ring_emit(ring
, 0);
1330 intel_ring_emit(ring
, 0);
1331 intel_ring_emit(ring
, MI_NOOP
);
1332 intel_ring_advance(ring
);
1337 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1338 u32 offset
, u32 len
)
1342 ret
= intel_ring_begin(ring
, 2);
1346 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
);
1347 /* bit0-7 is the length on GEN6+ */
1348 intel_ring_emit(ring
, offset
);
1349 intel_ring_advance(ring
);
1354 /* Blitter support (SandyBridge+) */
1356 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1357 u32 invalidate
, u32 flush
)
1362 ret
= intel_ring_begin(ring
, 4);
1367 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1368 cmd
|= MI_INVALIDATE_TLB
;
1369 intel_ring_emit(ring
, cmd
);
1370 intel_ring_emit(ring
, 0);
1371 intel_ring_emit(ring
, 0);
1372 intel_ring_emit(ring
, MI_NOOP
);
1373 intel_ring_advance(ring
);
1377 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1379 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1380 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1382 ring
->name
= "render ring";
1384 ring
->mmio_base
= RENDER_RING_BASE
;
1386 if (INTEL_INFO(dev
)->gen
>= 6) {
1387 ring
->add_request
= gen6_add_request
;
1388 ring
->flush
= gen6_render_ring_flush
;
1389 if (INTEL_INFO(dev
)->gen
== 6)
1390 ring
->flush
= gen6_render_ring_flush__wa
;
1391 ring
->irq_get
= gen6_ring_get_irq
;
1392 ring
->irq_put
= gen6_ring_put_irq
;
1393 ring
->irq_enable_mask
= GT_USER_INTERRUPT
;
1394 ring
->get_seqno
= gen6_ring_get_seqno
;
1395 ring
->sync_to
= gen6_ring_sync
;
1396 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_INVALID
;
1397 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_RV
;
1398 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_RB
;
1399 ring
->signal_mbox
[0] = GEN6_VRSYNC
;
1400 ring
->signal_mbox
[1] = GEN6_BRSYNC
;
1401 } else if (IS_GEN5(dev
)) {
1402 ring
->add_request
= pc_render_add_request
;
1403 ring
->flush
= gen4_render_ring_flush
;
1404 ring
->get_seqno
= pc_render_get_seqno
;
1405 ring
->irq_get
= gen5_ring_get_irq
;
1406 ring
->irq_put
= gen5_ring_put_irq
;
1407 ring
->irq_enable_mask
= GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
;
1409 ring
->add_request
= i9xx_add_request
;
1410 if (INTEL_INFO(dev
)->gen
< 4)
1411 ring
->flush
= gen2_render_ring_flush
;
1413 ring
->flush
= gen4_render_ring_flush
;
1414 ring
->get_seqno
= ring_get_seqno
;
1416 ring
->irq_get
= i8xx_ring_get_irq
;
1417 ring
->irq_put
= i8xx_ring_put_irq
;
1419 ring
->irq_get
= i9xx_ring_get_irq
;
1420 ring
->irq_put
= i9xx_ring_put_irq
;
1422 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1424 ring
->write_tail
= ring_write_tail
;
1425 if (INTEL_INFO(dev
)->gen
>= 6)
1426 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1427 else if (INTEL_INFO(dev
)->gen
>= 4)
1428 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1429 else if (IS_I830(dev
) || IS_845G(dev
))
1430 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1432 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1433 ring
->init
= init_render_ring
;
1434 ring
->cleanup
= render_ring_cleanup
;
1437 if (!I915_NEED_GFX_HWS(dev
)) {
1438 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1439 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1442 return intel_init_ring_buffer(dev
, ring
);
1445 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1447 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1448 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1450 ring
->name
= "render ring";
1452 ring
->mmio_base
= RENDER_RING_BASE
;
1454 if (INTEL_INFO(dev
)->gen
>= 6) {
1455 /* non-kms not supported on gen6+ */
1459 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1460 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1461 * the special gen5 functions. */
1462 ring
->add_request
= i9xx_add_request
;
1463 if (INTEL_INFO(dev
)->gen
< 4)
1464 ring
->flush
= gen2_render_ring_flush
;
1466 ring
->flush
= gen4_render_ring_flush
;
1467 ring
->get_seqno
= ring_get_seqno
;
1469 ring
->irq_get
= i8xx_ring_get_irq
;
1470 ring
->irq_put
= i8xx_ring_put_irq
;
1472 ring
->irq_get
= i9xx_ring_get_irq
;
1473 ring
->irq_put
= i9xx_ring_put_irq
;
1475 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1476 ring
->write_tail
= ring_write_tail
;
1477 if (INTEL_INFO(dev
)->gen
>= 4)
1478 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1479 else if (IS_I830(dev
) || IS_845G(dev
))
1480 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1482 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1483 ring
->init
= init_render_ring
;
1484 ring
->cleanup
= render_ring_cleanup
;
1486 if (!I915_NEED_GFX_HWS(dev
))
1487 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1490 INIT_LIST_HEAD(&ring
->active_list
);
1491 INIT_LIST_HEAD(&ring
->request_list
);
1494 ring
->effective_size
= ring
->size
;
1495 if (IS_I830(ring
->dev
))
1496 ring
->effective_size
-= 128;
1498 ring
->virtual_start
= ioremap_wc(start
, size
);
1499 if (ring
->virtual_start
== NULL
) {
1500 DRM_ERROR("can not ioremap virtual address for"
1508 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1513 ring
->name
= "bsd ring";
1516 ring
->write_tail
= ring_write_tail
;
1517 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1518 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1519 /* gen6 bsd needs a special wa for tail updates */
1521 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1522 ring
->flush
= gen6_ring_flush
;
1523 ring
->add_request
= gen6_add_request
;
1524 ring
->get_seqno
= gen6_ring_get_seqno
;
1525 ring
->irq_enable_mask
= GEN6_BSD_USER_INTERRUPT
;
1526 ring
->irq_get
= gen6_ring_get_irq
;
1527 ring
->irq_put
= gen6_ring_put_irq
;
1528 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1529 ring
->sync_to
= gen6_ring_sync
;
1530 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_VR
;
1531 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_INVALID
;
1532 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_VB
;
1533 ring
->signal_mbox
[0] = GEN6_RVSYNC
;
1534 ring
->signal_mbox
[1] = GEN6_BVSYNC
;
1536 ring
->mmio_base
= BSD_RING_BASE
;
1537 ring
->flush
= bsd_ring_flush
;
1538 ring
->add_request
= i9xx_add_request
;
1539 ring
->get_seqno
= ring_get_seqno
;
1541 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1542 ring
->irq_get
= gen5_ring_get_irq
;
1543 ring
->irq_put
= gen5_ring_put_irq
;
1545 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1546 ring
->irq_get
= i9xx_ring_get_irq
;
1547 ring
->irq_put
= i9xx_ring_put_irq
;
1549 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1551 ring
->init
= init_ring_common
;
1554 return intel_init_ring_buffer(dev
, ring
);
1557 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1559 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1560 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1562 ring
->name
= "blitter ring";
1565 ring
->mmio_base
= BLT_RING_BASE
;
1566 ring
->write_tail
= ring_write_tail
;
1567 ring
->flush
= blt_ring_flush
;
1568 ring
->add_request
= gen6_add_request
;
1569 ring
->get_seqno
= gen6_ring_get_seqno
;
1570 ring
->irq_enable_mask
= GEN6_BLITTER_USER_INTERRUPT
;
1571 ring
->irq_get
= gen6_ring_get_irq
;
1572 ring
->irq_put
= gen6_ring_put_irq
;
1573 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1574 ring
->sync_to
= gen6_ring_sync
;
1575 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_BR
;
1576 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_BV
;
1577 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_INVALID
;
1578 ring
->signal_mbox
[0] = GEN6_RBSYNC
;
1579 ring
->signal_mbox
[1] = GEN6_VBSYNC
;
1580 ring
->init
= init_ring_common
;
1582 return intel_init_ring_buffer(dev
, ring
);
1586 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
1590 if (!ring
->gpu_caches_dirty
)
1593 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1597 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1599 ring
->gpu_caches_dirty
= false;
1604 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
1606 uint32_t flush_domains
;
1610 if (ring
->gpu_caches_dirty
)
1611 flush_domains
= I915_GEM_GPU_DOMAINS
;
1613 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1617 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1619 ring
->gpu_caches_dirty
= false;