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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
286 {
287 u32 flags = 0;
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
290 int ret;
291
292 /*
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
295 *
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
299 */
300 flags |= PIPE_CONTROL_CS_STALL;
301
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
304 * impact.
305 */
306 if (flush_domains) {
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
309 }
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
317 /*
318 * TLB invalidate requires a post-sync write.
319 */
320 flags |= PIPE_CONTROL_QW_WRITE;
321
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring);
326 }
327
328 ret = intel_ring_begin(ring, 4);
329 if (ret)
330 return ret;
331
332 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring, flags);
334 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
335 intel_ring_emit(ring, 0);
336 intel_ring_advance(ring);
337
338 return 0;
339 }
340
341 static void ring_write_tail(struct intel_ring_buffer *ring,
342 u32 value)
343 {
344 drm_i915_private_t *dev_priv = ring->dev->dev_private;
345 I915_WRITE_TAIL(ring, value);
346 }
347
348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
349 {
350 drm_i915_private_t *dev_priv = ring->dev->dev_private;
351 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
352 RING_ACTHD(ring->mmio_base) : ACTHD;
353
354 return I915_READ(acthd_reg);
355 }
356
357 static int init_ring_common(struct intel_ring_buffer *ring)
358 {
359 struct drm_device *dev = ring->dev;
360 drm_i915_private_t *dev_priv = dev->dev_private;
361 struct drm_i915_gem_object *obj = ring->obj;
362 int ret = 0;
363 u32 head;
364
365 if (HAS_FORCE_WAKE(dev))
366 gen6_gt_force_wake_get(dev_priv);
367
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring, 0);
370 I915_WRITE_HEAD(ring, 0);
371 ring->write_tail(ring, 0);
372
373 head = I915_READ_HEAD(ring) & HEAD_ADDR;
374
375 /* G45 ring initialization fails to reset head to zero */
376 if (head != 0) {
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
379 ring->name,
380 I915_READ_CTL(ring),
381 I915_READ_HEAD(ring),
382 I915_READ_TAIL(ring),
383 I915_READ_START(ring));
384
385 I915_WRITE_HEAD(ring, 0);
386
387 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
390 ring->name,
391 I915_READ_CTL(ring),
392 I915_READ_HEAD(ring),
393 I915_READ_TAIL(ring),
394 I915_READ_START(ring));
395 }
396 }
397
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring, obj->gtt_offset);
403 I915_WRITE_CTL(ring,
404 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
405 | RING_VALID);
406
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
409 I915_READ_START(ring) == obj->gtt_offset &&
410 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
413 ring->name,
414 I915_READ_CTL(ring),
415 I915_READ_HEAD(ring),
416 I915_READ_TAIL(ring),
417 I915_READ_START(ring));
418 ret = -EIO;
419 goto out;
420 }
421
422 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
423 i915_kernel_lost_context(ring->dev);
424 else {
425 ring->head = I915_READ_HEAD(ring);
426 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
427 ring->space = ring_space(ring);
428 ring->last_retired_head = -1;
429 }
430
431 out:
432 if (HAS_FORCE_WAKE(dev))
433 gen6_gt_force_wake_put(dev_priv);
434
435 return ret;
436 }
437
438 static int
439 init_pipe_control(struct intel_ring_buffer *ring)
440 {
441 struct pipe_control *pc;
442 struct drm_i915_gem_object *obj;
443 int ret;
444
445 if (ring->private)
446 return 0;
447
448 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
449 if (!pc)
450 return -ENOMEM;
451
452 obj = i915_gem_alloc_object(ring->dev, 4096);
453 if (obj == NULL) {
454 DRM_ERROR("Failed to allocate seqno page\n");
455 ret = -ENOMEM;
456 goto err;
457 }
458
459 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
460
461 ret = i915_gem_object_pin(obj, 4096, true, false);
462 if (ret)
463 goto err_unref;
464
465 pc->gtt_offset = obj->gtt_offset;
466 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
467 if (pc->cpu_page == NULL)
468 goto err_unpin;
469
470 pc->obj = obj;
471 ring->private = pc;
472 return 0;
473
474 err_unpin:
475 i915_gem_object_unpin(obj);
476 err_unref:
477 drm_gem_object_unreference(&obj->base);
478 err:
479 kfree(pc);
480 return ret;
481 }
482
483 static void
484 cleanup_pipe_control(struct intel_ring_buffer *ring)
485 {
486 struct pipe_control *pc = ring->private;
487 struct drm_i915_gem_object *obj;
488
489 if (!ring->private)
490 return;
491
492 obj = pc->obj;
493
494 kunmap(sg_page(obj->pages->sgl));
495 i915_gem_object_unpin(obj);
496 drm_gem_object_unreference(&obj->base);
497
498 kfree(pc);
499 ring->private = NULL;
500 }
501
502 static int init_render_ring(struct intel_ring_buffer *ring)
503 {
504 struct drm_device *dev = ring->dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring);
507
508 if (INTEL_INFO(dev)->gen > 3) {
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
510 if (IS_GEN7(dev))
511 I915_WRITE(GFX_MODE_GEN7,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
514 }
515
516 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring);
518 if (ret)
519 return ret;
520 }
521
522 if (IS_GEN6(dev)) {
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
527 */
528 I915_WRITE(CACHE_MODE_0,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
530
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
534 */
535 ring->itlb_before_ctx_switch =
536 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
537 }
538
539 if (INTEL_INFO(dev)->gen >= 6)
540 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
541
542 if (HAS_L3_GPU_CACHE(dev))
543 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
544
545 return ret;
546 }
547
548 static void render_ring_cleanup(struct intel_ring_buffer *ring)
549 {
550 if (!ring->private)
551 return;
552
553 cleanup_pipe_control(ring);
554 }
555
556 static void
557 update_mboxes(struct intel_ring_buffer *ring,
558 u32 mmio_offset)
559 {
560 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
561 intel_ring_emit(ring, mmio_offset);
562 intel_ring_emit(ring, ring->outstanding_lazy_request);
563 }
564
565 /**
566 * gen6_add_request - Update the semaphore mailbox registers
567 *
568 * @ring - ring that is adding a request
569 * @seqno - return seqno stuck into the ring
570 *
571 * Update the mailbox registers in the *other* rings with the current seqno.
572 * This acts like a signal in the canonical semaphore.
573 */
574 static int
575 gen6_add_request(struct intel_ring_buffer *ring)
576 {
577 u32 mbox1_reg;
578 u32 mbox2_reg;
579 int ret;
580
581 ret = intel_ring_begin(ring, 10);
582 if (ret)
583 return ret;
584
585 mbox1_reg = ring->signal_mbox[0];
586 mbox2_reg = ring->signal_mbox[1];
587
588 update_mboxes(ring, mbox1_reg);
589 update_mboxes(ring, mbox2_reg);
590 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
591 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
592 intel_ring_emit(ring, ring->outstanding_lazy_request);
593 intel_ring_emit(ring, MI_USER_INTERRUPT);
594 intel_ring_advance(ring);
595
596 return 0;
597 }
598
599 /**
600 * intel_ring_sync - sync the waiter to the signaller on seqno
601 *
602 * @waiter - ring that is waiting
603 * @signaller - ring which has, or will signal
604 * @seqno - seqno which the waiter will block on
605 */
606 static int
607 gen6_ring_sync(struct intel_ring_buffer *waiter,
608 struct intel_ring_buffer *signaller,
609 u32 seqno)
610 {
611 int ret;
612 u32 dw1 = MI_SEMAPHORE_MBOX |
613 MI_SEMAPHORE_COMPARE |
614 MI_SEMAPHORE_REGISTER;
615
616 /* Throughout all of the GEM code, seqno passed implies our current
617 * seqno is >= the last seqno executed. However for hardware the
618 * comparison is strictly greater than.
619 */
620 seqno -= 1;
621
622 WARN_ON(signaller->semaphore_register[waiter->id] ==
623 MI_SEMAPHORE_SYNC_INVALID);
624
625 ret = intel_ring_begin(waiter, 4);
626 if (ret)
627 return ret;
628
629 intel_ring_emit(waiter,
630 dw1 | signaller->semaphore_register[waiter->id]);
631 intel_ring_emit(waiter, seqno);
632 intel_ring_emit(waiter, 0);
633 intel_ring_emit(waiter, MI_NOOP);
634 intel_ring_advance(waiter);
635
636 return 0;
637 }
638
639 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
640 do { \
641 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
642 PIPE_CONTROL_DEPTH_STALL); \
643 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
644 intel_ring_emit(ring__, 0); \
645 intel_ring_emit(ring__, 0); \
646 } while (0)
647
648 static int
649 pc_render_add_request(struct intel_ring_buffer *ring)
650 {
651 struct pipe_control *pc = ring->private;
652 u32 scratch_addr = pc->gtt_offset + 128;
653 int ret;
654
655 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
656 * incoherent with writes to memory, i.e. completely fubar,
657 * so we need to use PIPE_NOTIFY instead.
658 *
659 * However, we also need to workaround the qword write
660 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
661 * memory before requesting an interrupt.
662 */
663 ret = intel_ring_begin(ring, 32);
664 if (ret)
665 return ret;
666
667 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
668 PIPE_CONTROL_WRITE_FLUSH |
669 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
670 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
671 intel_ring_emit(ring, ring->outstanding_lazy_request);
672 intel_ring_emit(ring, 0);
673 PIPE_CONTROL_FLUSH(ring, scratch_addr);
674 scratch_addr += 128; /* write to separate cachelines */
675 PIPE_CONTROL_FLUSH(ring, scratch_addr);
676 scratch_addr += 128;
677 PIPE_CONTROL_FLUSH(ring, scratch_addr);
678 scratch_addr += 128;
679 PIPE_CONTROL_FLUSH(ring, scratch_addr);
680 scratch_addr += 128;
681 PIPE_CONTROL_FLUSH(ring, scratch_addr);
682 scratch_addr += 128;
683 PIPE_CONTROL_FLUSH(ring, scratch_addr);
684
685 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
686 PIPE_CONTROL_WRITE_FLUSH |
687 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
688 PIPE_CONTROL_NOTIFY);
689 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
690 intel_ring_emit(ring, ring->outstanding_lazy_request);
691 intel_ring_emit(ring, 0);
692 intel_ring_advance(ring);
693
694 return 0;
695 }
696
697 static u32
698 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
699 {
700 /* Workaround to force correct ordering between irq and seqno writes on
701 * ivb (and maybe also on snb) by reading from a CS register (like
702 * ACTHD) before reading the status page. */
703 if (!lazy_coherency)
704 intel_ring_get_active_head(ring);
705 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
706 }
707
708 static u32
709 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
710 {
711 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
712 }
713
714 static u32
715 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
716 {
717 struct pipe_control *pc = ring->private;
718 return pc->cpu_page[0];
719 }
720
721 static bool
722 gen5_ring_get_irq(struct intel_ring_buffer *ring)
723 {
724 struct drm_device *dev = ring->dev;
725 drm_i915_private_t *dev_priv = dev->dev_private;
726 unsigned long flags;
727
728 if (!dev->irq_enabled)
729 return false;
730
731 spin_lock_irqsave(&dev_priv->irq_lock, flags);
732 if (ring->irq_refcount++ == 0) {
733 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
734 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
735 POSTING_READ(GTIMR);
736 }
737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
738
739 return true;
740 }
741
742 static void
743 gen5_ring_put_irq(struct intel_ring_buffer *ring)
744 {
745 struct drm_device *dev = ring->dev;
746 drm_i915_private_t *dev_priv = dev->dev_private;
747 unsigned long flags;
748
749 spin_lock_irqsave(&dev_priv->irq_lock, flags);
750 if (--ring->irq_refcount == 0) {
751 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
752 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
753 POSTING_READ(GTIMR);
754 }
755 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
756 }
757
758 static bool
759 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
760 {
761 struct drm_device *dev = ring->dev;
762 drm_i915_private_t *dev_priv = dev->dev_private;
763 unsigned long flags;
764
765 if (!dev->irq_enabled)
766 return false;
767
768 spin_lock_irqsave(&dev_priv->irq_lock, flags);
769 if (ring->irq_refcount++ == 0) {
770 dev_priv->irq_mask &= ~ring->irq_enable_mask;
771 I915_WRITE(IMR, dev_priv->irq_mask);
772 POSTING_READ(IMR);
773 }
774 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
775
776 return true;
777 }
778
779 static void
780 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
781 {
782 struct drm_device *dev = ring->dev;
783 drm_i915_private_t *dev_priv = dev->dev_private;
784 unsigned long flags;
785
786 spin_lock_irqsave(&dev_priv->irq_lock, flags);
787 if (--ring->irq_refcount == 0) {
788 dev_priv->irq_mask |= ring->irq_enable_mask;
789 I915_WRITE(IMR, dev_priv->irq_mask);
790 POSTING_READ(IMR);
791 }
792 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
793 }
794
795 static bool
796 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
797 {
798 struct drm_device *dev = ring->dev;
799 drm_i915_private_t *dev_priv = dev->dev_private;
800 unsigned long flags;
801
802 if (!dev->irq_enabled)
803 return false;
804
805 spin_lock_irqsave(&dev_priv->irq_lock, flags);
806 if (ring->irq_refcount++ == 0) {
807 dev_priv->irq_mask &= ~ring->irq_enable_mask;
808 I915_WRITE16(IMR, dev_priv->irq_mask);
809 POSTING_READ16(IMR);
810 }
811 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
812
813 return true;
814 }
815
816 static void
817 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
818 {
819 struct drm_device *dev = ring->dev;
820 drm_i915_private_t *dev_priv = dev->dev_private;
821 unsigned long flags;
822
823 spin_lock_irqsave(&dev_priv->irq_lock, flags);
824 if (--ring->irq_refcount == 0) {
825 dev_priv->irq_mask |= ring->irq_enable_mask;
826 I915_WRITE16(IMR, dev_priv->irq_mask);
827 POSTING_READ16(IMR);
828 }
829 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
830 }
831
832 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
833 {
834 struct drm_device *dev = ring->dev;
835 drm_i915_private_t *dev_priv = ring->dev->dev_private;
836 u32 mmio = 0;
837
838 /* The ring status page addresses are no longer next to the rest of
839 * the ring registers as of gen7.
840 */
841 if (IS_GEN7(dev)) {
842 switch (ring->id) {
843 case RCS:
844 mmio = RENDER_HWS_PGA_GEN7;
845 break;
846 case BCS:
847 mmio = BLT_HWS_PGA_GEN7;
848 break;
849 case VCS:
850 mmio = BSD_HWS_PGA_GEN7;
851 break;
852 }
853 } else if (IS_GEN6(ring->dev)) {
854 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
855 } else {
856 mmio = RING_HWS_PGA(ring->mmio_base);
857 }
858
859 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
860 POSTING_READ(mmio);
861 }
862
863 static int
864 bsd_ring_flush(struct intel_ring_buffer *ring,
865 u32 invalidate_domains,
866 u32 flush_domains)
867 {
868 int ret;
869
870 ret = intel_ring_begin(ring, 2);
871 if (ret)
872 return ret;
873
874 intel_ring_emit(ring, MI_FLUSH);
875 intel_ring_emit(ring, MI_NOOP);
876 intel_ring_advance(ring);
877 return 0;
878 }
879
880 static int
881 i9xx_add_request(struct intel_ring_buffer *ring)
882 {
883 int ret;
884
885 ret = intel_ring_begin(ring, 4);
886 if (ret)
887 return ret;
888
889 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
890 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
891 intel_ring_emit(ring, ring->outstanding_lazy_request);
892 intel_ring_emit(ring, MI_USER_INTERRUPT);
893 intel_ring_advance(ring);
894
895 return 0;
896 }
897
898 static bool
899 gen6_ring_get_irq(struct intel_ring_buffer *ring)
900 {
901 struct drm_device *dev = ring->dev;
902 drm_i915_private_t *dev_priv = dev->dev_private;
903 unsigned long flags;
904
905 if (!dev->irq_enabled)
906 return false;
907
908 /* It looks like we need to prevent the gt from suspending while waiting
909 * for an notifiy irq, otherwise irqs seem to get lost on at least the
910 * blt/bsd rings on ivb. */
911 gen6_gt_force_wake_get(dev_priv);
912
913 spin_lock_irqsave(&dev_priv->irq_lock, flags);
914 if (ring->irq_refcount++ == 0) {
915 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
916 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
917 GEN6_RENDER_L3_PARITY_ERROR));
918 else
919 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
920 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
921 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
922 POSTING_READ(GTIMR);
923 }
924 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
925
926 return true;
927 }
928
929 static void
930 gen6_ring_put_irq(struct intel_ring_buffer *ring)
931 {
932 struct drm_device *dev = ring->dev;
933 drm_i915_private_t *dev_priv = dev->dev_private;
934 unsigned long flags;
935
936 spin_lock_irqsave(&dev_priv->irq_lock, flags);
937 if (--ring->irq_refcount == 0) {
938 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
939 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
940 else
941 I915_WRITE_IMR(ring, ~0);
942 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
943 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
944 POSTING_READ(GTIMR);
945 }
946 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
947
948 gen6_gt_force_wake_put(dev_priv);
949 }
950
951 static int
952 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
953 u32 offset, u32 length,
954 unsigned flags)
955 {
956 int ret;
957
958 ret = intel_ring_begin(ring, 2);
959 if (ret)
960 return ret;
961
962 intel_ring_emit(ring,
963 MI_BATCH_BUFFER_START |
964 MI_BATCH_GTT |
965 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
966 intel_ring_emit(ring, offset);
967 intel_ring_advance(ring);
968
969 return 0;
970 }
971
972 static int
973 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
974 u32 offset, u32 len,
975 unsigned flags)
976 {
977 int ret;
978
979 ret = intel_ring_begin(ring, 4);
980 if (ret)
981 return ret;
982
983 intel_ring_emit(ring, MI_BATCH_BUFFER);
984 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
985 intel_ring_emit(ring, offset + len - 8);
986 intel_ring_emit(ring, 0);
987 intel_ring_advance(ring);
988
989 return 0;
990 }
991
992 static int
993 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
994 u32 offset, u32 len,
995 unsigned flags)
996 {
997 int ret;
998
999 ret = intel_ring_begin(ring, 2);
1000 if (ret)
1001 return ret;
1002
1003 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1004 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1005 intel_ring_advance(ring);
1006
1007 return 0;
1008 }
1009
1010 static void cleanup_status_page(struct intel_ring_buffer *ring)
1011 {
1012 struct drm_i915_gem_object *obj;
1013
1014 obj = ring->status_page.obj;
1015 if (obj == NULL)
1016 return;
1017
1018 kunmap(sg_page(obj->pages->sgl));
1019 i915_gem_object_unpin(obj);
1020 drm_gem_object_unreference(&obj->base);
1021 ring->status_page.obj = NULL;
1022 }
1023
1024 static int init_status_page(struct intel_ring_buffer *ring)
1025 {
1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_gem_object *obj;
1028 int ret;
1029
1030 obj = i915_gem_alloc_object(dev, 4096);
1031 if (obj == NULL) {
1032 DRM_ERROR("Failed to allocate status page\n");
1033 ret = -ENOMEM;
1034 goto err;
1035 }
1036
1037 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1038
1039 ret = i915_gem_object_pin(obj, 4096, true, false);
1040 if (ret != 0) {
1041 goto err_unref;
1042 }
1043
1044 ring->status_page.gfx_addr = obj->gtt_offset;
1045 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1046 if (ring->status_page.page_addr == NULL) {
1047 ret = -ENOMEM;
1048 goto err_unpin;
1049 }
1050 ring->status_page.obj = obj;
1051 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1052
1053 intel_ring_setup_status_page(ring);
1054 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1055 ring->name, ring->status_page.gfx_addr);
1056
1057 return 0;
1058
1059 err_unpin:
1060 i915_gem_object_unpin(obj);
1061 err_unref:
1062 drm_gem_object_unreference(&obj->base);
1063 err:
1064 return ret;
1065 }
1066
1067 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1068 {
1069 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1070 u32 addr;
1071
1072 if (!dev_priv->status_page_dmah) {
1073 dev_priv->status_page_dmah =
1074 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1075 if (!dev_priv->status_page_dmah)
1076 return -ENOMEM;
1077 }
1078
1079 addr = dev_priv->status_page_dmah->busaddr;
1080 if (INTEL_INFO(ring->dev)->gen >= 4)
1081 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1082 I915_WRITE(HWS_PGA, addr);
1083
1084 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1085 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1086
1087 return 0;
1088 }
1089
1090 static int intel_init_ring_buffer(struct drm_device *dev,
1091 struct intel_ring_buffer *ring)
1092 {
1093 struct drm_i915_gem_object *obj;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 int ret;
1096
1097 ring->dev = dev;
1098 INIT_LIST_HEAD(&ring->active_list);
1099 INIT_LIST_HEAD(&ring->request_list);
1100 ring->size = 32 * PAGE_SIZE;
1101 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1102
1103 init_waitqueue_head(&ring->irq_queue);
1104
1105 if (I915_NEED_GFX_HWS(dev)) {
1106 ret = init_status_page(ring);
1107 if (ret)
1108 return ret;
1109 } else {
1110 BUG_ON(ring->id != RCS);
1111 ret = init_phys_hws_pga(ring);
1112 if (ret)
1113 return ret;
1114 }
1115
1116 obj = i915_gem_alloc_object(dev, ring->size);
1117 if (obj == NULL) {
1118 DRM_ERROR("Failed to allocate ringbuffer\n");
1119 ret = -ENOMEM;
1120 goto err_hws;
1121 }
1122
1123 ring->obj = obj;
1124
1125 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1126 if (ret)
1127 goto err_unref;
1128
1129 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1130 if (ret)
1131 goto err_unpin;
1132
1133 ring->virtual_start =
1134 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1135 ring->size);
1136 if (ring->virtual_start == NULL) {
1137 DRM_ERROR("Failed to map ringbuffer.\n");
1138 ret = -EINVAL;
1139 goto err_unpin;
1140 }
1141
1142 ret = ring->init(ring);
1143 if (ret)
1144 goto err_unmap;
1145
1146 /* Workaround an erratum on the i830 which causes a hang if
1147 * the TAIL pointer points to within the last 2 cachelines
1148 * of the buffer.
1149 */
1150 ring->effective_size = ring->size;
1151 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1152 ring->effective_size -= 128;
1153
1154 return 0;
1155
1156 err_unmap:
1157 iounmap(ring->virtual_start);
1158 err_unpin:
1159 i915_gem_object_unpin(obj);
1160 err_unref:
1161 drm_gem_object_unreference(&obj->base);
1162 ring->obj = NULL;
1163 err_hws:
1164 cleanup_status_page(ring);
1165 return ret;
1166 }
1167
1168 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1169 {
1170 struct drm_i915_private *dev_priv;
1171 int ret;
1172
1173 if (ring->obj == NULL)
1174 return;
1175
1176 /* Disable the ring buffer. The ring must be idle at this point */
1177 dev_priv = ring->dev->dev_private;
1178 ret = intel_ring_idle(ring);
1179 if (ret)
1180 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1181 ring->name, ret);
1182
1183 I915_WRITE_CTL(ring, 0);
1184
1185 iounmap(ring->virtual_start);
1186
1187 i915_gem_object_unpin(ring->obj);
1188 drm_gem_object_unreference(&ring->obj->base);
1189 ring->obj = NULL;
1190
1191 if (ring->cleanup)
1192 ring->cleanup(ring);
1193
1194 cleanup_status_page(ring);
1195 }
1196
1197 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1198 {
1199 int ret;
1200
1201 ret = i915_wait_seqno(ring, seqno);
1202 if (!ret)
1203 i915_gem_retire_requests_ring(ring);
1204
1205 return ret;
1206 }
1207
1208 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1209 {
1210 struct drm_i915_gem_request *request;
1211 u32 seqno = 0;
1212 int ret;
1213
1214 i915_gem_retire_requests_ring(ring);
1215
1216 if (ring->last_retired_head != -1) {
1217 ring->head = ring->last_retired_head;
1218 ring->last_retired_head = -1;
1219 ring->space = ring_space(ring);
1220 if (ring->space >= n)
1221 return 0;
1222 }
1223
1224 list_for_each_entry(request, &ring->request_list, list) {
1225 int space;
1226
1227 if (request->tail == -1)
1228 continue;
1229
1230 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1231 if (space < 0)
1232 space += ring->size;
1233 if (space >= n) {
1234 seqno = request->seqno;
1235 break;
1236 }
1237
1238 /* Consume this request in case we need more space than
1239 * is available and so need to prevent a race between
1240 * updating last_retired_head and direct reads of
1241 * I915_RING_HEAD. It also provides a nice sanity check.
1242 */
1243 request->tail = -1;
1244 }
1245
1246 if (seqno == 0)
1247 return -ENOSPC;
1248
1249 ret = intel_ring_wait_seqno(ring, seqno);
1250 if (ret)
1251 return ret;
1252
1253 if (WARN_ON(ring->last_retired_head == -1))
1254 return -ENOSPC;
1255
1256 ring->head = ring->last_retired_head;
1257 ring->last_retired_head = -1;
1258 ring->space = ring_space(ring);
1259 if (WARN_ON(ring->space < n))
1260 return -ENOSPC;
1261
1262 return 0;
1263 }
1264
1265 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1266 {
1267 struct drm_device *dev = ring->dev;
1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 unsigned long end;
1270 int ret;
1271
1272 ret = intel_ring_wait_request(ring, n);
1273 if (ret != -ENOSPC)
1274 return ret;
1275
1276 trace_i915_ring_wait_begin(ring);
1277 /* With GEM the hangcheck timer should kick us out of the loop,
1278 * leaving it early runs the risk of corrupting GEM state (due
1279 * to running on almost untested codepaths). But on resume
1280 * timers don't work yet, so prevent a complete hang in that
1281 * case by choosing an insanely large timeout. */
1282 end = jiffies + 60 * HZ;
1283
1284 do {
1285 ring->head = I915_READ_HEAD(ring);
1286 ring->space = ring_space(ring);
1287 if (ring->space >= n) {
1288 trace_i915_ring_wait_end(ring);
1289 return 0;
1290 }
1291
1292 if (dev->primary->master) {
1293 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1294 if (master_priv->sarea_priv)
1295 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1296 }
1297
1298 msleep(1);
1299
1300 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1301 if (ret)
1302 return ret;
1303 } while (!time_after(jiffies, end));
1304 trace_i915_ring_wait_end(ring);
1305 return -EBUSY;
1306 }
1307
1308 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1309 {
1310 uint32_t __iomem *virt;
1311 int rem = ring->size - ring->tail;
1312
1313 if (ring->space < rem) {
1314 int ret = ring_wait_for_space(ring, rem);
1315 if (ret)
1316 return ret;
1317 }
1318
1319 virt = ring->virtual_start + ring->tail;
1320 rem /= 4;
1321 while (rem--)
1322 iowrite32(MI_NOOP, virt++);
1323
1324 ring->tail = 0;
1325 ring->space = ring_space(ring);
1326
1327 return 0;
1328 }
1329
1330 int intel_ring_idle(struct intel_ring_buffer *ring)
1331 {
1332 u32 seqno;
1333 int ret;
1334
1335 /* We need to add any requests required to flush the objects and ring */
1336 if (ring->outstanding_lazy_request) {
1337 ret = i915_add_request(ring, NULL, NULL);
1338 if (ret)
1339 return ret;
1340 }
1341
1342 /* Wait upon the last request to be completed */
1343 if (list_empty(&ring->request_list))
1344 return 0;
1345
1346 seqno = list_entry(ring->request_list.prev,
1347 struct drm_i915_gem_request,
1348 list)->seqno;
1349
1350 return i915_wait_seqno(ring, seqno);
1351 }
1352
1353 static int
1354 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1355 {
1356 if (ring->outstanding_lazy_request)
1357 return 0;
1358
1359 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1360 }
1361
1362 int intel_ring_begin(struct intel_ring_buffer *ring,
1363 int num_dwords)
1364 {
1365 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1366 int n = 4*num_dwords;
1367 int ret;
1368
1369 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1370 if (ret)
1371 return ret;
1372
1373 /* Preallocate the olr before touching the ring */
1374 ret = intel_ring_alloc_seqno(ring);
1375 if (ret)
1376 return ret;
1377
1378 if (unlikely(ring->tail + n > ring->effective_size)) {
1379 ret = intel_wrap_ring_buffer(ring);
1380 if (unlikely(ret))
1381 return ret;
1382 }
1383
1384 if (unlikely(ring->space < n)) {
1385 ret = ring_wait_for_space(ring, n);
1386 if (unlikely(ret))
1387 return ret;
1388 }
1389
1390 ring->space -= n;
1391 return 0;
1392 }
1393
1394 void intel_ring_advance(struct intel_ring_buffer *ring)
1395 {
1396 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1397
1398 ring->tail &= ring->size - 1;
1399 if (dev_priv->stop_rings & intel_ring_flag(ring))
1400 return;
1401 ring->write_tail(ring, ring->tail);
1402 }
1403
1404
1405 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1406 u32 value)
1407 {
1408 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1409
1410 /* Every tail move must follow the sequence below */
1411
1412 /* Disable notification that the ring is IDLE. The GT
1413 * will then assume that it is busy and bring it out of rc6.
1414 */
1415 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1416 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1417
1418 /* Clear the context id. Here be magic! */
1419 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1420
1421 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1422 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1423 GEN6_BSD_SLEEP_INDICATOR) == 0,
1424 50))
1425 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1426
1427 /* Now that the ring is fully powered up, update the tail */
1428 I915_WRITE_TAIL(ring, value);
1429 POSTING_READ(RING_TAIL(ring->mmio_base));
1430
1431 /* Let the ring send IDLE messages to the GT again,
1432 * and so let it sleep to conserve power when idle.
1433 */
1434 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1435 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1436 }
1437
1438 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1439 u32 invalidate, u32 flush)
1440 {
1441 uint32_t cmd;
1442 int ret;
1443
1444 ret = intel_ring_begin(ring, 4);
1445 if (ret)
1446 return ret;
1447
1448 cmd = MI_FLUSH_DW;
1449 /*
1450 * Bspec vol 1c.5 - video engine command streamer:
1451 * "If ENABLED, all TLBs will be invalidated once the flush
1452 * operation is complete. This bit is only valid when the
1453 * Post-Sync Operation field is a value of 1h or 3h."
1454 */
1455 if (invalidate & I915_GEM_GPU_DOMAINS)
1456 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1457 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1458 intel_ring_emit(ring, cmd);
1459 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1460 intel_ring_emit(ring, 0);
1461 intel_ring_emit(ring, MI_NOOP);
1462 intel_ring_advance(ring);
1463 return 0;
1464 }
1465
1466 static int
1467 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1468 u32 offset, u32 len,
1469 unsigned flags)
1470 {
1471 int ret;
1472
1473 ret = intel_ring_begin(ring, 2);
1474 if (ret)
1475 return ret;
1476
1477 intel_ring_emit(ring,
1478 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1479 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1480 /* bit0-7 is the length on GEN6+ */
1481 intel_ring_emit(ring, offset);
1482 intel_ring_advance(ring);
1483
1484 return 0;
1485 }
1486
1487 static int
1488 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1489 u32 offset, u32 len,
1490 unsigned flags)
1491 {
1492 int ret;
1493
1494 ret = intel_ring_begin(ring, 2);
1495 if (ret)
1496 return ret;
1497
1498 intel_ring_emit(ring,
1499 MI_BATCH_BUFFER_START |
1500 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1501 /* bit0-7 is the length on GEN6+ */
1502 intel_ring_emit(ring, offset);
1503 intel_ring_advance(ring);
1504
1505 return 0;
1506 }
1507
1508 /* Blitter support (SandyBridge+) */
1509
1510 static int blt_ring_flush(struct intel_ring_buffer *ring,
1511 u32 invalidate, u32 flush)
1512 {
1513 uint32_t cmd;
1514 int ret;
1515
1516 ret = intel_ring_begin(ring, 4);
1517 if (ret)
1518 return ret;
1519
1520 cmd = MI_FLUSH_DW;
1521 /*
1522 * Bspec vol 1c.3 - blitter engine command streamer:
1523 * "If ENABLED, all TLBs will be invalidated once the flush
1524 * operation is complete. This bit is only valid when the
1525 * Post-Sync Operation field is a value of 1h or 3h."
1526 */
1527 if (invalidate & I915_GEM_DOMAIN_RENDER)
1528 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1529 MI_FLUSH_DW_OP_STOREDW;
1530 intel_ring_emit(ring, cmd);
1531 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1532 intel_ring_emit(ring, 0);
1533 intel_ring_emit(ring, MI_NOOP);
1534 intel_ring_advance(ring);
1535 return 0;
1536 }
1537
1538 int intel_init_render_ring_buffer(struct drm_device *dev)
1539 {
1540 drm_i915_private_t *dev_priv = dev->dev_private;
1541 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1542
1543 ring->name = "render ring";
1544 ring->id = RCS;
1545 ring->mmio_base = RENDER_RING_BASE;
1546
1547 if (INTEL_INFO(dev)->gen >= 6) {
1548 ring->add_request = gen6_add_request;
1549 ring->flush = gen7_render_ring_flush;
1550 if (INTEL_INFO(dev)->gen == 6)
1551 ring->flush = gen6_render_ring_flush;
1552 ring->irq_get = gen6_ring_get_irq;
1553 ring->irq_put = gen6_ring_put_irq;
1554 ring->irq_enable_mask = GT_USER_INTERRUPT;
1555 ring->get_seqno = gen6_ring_get_seqno;
1556 ring->sync_to = gen6_ring_sync;
1557 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1558 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1559 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1560 ring->signal_mbox[0] = GEN6_VRSYNC;
1561 ring->signal_mbox[1] = GEN6_BRSYNC;
1562 } else if (IS_GEN5(dev)) {
1563 ring->add_request = pc_render_add_request;
1564 ring->flush = gen4_render_ring_flush;
1565 ring->get_seqno = pc_render_get_seqno;
1566 ring->irq_get = gen5_ring_get_irq;
1567 ring->irq_put = gen5_ring_put_irq;
1568 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1569 } else {
1570 ring->add_request = i9xx_add_request;
1571 if (INTEL_INFO(dev)->gen < 4)
1572 ring->flush = gen2_render_ring_flush;
1573 else
1574 ring->flush = gen4_render_ring_flush;
1575 ring->get_seqno = ring_get_seqno;
1576 if (IS_GEN2(dev)) {
1577 ring->irq_get = i8xx_ring_get_irq;
1578 ring->irq_put = i8xx_ring_put_irq;
1579 } else {
1580 ring->irq_get = i9xx_ring_get_irq;
1581 ring->irq_put = i9xx_ring_put_irq;
1582 }
1583 ring->irq_enable_mask = I915_USER_INTERRUPT;
1584 }
1585 ring->write_tail = ring_write_tail;
1586 if (IS_HASWELL(dev))
1587 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1588 else if (INTEL_INFO(dev)->gen >= 6)
1589 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1590 else if (INTEL_INFO(dev)->gen >= 4)
1591 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1592 else if (IS_I830(dev) || IS_845G(dev))
1593 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1594 else
1595 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1596 ring->init = init_render_ring;
1597 ring->cleanup = render_ring_cleanup;
1598
1599 return intel_init_ring_buffer(dev, ring);
1600 }
1601
1602 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1603 {
1604 drm_i915_private_t *dev_priv = dev->dev_private;
1605 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1606 int ret;
1607
1608 ring->name = "render ring";
1609 ring->id = RCS;
1610 ring->mmio_base = RENDER_RING_BASE;
1611
1612 if (INTEL_INFO(dev)->gen >= 6) {
1613 /* non-kms not supported on gen6+ */
1614 return -ENODEV;
1615 }
1616
1617 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1618 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1619 * the special gen5 functions. */
1620 ring->add_request = i9xx_add_request;
1621 if (INTEL_INFO(dev)->gen < 4)
1622 ring->flush = gen2_render_ring_flush;
1623 else
1624 ring->flush = gen4_render_ring_flush;
1625 ring->get_seqno = ring_get_seqno;
1626 if (IS_GEN2(dev)) {
1627 ring->irq_get = i8xx_ring_get_irq;
1628 ring->irq_put = i8xx_ring_put_irq;
1629 } else {
1630 ring->irq_get = i9xx_ring_get_irq;
1631 ring->irq_put = i9xx_ring_put_irq;
1632 }
1633 ring->irq_enable_mask = I915_USER_INTERRUPT;
1634 ring->write_tail = ring_write_tail;
1635 if (INTEL_INFO(dev)->gen >= 4)
1636 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1637 else if (IS_I830(dev) || IS_845G(dev))
1638 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1639 else
1640 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1641 ring->init = init_render_ring;
1642 ring->cleanup = render_ring_cleanup;
1643
1644 ring->dev = dev;
1645 INIT_LIST_HEAD(&ring->active_list);
1646 INIT_LIST_HEAD(&ring->request_list);
1647
1648 ring->size = size;
1649 ring->effective_size = ring->size;
1650 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1651 ring->effective_size -= 128;
1652
1653 ring->virtual_start = ioremap_wc(start, size);
1654 if (ring->virtual_start == NULL) {
1655 DRM_ERROR("can not ioremap virtual address for"
1656 " ring buffer\n");
1657 return -ENOMEM;
1658 }
1659
1660 if (!I915_NEED_GFX_HWS(dev)) {
1661 ret = init_phys_hws_pga(ring);
1662 if (ret)
1663 return ret;
1664 }
1665
1666 return 0;
1667 }
1668
1669 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1670 {
1671 drm_i915_private_t *dev_priv = dev->dev_private;
1672 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1673
1674 ring->name = "bsd ring";
1675 ring->id = VCS;
1676
1677 ring->write_tail = ring_write_tail;
1678 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1679 ring->mmio_base = GEN6_BSD_RING_BASE;
1680 /* gen6 bsd needs a special wa for tail updates */
1681 if (IS_GEN6(dev))
1682 ring->write_tail = gen6_bsd_ring_write_tail;
1683 ring->flush = gen6_ring_flush;
1684 ring->add_request = gen6_add_request;
1685 ring->get_seqno = gen6_ring_get_seqno;
1686 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1687 ring->irq_get = gen6_ring_get_irq;
1688 ring->irq_put = gen6_ring_put_irq;
1689 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1690 ring->sync_to = gen6_ring_sync;
1691 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1692 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1693 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1694 ring->signal_mbox[0] = GEN6_RVSYNC;
1695 ring->signal_mbox[1] = GEN6_BVSYNC;
1696 } else {
1697 ring->mmio_base = BSD_RING_BASE;
1698 ring->flush = bsd_ring_flush;
1699 ring->add_request = i9xx_add_request;
1700 ring->get_seqno = ring_get_seqno;
1701 if (IS_GEN5(dev)) {
1702 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1703 ring->irq_get = gen5_ring_get_irq;
1704 ring->irq_put = gen5_ring_put_irq;
1705 } else {
1706 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1707 ring->irq_get = i9xx_ring_get_irq;
1708 ring->irq_put = i9xx_ring_put_irq;
1709 }
1710 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1711 }
1712 ring->init = init_ring_common;
1713
1714 return intel_init_ring_buffer(dev, ring);
1715 }
1716
1717 int intel_init_blt_ring_buffer(struct drm_device *dev)
1718 {
1719 drm_i915_private_t *dev_priv = dev->dev_private;
1720 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1721
1722 ring->name = "blitter ring";
1723 ring->id = BCS;
1724
1725 ring->mmio_base = BLT_RING_BASE;
1726 ring->write_tail = ring_write_tail;
1727 ring->flush = blt_ring_flush;
1728 ring->add_request = gen6_add_request;
1729 ring->get_seqno = gen6_ring_get_seqno;
1730 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1731 ring->irq_get = gen6_ring_get_irq;
1732 ring->irq_put = gen6_ring_put_irq;
1733 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1734 ring->sync_to = gen6_ring_sync;
1735 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1736 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1737 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1738 ring->signal_mbox[0] = GEN6_RBSYNC;
1739 ring->signal_mbox[1] = GEN6_VBSYNC;
1740 ring->init = init_ring_common;
1741
1742 return intel_init_ring_buffer(dev, ring);
1743 }
1744
1745 int
1746 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1747 {
1748 int ret;
1749
1750 if (!ring->gpu_caches_dirty)
1751 return 0;
1752
1753 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1754 if (ret)
1755 return ret;
1756
1757 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1758
1759 ring->gpu_caches_dirty = false;
1760 return 0;
1761 }
1762
1763 int
1764 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1765 {
1766 uint32_t flush_domains;
1767 int ret;
1768
1769 flush_domains = 0;
1770 if (ring->gpu_caches_dirty)
1771 flush_domains = I915_GEM_GPU_DOMAINS;
1772
1773 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1774 if (ret)
1775 return ret;
1776
1777 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1778
1779 ring->gpu_caches_dirty = false;
1780 return 0;
1781 }
Linux kernel - Deliverables
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