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drm/i915: create macros to handle masked bits
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
235
236 ret = intel_ring_begin(ring, 6);
237 if (ret)
238 return ret;
239
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, flags);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
243 intel_ring_emit(ring, 0); /* lower dword */
244 intel_ring_emit(ring, 0); /* uppwer dword */
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
247
248 return 0;
249 }
250
251 static void ring_write_tail(struct intel_ring_buffer *ring,
252 u32 value)
253 {
254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
255 I915_WRITE_TAIL(ring, value);
256 }
257
258 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
259 {
260 drm_i915_private_t *dev_priv = ring->dev->dev_private;
261 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
262 RING_ACTHD(ring->mmio_base) : ACTHD;
263
264 return I915_READ(acthd_reg);
265 }
266
267 static int init_ring_common(struct intel_ring_buffer *ring)
268 {
269 drm_i915_private_t *dev_priv = ring->dev->dev_private;
270 struct drm_i915_gem_object *obj = ring->obj;
271 u32 head;
272
273 /* Stop the ring if it's running. */
274 I915_WRITE_CTL(ring, 0);
275 I915_WRITE_HEAD(ring, 0);
276 ring->write_tail(ring, 0);
277
278 /* Initialize the ring. */
279 I915_WRITE_START(ring, obj->gtt_offset);
280 head = I915_READ_HEAD(ring) & HEAD_ADDR;
281
282 /* G45 ring initialization fails to reset head to zero */
283 if (head != 0) {
284 DRM_DEBUG_KMS("%s head not reset to zero "
285 "ctl %08x head %08x tail %08x start %08x\n",
286 ring->name,
287 I915_READ_CTL(ring),
288 I915_READ_HEAD(ring),
289 I915_READ_TAIL(ring),
290 I915_READ_START(ring));
291
292 I915_WRITE_HEAD(ring, 0);
293
294 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
295 DRM_ERROR("failed to set %s head to zero "
296 "ctl %08x head %08x tail %08x start %08x\n",
297 ring->name,
298 I915_READ_CTL(ring),
299 I915_READ_HEAD(ring),
300 I915_READ_TAIL(ring),
301 I915_READ_START(ring));
302 }
303 }
304
305 I915_WRITE_CTL(ring,
306 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
307 | RING_VALID);
308
309 /* If the head is still not zero, the ring is dead */
310 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
311 I915_READ_START(ring) == obj->gtt_offset &&
312 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
313 DRM_ERROR("%s initialization failed "
314 "ctl %08x head %08x tail %08x start %08x\n",
315 ring->name,
316 I915_READ_CTL(ring),
317 I915_READ_HEAD(ring),
318 I915_READ_TAIL(ring),
319 I915_READ_START(ring));
320 return -EIO;
321 }
322
323 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
324 i915_kernel_lost_context(ring->dev);
325 else {
326 ring->head = I915_READ_HEAD(ring);
327 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
328 ring->space = ring_space(ring);
329 }
330
331 return 0;
332 }
333
334 static int
335 init_pipe_control(struct intel_ring_buffer *ring)
336 {
337 struct pipe_control *pc;
338 struct drm_i915_gem_object *obj;
339 int ret;
340
341 if (ring->private)
342 return 0;
343
344 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
345 if (!pc)
346 return -ENOMEM;
347
348 obj = i915_gem_alloc_object(ring->dev, 4096);
349 if (obj == NULL) {
350 DRM_ERROR("Failed to allocate seqno page\n");
351 ret = -ENOMEM;
352 goto err;
353 }
354
355 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
356
357 ret = i915_gem_object_pin(obj, 4096, true);
358 if (ret)
359 goto err_unref;
360
361 pc->gtt_offset = obj->gtt_offset;
362 pc->cpu_page = kmap(obj->pages[0]);
363 if (pc->cpu_page == NULL)
364 goto err_unpin;
365
366 pc->obj = obj;
367 ring->private = pc;
368 return 0;
369
370 err_unpin:
371 i915_gem_object_unpin(obj);
372 err_unref:
373 drm_gem_object_unreference(&obj->base);
374 err:
375 kfree(pc);
376 return ret;
377 }
378
379 static void
380 cleanup_pipe_control(struct intel_ring_buffer *ring)
381 {
382 struct pipe_control *pc = ring->private;
383 struct drm_i915_gem_object *obj;
384
385 if (!ring->private)
386 return;
387
388 obj = pc->obj;
389 kunmap(obj->pages[0]);
390 i915_gem_object_unpin(obj);
391 drm_gem_object_unreference(&obj->base);
392
393 kfree(pc);
394 ring->private = NULL;
395 }
396
397 static int init_render_ring(struct intel_ring_buffer *ring)
398 {
399 struct drm_device *dev = ring->dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 int ret = init_ring_common(ring);
402
403 if (INTEL_INFO(dev)->gen > 3) {
404 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
405 if (IS_GEN7(dev))
406 I915_WRITE(GFX_MODE_GEN7,
407 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
408 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
409 }
410
411 if (INTEL_INFO(dev)->gen >= 5) {
412 ret = init_pipe_control(ring);
413 if (ret)
414 return ret;
415 }
416
417 if (INTEL_INFO(dev)->gen >= 6)
418 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
419
420 return ret;
421 }
422
423 static void render_ring_cleanup(struct intel_ring_buffer *ring)
424 {
425 if (!ring->private)
426 return;
427
428 cleanup_pipe_control(ring);
429 }
430
431 static void
432 update_mboxes(struct intel_ring_buffer *ring,
433 u32 seqno,
434 u32 mmio_offset)
435 {
436 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
437 MI_SEMAPHORE_GLOBAL_GTT |
438 MI_SEMAPHORE_REGISTER |
439 MI_SEMAPHORE_UPDATE);
440 intel_ring_emit(ring, seqno);
441 intel_ring_emit(ring, mmio_offset);
442 }
443
444 /**
445 * gen6_add_request - Update the semaphore mailbox registers
446 *
447 * @ring - ring that is adding a request
448 * @seqno - return seqno stuck into the ring
449 *
450 * Update the mailbox registers in the *other* rings with the current seqno.
451 * This acts like a signal in the canonical semaphore.
452 */
453 static int
454 gen6_add_request(struct intel_ring_buffer *ring,
455 u32 *seqno)
456 {
457 u32 mbox1_reg;
458 u32 mbox2_reg;
459 int ret;
460
461 ret = intel_ring_begin(ring, 10);
462 if (ret)
463 return ret;
464
465 mbox1_reg = ring->signal_mbox[0];
466 mbox2_reg = ring->signal_mbox[1];
467
468 *seqno = i915_gem_next_request_seqno(ring);
469
470 update_mboxes(ring, *seqno, mbox1_reg);
471 update_mboxes(ring, *seqno, mbox2_reg);
472 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
473 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
474 intel_ring_emit(ring, *seqno);
475 intel_ring_emit(ring, MI_USER_INTERRUPT);
476 intel_ring_advance(ring);
477
478 return 0;
479 }
480
481 /**
482 * intel_ring_sync - sync the waiter to the signaller on seqno
483 *
484 * @waiter - ring that is waiting
485 * @signaller - ring which has, or will signal
486 * @seqno - seqno which the waiter will block on
487 */
488 static int
489 gen6_ring_sync(struct intel_ring_buffer *waiter,
490 struct intel_ring_buffer *signaller,
491 u32 seqno)
492 {
493 int ret;
494 u32 dw1 = MI_SEMAPHORE_MBOX |
495 MI_SEMAPHORE_COMPARE |
496 MI_SEMAPHORE_REGISTER;
497
498 /* Throughout all of the GEM code, seqno passed implies our current
499 * seqno is >= the last seqno executed. However for hardware the
500 * comparison is strictly greater than.
501 */
502 seqno -= 1;
503
504 WARN_ON(signaller->semaphore_register[waiter->id] ==
505 MI_SEMAPHORE_SYNC_INVALID);
506
507 ret = intel_ring_begin(waiter, 4);
508 if (ret)
509 return ret;
510
511 intel_ring_emit(waiter,
512 dw1 | signaller->semaphore_register[waiter->id]);
513 intel_ring_emit(waiter, seqno);
514 intel_ring_emit(waiter, 0);
515 intel_ring_emit(waiter, MI_NOOP);
516 intel_ring_advance(waiter);
517
518 return 0;
519 }
520
521 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
522 do { \
523 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
524 PIPE_CONTROL_DEPTH_STALL); \
525 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
526 intel_ring_emit(ring__, 0); \
527 intel_ring_emit(ring__, 0); \
528 } while (0)
529
530 static int
531 pc_render_add_request(struct intel_ring_buffer *ring,
532 u32 *result)
533 {
534 u32 seqno = i915_gem_next_request_seqno(ring);
535 struct pipe_control *pc = ring->private;
536 u32 scratch_addr = pc->gtt_offset + 128;
537 int ret;
538
539 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
540 * incoherent with writes to memory, i.e. completely fubar,
541 * so we need to use PIPE_NOTIFY instead.
542 *
543 * However, we also need to workaround the qword write
544 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
545 * memory before requesting an interrupt.
546 */
547 ret = intel_ring_begin(ring, 32);
548 if (ret)
549 return ret;
550
551 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
552 PIPE_CONTROL_WRITE_FLUSH |
553 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
554 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
555 intel_ring_emit(ring, seqno);
556 intel_ring_emit(ring, 0);
557 PIPE_CONTROL_FLUSH(ring, scratch_addr);
558 scratch_addr += 128; /* write to separate cachelines */
559 PIPE_CONTROL_FLUSH(ring, scratch_addr);
560 scratch_addr += 128;
561 PIPE_CONTROL_FLUSH(ring, scratch_addr);
562 scratch_addr += 128;
563 PIPE_CONTROL_FLUSH(ring, scratch_addr);
564 scratch_addr += 128;
565 PIPE_CONTROL_FLUSH(ring, scratch_addr);
566 scratch_addr += 128;
567 PIPE_CONTROL_FLUSH(ring, scratch_addr);
568
569 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
570 PIPE_CONTROL_WRITE_FLUSH |
571 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
572 PIPE_CONTROL_NOTIFY);
573 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
574 intel_ring_emit(ring, seqno);
575 intel_ring_emit(ring, 0);
576 intel_ring_advance(ring);
577
578 *result = seqno;
579 return 0;
580 }
581
582 static u32
583 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
584 {
585 struct drm_device *dev = ring->dev;
586
587 /* Workaround to force correct ordering between irq and seqno writes on
588 * ivb (and maybe also on snb) by reading from a CS register (like
589 * ACTHD) before reading the status page. */
590 if (IS_GEN6(dev) || IS_GEN7(dev))
591 intel_ring_get_active_head(ring);
592 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
593 }
594
595 static u32
596 ring_get_seqno(struct intel_ring_buffer *ring)
597 {
598 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
599 }
600
601 static u32
602 pc_render_get_seqno(struct intel_ring_buffer *ring)
603 {
604 struct pipe_control *pc = ring->private;
605 return pc->cpu_page[0];
606 }
607
608 static bool
609 gen5_ring_get_irq(struct intel_ring_buffer *ring)
610 {
611 struct drm_device *dev = ring->dev;
612 drm_i915_private_t *dev_priv = dev->dev_private;
613
614 if (!dev->irq_enabled)
615 return false;
616
617 spin_lock(&ring->irq_lock);
618 if (ring->irq_refcount++ == 0) {
619 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
620 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
621 POSTING_READ(GTIMR);
622 }
623 spin_unlock(&ring->irq_lock);
624
625 return true;
626 }
627
628 static void
629 gen5_ring_put_irq(struct intel_ring_buffer *ring)
630 {
631 struct drm_device *dev = ring->dev;
632 drm_i915_private_t *dev_priv = dev->dev_private;
633
634 spin_lock(&ring->irq_lock);
635 if (--ring->irq_refcount == 0) {
636 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
637 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
638 POSTING_READ(GTIMR);
639 }
640 spin_unlock(&ring->irq_lock);
641 }
642
643 static bool
644 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
645 {
646 struct drm_device *dev = ring->dev;
647 drm_i915_private_t *dev_priv = dev->dev_private;
648
649 if (!dev->irq_enabled)
650 return false;
651
652 spin_lock(&ring->irq_lock);
653 if (ring->irq_refcount++ == 0) {
654 dev_priv->irq_mask &= ~ring->irq_enable_mask;
655 I915_WRITE(IMR, dev_priv->irq_mask);
656 POSTING_READ(IMR);
657 }
658 spin_unlock(&ring->irq_lock);
659
660 return true;
661 }
662
663 static void
664 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
665 {
666 struct drm_device *dev = ring->dev;
667 drm_i915_private_t *dev_priv = dev->dev_private;
668
669 spin_lock(&ring->irq_lock);
670 if (--ring->irq_refcount == 0) {
671 dev_priv->irq_mask |= ring->irq_enable_mask;
672 I915_WRITE(IMR, dev_priv->irq_mask);
673 POSTING_READ(IMR);
674 }
675 spin_unlock(&ring->irq_lock);
676 }
677
678 static bool
679 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
680 {
681 struct drm_device *dev = ring->dev;
682 drm_i915_private_t *dev_priv = dev->dev_private;
683
684 if (!dev->irq_enabled)
685 return false;
686
687 spin_lock(&ring->irq_lock);
688 if (ring->irq_refcount++ == 0) {
689 dev_priv->irq_mask &= ~ring->irq_enable_mask;
690 I915_WRITE16(IMR, dev_priv->irq_mask);
691 POSTING_READ16(IMR);
692 }
693 spin_unlock(&ring->irq_lock);
694
695 return true;
696 }
697
698 static void
699 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
700 {
701 struct drm_device *dev = ring->dev;
702 drm_i915_private_t *dev_priv = dev->dev_private;
703
704 spin_lock(&ring->irq_lock);
705 if (--ring->irq_refcount == 0) {
706 dev_priv->irq_mask |= ring->irq_enable_mask;
707 I915_WRITE16(IMR, dev_priv->irq_mask);
708 POSTING_READ16(IMR);
709 }
710 spin_unlock(&ring->irq_lock);
711 }
712
713 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
714 {
715 struct drm_device *dev = ring->dev;
716 drm_i915_private_t *dev_priv = ring->dev->dev_private;
717 u32 mmio = 0;
718
719 /* The ring status page addresses are no longer next to the rest of
720 * the ring registers as of gen7.
721 */
722 if (IS_GEN7(dev)) {
723 switch (ring->id) {
724 case RCS:
725 mmio = RENDER_HWS_PGA_GEN7;
726 break;
727 case BCS:
728 mmio = BLT_HWS_PGA_GEN7;
729 break;
730 case VCS:
731 mmio = BSD_HWS_PGA_GEN7;
732 break;
733 }
734 } else if (IS_GEN6(ring->dev)) {
735 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
736 } else {
737 mmio = RING_HWS_PGA(ring->mmio_base);
738 }
739
740 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
741 POSTING_READ(mmio);
742 }
743
744 static int
745 bsd_ring_flush(struct intel_ring_buffer *ring,
746 u32 invalidate_domains,
747 u32 flush_domains)
748 {
749 int ret;
750
751 ret = intel_ring_begin(ring, 2);
752 if (ret)
753 return ret;
754
755 intel_ring_emit(ring, MI_FLUSH);
756 intel_ring_emit(ring, MI_NOOP);
757 intel_ring_advance(ring);
758 return 0;
759 }
760
761 static int
762 i9xx_add_request(struct intel_ring_buffer *ring,
763 u32 *result)
764 {
765 u32 seqno;
766 int ret;
767
768 ret = intel_ring_begin(ring, 4);
769 if (ret)
770 return ret;
771
772 seqno = i915_gem_next_request_seqno(ring);
773
774 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
775 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
776 intel_ring_emit(ring, seqno);
777 intel_ring_emit(ring, MI_USER_INTERRUPT);
778 intel_ring_advance(ring);
779
780 *result = seqno;
781 return 0;
782 }
783
784 static bool
785 gen6_ring_get_irq(struct intel_ring_buffer *ring)
786 {
787 struct drm_device *dev = ring->dev;
788 drm_i915_private_t *dev_priv = dev->dev_private;
789
790 if (!dev->irq_enabled)
791 return false;
792
793 /* It looks like we need to prevent the gt from suspending while waiting
794 * for an notifiy irq, otherwise irqs seem to get lost on at least the
795 * blt/bsd rings on ivb. */
796 gen6_gt_force_wake_get(dev_priv);
797
798 spin_lock(&ring->irq_lock);
799 if (ring->irq_refcount++ == 0) {
800 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
801 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
802 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
803 POSTING_READ(GTIMR);
804 }
805 spin_unlock(&ring->irq_lock);
806
807 return true;
808 }
809
810 static void
811 gen6_ring_put_irq(struct intel_ring_buffer *ring)
812 {
813 struct drm_device *dev = ring->dev;
814 drm_i915_private_t *dev_priv = dev->dev_private;
815
816 spin_lock(&ring->irq_lock);
817 if (--ring->irq_refcount == 0) {
818 I915_WRITE_IMR(ring, ~0);
819 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
820 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
821 POSTING_READ(GTIMR);
822 }
823 spin_unlock(&ring->irq_lock);
824
825 gen6_gt_force_wake_put(dev_priv);
826 }
827
828 static int
829 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
830 {
831 int ret;
832
833 ret = intel_ring_begin(ring, 2);
834 if (ret)
835 return ret;
836
837 intel_ring_emit(ring,
838 MI_BATCH_BUFFER_START |
839 MI_BATCH_GTT |
840 MI_BATCH_NON_SECURE_I965);
841 intel_ring_emit(ring, offset);
842 intel_ring_advance(ring);
843
844 return 0;
845 }
846
847 static int
848 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
849 u32 offset, u32 len)
850 {
851 int ret;
852
853 ret = intel_ring_begin(ring, 4);
854 if (ret)
855 return ret;
856
857 intel_ring_emit(ring, MI_BATCH_BUFFER);
858 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
859 intel_ring_emit(ring, offset + len - 8);
860 intel_ring_emit(ring, 0);
861 intel_ring_advance(ring);
862
863 return 0;
864 }
865
866 static int
867 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
868 u32 offset, u32 len)
869 {
870 int ret;
871
872 ret = intel_ring_begin(ring, 2);
873 if (ret)
874 return ret;
875
876 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
877 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
878 intel_ring_advance(ring);
879
880 return 0;
881 }
882
883 static void cleanup_status_page(struct intel_ring_buffer *ring)
884 {
885 drm_i915_private_t *dev_priv = ring->dev->dev_private;
886 struct drm_i915_gem_object *obj;
887
888 obj = ring->status_page.obj;
889 if (obj == NULL)
890 return;
891
892 kunmap(obj->pages[0]);
893 i915_gem_object_unpin(obj);
894 drm_gem_object_unreference(&obj->base);
895 ring->status_page.obj = NULL;
896
897 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
898 }
899
900 static int init_status_page(struct intel_ring_buffer *ring)
901 {
902 struct drm_device *dev = ring->dev;
903 drm_i915_private_t *dev_priv = dev->dev_private;
904 struct drm_i915_gem_object *obj;
905 int ret;
906
907 obj = i915_gem_alloc_object(dev, 4096);
908 if (obj == NULL) {
909 DRM_ERROR("Failed to allocate status page\n");
910 ret = -ENOMEM;
911 goto err;
912 }
913
914 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
915
916 ret = i915_gem_object_pin(obj, 4096, true);
917 if (ret != 0) {
918 goto err_unref;
919 }
920
921 ring->status_page.gfx_addr = obj->gtt_offset;
922 ring->status_page.page_addr = kmap(obj->pages[0]);
923 if (ring->status_page.page_addr == NULL) {
924 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
925 goto err_unpin;
926 }
927 ring->status_page.obj = obj;
928 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
929
930 intel_ring_setup_status_page(ring);
931 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
932 ring->name, ring->status_page.gfx_addr);
933
934 return 0;
935
936 err_unpin:
937 i915_gem_object_unpin(obj);
938 err_unref:
939 drm_gem_object_unreference(&obj->base);
940 err:
941 return ret;
942 }
943
944 static int intel_init_ring_buffer(struct drm_device *dev,
945 struct intel_ring_buffer *ring)
946 {
947 struct drm_i915_gem_object *obj;
948 int ret;
949
950 ring->dev = dev;
951 INIT_LIST_HEAD(&ring->active_list);
952 INIT_LIST_HEAD(&ring->request_list);
953 INIT_LIST_HEAD(&ring->gpu_write_list);
954 ring->size = 32 * PAGE_SIZE;
955
956 init_waitqueue_head(&ring->irq_queue);
957 spin_lock_init(&ring->irq_lock);
958
959 if (I915_NEED_GFX_HWS(dev)) {
960 ret = init_status_page(ring);
961 if (ret)
962 return ret;
963 }
964
965 obj = i915_gem_alloc_object(dev, ring->size);
966 if (obj == NULL) {
967 DRM_ERROR("Failed to allocate ringbuffer\n");
968 ret = -ENOMEM;
969 goto err_hws;
970 }
971
972 ring->obj = obj;
973
974 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
975 if (ret)
976 goto err_unref;
977
978 ring->map.size = ring->size;
979 ring->map.offset = dev->agp->base + obj->gtt_offset;
980 ring->map.type = 0;
981 ring->map.flags = 0;
982 ring->map.mtrr = 0;
983
984 drm_core_ioremap_wc(&ring->map, dev);
985 if (ring->map.handle == NULL) {
986 DRM_ERROR("Failed to map ringbuffer.\n");
987 ret = -EINVAL;
988 goto err_unpin;
989 }
990
991 ring->virtual_start = ring->map.handle;
992 ret = ring->init(ring);
993 if (ret)
994 goto err_unmap;
995
996 /* Workaround an erratum on the i830 which causes a hang if
997 * the TAIL pointer points to within the last 2 cachelines
998 * of the buffer.
999 */
1000 ring->effective_size = ring->size;
1001 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1002 ring->effective_size -= 128;
1003
1004 return 0;
1005
1006 err_unmap:
1007 drm_core_ioremapfree(&ring->map, dev);
1008 err_unpin:
1009 i915_gem_object_unpin(obj);
1010 err_unref:
1011 drm_gem_object_unreference(&obj->base);
1012 ring->obj = NULL;
1013 err_hws:
1014 cleanup_status_page(ring);
1015 return ret;
1016 }
1017
1018 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1019 {
1020 struct drm_i915_private *dev_priv;
1021 int ret;
1022
1023 if (ring->obj == NULL)
1024 return;
1025
1026 /* Disable the ring buffer. The ring must be idle at this point */
1027 dev_priv = ring->dev->dev_private;
1028 ret = intel_wait_ring_idle(ring);
1029 if (ret)
1030 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1031 ring->name, ret);
1032
1033 I915_WRITE_CTL(ring, 0);
1034
1035 drm_core_ioremapfree(&ring->map, ring->dev);
1036
1037 i915_gem_object_unpin(ring->obj);
1038 drm_gem_object_unreference(&ring->obj->base);
1039 ring->obj = NULL;
1040
1041 if (ring->cleanup)
1042 ring->cleanup(ring);
1043
1044 cleanup_status_page(ring);
1045 }
1046
1047 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1048 {
1049 unsigned int *virt;
1050 int rem = ring->size - ring->tail;
1051
1052 if (ring->space < rem) {
1053 int ret = intel_wait_ring_buffer(ring, rem);
1054 if (ret)
1055 return ret;
1056 }
1057
1058 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1059 rem /= 8;
1060 while (rem--) {
1061 *virt++ = MI_NOOP;
1062 *virt++ = MI_NOOP;
1063 }
1064
1065 ring->tail = 0;
1066 ring->space = ring_space(ring);
1067
1068 return 0;
1069 }
1070
1071 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1072 {
1073 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1074 bool was_interruptible;
1075 int ret;
1076
1077 /* XXX As we have not yet audited all the paths to check that
1078 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1079 * allow us to be interruptible by a signal.
1080 */
1081 was_interruptible = dev_priv->mm.interruptible;
1082 dev_priv->mm.interruptible = false;
1083
1084 ret = i915_wait_request(ring, seqno, true);
1085
1086 dev_priv->mm.interruptible = was_interruptible;
1087
1088 return ret;
1089 }
1090
1091 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1092 {
1093 struct drm_i915_gem_request *request;
1094 u32 seqno = 0;
1095 int ret;
1096
1097 i915_gem_retire_requests_ring(ring);
1098
1099 if (ring->last_retired_head != -1) {
1100 ring->head = ring->last_retired_head;
1101 ring->last_retired_head = -1;
1102 ring->space = ring_space(ring);
1103 if (ring->space >= n)
1104 return 0;
1105 }
1106
1107 list_for_each_entry(request, &ring->request_list, list) {
1108 int space;
1109
1110 if (request->tail == -1)
1111 continue;
1112
1113 space = request->tail - (ring->tail + 8);
1114 if (space < 0)
1115 space += ring->size;
1116 if (space >= n) {
1117 seqno = request->seqno;
1118 break;
1119 }
1120
1121 /* Consume this request in case we need more space than
1122 * is available and so need to prevent a race between
1123 * updating last_retired_head and direct reads of
1124 * I915_RING_HEAD. It also provides a nice sanity check.
1125 */
1126 request->tail = -1;
1127 }
1128
1129 if (seqno == 0)
1130 return -ENOSPC;
1131
1132 ret = intel_ring_wait_seqno(ring, seqno);
1133 if (ret)
1134 return ret;
1135
1136 if (WARN_ON(ring->last_retired_head == -1))
1137 return -ENOSPC;
1138
1139 ring->head = ring->last_retired_head;
1140 ring->last_retired_head = -1;
1141 ring->space = ring_space(ring);
1142 if (WARN_ON(ring->space < n))
1143 return -ENOSPC;
1144
1145 return 0;
1146 }
1147
1148 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1149 {
1150 struct drm_device *dev = ring->dev;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 unsigned long end;
1153 int ret;
1154
1155 ret = intel_ring_wait_request(ring, n);
1156 if (ret != -ENOSPC)
1157 return ret;
1158
1159 trace_i915_ring_wait_begin(ring);
1160 if (drm_core_check_feature(dev, DRIVER_GEM))
1161 /* With GEM the hangcheck timer should kick us out of the loop,
1162 * leaving it early runs the risk of corrupting GEM state (due
1163 * to running on almost untested codepaths). But on resume
1164 * timers don't work yet, so prevent a complete hang in that
1165 * case by choosing an insanely large timeout. */
1166 end = jiffies + 60 * HZ;
1167 else
1168 end = jiffies + 3 * HZ;
1169
1170 do {
1171 ring->head = I915_READ_HEAD(ring);
1172 ring->space = ring_space(ring);
1173 if (ring->space >= n) {
1174 trace_i915_ring_wait_end(ring);
1175 return 0;
1176 }
1177
1178 if (dev->primary->master) {
1179 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1180 if (master_priv->sarea_priv)
1181 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1182 }
1183
1184 msleep(1);
1185 if (atomic_read(&dev_priv->mm.wedged))
1186 return -EAGAIN;
1187 } while (!time_after(jiffies, end));
1188 trace_i915_ring_wait_end(ring);
1189 return -EBUSY;
1190 }
1191
1192 int intel_ring_begin(struct intel_ring_buffer *ring,
1193 int num_dwords)
1194 {
1195 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1196 int n = 4*num_dwords;
1197 int ret;
1198
1199 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1200 return -EIO;
1201
1202 if (unlikely(ring->tail + n > ring->effective_size)) {
1203 ret = intel_wrap_ring_buffer(ring);
1204 if (unlikely(ret))
1205 return ret;
1206 }
1207
1208 if (unlikely(ring->space < n)) {
1209 ret = intel_wait_ring_buffer(ring, n);
1210 if (unlikely(ret))
1211 return ret;
1212 }
1213
1214 ring->space -= n;
1215 return 0;
1216 }
1217
1218 void intel_ring_advance(struct intel_ring_buffer *ring)
1219 {
1220 ring->tail &= ring->size - 1;
1221 ring->write_tail(ring, ring->tail);
1222 }
1223
1224
1225 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1226 u32 value)
1227 {
1228 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1229
1230 /* Every tail move must follow the sequence below */
1231 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1232 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1233 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1234 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1235
1236 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1237 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1238 50))
1239 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1240
1241 I915_WRITE_TAIL(ring, value);
1242 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1243 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1244 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1245 }
1246
1247 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1248 u32 invalidate, u32 flush)
1249 {
1250 uint32_t cmd;
1251 int ret;
1252
1253 ret = intel_ring_begin(ring, 4);
1254 if (ret)
1255 return ret;
1256
1257 cmd = MI_FLUSH_DW;
1258 if (invalidate & I915_GEM_GPU_DOMAINS)
1259 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1260 intel_ring_emit(ring, cmd);
1261 intel_ring_emit(ring, 0);
1262 intel_ring_emit(ring, 0);
1263 intel_ring_emit(ring, MI_NOOP);
1264 intel_ring_advance(ring);
1265 return 0;
1266 }
1267
1268 static int
1269 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1270 u32 offset, u32 len)
1271 {
1272 int ret;
1273
1274 ret = intel_ring_begin(ring, 2);
1275 if (ret)
1276 return ret;
1277
1278 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1279 /* bit0-7 is the length on GEN6+ */
1280 intel_ring_emit(ring, offset);
1281 intel_ring_advance(ring);
1282
1283 return 0;
1284 }
1285
1286 /* Blitter support (SandyBridge+) */
1287
1288 static int blt_ring_flush(struct intel_ring_buffer *ring,
1289 u32 invalidate, u32 flush)
1290 {
1291 uint32_t cmd;
1292 int ret;
1293
1294 ret = intel_ring_begin(ring, 4);
1295 if (ret)
1296 return ret;
1297
1298 cmd = MI_FLUSH_DW;
1299 if (invalidate & I915_GEM_DOMAIN_RENDER)
1300 cmd |= MI_INVALIDATE_TLB;
1301 intel_ring_emit(ring, cmd);
1302 intel_ring_emit(ring, 0);
1303 intel_ring_emit(ring, 0);
1304 intel_ring_emit(ring, MI_NOOP);
1305 intel_ring_advance(ring);
1306 return 0;
1307 }
1308
1309 int intel_init_render_ring_buffer(struct drm_device *dev)
1310 {
1311 drm_i915_private_t *dev_priv = dev->dev_private;
1312 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1313
1314 ring->name = "render ring";
1315 ring->id = RCS;
1316 ring->mmio_base = RENDER_RING_BASE;
1317
1318 if (INTEL_INFO(dev)->gen >= 6) {
1319 ring->add_request = gen6_add_request;
1320 ring->flush = gen6_render_ring_flush;
1321 ring->irq_get = gen6_ring_get_irq;
1322 ring->irq_put = gen6_ring_put_irq;
1323 ring->irq_enable_mask = GT_USER_INTERRUPT;
1324 ring->get_seqno = gen6_ring_get_seqno;
1325 ring->sync_to = gen6_ring_sync;
1326 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1327 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1328 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1329 ring->signal_mbox[0] = GEN6_VRSYNC;
1330 ring->signal_mbox[1] = GEN6_BRSYNC;
1331 } else if (IS_GEN5(dev)) {
1332 ring->add_request = pc_render_add_request;
1333 ring->flush = gen4_render_ring_flush;
1334 ring->get_seqno = pc_render_get_seqno;
1335 ring->irq_get = gen5_ring_get_irq;
1336 ring->irq_put = gen5_ring_put_irq;
1337 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1338 } else {
1339 ring->add_request = i9xx_add_request;
1340 if (INTEL_INFO(dev)->gen < 4)
1341 ring->flush = gen2_render_ring_flush;
1342 else
1343 ring->flush = gen4_render_ring_flush;
1344 ring->get_seqno = ring_get_seqno;
1345 if (IS_GEN2(dev)) {
1346 ring->irq_get = i8xx_ring_get_irq;
1347 ring->irq_put = i8xx_ring_put_irq;
1348 } else {
1349 ring->irq_get = i9xx_ring_get_irq;
1350 ring->irq_put = i9xx_ring_put_irq;
1351 }
1352 ring->irq_enable_mask = I915_USER_INTERRUPT;
1353 }
1354 ring->write_tail = ring_write_tail;
1355 if (INTEL_INFO(dev)->gen >= 6)
1356 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1357 else if (INTEL_INFO(dev)->gen >= 4)
1358 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1359 else if (IS_I830(dev) || IS_845G(dev))
1360 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1361 else
1362 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1363 ring->init = init_render_ring;
1364 ring->cleanup = render_ring_cleanup;
1365
1366
1367 if (!I915_NEED_GFX_HWS(dev)) {
1368 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1369 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1370 }
1371
1372 return intel_init_ring_buffer(dev, ring);
1373 }
1374
1375 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1376 {
1377 drm_i915_private_t *dev_priv = dev->dev_private;
1378 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1379
1380 ring->name = "render ring";
1381 ring->id = RCS;
1382 ring->mmio_base = RENDER_RING_BASE;
1383
1384 if (INTEL_INFO(dev)->gen >= 6) {
1385 /* non-kms not supported on gen6+ */
1386 return -ENODEV;
1387 }
1388
1389 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1390 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1391 * the special gen5 functions. */
1392 ring->add_request = i9xx_add_request;
1393 if (INTEL_INFO(dev)->gen < 4)
1394 ring->flush = gen2_render_ring_flush;
1395 else
1396 ring->flush = gen4_render_ring_flush;
1397 ring->get_seqno = ring_get_seqno;
1398 if (IS_GEN2(dev)) {
1399 ring->irq_get = i8xx_ring_get_irq;
1400 ring->irq_put = i8xx_ring_put_irq;
1401 } else {
1402 ring->irq_get = i9xx_ring_get_irq;
1403 ring->irq_put = i9xx_ring_put_irq;
1404 }
1405 ring->irq_enable_mask = I915_USER_INTERRUPT;
1406 ring->write_tail = ring_write_tail;
1407 if (INTEL_INFO(dev)->gen >= 4)
1408 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1409 else if (IS_I830(dev) || IS_845G(dev))
1410 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1411 else
1412 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1413 ring->init = init_render_ring;
1414 ring->cleanup = render_ring_cleanup;
1415
1416 if (!I915_NEED_GFX_HWS(dev))
1417 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1418
1419 ring->dev = dev;
1420 INIT_LIST_HEAD(&ring->active_list);
1421 INIT_LIST_HEAD(&ring->request_list);
1422 INIT_LIST_HEAD(&ring->gpu_write_list);
1423
1424 ring->size = size;
1425 ring->effective_size = ring->size;
1426 if (IS_I830(ring->dev))
1427 ring->effective_size -= 128;
1428
1429 ring->map.offset = start;
1430 ring->map.size = size;
1431 ring->map.type = 0;
1432 ring->map.flags = 0;
1433 ring->map.mtrr = 0;
1434
1435 drm_core_ioremap_wc(&ring->map, dev);
1436 if (ring->map.handle == NULL) {
1437 DRM_ERROR("can not ioremap virtual address for"
1438 " ring buffer\n");
1439 return -ENOMEM;
1440 }
1441
1442 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1443 return 0;
1444 }
1445
1446 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1447 {
1448 drm_i915_private_t *dev_priv = dev->dev_private;
1449 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1450
1451 ring->name = "bsd ring";
1452 ring->id = VCS;
1453
1454 ring->write_tail = ring_write_tail;
1455 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1456 ring->mmio_base = GEN6_BSD_RING_BASE;
1457 /* gen6 bsd needs a special wa for tail updates */
1458 if (IS_GEN6(dev))
1459 ring->write_tail = gen6_bsd_ring_write_tail;
1460 ring->flush = gen6_ring_flush;
1461 ring->add_request = gen6_add_request;
1462 ring->get_seqno = gen6_ring_get_seqno;
1463 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1464 ring->irq_get = gen6_ring_get_irq;
1465 ring->irq_put = gen6_ring_put_irq;
1466 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1467 ring->sync_to = gen6_ring_sync;
1468 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1469 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1470 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1471 ring->signal_mbox[0] = GEN6_RVSYNC;
1472 ring->signal_mbox[1] = GEN6_BVSYNC;
1473 } else {
1474 ring->mmio_base = BSD_RING_BASE;
1475 ring->flush = bsd_ring_flush;
1476 ring->add_request = i9xx_add_request;
1477 ring->get_seqno = ring_get_seqno;
1478 if (IS_GEN5(dev)) {
1479 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1480 ring->irq_get = gen5_ring_get_irq;
1481 ring->irq_put = gen5_ring_put_irq;
1482 } else {
1483 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1484 ring->irq_get = i9xx_ring_get_irq;
1485 ring->irq_put = i9xx_ring_put_irq;
1486 }
1487 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1488 }
1489 ring->init = init_ring_common;
1490
1491
1492 return intel_init_ring_buffer(dev, ring);
1493 }
1494
1495 int intel_init_blt_ring_buffer(struct drm_device *dev)
1496 {
1497 drm_i915_private_t *dev_priv = dev->dev_private;
1498 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1499
1500 ring->name = "blitter ring";
1501 ring->id = BCS;
1502
1503 ring->mmio_base = BLT_RING_BASE;
1504 ring->write_tail = ring_write_tail;
1505 ring->flush = blt_ring_flush;
1506 ring->add_request = gen6_add_request;
1507 ring->get_seqno = gen6_ring_get_seqno;
1508 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1509 ring->irq_get = gen6_ring_get_irq;
1510 ring->irq_put = gen6_ring_put_irq;
1511 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1512 ring->sync_to = gen6_ring_sync;
1513 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1514 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1515 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1516 ring->signal_mbox[0] = GEN6_RBSYNC;
1517 ring->signal_mbox[1] = GEN6_VBSYNC;
1518 ring->init = init_ring_common;
1519
1520 return intel_init_ring_buffer(dev, ring);
1521 }
Linux kernel - Deliverables
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