projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 ret = intel_emit_post_sync_nonzero_flush(ring);
223 if (ret)
224 return ret;
225
226 /* Just flush everything. Experiments have shown that reducing the
227 * number of bits based on the write domains has little performance
228 * impact.
229 */
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_TLB_INVALIDATE;
232 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
235 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
236 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
237 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
238 /*
239 * Ensure that any following seqno writes only happen when the render
240 * cache is indeed flushed (but only if the caller actually wants that).
241 */
242 if (flush_domains)
243 flags |= PIPE_CONTROL_CS_STALL;
244
245 ret = intel_ring_begin(ring, 6);
246 if (ret)
247 return ret;
248
249 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
250 intel_ring_emit(ring, flags);
251 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
252 intel_ring_emit(ring, 0); /* lower dword */
253 intel_ring_emit(ring, 0); /* uppwer dword */
254 intel_ring_emit(ring, MI_NOOP);
255 intel_ring_advance(ring);
256
257 return 0;
258 }
259
260 static void ring_write_tail(struct intel_ring_buffer *ring,
261 u32 value)
262 {
263 drm_i915_private_t *dev_priv = ring->dev->dev_private;
264 I915_WRITE_TAIL(ring, value);
265 }
266
267 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
268 {
269 drm_i915_private_t *dev_priv = ring->dev->dev_private;
270 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
271 RING_ACTHD(ring->mmio_base) : ACTHD;
272
273 return I915_READ(acthd_reg);
274 }
275
276 static int init_ring_common(struct intel_ring_buffer *ring)
277 {
278 struct drm_device *dev = ring->dev;
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 struct drm_i915_gem_object *obj = ring->obj;
281 int ret = 0;
282 u32 head;
283
284 if (HAS_FORCE_WAKE(dev))
285 gen6_gt_force_wake_get(dev_priv);
286
287 /* Stop the ring if it's running. */
288 I915_WRITE_CTL(ring, 0);
289 I915_WRITE_HEAD(ring, 0);
290 ring->write_tail(ring, 0);
291
292 head = I915_READ_HEAD(ring) & HEAD_ADDR;
293
294 /* G45 ring initialization fails to reset head to zero */
295 if (head != 0) {
296 DRM_DEBUG_KMS("%s head not reset to zero "
297 "ctl %08x head %08x tail %08x start %08x\n",
298 ring->name,
299 I915_READ_CTL(ring),
300 I915_READ_HEAD(ring),
301 I915_READ_TAIL(ring),
302 I915_READ_START(ring));
303
304 I915_WRITE_HEAD(ring, 0);
305
306 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
307 DRM_ERROR("failed to set %s head to zero "
308 "ctl %08x head %08x tail %08x start %08x\n",
309 ring->name,
310 I915_READ_CTL(ring),
311 I915_READ_HEAD(ring),
312 I915_READ_TAIL(ring),
313 I915_READ_START(ring));
314 }
315 }
316
317 /* Initialize the ring. This must happen _after_ we've cleared the ring
318 * registers with the above sequence (the readback of the HEAD registers
319 * also enforces ordering), otherwise the hw might lose the new ring
320 * register values. */
321 I915_WRITE_START(ring, obj->gtt_offset);
322 I915_WRITE_CTL(ring,
323 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
324 | RING_VALID);
325
326 /* If the head is still not zero, the ring is dead */
327 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
328 I915_READ_START(ring) == obj->gtt_offset &&
329 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
330 DRM_ERROR("%s initialization failed "
331 "ctl %08x head %08x tail %08x start %08x\n",
332 ring->name,
333 I915_READ_CTL(ring),
334 I915_READ_HEAD(ring),
335 I915_READ_TAIL(ring),
336 I915_READ_START(ring));
337 ret = -EIO;
338 goto out;
339 }
340
341 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
342 i915_kernel_lost_context(ring->dev);
343 else {
344 ring->head = I915_READ_HEAD(ring);
345 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
346 ring->space = ring_space(ring);
347 ring->last_retired_head = -1;
348 }
349
350 out:
351 if (HAS_FORCE_WAKE(dev))
352 gen6_gt_force_wake_put(dev_priv);
353
354 return ret;
355 }
356
357 static int
358 init_pipe_control(struct intel_ring_buffer *ring)
359 {
360 struct pipe_control *pc;
361 struct drm_i915_gem_object *obj;
362 int ret;
363
364 if (ring->private)
365 return 0;
366
367 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
368 if (!pc)
369 return -ENOMEM;
370
371 obj = i915_gem_alloc_object(ring->dev, 4096);
372 if (obj == NULL) {
373 DRM_ERROR("Failed to allocate seqno page\n");
374 ret = -ENOMEM;
375 goto err;
376 }
377
378 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
379
380 ret = i915_gem_object_pin(obj, 4096, true);
381 if (ret)
382 goto err_unref;
383
384 pc->gtt_offset = obj->gtt_offset;
385 pc->cpu_page = kmap(obj->pages[0]);
386 if (pc->cpu_page == NULL)
387 goto err_unpin;
388
389 pc->obj = obj;
390 ring->private = pc;
391 return 0;
392
393 err_unpin:
394 i915_gem_object_unpin(obj);
395 err_unref:
396 drm_gem_object_unreference(&obj->base);
397 err:
398 kfree(pc);
399 return ret;
400 }
401
402 static void
403 cleanup_pipe_control(struct intel_ring_buffer *ring)
404 {
405 struct pipe_control *pc = ring->private;
406 struct drm_i915_gem_object *obj;
407
408 if (!ring->private)
409 return;
410
411 obj = pc->obj;
412 kunmap(obj->pages[0]);
413 i915_gem_object_unpin(obj);
414 drm_gem_object_unreference(&obj->base);
415
416 kfree(pc);
417 ring->private = NULL;
418 }
419
420 static int init_render_ring(struct intel_ring_buffer *ring)
421 {
422 struct drm_device *dev = ring->dev;
423 struct drm_i915_private *dev_priv = dev->dev_private;
424 int ret = init_ring_common(ring);
425
426 if (INTEL_INFO(dev)->gen > 3) {
427 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
428 if (IS_GEN7(dev))
429 I915_WRITE(GFX_MODE_GEN7,
430 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
431 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
432 }
433
434 if (INTEL_INFO(dev)->gen >= 5) {
435 ret = init_pipe_control(ring);
436 if (ret)
437 return ret;
438 }
439
440 if (IS_GEN6(dev)) {
441 /* From the Sandybridge PRM, volume 1 part 3, page 24:
442 * "If this bit is set, STCunit will have LRA as replacement
443 * policy. [...] This bit must be reset. LRA replacement
444 * policy is not supported."
445 */
446 I915_WRITE(CACHE_MODE_0,
447 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
448
449 /* This is not explicitly set for GEN6, so read the register.
450 * see intel_ring_mi_set_context() for why we care.
451 * TODO: consider explicitly setting the bit for GEN5
452 */
453 ring->itlb_before_ctx_switch =
454 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
455 }
456
457 if (INTEL_INFO(dev)->gen >= 6)
458 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
459
460 if (IS_IVYBRIDGE(dev))
461 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
462
463 return ret;
464 }
465
466 static void render_ring_cleanup(struct intel_ring_buffer *ring)
467 {
468 if (!ring->private)
469 return;
470
471 cleanup_pipe_control(ring);
472 }
473
474 static void
475 update_mboxes(struct intel_ring_buffer *ring,
476 u32 seqno,
477 u32 mmio_offset)
478 {
479 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
480 MI_SEMAPHORE_GLOBAL_GTT |
481 MI_SEMAPHORE_REGISTER |
482 MI_SEMAPHORE_UPDATE);
483 intel_ring_emit(ring, seqno);
484 intel_ring_emit(ring, mmio_offset);
485 }
486
487 /**
488 * gen6_add_request - Update the semaphore mailbox registers
489 *
490 * @ring - ring that is adding a request
491 * @seqno - return seqno stuck into the ring
492 *
493 * Update the mailbox registers in the *other* rings with the current seqno.
494 * This acts like a signal in the canonical semaphore.
495 */
496 static int
497 gen6_add_request(struct intel_ring_buffer *ring,
498 u32 *seqno)
499 {
500 u32 mbox1_reg;
501 u32 mbox2_reg;
502 int ret;
503
504 ret = intel_ring_begin(ring, 10);
505 if (ret)
506 return ret;
507
508 mbox1_reg = ring->signal_mbox[0];
509 mbox2_reg = ring->signal_mbox[1];
510
511 *seqno = i915_gem_next_request_seqno(ring);
512
513 update_mboxes(ring, *seqno, mbox1_reg);
514 update_mboxes(ring, *seqno, mbox2_reg);
515 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
516 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
517 intel_ring_emit(ring, *seqno);
518 intel_ring_emit(ring, MI_USER_INTERRUPT);
519 intel_ring_advance(ring);
520
521 return 0;
522 }
523
524 /**
525 * intel_ring_sync - sync the waiter to the signaller on seqno
526 *
527 * @waiter - ring that is waiting
528 * @signaller - ring which has, or will signal
529 * @seqno - seqno which the waiter will block on
530 */
531 static int
532 gen6_ring_sync(struct intel_ring_buffer *waiter,
533 struct intel_ring_buffer *signaller,
534 u32 seqno)
535 {
536 int ret;
537 u32 dw1 = MI_SEMAPHORE_MBOX |
538 MI_SEMAPHORE_COMPARE |
539 MI_SEMAPHORE_REGISTER;
540
541 /* Throughout all of the GEM code, seqno passed implies our current
542 * seqno is >= the last seqno executed. However for hardware the
543 * comparison is strictly greater than.
544 */
545 seqno -= 1;
546
547 WARN_ON(signaller->semaphore_register[waiter->id] ==
548 MI_SEMAPHORE_SYNC_INVALID);
549
550 ret = intel_ring_begin(waiter, 4);
551 if (ret)
552 return ret;
553
554 intel_ring_emit(waiter,
555 dw1 | signaller->semaphore_register[waiter->id]);
556 intel_ring_emit(waiter, seqno);
557 intel_ring_emit(waiter, 0);
558 intel_ring_emit(waiter, MI_NOOP);
559 intel_ring_advance(waiter);
560
561 return 0;
562 }
563
564 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
565 do { \
566 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
567 PIPE_CONTROL_DEPTH_STALL); \
568 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
569 intel_ring_emit(ring__, 0); \
570 intel_ring_emit(ring__, 0); \
571 } while (0)
572
573 static int
574 pc_render_add_request(struct intel_ring_buffer *ring,
575 u32 *result)
576 {
577 u32 seqno = i915_gem_next_request_seqno(ring);
578 struct pipe_control *pc = ring->private;
579 u32 scratch_addr = pc->gtt_offset + 128;
580 int ret;
581
582 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
583 * incoherent with writes to memory, i.e. completely fubar,
584 * so we need to use PIPE_NOTIFY instead.
585 *
586 * However, we also need to workaround the qword write
587 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
588 * memory before requesting an interrupt.
589 */
590 ret = intel_ring_begin(ring, 32);
591 if (ret)
592 return ret;
593
594 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
595 PIPE_CONTROL_WRITE_FLUSH |
596 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
597 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
598 intel_ring_emit(ring, seqno);
599 intel_ring_emit(ring, 0);
600 PIPE_CONTROL_FLUSH(ring, scratch_addr);
601 scratch_addr += 128; /* write to separate cachelines */
602 PIPE_CONTROL_FLUSH(ring, scratch_addr);
603 scratch_addr += 128;
604 PIPE_CONTROL_FLUSH(ring, scratch_addr);
605 scratch_addr += 128;
606 PIPE_CONTROL_FLUSH(ring, scratch_addr);
607 scratch_addr += 128;
608 PIPE_CONTROL_FLUSH(ring, scratch_addr);
609 scratch_addr += 128;
610 PIPE_CONTROL_FLUSH(ring, scratch_addr);
611
612 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
613 PIPE_CONTROL_WRITE_FLUSH |
614 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
615 PIPE_CONTROL_NOTIFY);
616 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
617 intel_ring_emit(ring, seqno);
618 intel_ring_emit(ring, 0);
619 intel_ring_advance(ring);
620
621 *result = seqno;
622 return 0;
623 }
624
625 static u32
626 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
627 {
628 struct drm_device *dev = ring->dev;
629
630 /* Workaround to force correct ordering between irq and seqno writes on
631 * ivb (and maybe also on snb) by reading from a CS register (like
632 * ACTHD) before reading the status page. */
633 if (IS_GEN6(dev) || IS_GEN7(dev))
634 intel_ring_get_active_head(ring);
635 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
636 }
637
638 static u32
639 ring_get_seqno(struct intel_ring_buffer *ring)
640 {
641 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
642 }
643
644 static u32
645 pc_render_get_seqno(struct intel_ring_buffer *ring)
646 {
647 struct pipe_control *pc = ring->private;
648 return pc->cpu_page[0];
649 }
650
651 static bool
652 gen5_ring_get_irq(struct intel_ring_buffer *ring)
653 {
654 struct drm_device *dev = ring->dev;
655 drm_i915_private_t *dev_priv = dev->dev_private;
656 unsigned long flags;
657
658 if (!dev->irq_enabled)
659 return false;
660
661 spin_lock_irqsave(&dev_priv->irq_lock, flags);
662 if (ring->irq_refcount++ == 0) {
663 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
664 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
665 POSTING_READ(GTIMR);
666 }
667 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
668
669 return true;
670 }
671
672 static void
673 gen5_ring_put_irq(struct intel_ring_buffer *ring)
674 {
675 struct drm_device *dev = ring->dev;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 unsigned long flags;
678
679 spin_lock_irqsave(&dev_priv->irq_lock, flags);
680 if (--ring->irq_refcount == 0) {
681 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
682 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
683 POSTING_READ(GTIMR);
684 }
685 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
686 }
687
688 static bool
689 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
690 {
691 struct drm_device *dev = ring->dev;
692 drm_i915_private_t *dev_priv = dev->dev_private;
693 unsigned long flags;
694
695 if (!dev->irq_enabled)
696 return false;
697
698 spin_lock_irqsave(&dev_priv->irq_lock, flags);
699 if (ring->irq_refcount++ == 0) {
700 dev_priv->irq_mask &= ~ring->irq_enable_mask;
701 I915_WRITE(IMR, dev_priv->irq_mask);
702 POSTING_READ(IMR);
703 }
704 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
705
706 return true;
707 }
708
709 static void
710 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
711 {
712 struct drm_device *dev = ring->dev;
713 drm_i915_private_t *dev_priv = dev->dev_private;
714 unsigned long flags;
715
716 spin_lock_irqsave(&dev_priv->irq_lock, flags);
717 if (--ring->irq_refcount == 0) {
718 dev_priv->irq_mask |= ring->irq_enable_mask;
719 I915_WRITE(IMR, dev_priv->irq_mask);
720 POSTING_READ(IMR);
721 }
722 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
723 }
724
725 static bool
726 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
727 {
728 struct drm_device *dev = ring->dev;
729 drm_i915_private_t *dev_priv = dev->dev_private;
730 unsigned long flags;
731
732 if (!dev->irq_enabled)
733 return false;
734
735 spin_lock_irqsave(&dev_priv->irq_lock, flags);
736 if (ring->irq_refcount++ == 0) {
737 dev_priv->irq_mask &= ~ring->irq_enable_mask;
738 I915_WRITE16(IMR, dev_priv->irq_mask);
739 POSTING_READ16(IMR);
740 }
741 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
742
743 return true;
744 }
745
746 static void
747 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
748 {
749 struct drm_device *dev = ring->dev;
750 drm_i915_private_t *dev_priv = dev->dev_private;
751 unsigned long flags;
752
753 spin_lock_irqsave(&dev_priv->irq_lock, flags);
754 if (--ring->irq_refcount == 0) {
755 dev_priv->irq_mask |= ring->irq_enable_mask;
756 I915_WRITE16(IMR, dev_priv->irq_mask);
757 POSTING_READ16(IMR);
758 }
759 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
760 }
761
762 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
763 {
764 struct drm_device *dev = ring->dev;
765 drm_i915_private_t *dev_priv = ring->dev->dev_private;
766 u32 mmio = 0;
767
768 /* The ring status page addresses are no longer next to the rest of
769 * the ring registers as of gen7.
770 */
771 if (IS_GEN7(dev)) {
772 switch (ring->id) {
773 case RCS:
774 mmio = RENDER_HWS_PGA_GEN7;
775 break;
776 case BCS:
777 mmio = BLT_HWS_PGA_GEN7;
778 break;
779 case VCS:
780 mmio = BSD_HWS_PGA_GEN7;
781 break;
782 }
783 } else if (IS_GEN6(ring->dev)) {
784 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
785 } else {
786 mmio = RING_HWS_PGA(ring->mmio_base);
787 }
788
789 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
790 POSTING_READ(mmio);
791 }
792
793 static int
794 bsd_ring_flush(struct intel_ring_buffer *ring,
795 u32 invalidate_domains,
796 u32 flush_domains)
797 {
798 int ret;
799
800 ret = intel_ring_begin(ring, 2);
801 if (ret)
802 return ret;
803
804 intel_ring_emit(ring, MI_FLUSH);
805 intel_ring_emit(ring, MI_NOOP);
806 intel_ring_advance(ring);
807 return 0;
808 }
809
810 static int
811 i9xx_add_request(struct intel_ring_buffer *ring,
812 u32 *result)
813 {
814 u32 seqno;
815 int ret;
816
817 ret = intel_ring_begin(ring, 4);
818 if (ret)
819 return ret;
820
821 seqno = i915_gem_next_request_seqno(ring);
822
823 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
824 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
825 intel_ring_emit(ring, seqno);
826 intel_ring_emit(ring, MI_USER_INTERRUPT);
827 intel_ring_advance(ring);
828
829 *result = seqno;
830 return 0;
831 }
832
833 static bool
834 gen6_ring_get_irq(struct intel_ring_buffer *ring)
835 {
836 struct drm_device *dev = ring->dev;
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 unsigned long flags;
839
840 if (!dev->irq_enabled)
841 return false;
842
843 /* It looks like we need to prevent the gt from suspending while waiting
844 * for an notifiy irq, otherwise irqs seem to get lost on at least the
845 * blt/bsd rings on ivb. */
846 gen6_gt_force_wake_get(dev_priv);
847
848 spin_lock_irqsave(&dev_priv->irq_lock, flags);
849 if (ring->irq_refcount++ == 0) {
850 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
851 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
852 GEN6_RENDER_L3_PARITY_ERROR));
853 else
854 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
855 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
856 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
857 POSTING_READ(GTIMR);
858 }
859 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
860
861 return true;
862 }
863
864 static void
865 gen6_ring_put_irq(struct intel_ring_buffer *ring)
866 {
867 struct drm_device *dev = ring->dev;
868 drm_i915_private_t *dev_priv = dev->dev_private;
869 unsigned long flags;
870
871 spin_lock_irqsave(&dev_priv->irq_lock, flags);
872 if (--ring->irq_refcount == 0) {
873 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
874 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
875 else
876 I915_WRITE_IMR(ring, ~0);
877 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
878 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
879 POSTING_READ(GTIMR);
880 }
881 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
882
883 gen6_gt_force_wake_put(dev_priv);
884 }
885
886 static int
887 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
888 {
889 int ret;
890
891 ret = intel_ring_begin(ring, 2);
892 if (ret)
893 return ret;
894
895 intel_ring_emit(ring,
896 MI_BATCH_BUFFER_START |
897 MI_BATCH_GTT |
898 MI_BATCH_NON_SECURE_I965);
899 intel_ring_emit(ring, offset);
900 intel_ring_advance(ring);
901
902 return 0;
903 }
904
905 static int
906 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
907 u32 offset, u32 len)
908 {
909 int ret;
910
911 ret = intel_ring_begin(ring, 4);
912 if (ret)
913 return ret;
914
915 intel_ring_emit(ring, MI_BATCH_BUFFER);
916 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
917 intel_ring_emit(ring, offset + len - 8);
918 intel_ring_emit(ring, 0);
919 intel_ring_advance(ring);
920
921 return 0;
922 }
923
924 static int
925 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
926 u32 offset, u32 len)
927 {
928 int ret;
929
930 ret = intel_ring_begin(ring, 2);
931 if (ret)
932 return ret;
933
934 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
935 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
936 intel_ring_advance(ring);
937
938 return 0;
939 }
940
941 static void cleanup_status_page(struct intel_ring_buffer *ring)
942 {
943 struct drm_i915_gem_object *obj;
944
945 obj = ring->status_page.obj;
946 if (obj == NULL)
947 return;
948
949 kunmap(obj->pages[0]);
950 i915_gem_object_unpin(obj);
951 drm_gem_object_unreference(&obj->base);
952 ring->status_page.obj = NULL;
953 }
954
955 static int init_status_page(struct intel_ring_buffer *ring)
956 {
957 struct drm_device *dev = ring->dev;
958 struct drm_i915_gem_object *obj;
959 int ret;
960
961 obj = i915_gem_alloc_object(dev, 4096);
962 if (obj == NULL) {
963 DRM_ERROR("Failed to allocate status page\n");
964 ret = -ENOMEM;
965 goto err;
966 }
967
968 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
969
970 ret = i915_gem_object_pin(obj, 4096, true);
971 if (ret != 0) {
972 goto err_unref;
973 }
974
975 ring->status_page.gfx_addr = obj->gtt_offset;
976 ring->status_page.page_addr = kmap(obj->pages[0]);
977 if (ring->status_page.page_addr == NULL) {
978 ret = -ENOMEM;
979 goto err_unpin;
980 }
981 ring->status_page.obj = obj;
982 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
983
984 intel_ring_setup_status_page(ring);
985 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
986 ring->name, ring->status_page.gfx_addr);
987
988 return 0;
989
990 err_unpin:
991 i915_gem_object_unpin(obj);
992 err_unref:
993 drm_gem_object_unreference(&obj->base);
994 err:
995 return ret;
996 }
997
998 static int intel_init_ring_buffer(struct drm_device *dev,
999 struct intel_ring_buffer *ring)
1000 {
1001 struct drm_i915_gem_object *obj;
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 int ret;
1004
1005 ring->dev = dev;
1006 INIT_LIST_HEAD(&ring->active_list);
1007 INIT_LIST_HEAD(&ring->request_list);
1008 INIT_LIST_HEAD(&ring->gpu_write_list);
1009 ring->size = 32 * PAGE_SIZE;
1010
1011 init_waitqueue_head(&ring->irq_queue);
1012
1013 if (I915_NEED_GFX_HWS(dev)) {
1014 ret = init_status_page(ring);
1015 if (ret)
1016 return ret;
1017 }
1018
1019 obj = i915_gem_alloc_object(dev, ring->size);
1020 if (obj == NULL) {
1021 DRM_ERROR("Failed to allocate ringbuffer\n");
1022 ret = -ENOMEM;
1023 goto err_hws;
1024 }
1025
1026 ring->obj = obj;
1027
1028 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1029 if (ret)
1030 goto err_unref;
1031
1032 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1033 if (ret)
1034 goto err_unpin;
1035
1036 ring->virtual_start =
1037 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1038 ring->size);
1039 if (ring->virtual_start == NULL) {
1040 DRM_ERROR("Failed to map ringbuffer.\n");
1041 ret = -EINVAL;
1042 goto err_unpin;
1043 }
1044
1045 ret = ring->init(ring);
1046 if (ret)
1047 goto err_unmap;
1048
1049 /* Workaround an erratum on the i830 which causes a hang if
1050 * the TAIL pointer points to within the last 2 cachelines
1051 * of the buffer.
1052 */
1053 ring->effective_size = ring->size;
1054 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1055 ring->effective_size -= 128;
1056
1057 return 0;
1058
1059 err_unmap:
1060 iounmap(ring->virtual_start);
1061 err_unpin:
1062 i915_gem_object_unpin(obj);
1063 err_unref:
1064 drm_gem_object_unreference(&obj->base);
1065 ring->obj = NULL;
1066 err_hws:
1067 cleanup_status_page(ring);
1068 return ret;
1069 }
1070
1071 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1072 {
1073 struct drm_i915_private *dev_priv;
1074 int ret;
1075
1076 if (ring->obj == NULL)
1077 return;
1078
1079 /* Disable the ring buffer. The ring must be idle at this point */
1080 dev_priv = ring->dev->dev_private;
1081 ret = intel_wait_ring_idle(ring);
1082 if (ret)
1083 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1084 ring->name, ret);
1085
1086 I915_WRITE_CTL(ring, 0);
1087
1088 iounmap(ring->virtual_start);
1089
1090 i915_gem_object_unpin(ring->obj);
1091 drm_gem_object_unreference(&ring->obj->base);
1092 ring->obj = NULL;
1093
1094 if (ring->cleanup)
1095 ring->cleanup(ring);
1096
1097 cleanup_status_page(ring);
1098 }
1099
1100 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1101 {
1102 uint32_t __iomem *virt;
1103 int rem = ring->size - ring->tail;
1104
1105 if (ring->space < rem) {
1106 int ret = intel_wait_ring_buffer(ring, rem);
1107 if (ret)
1108 return ret;
1109 }
1110
1111 virt = ring->virtual_start + ring->tail;
1112 rem /= 4;
1113 while (rem--)
1114 iowrite32(MI_NOOP, virt++);
1115
1116 ring->tail = 0;
1117 ring->space = ring_space(ring);
1118
1119 return 0;
1120 }
1121
1122 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1123 {
1124 int ret;
1125
1126 ret = i915_wait_seqno(ring, seqno);
1127 if (!ret)
1128 i915_gem_retire_requests_ring(ring);
1129
1130 return ret;
1131 }
1132
1133 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1134 {
1135 struct drm_i915_gem_request *request;
1136 u32 seqno = 0;
1137 int ret;
1138
1139 i915_gem_retire_requests_ring(ring);
1140
1141 if (ring->last_retired_head != -1) {
1142 ring->head = ring->last_retired_head;
1143 ring->last_retired_head = -1;
1144 ring->space = ring_space(ring);
1145 if (ring->space >= n)
1146 return 0;
1147 }
1148
1149 list_for_each_entry(request, &ring->request_list, list) {
1150 int space;
1151
1152 if (request->tail == -1)
1153 continue;
1154
1155 space = request->tail - (ring->tail + 8);
1156 if (space < 0)
1157 space += ring->size;
1158 if (space >= n) {
1159 seqno = request->seqno;
1160 break;
1161 }
1162
1163 /* Consume this request in case we need more space than
1164 * is available and so need to prevent a race between
1165 * updating last_retired_head and direct reads of
1166 * I915_RING_HEAD. It also provides a nice sanity check.
1167 */
1168 request->tail = -1;
1169 }
1170
1171 if (seqno == 0)
1172 return -ENOSPC;
1173
1174 ret = intel_ring_wait_seqno(ring, seqno);
1175 if (ret)
1176 return ret;
1177
1178 if (WARN_ON(ring->last_retired_head == -1))
1179 return -ENOSPC;
1180
1181 ring->head = ring->last_retired_head;
1182 ring->last_retired_head = -1;
1183 ring->space = ring_space(ring);
1184 if (WARN_ON(ring->space < n))
1185 return -ENOSPC;
1186
1187 return 0;
1188 }
1189
1190 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1191 {
1192 struct drm_device *dev = ring->dev;
1193 struct drm_i915_private *dev_priv = dev->dev_private;
1194 unsigned long end;
1195 int ret;
1196
1197 ret = intel_ring_wait_request(ring, n);
1198 if (ret != -ENOSPC)
1199 return ret;
1200
1201 trace_i915_ring_wait_begin(ring);
1202 /* With GEM the hangcheck timer should kick us out of the loop,
1203 * leaving it early runs the risk of corrupting GEM state (due
1204 * to running on almost untested codepaths). But on resume
1205 * timers don't work yet, so prevent a complete hang in that
1206 * case by choosing an insanely large timeout. */
1207 end = jiffies + 60 * HZ;
1208
1209 do {
1210 ring->head = I915_READ_HEAD(ring);
1211 ring->space = ring_space(ring);
1212 if (ring->space >= n) {
1213 trace_i915_ring_wait_end(ring);
1214 return 0;
1215 }
1216
1217 if (dev->primary->master) {
1218 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1219 if (master_priv->sarea_priv)
1220 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1221 }
1222
1223 msleep(1);
1224
1225 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1226 if (ret)
1227 return ret;
1228 } while (!time_after(jiffies, end));
1229 trace_i915_ring_wait_end(ring);
1230 return -EBUSY;
1231 }
1232
1233 int intel_ring_begin(struct intel_ring_buffer *ring,
1234 int num_dwords)
1235 {
1236 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1237 int n = 4*num_dwords;
1238 int ret;
1239
1240 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1241 if (ret)
1242 return ret;
1243
1244 if (unlikely(ring->tail + n > ring->effective_size)) {
1245 ret = intel_wrap_ring_buffer(ring);
1246 if (unlikely(ret))
1247 return ret;
1248 }
1249
1250 if (unlikely(ring->space < n)) {
1251 ret = intel_wait_ring_buffer(ring, n);
1252 if (unlikely(ret))
1253 return ret;
1254 }
1255
1256 ring->space -= n;
1257 return 0;
1258 }
1259
1260 void intel_ring_advance(struct intel_ring_buffer *ring)
1261 {
1262 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1263
1264 ring->tail &= ring->size - 1;
1265 if (dev_priv->stop_rings & intel_ring_flag(ring))
1266 return;
1267 ring->write_tail(ring, ring->tail);
1268 }
1269
1270
1271 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1272 u32 value)
1273 {
1274 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1275
1276 /* Every tail move must follow the sequence below */
1277
1278 /* Disable notification that the ring is IDLE. The GT
1279 * will then assume that it is busy and bring it out of rc6.
1280 */
1281 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1282 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1283
1284 /* Clear the context id. Here be magic! */
1285 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1286
1287 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1288 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1289 GEN6_BSD_SLEEP_INDICATOR) == 0,
1290 50))
1291 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1292
1293 /* Now that the ring is fully powered up, update the tail */
1294 I915_WRITE_TAIL(ring, value);
1295 POSTING_READ(RING_TAIL(ring->mmio_base));
1296
1297 /* Let the ring send IDLE messages to the GT again,
1298 * and so let it sleep to conserve power when idle.
1299 */
1300 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1301 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1302 }
1303
1304 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1305 u32 invalidate, u32 flush)
1306 {
1307 uint32_t cmd;
1308 int ret;
1309
1310 ret = intel_ring_begin(ring, 4);
1311 if (ret)
1312 return ret;
1313
1314 cmd = MI_FLUSH_DW;
1315 if (invalidate & I915_GEM_GPU_DOMAINS)
1316 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1317 intel_ring_emit(ring, cmd);
1318 intel_ring_emit(ring, 0);
1319 intel_ring_emit(ring, 0);
1320 intel_ring_emit(ring, MI_NOOP);
1321 intel_ring_advance(ring);
1322 return 0;
1323 }
1324
1325 static int
1326 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1327 u32 offset, u32 len)
1328 {
1329 int ret;
1330
1331 ret = intel_ring_begin(ring, 2);
1332 if (ret)
1333 return ret;
1334
1335 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1336 /* bit0-7 is the length on GEN6+ */
1337 intel_ring_emit(ring, offset);
1338 intel_ring_advance(ring);
1339
1340 return 0;
1341 }
1342
1343 /* Blitter support (SandyBridge+) */
1344
1345 static int blt_ring_flush(struct intel_ring_buffer *ring,
1346 u32 invalidate, u32 flush)
1347 {
1348 uint32_t cmd;
1349 int ret;
1350
1351 ret = intel_ring_begin(ring, 4);
1352 if (ret)
1353 return ret;
1354
1355 cmd = MI_FLUSH_DW;
1356 if (invalidate & I915_GEM_DOMAIN_RENDER)
1357 cmd |= MI_INVALIDATE_TLB;
1358 intel_ring_emit(ring, cmd);
1359 intel_ring_emit(ring, 0);
1360 intel_ring_emit(ring, 0);
1361 intel_ring_emit(ring, MI_NOOP);
1362 intel_ring_advance(ring);
1363 return 0;
1364 }
1365
1366 int intel_init_render_ring_buffer(struct drm_device *dev)
1367 {
1368 drm_i915_private_t *dev_priv = dev->dev_private;
1369 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1370
1371 ring->name = "render ring";
1372 ring->id = RCS;
1373 ring->mmio_base = RENDER_RING_BASE;
1374
1375 if (INTEL_INFO(dev)->gen >= 6) {
1376 ring->add_request = gen6_add_request;
1377 ring->flush = gen6_render_ring_flush;
1378 ring->irq_get = gen6_ring_get_irq;
1379 ring->irq_put = gen6_ring_put_irq;
1380 ring->irq_enable_mask = GT_USER_INTERRUPT;
1381 ring->get_seqno = gen6_ring_get_seqno;
1382 ring->sync_to = gen6_ring_sync;
1383 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1384 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1385 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1386 ring->signal_mbox[0] = GEN6_VRSYNC;
1387 ring->signal_mbox[1] = GEN6_BRSYNC;
1388 } else if (IS_GEN5(dev)) {
1389 ring->add_request = pc_render_add_request;
1390 ring->flush = gen4_render_ring_flush;
1391 ring->get_seqno = pc_render_get_seqno;
1392 ring->irq_get = gen5_ring_get_irq;
1393 ring->irq_put = gen5_ring_put_irq;
1394 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1395 } else {
1396 ring->add_request = i9xx_add_request;
1397 if (INTEL_INFO(dev)->gen < 4)
1398 ring->flush = gen2_render_ring_flush;
1399 else
1400 ring->flush = gen4_render_ring_flush;
1401 ring->get_seqno = ring_get_seqno;
1402 if (IS_GEN2(dev)) {
1403 ring->irq_get = i8xx_ring_get_irq;
1404 ring->irq_put = i8xx_ring_put_irq;
1405 } else {
1406 ring->irq_get = i9xx_ring_get_irq;
1407 ring->irq_put = i9xx_ring_put_irq;
1408 }
1409 ring->irq_enable_mask = I915_USER_INTERRUPT;
1410 }
1411 ring->write_tail = ring_write_tail;
1412 if (INTEL_INFO(dev)->gen >= 6)
1413 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1414 else if (INTEL_INFO(dev)->gen >= 4)
1415 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1416 else if (IS_I830(dev) || IS_845G(dev))
1417 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1418 else
1419 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1420 ring->init = init_render_ring;
1421 ring->cleanup = render_ring_cleanup;
1422
1423
1424 if (!I915_NEED_GFX_HWS(dev)) {
1425 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1426 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1427 }
1428
1429 return intel_init_ring_buffer(dev, ring);
1430 }
1431
1432 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1433 {
1434 drm_i915_private_t *dev_priv = dev->dev_private;
1435 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1436
1437 ring->name = "render ring";
1438 ring->id = RCS;
1439 ring->mmio_base = RENDER_RING_BASE;
1440
1441 if (INTEL_INFO(dev)->gen >= 6) {
1442 /* non-kms not supported on gen6+ */
1443 return -ENODEV;
1444 }
1445
1446 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1447 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1448 * the special gen5 functions. */
1449 ring->add_request = i9xx_add_request;
1450 if (INTEL_INFO(dev)->gen < 4)
1451 ring->flush = gen2_render_ring_flush;
1452 else
1453 ring->flush = gen4_render_ring_flush;
1454 ring->get_seqno = ring_get_seqno;
1455 if (IS_GEN2(dev)) {
1456 ring->irq_get = i8xx_ring_get_irq;
1457 ring->irq_put = i8xx_ring_put_irq;
1458 } else {
1459 ring->irq_get = i9xx_ring_get_irq;
1460 ring->irq_put = i9xx_ring_put_irq;
1461 }
1462 ring->irq_enable_mask = I915_USER_INTERRUPT;
1463 ring->write_tail = ring_write_tail;
1464 if (INTEL_INFO(dev)->gen >= 4)
1465 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1466 else if (IS_I830(dev) || IS_845G(dev))
1467 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1468 else
1469 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1470 ring->init = init_render_ring;
1471 ring->cleanup = render_ring_cleanup;
1472
1473 if (!I915_NEED_GFX_HWS(dev))
1474 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1475
1476 ring->dev = dev;
1477 INIT_LIST_HEAD(&ring->active_list);
1478 INIT_LIST_HEAD(&ring->request_list);
1479 INIT_LIST_HEAD(&ring->gpu_write_list);
1480
1481 ring->size = size;
1482 ring->effective_size = ring->size;
1483 if (IS_I830(ring->dev))
1484 ring->effective_size -= 128;
1485
1486 ring->virtual_start = ioremap_wc(start, size);
1487 if (ring->virtual_start == NULL) {
1488 DRM_ERROR("can not ioremap virtual address for"
1489 " ring buffer\n");
1490 return -ENOMEM;
1491 }
1492
1493 return 0;
1494 }
1495
1496 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1497 {
1498 drm_i915_private_t *dev_priv = dev->dev_private;
1499 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1500
1501 ring->name = "bsd ring";
1502 ring->id = VCS;
1503
1504 ring->write_tail = ring_write_tail;
1505 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1506 ring->mmio_base = GEN6_BSD_RING_BASE;
1507 /* gen6 bsd needs a special wa for tail updates */
1508 if (IS_GEN6(dev))
1509 ring->write_tail = gen6_bsd_ring_write_tail;
1510 ring->flush = gen6_ring_flush;
1511 ring->add_request = gen6_add_request;
1512 ring->get_seqno = gen6_ring_get_seqno;
1513 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1514 ring->irq_get = gen6_ring_get_irq;
1515 ring->irq_put = gen6_ring_put_irq;
1516 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1517 ring->sync_to = gen6_ring_sync;
1518 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1519 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1520 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1521 ring->signal_mbox[0] = GEN6_RVSYNC;
1522 ring->signal_mbox[1] = GEN6_BVSYNC;
1523 } else {
1524 ring->mmio_base = BSD_RING_BASE;
1525 ring->flush = bsd_ring_flush;
1526 ring->add_request = i9xx_add_request;
1527 ring->get_seqno = ring_get_seqno;
1528 if (IS_GEN5(dev)) {
1529 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1530 ring->irq_get = gen5_ring_get_irq;
1531 ring->irq_put = gen5_ring_put_irq;
1532 } else {
1533 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1534 ring->irq_get = i9xx_ring_get_irq;
1535 ring->irq_put = i9xx_ring_put_irq;
1536 }
1537 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1538 }
1539 ring->init = init_ring_common;
1540
1541
1542 return intel_init_ring_buffer(dev, ring);
1543 }
1544
1545 int intel_init_blt_ring_buffer(struct drm_device *dev)
1546 {
1547 drm_i915_private_t *dev_priv = dev->dev_private;
1548 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1549
1550 ring->name = "blitter ring";
1551 ring->id = BCS;
1552
1553 ring->mmio_base = BLT_RING_BASE;
1554 ring->write_tail = ring_write_tail;
1555 ring->flush = blt_ring_flush;
1556 ring->add_request = gen6_add_request;
1557 ring->get_seqno = gen6_ring_get_seqno;
1558 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1559 ring->irq_get = gen6_ring_get_irq;
1560 ring->irq_put = gen6_ring_put_irq;
1561 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1562 ring->sync_to = gen6_ring_sync;
1563 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1564 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1565 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1566 ring->signal_mbox[0] = GEN6_RBSYNC;
1567 ring->signal_mbox[1] = GEN6_VBSYNC;
1568 ring->init = init_ring_common;
1569
1570 return intel_init_ring_buffer(dev, ring);
1571 }
Linux kernel - Deliverables
This page took 0.063839 seconds and 6 git commands to generate.