2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
41 struct drm_i915_gem_object
*obj
;
42 volatile u32
*cpu_page
;
46 static inline int ring_space(struct intel_ring_buffer
*ring
)
48 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 struct pipe_control
*pc
= ring
->private;
179 u32 scratch_addr
= pc
->gtt_offset
+ 128;
183 ret
= intel_ring_begin(ring
, 6);
187 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
189 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
190 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
191 intel_ring_emit(ring
, 0); /* low dword */
192 intel_ring_emit(ring
, 0); /* high dword */
193 intel_ring_emit(ring
, MI_NOOP
);
194 intel_ring_advance(ring
);
196 ret
= intel_ring_begin(ring
, 6);
200 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
202 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, MI_NOOP
);
206 intel_ring_advance(ring
);
212 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
213 u32 invalidate_domains
, u32 flush_domains
)
216 struct pipe_control
*pc
= ring
->private;
217 u32 scratch_addr
= pc
->gtt_offset
+ 128;
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret
= intel_emit_post_sync_nonzero_flush(ring
);
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
230 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
231 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
236 flags
|= PIPE_CONTROL_CS_STALL
;
238 if (invalidate_domains
) {
239 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
240 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
244 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
246 * TLB invalidate requires a post-sync write.
248 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
251 ret
= intel_ring_begin(ring
, 4);
255 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring
, flags
);
257 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
258 intel_ring_emit(ring
, 0);
259 intel_ring_advance(ring
);
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
269 ret
= intel_ring_begin(ring
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
275 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
276 intel_ring_emit(ring
, 0);
277 intel_ring_emit(ring
, 0);
278 intel_ring_advance(ring
);
284 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
285 u32 invalidate_domains
, u32 flush_domains
)
288 struct pipe_control
*pc
= ring
->private;
289 u32 scratch_addr
= pc
->gtt_offset
+ 128;
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
300 flags
|= PIPE_CONTROL_CS_STALL
;
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
307 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
308 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
310 if (invalidate_domains
) {
311 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
312 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
313 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
314 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
315 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
316 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
318 * TLB invalidate requires a post-sync write.
320 flags
|= PIPE_CONTROL_QW_WRITE
;
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring
);
328 ret
= intel_ring_begin(ring
, 4);
332 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring
, flags
);
334 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
335 intel_ring_emit(ring
, 0);
336 intel_ring_advance(ring
);
341 static void ring_write_tail(struct intel_ring_buffer
*ring
,
344 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
345 I915_WRITE_TAIL(ring
, value
);
348 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
350 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
351 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
352 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
354 return I915_READ(acthd_reg
);
357 static int init_ring_common(struct intel_ring_buffer
*ring
)
359 struct drm_device
*dev
= ring
->dev
;
360 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
361 struct drm_i915_gem_object
*obj
= ring
->obj
;
365 if (HAS_FORCE_WAKE(dev
))
366 gen6_gt_force_wake_get(dev_priv
);
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring
, 0);
370 I915_WRITE_HEAD(ring
, 0);
371 ring
->write_tail(ring
, 0);
373 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
375 /* G45 ring initialization fails to reset head to zero */
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
381 I915_READ_HEAD(ring
),
382 I915_READ_TAIL(ring
),
383 I915_READ_START(ring
));
385 I915_WRITE_HEAD(ring
, 0);
387 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
392 I915_READ_HEAD(ring
),
393 I915_READ_TAIL(ring
),
394 I915_READ_START(ring
));
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring
, obj
->gtt_offset
);
404 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
409 I915_READ_START(ring
) == obj
->gtt_offset
&&
410 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
415 I915_READ_HEAD(ring
),
416 I915_READ_TAIL(ring
),
417 I915_READ_START(ring
));
422 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
423 i915_kernel_lost_context(ring
->dev
);
425 ring
->head
= I915_READ_HEAD(ring
);
426 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
427 ring
->space
= ring_space(ring
);
428 ring
->last_retired_head
= -1;
432 if (HAS_FORCE_WAKE(dev
))
433 gen6_gt_force_wake_put(dev_priv
);
439 init_pipe_control(struct intel_ring_buffer
*ring
)
441 struct pipe_control
*pc
;
442 struct drm_i915_gem_object
*obj
;
448 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
452 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
454 DRM_ERROR("Failed to allocate seqno page\n");
459 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
461 ret
= i915_gem_object_pin(obj
, 4096, true, false);
465 pc
->gtt_offset
= obj
->gtt_offset
;
466 pc
->cpu_page
= kmap(sg_page(obj
->pages
->sgl
));
467 if (pc
->cpu_page
== NULL
)
475 i915_gem_object_unpin(obj
);
477 drm_gem_object_unreference(&obj
->base
);
484 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
486 struct pipe_control
*pc
= ring
->private;
487 struct drm_i915_gem_object
*obj
;
494 kunmap(sg_page(obj
->pages
->sgl
));
495 i915_gem_object_unpin(obj
);
496 drm_gem_object_unreference(&obj
->base
);
499 ring
->private = NULL
;
502 static int init_render_ring(struct intel_ring_buffer
*ring
)
504 struct drm_device
*dev
= ring
->dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 int ret
= init_ring_common(ring
);
508 if (INTEL_INFO(dev
)->gen
> 3) {
509 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
511 I915_WRITE(GFX_MODE_GEN7
,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
516 if (INTEL_INFO(dev
)->gen
>= 5) {
517 ret
= init_pipe_control(ring
);
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
528 I915_WRITE(CACHE_MODE_0
,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
535 ring
->itlb_before_ctx_switch
=
536 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
539 if (INTEL_INFO(dev
)->gen
>= 6)
540 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
542 if (HAS_L3_GPU_CACHE(dev
))
543 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
548 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
553 cleanup_pipe_control(ring
);
557 update_mboxes(struct intel_ring_buffer
*ring
,
560 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
561 intel_ring_emit(ring
, mmio_offset
);
562 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
566 * gen6_add_request - Update the semaphore mailbox registers
568 * @ring - ring that is adding a request
569 * @seqno - return seqno stuck into the ring
571 * Update the mailbox registers in the *other* rings with the current seqno.
572 * This acts like a signal in the canonical semaphore.
575 gen6_add_request(struct intel_ring_buffer
*ring
)
581 ret
= intel_ring_begin(ring
, 10);
585 mbox1_reg
= ring
->signal_mbox
[0];
586 mbox2_reg
= ring
->signal_mbox
[1];
588 update_mboxes(ring
, mbox1_reg
);
589 update_mboxes(ring
, mbox2_reg
);
590 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
591 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
592 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
593 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
594 intel_ring_advance(ring
);
600 * intel_ring_sync - sync the waiter to the signaller on seqno
602 * @waiter - ring that is waiting
603 * @signaller - ring which has, or will signal
604 * @seqno - seqno which the waiter will block on
607 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
608 struct intel_ring_buffer
*signaller
,
612 u32 dw1
= MI_SEMAPHORE_MBOX
|
613 MI_SEMAPHORE_COMPARE
|
614 MI_SEMAPHORE_REGISTER
;
616 /* Throughout all of the GEM code, seqno passed implies our current
617 * seqno is >= the last seqno executed. However for hardware the
618 * comparison is strictly greater than.
622 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
623 MI_SEMAPHORE_SYNC_INVALID
);
625 ret
= intel_ring_begin(waiter
, 4);
629 intel_ring_emit(waiter
,
630 dw1
| signaller
->semaphore_register
[waiter
->id
]);
631 intel_ring_emit(waiter
, seqno
);
632 intel_ring_emit(waiter
, 0);
633 intel_ring_emit(waiter
, MI_NOOP
);
634 intel_ring_advance(waiter
);
639 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
641 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
642 PIPE_CONTROL_DEPTH_STALL); \
643 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
644 intel_ring_emit(ring__, 0); \
645 intel_ring_emit(ring__, 0); \
649 pc_render_add_request(struct intel_ring_buffer
*ring
)
651 struct pipe_control
*pc
= ring
->private;
652 u32 scratch_addr
= pc
->gtt_offset
+ 128;
655 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
656 * incoherent with writes to memory, i.e. completely fubar,
657 * so we need to use PIPE_NOTIFY instead.
659 * However, we also need to workaround the qword write
660 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
661 * memory before requesting an interrupt.
663 ret
= intel_ring_begin(ring
, 32);
667 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
668 PIPE_CONTROL_WRITE_FLUSH
|
669 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
670 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
671 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
672 intel_ring_emit(ring
, 0);
673 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
674 scratch_addr
+= 128; /* write to separate cachelines */
675 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
677 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
679 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
681 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
683 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
685 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
686 PIPE_CONTROL_WRITE_FLUSH
|
687 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
688 PIPE_CONTROL_NOTIFY
);
689 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
690 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
691 intel_ring_emit(ring
, 0);
692 intel_ring_advance(ring
);
698 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
700 /* Workaround to force correct ordering between irq and seqno writes on
701 * ivb (and maybe also on snb) by reading from a CS register (like
702 * ACTHD) before reading the status page. */
704 intel_ring_get_active_head(ring
);
705 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
709 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
711 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
715 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
717 struct pipe_control
*pc
= ring
->private;
718 return pc
->cpu_page
[0];
722 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
724 struct drm_device
*dev
= ring
->dev
;
725 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
728 if (!dev
->irq_enabled
)
731 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
732 if (ring
->irq_refcount
++ == 0) {
733 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
734 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
737 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
743 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
745 struct drm_device
*dev
= ring
->dev
;
746 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
749 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
750 if (--ring
->irq_refcount
== 0) {
751 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
752 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
755 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
759 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
761 struct drm_device
*dev
= ring
->dev
;
762 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
765 if (!dev
->irq_enabled
)
768 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
769 if (ring
->irq_refcount
++ == 0) {
770 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
771 I915_WRITE(IMR
, dev_priv
->irq_mask
);
774 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
780 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
782 struct drm_device
*dev
= ring
->dev
;
783 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
786 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
787 if (--ring
->irq_refcount
== 0) {
788 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
789 I915_WRITE(IMR
, dev_priv
->irq_mask
);
792 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
796 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
798 struct drm_device
*dev
= ring
->dev
;
799 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
802 if (!dev
->irq_enabled
)
805 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
806 if (ring
->irq_refcount
++ == 0) {
807 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
808 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
811 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
817 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
819 struct drm_device
*dev
= ring
->dev
;
820 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
823 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
824 if (--ring
->irq_refcount
== 0) {
825 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
826 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
829 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
832 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
834 struct drm_device
*dev
= ring
->dev
;
835 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
838 /* The ring status page addresses are no longer next to the rest of
839 * the ring registers as of gen7.
844 mmio
= RENDER_HWS_PGA_GEN7
;
847 mmio
= BLT_HWS_PGA_GEN7
;
850 mmio
= BSD_HWS_PGA_GEN7
;
853 } else if (IS_GEN6(ring
->dev
)) {
854 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
856 mmio
= RING_HWS_PGA(ring
->mmio_base
);
859 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
864 bsd_ring_flush(struct intel_ring_buffer
*ring
,
865 u32 invalidate_domains
,
870 ret
= intel_ring_begin(ring
, 2);
874 intel_ring_emit(ring
, MI_FLUSH
);
875 intel_ring_emit(ring
, MI_NOOP
);
876 intel_ring_advance(ring
);
881 i9xx_add_request(struct intel_ring_buffer
*ring
)
885 ret
= intel_ring_begin(ring
, 4);
889 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
890 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
891 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
892 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
893 intel_ring_advance(ring
);
899 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
901 struct drm_device
*dev
= ring
->dev
;
902 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
905 if (!dev
->irq_enabled
)
908 /* It looks like we need to prevent the gt from suspending while waiting
909 * for an notifiy irq, otherwise irqs seem to get lost on at least the
910 * blt/bsd rings on ivb. */
911 gen6_gt_force_wake_get(dev_priv
);
913 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
914 if (ring
->irq_refcount
++ == 0) {
915 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
916 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
|
917 GEN6_RENDER_L3_PARITY_ERROR
));
919 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
920 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
921 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
924 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
930 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
932 struct drm_device
*dev
= ring
->dev
;
933 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
936 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
937 if (--ring
->irq_refcount
== 0) {
938 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
939 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
941 I915_WRITE_IMR(ring
, ~0);
942 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
943 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
946 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
948 gen6_gt_force_wake_put(dev_priv
);
952 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
953 u32 offset
, u32 length
,
958 ret
= intel_ring_begin(ring
, 2);
962 intel_ring_emit(ring
,
963 MI_BATCH_BUFFER_START
|
965 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
966 intel_ring_emit(ring
, offset
);
967 intel_ring_advance(ring
);
973 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
979 ret
= intel_ring_begin(ring
, 4);
983 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
984 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
985 intel_ring_emit(ring
, offset
+ len
- 8);
986 intel_ring_emit(ring
, 0);
987 intel_ring_advance(ring
);
993 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
999 ret
= intel_ring_begin(ring
, 2);
1003 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1004 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1005 intel_ring_advance(ring
);
1010 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1012 struct drm_i915_gem_object
*obj
;
1014 obj
= ring
->status_page
.obj
;
1018 kunmap(sg_page(obj
->pages
->sgl
));
1019 i915_gem_object_unpin(obj
);
1020 drm_gem_object_unreference(&obj
->base
);
1021 ring
->status_page
.obj
= NULL
;
1024 static int init_status_page(struct intel_ring_buffer
*ring
)
1026 struct drm_device
*dev
= ring
->dev
;
1027 struct drm_i915_gem_object
*obj
;
1030 obj
= i915_gem_alloc_object(dev
, 4096);
1032 DRM_ERROR("Failed to allocate status page\n");
1037 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1039 ret
= i915_gem_object_pin(obj
, 4096, true, false);
1044 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
1045 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1046 if (ring
->status_page
.page_addr
== NULL
) {
1050 ring
->status_page
.obj
= obj
;
1051 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1053 intel_ring_setup_status_page(ring
);
1054 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1055 ring
->name
, ring
->status_page
.gfx_addr
);
1060 i915_gem_object_unpin(obj
);
1062 drm_gem_object_unreference(&obj
->base
);
1067 static int init_phys_hws_pga(struct intel_ring_buffer
*ring
)
1069 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1072 if (!dev_priv
->status_page_dmah
) {
1073 dev_priv
->status_page_dmah
=
1074 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1075 if (!dev_priv
->status_page_dmah
)
1079 addr
= dev_priv
->status_page_dmah
->busaddr
;
1080 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
1081 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
1082 I915_WRITE(HWS_PGA
, addr
);
1084 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1085 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1090 static int intel_init_ring_buffer(struct drm_device
*dev
,
1091 struct intel_ring_buffer
*ring
)
1093 struct drm_i915_gem_object
*obj
;
1094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 INIT_LIST_HEAD(&ring
->active_list
);
1099 INIT_LIST_HEAD(&ring
->request_list
);
1100 ring
->size
= 32 * PAGE_SIZE
;
1101 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1103 init_waitqueue_head(&ring
->irq_queue
);
1105 if (I915_NEED_GFX_HWS(dev
)) {
1106 ret
= init_status_page(ring
);
1110 BUG_ON(ring
->id
!= RCS
);
1111 ret
= init_phys_hws_pga(ring
);
1116 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1118 DRM_ERROR("Failed to allocate ringbuffer\n");
1125 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true, false);
1129 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1133 ring
->virtual_start
=
1134 ioremap_wc(dev_priv
->mm
.gtt
->gma_bus_addr
+ obj
->gtt_offset
,
1136 if (ring
->virtual_start
== NULL
) {
1137 DRM_ERROR("Failed to map ringbuffer.\n");
1142 ret
= ring
->init(ring
);
1146 /* Workaround an erratum on the i830 which causes a hang if
1147 * the TAIL pointer points to within the last 2 cachelines
1150 ring
->effective_size
= ring
->size
;
1151 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1152 ring
->effective_size
-= 128;
1157 iounmap(ring
->virtual_start
);
1159 i915_gem_object_unpin(obj
);
1161 drm_gem_object_unreference(&obj
->base
);
1164 cleanup_status_page(ring
);
1168 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1170 struct drm_i915_private
*dev_priv
;
1173 if (ring
->obj
== NULL
)
1176 /* Disable the ring buffer. The ring must be idle at this point */
1177 dev_priv
= ring
->dev
->dev_private
;
1178 ret
= intel_ring_idle(ring
);
1180 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1183 I915_WRITE_CTL(ring
, 0);
1185 iounmap(ring
->virtual_start
);
1187 i915_gem_object_unpin(ring
->obj
);
1188 drm_gem_object_unreference(&ring
->obj
->base
);
1192 ring
->cleanup(ring
);
1194 cleanup_status_page(ring
);
1197 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1201 ret
= i915_wait_seqno(ring
, seqno
);
1203 i915_gem_retire_requests_ring(ring
);
1208 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1210 struct drm_i915_gem_request
*request
;
1214 i915_gem_retire_requests_ring(ring
);
1216 if (ring
->last_retired_head
!= -1) {
1217 ring
->head
= ring
->last_retired_head
;
1218 ring
->last_retired_head
= -1;
1219 ring
->space
= ring_space(ring
);
1220 if (ring
->space
>= n
)
1224 list_for_each_entry(request
, &ring
->request_list
, list
) {
1227 if (request
->tail
== -1)
1230 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1232 space
+= ring
->size
;
1234 seqno
= request
->seqno
;
1238 /* Consume this request in case we need more space than
1239 * is available and so need to prevent a race between
1240 * updating last_retired_head and direct reads of
1241 * I915_RING_HEAD. It also provides a nice sanity check.
1249 ret
= intel_ring_wait_seqno(ring
, seqno
);
1253 if (WARN_ON(ring
->last_retired_head
== -1))
1256 ring
->head
= ring
->last_retired_head
;
1257 ring
->last_retired_head
= -1;
1258 ring
->space
= ring_space(ring
);
1259 if (WARN_ON(ring
->space
< n
))
1265 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1267 struct drm_device
*dev
= ring
->dev
;
1268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1272 ret
= intel_ring_wait_request(ring
, n
);
1276 trace_i915_ring_wait_begin(ring
);
1277 /* With GEM the hangcheck timer should kick us out of the loop,
1278 * leaving it early runs the risk of corrupting GEM state (due
1279 * to running on almost untested codepaths). But on resume
1280 * timers don't work yet, so prevent a complete hang in that
1281 * case by choosing an insanely large timeout. */
1282 end
= jiffies
+ 60 * HZ
;
1285 ring
->head
= I915_READ_HEAD(ring
);
1286 ring
->space
= ring_space(ring
);
1287 if (ring
->space
>= n
) {
1288 trace_i915_ring_wait_end(ring
);
1292 if (dev
->primary
->master
) {
1293 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1294 if (master_priv
->sarea_priv
)
1295 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1300 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1303 } while (!time_after(jiffies
, end
));
1304 trace_i915_ring_wait_end(ring
);
1308 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1310 uint32_t __iomem
*virt
;
1311 int rem
= ring
->size
- ring
->tail
;
1313 if (ring
->space
< rem
) {
1314 int ret
= ring_wait_for_space(ring
, rem
);
1319 virt
= ring
->virtual_start
+ ring
->tail
;
1322 iowrite32(MI_NOOP
, virt
++);
1325 ring
->space
= ring_space(ring
);
1330 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1335 /* We need to add any requests required to flush the objects and ring */
1336 if (ring
->outstanding_lazy_request
) {
1337 ret
= i915_add_request(ring
, NULL
, NULL
);
1342 /* Wait upon the last request to be completed */
1343 if (list_empty(&ring
->request_list
))
1346 seqno
= list_entry(ring
->request_list
.prev
,
1347 struct drm_i915_gem_request
,
1350 return i915_wait_seqno(ring
, seqno
);
1354 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1356 if (ring
->outstanding_lazy_request
)
1359 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_request
);
1362 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1365 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1366 int n
= 4*num_dwords
;
1369 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1373 /* Preallocate the olr before touching the ring */
1374 ret
= intel_ring_alloc_seqno(ring
);
1378 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1379 ret
= intel_wrap_ring_buffer(ring
);
1384 if (unlikely(ring
->space
< n
)) {
1385 ret
= ring_wait_for_space(ring
, n
);
1394 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1396 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1398 ring
->tail
&= ring
->size
- 1;
1399 if (dev_priv
->stop_rings
& intel_ring_flag(ring
))
1401 ring
->write_tail(ring
, ring
->tail
);
1405 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1408 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1410 /* Every tail move must follow the sequence below */
1412 /* Disable notification that the ring is IDLE. The GT
1413 * will then assume that it is busy and bring it out of rc6.
1415 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1416 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1418 /* Clear the context id. Here be magic! */
1419 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1421 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1422 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1423 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1425 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1427 /* Now that the ring is fully powered up, update the tail */
1428 I915_WRITE_TAIL(ring
, value
);
1429 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1431 /* Let the ring send IDLE messages to the GT again,
1432 * and so let it sleep to conserve power when idle.
1434 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1435 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1438 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1439 u32 invalidate
, u32 flush
)
1444 ret
= intel_ring_begin(ring
, 4);
1450 * Bspec vol 1c.5 - video engine command streamer:
1451 * "If ENABLED, all TLBs will be invalidated once the flush
1452 * operation is complete. This bit is only valid when the
1453 * Post-Sync Operation field is a value of 1h or 3h."
1455 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1456 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1457 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1458 intel_ring_emit(ring
, cmd
);
1459 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1460 intel_ring_emit(ring
, 0);
1461 intel_ring_emit(ring
, MI_NOOP
);
1462 intel_ring_advance(ring
);
1467 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1468 u32 offset
, u32 len
,
1473 ret
= intel_ring_begin(ring
, 2);
1477 intel_ring_emit(ring
,
1478 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1479 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1480 /* bit0-7 is the length on GEN6+ */
1481 intel_ring_emit(ring
, offset
);
1482 intel_ring_advance(ring
);
1488 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1489 u32 offset
, u32 len
,
1494 ret
= intel_ring_begin(ring
, 2);
1498 intel_ring_emit(ring
,
1499 MI_BATCH_BUFFER_START
|
1500 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1501 /* bit0-7 is the length on GEN6+ */
1502 intel_ring_emit(ring
, offset
);
1503 intel_ring_advance(ring
);
1508 /* Blitter support (SandyBridge+) */
1510 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1511 u32 invalidate
, u32 flush
)
1516 ret
= intel_ring_begin(ring
, 4);
1522 * Bspec vol 1c.3 - blitter engine command streamer:
1523 * "If ENABLED, all TLBs will be invalidated once the flush
1524 * operation is complete. This bit is only valid when the
1525 * Post-Sync Operation field is a value of 1h or 3h."
1527 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1528 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1529 MI_FLUSH_DW_OP_STOREDW
;
1530 intel_ring_emit(ring
, cmd
);
1531 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1532 intel_ring_emit(ring
, 0);
1533 intel_ring_emit(ring
, MI_NOOP
);
1534 intel_ring_advance(ring
);
1538 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1540 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1541 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1543 ring
->name
= "render ring";
1545 ring
->mmio_base
= RENDER_RING_BASE
;
1547 if (INTEL_INFO(dev
)->gen
>= 6) {
1548 ring
->add_request
= gen6_add_request
;
1549 ring
->flush
= gen7_render_ring_flush
;
1550 if (INTEL_INFO(dev
)->gen
== 6)
1551 ring
->flush
= gen6_render_ring_flush
;
1552 ring
->irq_get
= gen6_ring_get_irq
;
1553 ring
->irq_put
= gen6_ring_put_irq
;
1554 ring
->irq_enable_mask
= GT_USER_INTERRUPT
;
1555 ring
->get_seqno
= gen6_ring_get_seqno
;
1556 ring
->sync_to
= gen6_ring_sync
;
1557 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_INVALID
;
1558 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_RV
;
1559 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_RB
;
1560 ring
->signal_mbox
[0] = GEN6_VRSYNC
;
1561 ring
->signal_mbox
[1] = GEN6_BRSYNC
;
1562 } else if (IS_GEN5(dev
)) {
1563 ring
->add_request
= pc_render_add_request
;
1564 ring
->flush
= gen4_render_ring_flush
;
1565 ring
->get_seqno
= pc_render_get_seqno
;
1566 ring
->irq_get
= gen5_ring_get_irq
;
1567 ring
->irq_put
= gen5_ring_put_irq
;
1568 ring
->irq_enable_mask
= GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
;
1570 ring
->add_request
= i9xx_add_request
;
1571 if (INTEL_INFO(dev
)->gen
< 4)
1572 ring
->flush
= gen2_render_ring_flush
;
1574 ring
->flush
= gen4_render_ring_flush
;
1575 ring
->get_seqno
= ring_get_seqno
;
1577 ring
->irq_get
= i8xx_ring_get_irq
;
1578 ring
->irq_put
= i8xx_ring_put_irq
;
1580 ring
->irq_get
= i9xx_ring_get_irq
;
1581 ring
->irq_put
= i9xx_ring_put_irq
;
1583 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1585 ring
->write_tail
= ring_write_tail
;
1586 if (IS_HASWELL(dev
))
1587 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1588 else if (INTEL_INFO(dev
)->gen
>= 6)
1589 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1590 else if (INTEL_INFO(dev
)->gen
>= 4)
1591 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1592 else if (IS_I830(dev
) || IS_845G(dev
))
1593 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1595 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1596 ring
->init
= init_render_ring
;
1597 ring
->cleanup
= render_ring_cleanup
;
1599 return intel_init_ring_buffer(dev
, ring
);
1602 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1604 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1605 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1608 ring
->name
= "render ring";
1610 ring
->mmio_base
= RENDER_RING_BASE
;
1612 if (INTEL_INFO(dev
)->gen
>= 6) {
1613 /* non-kms not supported on gen6+ */
1617 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1618 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1619 * the special gen5 functions. */
1620 ring
->add_request
= i9xx_add_request
;
1621 if (INTEL_INFO(dev
)->gen
< 4)
1622 ring
->flush
= gen2_render_ring_flush
;
1624 ring
->flush
= gen4_render_ring_flush
;
1625 ring
->get_seqno
= ring_get_seqno
;
1627 ring
->irq_get
= i8xx_ring_get_irq
;
1628 ring
->irq_put
= i8xx_ring_put_irq
;
1630 ring
->irq_get
= i9xx_ring_get_irq
;
1631 ring
->irq_put
= i9xx_ring_put_irq
;
1633 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1634 ring
->write_tail
= ring_write_tail
;
1635 if (INTEL_INFO(dev
)->gen
>= 4)
1636 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1637 else if (IS_I830(dev
) || IS_845G(dev
))
1638 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1640 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1641 ring
->init
= init_render_ring
;
1642 ring
->cleanup
= render_ring_cleanup
;
1645 INIT_LIST_HEAD(&ring
->active_list
);
1646 INIT_LIST_HEAD(&ring
->request_list
);
1649 ring
->effective_size
= ring
->size
;
1650 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1651 ring
->effective_size
-= 128;
1653 ring
->virtual_start
= ioremap_wc(start
, size
);
1654 if (ring
->virtual_start
== NULL
) {
1655 DRM_ERROR("can not ioremap virtual address for"
1660 if (!I915_NEED_GFX_HWS(dev
)) {
1661 ret
= init_phys_hws_pga(ring
);
1669 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1671 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1672 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1674 ring
->name
= "bsd ring";
1677 ring
->write_tail
= ring_write_tail
;
1678 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1679 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1680 /* gen6 bsd needs a special wa for tail updates */
1682 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1683 ring
->flush
= gen6_ring_flush
;
1684 ring
->add_request
= gen6_add_request
;
1685 ring
->get_seqno
= gen6_ring_get_seqno
;
1686 ring
->irq_enable_mask
= GEN6_BSD_USER_INTERRUPT
;
1687 ring
->irq_get
= gen6_ring_get_irq
;
1688 ring
->irq_put
= gen6_ring_put_irq
;
1689 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1690 ring
->sync_to
= gen6_ring_sync
;
1691 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_VR
;
1692 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_INVALID
;
1693 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_VB
;
1694 ring
->signal_mbox
[0] = GEN6_RVSYNC
;
1695 ring
->signal_mbox
[1] = GEN6_BVSYNC
;
1697 ring
->mmio_base
= BSD_RING_BASE
;
1698 ring
->flush
= bsd_ring_flush
;
1699 ring
->add_request
= i9xx_add_request
;
1700 ring
->get_seqno
= ring_get_seqno
;
1702 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1703 ring
->irq_get
= gen5_ring_get_irq
;
1704 ring
->irq_put
= gen5_ring_put_irq
;
1706 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1707 ring
->irq_get
= i9xx_ring_get_irq
;
1708 ring
->irq_put
= i9xx_ring_put_irq
;
1710 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1712 ring
->init
= init_ring_common
;
1714 return intel_init_ring_buffer(dev
, ring
);
1717 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1719 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1720 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1722 ring
->name
= "blitter ring";
1725 ring
->mmio_base
= BLT_RING_BASE
;
1726 ring
->write_tail
= ring_write_tail
;
1727 ring
->flush
= blt_ring_flush
;
1728 ring
->add_request
= gen6_add_request
;
1729 ring
->get_seqno
= gen6_ring_get_seqno
;
1730 ring
->irq_enable_mask
= GEN6_BLITTER_USER_INTERRUPT
;
1731 ring
->irq_get
= gen6_ring_get_irq
;
1732 ring
->irq_put
= gen6_ring_put_irq
;
1733 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1734 ring
->sync_to
= gen6_ring_sync
;
1735 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_BR
;
1736 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_BV
;
1737 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_INVALID
;
1738 ring
->signal_mbox
[0] = GEN6_RBSYNC
;
1739 ring
->signal_mbox
[1] = GEN6_VBSYNC
;
1740 ring
->init
= init_ring_common
;
1742 return intel_init_ring_buffer(dev
, ring
);
1746 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
1750 if (!ring
->gpu_caches_dirty
)
1753 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1757 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1759 ring
->gpu_caches_dirty
= false;
1764 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
1766 uint32_t flush_domains
;
1770 if (ring
->gpu_caches_dirty
)
1771 flush_domains
= I915_GEM_GPU_DOMAINS
;
1773 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1777 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1779 ring
->gpu_caches_dirty
= false;