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Merge branch 'drm-intel-fixes' into drm-intel-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 static u32 i915_gem_get_seqno(struct drm_device *dev)
38 {
39 drm_i915_private_t *dev_priv = dev->dev_private;
40 u32 seqno;
41
42 seqno = dev_priv->next_seqno;
43
44 /* reserve 0 for non-seqno */
45 if (++dev_priv->next_seqno == 0)
46 dev_priv->next_seqno = 1;
47
48 return seqno;
49 }
50
51 static void
52 render_ring_flush(struct intel_ring_buffer *ring,
53 u32 invalidate_domains,
54 u32 flush_domains)
55 {
56 struct drm_device *dev = ring->dev;
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 cmd;
59
60 #if WATCH_EXEC
61 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
62 invalidate_domains, flush_domains);
63 #endif
64
65 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
66 invalidate_domains, flush_domains);
67
68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69 /*
70 * read/write caches:
71 *
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */
96
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98 if ((invalidate_domains|flush_domains) &
99 I915_GEM_DOMAIN_RENDER)
100 cmd &= ~MI_NO_WRITE_FLUSH;
101 if (INTEL_INFO(dev)->gen < 4) {
102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
112 #if WATCH_EXEC
113 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
114 #endif
115 if (intel_ring_begin(ring, 2) == 0) {
116 intel_ring_emit(ring, cmd);
117 intel_ring_emit(ring, MI_NOOP);
118 intel_ring_advance(ring);
119 }
120 }
121 }
122
123 static void ring_write_tail(struct intel_ring_buffer *ring,
124 u32 value)
125 {
126 drm_i915_private_t *dev_priv = ring->dev->dev_private;
127 I915_WRITE_TAIL(ring, value);
128 }
129
130 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
131 {
132 drm_i915_private_t *dev_priv = ring->dev->dev_private;
133 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
134 RING_ACTHD(ring->mmio_base) : ACTHD;
135
136 return I915_READ(acthd_reg);
137 }
138
139 static int init_ring_common(struct intel_ring_buffer *ring)
140 {
141 drm_i915_private_t *dev_priv = ring->dev->dev_private;
142 struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object);
143 u32 head;
144
145 /* Stop the ring if it's running. */
146 I915_WRITE_CTL(ring, 0);
147 I915_WRITE_HEAD(ring, 0);
148 ring->write_tail(ring, 0);
149
150 /* Initialize the ring. */
151 I915_WRITE_START(ring, obj_priv->gtt_offset);
152 head = I915_READ_HEAD(ring) & HEAD_ADDR;
153
154 /* G45 ring initialization fails to reset head to zero */
155 if (head != 0) {
156 DRM_ERROR("%s head not reset to zero "
157 "ctl %08x head %08x tail %08x start %08x\n",
158 ring->name,
159 I915_READ_CTL(ring),
160 I915_READ_HEAD(ring),
161 I915_READ_TAIL(ring),
162 I915_READ_START(ring));
163
164 I915_WRITE_HEAD(ring, 0);
165
166 DRM_ERROR("%s head forced to zero "
167 "ctl %08x head %08x tail %08x start %08x\n",
168 ring->name,
169 I915_READ_CTL(ring),
170 I915_READ_HEAD(ring),
171 I915_READ_TAIL(ring),
172 I915_READ_START(ring));
173 }
174
175 I915_WRITE_CTL(ring,
176 ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
177 | RING_REPORT_64K | RING_VALID);
178
179 /* If the head is still not zero, the ring is dead */
180 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
181 I915_READ_START(ring) != obj_priv->gtt_offset ||
182 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
183 DRM_ERROR("%s initialization failed "
184 "ctl %08x head %08x tail %08x start %08x\n",
185 ring->name,
186 I915_READ_CTL(ring),
187 I915_READ_HEAD(ring),
188 I915_READ_TAIL(ring),
189 I915_READ_START(ring));
190 return -EIO;
191 }
192
193 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
194 i915_kernel_lost_context(ring->dev);
195 else {
196 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
197 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
198 ring->space = ring->head - (ring->tail + 8);
199 if (ring->space < 0)
200 ring->space += ring->size;
201 }
202 return 0;
203 }
204
205 static int init_render_ring(struct intel_ring_buffer *ring)
206 {
207 struct drm_device *dev = ring->dev;
208 int ret = init_ring_common(ring);
209
210 if (INTEL_INFO(dev)->gen > 3) {
211 drm_i915_private_t *dev_priv = dev->dev_private;
212 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
213 if (IS_GEN6(dev))
214 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
215 I915_WRITE(MI_MODE, mode);
216 }
217
218 return ret;
219 }
220
221 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
222 do { \
223 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
224 PIPE_CONTROL_DEPTH_STALL | 2); \
225 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
226 intel_ring_emit(ring__, 0); \
227 intel_ring_emit(ring__, 0); \
228 } while (0)
229
230 /**
231 * Creates a new sequence number, emitting a write of it to the status page
232 * plus an interrupt, which will trigger i915_user_interrupt_handler.
233 *
234 * Must be called with struct_lock held.
235 *
236 * Returned sequence numbers are nonzero on success.
237 */
238 static int
239 render_ring_add_request(struct intel_ring_buffer *ring,
240 u32 *result)
241 {
242 struct drm_device *dev = ring->dev;
243 drm_i915_private_t *dev_priv = dev->dev_private;
244 u32 seqno = i915_gem_get_seqno(dev);
245 int ret;
246
247 if (IS_GEN6(dev)) {
248 ret = intel_ring_begin(ring, 6);
249 if (ret)
250 return ret;
251
252 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3);
253 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE |
254 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
255 PIPE_CONTROL_NOTIFY);
256 intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
257 intel_ring_emit(ring, seqno);
258 intel_ring_emit(ring, 0);
259 intel_ring_emit(ring, 0);
260 } else if (HAS_PIPE_CONTROL(dev)) {
261 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
262
263 /*
264 * Workaround qword write incoherence by flushing the
265 * PIPE_NOTIFY buffers out to memory before requesting
266 * an interrupt.
267 */
268 ret = intel_ring_begin(ring, 32);
269 if (ret)
270 return ret;
271
272 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
273 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
274 intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
275 intel_ring_emit(ring, seqno);
276 intel_ring_emit(ring, 0);
277 PIPE_CONTROL_FLUSH(ring, scratch_addr);
278 scratch_addr += 128; /* write to separate cachelines */
279 PIPE_CONTROL_FLUSH(ring, scratch_addr);
280 scratch_addr += 128;
281 PIPE_CONTROL_FLUSH(ring, scratch_addr);
282 scratch_addr += 128;
283 PIPE_CONTROL_FLUSH(ring, scratch_addr);
284 scratch_addr += 128;
285 PIPE_CONTROL_FLUSH(ring, scratch_addr);
286 scratch_addr += 128;
287 PIPE_CONTROL_FLUSH(ring, scratch_addr);
288 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
289 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
290 PIPE_CONTROL_NOTIFY);
291 intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
292 intel_ring_emit(ring, seqno);
293 intel_ring_emit(ring, 0);
294 } else {
295 ret = intel_ring_begin(ring, 4);
296 if (ret)
297 return ret;
298
299 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
300 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
301 intel_ring_emit(ring, seqno);
302
303 intel_ring_emit(ring, MI_USER_INTERRUPT);
304 }
305
306 intel_ring_advance(ring);
307 *result = seqno;
308 return 0;
309 }
310
311 static u32
312 render_ring_get_seqno(struct intel_ring_buffer *ring)
313 {
314 struct drm_device *dev = ring->dev;
315 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
316 if (HAS_PIPE_CONTROL(dev))
317 return ((volatile u32 *)(dev_priv->seqno_page))[0];
318 else
319 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
320 }
321
322 static void
323 render_ring_get_user_irq(struct intel_ring_buffer *ring)
324 {
325 struct drm_device *dev = ring->dev;
326 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
327 unsigned long irqflags;
328
329 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
330 if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
331 if (HAS_PCH_SPLIT(dev))
332 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
333 else
334 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
335 }
336 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
337 }
338
339 static void
340 render_ring_put_user_irq(struct intel_ring_buffer *ring)
341 {
342 struct drm_device *dev = ring->dev;
343 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
344 unsigned long irqflags;
345
346 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
347 BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
348 if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
349 if (HAS_PCH_SPLIT(dev))
350 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
351 else
352 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
353 }
354 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
355 }
356
357 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
358 {
359 drm_i915_private_t *dev_priv = ring->dev->dev_private;
360 u32 mmio = IS_GEN6(ring->dev) ?
361 RING_HWS_PGA_GEN6(ring->mmio_base) :
362 RING_HWS_PGA(ring->mmio_base);
363 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
364 POSTING_READ(mmio);
365 }
366
367 static void
368 bsd_ring_flush(struct intel_ring_buffer *ring,
369 u32 invalidate_domains,
370 u32 flush_domains)
371 {
372 if (intel_ring_begin(ring, 2) == 0) {
373 intel_ring_emit(ring, MI_FLUSH);
374 intel_ring_emit(ring, MI_NOOP);
375 intel_ring_advance(ring);
376 }
377 }
378
379 static int
380 ring_add_request(struct intel_ring_buffer *ring,
381 u32 *result)
382 {
383 u32 seqno;
384 int ret;
385
386 ret = intel_ring_begin(ring, 4);
387 if (ret)
388 return ret;
389
390 seqno = i915_gem_get_seqno(ring->dev);
391
392 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
393 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
394 intel_ring_emit(ring, seqno);
395 intel_ring_emit(ring, MI_USER_INTERRUPT);
396 intel_ring_advance(ring);
397
398 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
399 *result = seqno;
400 return 0;
401 }
402
403 static void
404 bsd_ring_get_user_irq(struct intel_ring_buffer *ring)
405 {
406 /* do nothing */
407 }
408 static void
409 bsd_ring_put_user_irq(struct intel_ring_buffer *ring)
410 {
411 /* do nothing */
412 }
413
414 static u32
415 ring_status_page_get_seqno(struct intel_ring_buffer *ring)
416 {
417 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
418 }
419
420 static int
421 ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
422 struct drm_i915_gem_execbuffer2 *exec,
423 struct drm_clip_rect *cliprects,
424 uint64_t exec_offset)
425 {
426 uint32_t exec_start;
427 int ret;
428
429 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
430
431 ret = intel_ring_begin(ring, 2);
432 if (ret)
433 return ret;
434
435 intel_ring_emit(ring,
436 MI_BATCH_BUFFER_START |
437 (2 << 6) |
438 MI_BATCH_NON_SECURE_I965);
439 intel_ring_emit(ring, exec_start);
440 intel_ring_advance(ring);
441
442 return 0;
443 }
444
445 static int
446 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
447 struct drm_i915_gem_execbuffer2 *exec,
448 struct drm_clip_rect *cliprects,
449 uint64_t exec_offset)
450 {
451 struct drm_device *dev = ring->dev;
452 drm_i915_private_t *dev_priv = dev->dev_private;
453 int nbox = exec->num_cliprects;
454 uint32_t exec_start, exec_len;
455 int i, count, ret;
456
457 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
458 exec_len = (uint32_t) exec->batch_len;
459
460 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
461
462 count = nbox ? nbox : 1;
463 for (i = 0; i < count; i++) {
464 if (i < nbox) {
465 ret = i915_emit_box(dev, cliprects, i,
466 exec->DR1, exec->DR4);
467 if (ret)
468 return ret;
469 }
470
471 if (IS_I830(dev) || IS_845G(dev)) {
472 ret = intel_ring_begin(ring, 4);
473 if (ret)
474 return ret;
475
476 intel_ring_emit(ring, MI_BATCH_BUFFER);
477 intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE);
478 intel_ring_emit(ring, exec_start + exec_len - 4);
479 intel_ring_emit(ring, 0);
480 } else {
481 ret = intel_ring_begin(ring, 2);
482 if (ret)
483 return ret;
484
485 if (INTEL_INFO(dev)->gen >= 4) {
486 intel_ring_emit(ring,
487 MI_BATCH_BUFFER_START | (2 << 6)
488 | MI_BATCH_NON_SECURE_I965);
489 intel_ring_emit(ring, exec_start);
490 } else {
491 intel_ring_emit(ring, MI_BATCH_BUFFER_START
492 | (2 << 6));
493 intel_ring_emit(ring, exec_start |
494 MI_BATCH_NON_SECURE);
495 }
496 }
497 intel_ring_advance(ring);
498 }
499
500 if (IS_G4X(dev) || IS_GEN5(dev)) {
501 if (intel_ring_begin(ring, 2) == 0) {
502 intel_ring_emit(ring, MI_FLUSH |
503 MI_NO_WRITE_FLUSH |
504 MI_INVALIDATE_ISP );
505 intel_ring_emit(ring, MI_NOOP);
506 intel_ring_advance(ring);
507 }
508 }
509 /* XXX breadcrumb */
510
511 return 0;
512 }
513
514 static void cleanup_status_page(struct intel_ring_buffer *ring)
515 {
516 drm_i915_private_t *dev_priv = ring->dev->dev_private;
517 struct drm_gem_object *obj;
518 struct drm_i915_gem_object *obj_priv;
519
520 obj = ring->status_page.obj;
521 if (obj == NULL)
522 return;
523 obj_priv = to_intel_bo(obj);
524
525 kunmap(obj_priv->pages[0]);
526 i915_gem_object_unpin(obj);
527 drm_gem_object_unreference(obj);
528 ring->status_page.obj = NULL;
529
530 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
531 }
532
533 static int init_status_page(struct intel_ring_buffer *ring)
534 {
535 struct drm_device *dev = ring->dev;
536 drm_i915_private_t *dev_priv = dev->dev_private;
537 struct drm_gem_object *obj;
538 struct drm_i915_gem_object *obj_priv;
539 int ret;
540
541 obj = i915_gem_alloc_object(dev, 4096);
542 if (obj == NULL) {
543 DRM_ERROR("Failed to allocate status page\n");
544 ret = -ENOMEM;
545 goto err;
546 }
547 obj_priv = to_intel_bo(obj);
548 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
549
550 ret = i915_gem_object_pin(obj, 4096, true, false);
551 if (ret != 0) {
552 goto err_unref;
553 }
554
555 ring->status_page.gfx_addr = obj_priv->gtt_offset;
556 ring->status_page.page_addr = kmap(obj_priv->pages[0]);
557 if (ring->status_page.page_addr == NULL) {
558 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
559 goto err_unpin;
560 }
561 ring->status_page.obj = obj;
562 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
563
564 intel_ring_setup_status_page(ring);
565 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
566 ring->name, ring->status_page.gfx_addr);
567
568 return 0;
569
570 err_unpin:
571 i915_gem_object_unpin(obj);
572 err_unref:
573 drm_gem_object_unreference(obj);
574 err:
575 return ret;
576 }
577
578 int intel_init_ring_buffer(struct drm_device *dev,
579 struct intel_ring_buffer *ring)
580 {
581 struct drm_i915_gem_object *obj_priv;
582 struct drm_gem_object *obj;
583 int ret;
584
585 ring->dev = dev;
586 INIT_LIST_HEAD(&ring->active_list);
587 INIT_LIST_HEAD(&ring->request_list);
588 INIT_LIST_HEAD(&ring->gpu_write_list);
589
590 if (I915_NEED_GFX_HWS(dev)) {
591 ret = init_status_page(ring);
592 if (ret)
593 return ret;
594 }
595
596 obj = i915_gem_alloc_object(dev, ring->size);
597 if (obj == NULL) {
598 DRM_ERROR("Failed to allocate ringbuffer\n");
599 ret = -ENOMEM;
600 goto err_hws;
601 }
602
603 ring->gem_object = obj;
604
605 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
606 if (ret)
607 goto err_unref;
608
609 obj_priv = to_intel_bo(obj);
610 ring->map.size = ring->size;
611 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
612 ring->map.type = 0;
613 ring->map.flags = 0;
614 ring->map.mtrr = 0;
615
616 drm_core_ioremap_wc(&ring->map, dev);
617 if (ring->map.handle == NULL) {
618 DRM_ERROR("Failed to map ringbuffer.\n");
619 ret = -EINVAL;
620 goto err_unpin;
621 }
622
623 ring->virtual_start = ring->map.handle;
624 ret = ring->init(ring);
625 if (ret)
626 goto err_unmap;
627
628 return 0;
629
630 err_unmap:
631 drm_core_ioremapfree(&ring->map, dev);
632 err_unpin:
633 i915_gem_object_unpin(obj);
634 err_unref:
635 drm_gem_object_unreference(obj);
636 ring->gem_object = NULL;
637 err_hws:
638 cleanup_status_page(ring);
639 return ret;
640 }
641
642 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
643 {
644 struct drm_i915_private *dev_priv;
645 int ret;
646
647 if (ring->gem_object == NULL)
648 return;
649
650 /* Disable the ring buffer. The ring must be idle at this point */
651 dev_priv = ring->dev->dev_private;
652 ret = intel_wait_ring_buffer(ring, ring->size - 8);
653 I915_WRITE_CTL(ring, 0);
654
655 drm_core_ioremapfree(&ring->map, ring->dev);
656
657 i915_gem_object_unpin(ring->gem_object);
658 drm_gem_object_unreference(ring->gem_object);
659 ring->gem_object = NULL;
660
661 if (ring->cleanup)
662 ring->cleanup(ring);
663
664 cleanup_status_page(ring);
665 }
666
667 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
668 {
669 unsigned int *virt;
670 int rem;
671 rem = ring->size - ring->tail;
672
673 if (ring->space < rem) {
674 int ret = intel_wait_ring_buffer(ring, rem);
675 if (ret)
676 return ret;
677 }
678
679 virt = (unsigned int *)(ring->virtual_start + ring->tail);
680 rem /= 8;
681 while (rem--) {
682 *virt++ = MI_NOOP;
683 *virt++ = MI_NOOP;
684 }
685
686 ring->tail = 0;
687 ring->space = ring->head - 8;
688
689 return 0;
690 }
691
692 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
693 {
694 struct drm_device *dev = ring->dev;
695 drm_i915_private_t *dev_priv = dev->dev_private;
696 unsigned long end;
697 u32 head;
698
699 head = intel_read_status_page(ring, 4);
700 if (head) {
701 ring->head = head & HEAD_ADDR;
702 ring->space = ring->head - (ring->tail + 8);
703 if (ring->space < 0)
704 ring->space += ring->size;
705 if (ring->space >= n)
706 return 0;
707 }
708
709 trace_i915_ring_wait_begin (dev);
710 end = jiffies + 3 * HZ;
711 do {
712 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
713 ring->space = ring->head - (ring->tail + 8);
714 if (ring->space < 0)
715 ring->space += ring->size;
716 if (ring->space >= n) {
717 trace_i915_ring_wait_end(dev);
718 return 0;
719 }
720
721 if (dev->primary->master) {
722 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
723 if (master_priv->sarea_priv)
724 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
725 }
726
727 msleep(1);
728 if (atomic_read(&dev_priv->mm.wedged))
729 return -EAGAIN;
730 } while (!time_after(jiffies, end));
731 trace_i915_ring_wait_end (dev);
732 return -EBUSY;
733 }
734
735 int intel_ring_begin(struct intel_ring_buffer *ring,
736 int num_dwords)
737 {
738 int n = 4*num_dwords;
739 int ret;
740
741 if (unlikely(ring->tail + n > ring->size)) {
742 ret = intel_wrap_ring_buffer(ring);
743 if (unlikely(ret))
744 return ret;
745 }
746
747 if (unlikely(ring->space < n)) {
748 ret = intel_wait_ring_buffer(ring, n);
749 if (unlikely(ret))
750 return ret;
751 }
752
753 ring->space -= n;
754 return 0;
755 }
756
757 void intel_ring_advance(struct intel_ring_buffer *ring)
758 {
759 ring->tail &= ring->size - 1;
760 ring->write_tail(ring, ring->tail);
761 }
762
763 static const struct intel_ring_buffer render_ring = {
764 .name = "render ring",
765 .id = RING_RENDER,
766 .mmio_base = RENDER_RING_BASE,
767 .size = 32 * PAGE_SIZE,
768 .init = init_render_ring,
769 .write_tail = ring_write_tail,
770 .flush = render_ring_flush,
771 .add_request = render_ring_add_request,
772 .get_seqno = render_ring_get_seqno,
773 .user_irq_get = render_ring_get_user_irq,
774 .user_irq_put = render_ring_put_user_irq,
775 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
776 };
777
778 /* ring buffer for bit-stream decoder */
779
780 static const struct intel_ring_buffer bsd_ring = {
781 .name = "bsd ring",
782 .id = RING_BSD,
783 .mmio_base = BSD_RING_BASE,
784 .size = 32 * PAGE_SIZE,
785 .init = init_ring_common,
786 .write_tail = ring_write_tail,
787 .flush = bsd_ring_flush,
788 .add_request = ring_add_request,
789 .get_seqno = ring_status_page_get_seqno,
790 .user_irq_get = bsd_ring_get_user_irq,
791 .user_irq_put = bsd_ring_put_user_irq,
792 .dispatch_execbuffer = ring_dispatch_execbuffer,
793 };
794
795
796 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
797 u32 value)
798 {
799 drm_i915_private_t *dev_priv = ring->dev->dev_private;
800
801 /* Every tail move must follow the sequence below */
802 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
803 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
804 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
805 I915_WRITE(GEN6_BSD_RNCID, 0x0);
806
807 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
808 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
809 50))
810 DRM_ERROR("timed out waiting for IDLE Indicator\n");
811
812 I915_WRITE_TAIL(ring, value);
813 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
814 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
815 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
816 }
817
818 static void gen6_ring_flush(struct intel_ring_buffer *ring,
819 u32 invalidate_domains,
820 u32 flush_domains)
821 {
822 if (intel_ring_begin(ring, 4) == 0) {
823 intel_ring_emit(ring, MI_FLUSH_DW);
824 intel_ring_emit(ring, 0);
825 intel_ring_emit(ring, 0);
826 intel_ring_emit(ring, 0);
827 intel_ring_advance(ring);
828 }
829 }
830
831 static int
832 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
833 struct drm_i915_gem_execbuffer2 *exec,
834 struct drm_clip_rect *cliprects,
835 uint64_t exec_offset)
836 {
837 uint32_t exec_start;
838 int ret;
839
840 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
841
842 ret = intel_ring_begin(ring, 2);
843 if (ret)
844 return ret;
845
846 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
847 /* bit0-7 is the length on GEN6+ */
848 intel_ring_emit(ring, exec_start);
849 intel_ring_advance(ring);
850
851 return 0;
852 }
853
854 /* ring buffer for Video Codec for Gen6+ */
855 static const struct intel_ring_buffer gen6_bsd_ring = {
856 .name = "gen6 bsd ring",
857 .id = RING_BSD,
858 .mmio_base = GEN6_BSD_RING_BASE,
859 .size = 32 * PAGE_SIZE,
860 .init = init_ring_common,
861 .write_tail = gen6_bsd_ring_write_tail,
862 .flush = gen6_ring_flush,
863 .add_request = ring_add_request,
864 .get_seqno = ring_status_page_get_seqno,
865 .user_irq_get = bsd_ring_get_user_irq,
866 .user_irq_put = bsd_ring_put_user_irq,
867 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
868 };
869
870 /* Blitter support (SandyBridge+) */
871
872 static void
873 blt_ring_get_user_irq(struct intel_ring_buffer *ring)
874 {
875 /* do nothing */
876 }
877 static void
878 blt_ring_put_user_irq(struct intel_ring_buffer *ring)
879 {
880 /* do nothing */
881 }
882
883
884 /* Workaround for some stepping of SNB,
885 * each time when BLT engine ring tail moved,
886 * the first command in the ring to be parsed
887 * should be MI_BATCH_BUFFER_START
888 */
889 #define NEED_BLT_WORKAROUND(dev) \
890 (IS_GEN6(dev) && (dev->pdev->revision < 8))
891
892 static inline struct drm_i915_gem_object *
893 to_blt_workaround(struct intel_ring_buffer *ring)
894 {
895 return ring->private;
896 }
897
898 static int blt_ring_init(struct intel_ring_buffer *ring)
899 {
900 if (NEED_BLT_WORKAROUND(ring->dev)) {
901 struct drm_i915_gem_object *obj;
902 u32 __iomem *ptr;
903 int ret;
904
905 obj = to_intel_bo(i915_gem_alloc_object(ring->dev, 4096));
906 if (obj == NULL)
907 return -ENOMEM;
908
909 ret = i915_gem_object_pin(&obj->base, 4096, true, false);
910 if (ret) {
911 drm_gem_object_unreference(&obj->base);
912 return ret;
913 }
914
915 ptr = kmap(obj->pages[0]);
916 iowrite32(MI_BATCH_BUFFER_END, ptr);
917 iowrite32(MI_NOOP, ptr+1);
918 kunmap(obj->pages[0]);
919
920 ret = i915_gem_object_set_to_gtt_domain(&obj->base, false);
921 if (ret) {
922 i915_gem_object_unpin(&obj->base);
923 drm_gem_object_unreference(&obj->base);
924 return ret;
925 }
926
927 ring->private = obj;
928 }
929
930 return init_ring_common(ring);
931 }
932
933 static int blt_ring_begin(struct intel_ring_buffer *ring,
934 int num_dwords)
935 {
936 if (ring->private) {
937 int ret = intel_ring_begin(ring, num_dwords+2);
938 if (ret)
939 return ret;
940
941 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
942 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
943
944 return 0;
945 } else
946 return intel_ring_begin(ring, 4);
947 }
948
949 static void blt_ring_flush(struct intel_ring_buffer *ring,
950 u32 invalidate_domains,
951 u32 flush_domains)
952 {
953 if (blt_ring_begin(ring, 4) == 0) {
954 intel_ring_emit(ring, MI_FLUSH_DW);
955 intel_ring_emit(ring, 0);
956 intel_ring_emit(ring, 0);
957 intel_ring_emit(ring, 0);
958 intel_ring_advance(ring);
959 }
960 }
961
962 static int
963 blt_ring_add_request(struct intel_ring_buffer *ring,
964 u32 *result)
965 {
966 u32 seqno;
967 int ret;
968
969 ret = blt_ring_begin(ring, 4);
970 if (ret)
971 return ret;
972
973 seqno = i915_gem_get_seqno(ring->dev);
974
975 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
976 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
977 intel_ring_emit(ring, seqno);
978 intel_ring_emit(ring, MI_USER_INTERRUPT);
979 intel_ring_advance(ring);
980
981 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
982 *result = seqno;
983 return 0;
984 }
985
986 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
987 {
988 if (!ring->private)
989 return;
990
991 i915_gem_object_unpin(ring->private);
992 drm_gem_object_unreference(ring->private);
993 ring->private = NULL;
994 }
995
996 static const struct intel_ring_buffer gen6_blt_ring = {
997 .name = "blt ring",
998 .id = RING_BLT,
999 .mmio_base = BLT_RING_BASE,
1000 .size = 32 * PAGE_SIZE,
1001 .init = blt_ring_init,
1002 .write_tail = ring_write_tail,
1003 .flush = blt_ring_flush,
1004 .add_request = blt_ring_add_request,
1005 .get_seqno = ring_status_page_get_seqno,
1006 .user_irq_get = blt_ring_get_user_irq,
1007 .user_irq_put = blt_ring_put_user_irq,
1008 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
1009 .cleanup = blt_ring_cleanup,
1010 };
1011
1012 int intel_init_render_ring_buffer(struct drm_device *dev)
1013 {
1014 drm_i915_private_t *dev_priv = dev->dev_private;
1015
1016 dev_priv->render_ring = render_ring;
1017
1018 if (!I915_NEED_GFX_HWS(dev)) {
1019 dev_priv->render_ring.status_page.page_addr
1020 = dev_priv->status_page_dmah->vaddr;
1021 memset(dev_priv->render_ring.status_page.page_addr,
1022 0, PAGE_SIZE);
1023 }
1024
1025 return intel_init_ring_buffer(dev, &dev_priv->render_ring);
1026 }
1027
1028 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1029 {
1030 drm_i915_private_t *dev_priv = dev->dev_private;
1031
1032 if (IS_GEN6(dev))
1033 dev_priv->bsd_ring = gen6_bsd_ring;
1034 else
1035 dev_priv->bsd_ring = bsd_ring;
1036
1037 return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
1038 }
1039
1040 int intel_init_blt_ring_buffer(struct drm_device *dev)
1041 {
1042 drm_i915_private_t *dev_priv = dev->dev_private;
1043
1044 dev_priv->blt_ring = gen6_blt_ring;
1045
1046 return intel_init_ring_buffer(dev, &dev_priv->blt_ring);
1047 }
Linux kernel - Deliverables
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