2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object
*obj
;
43 volatile u32
*cpu_page
;
47 static inline int ring_space(struct intel_ring_buffer
*ring
)
49 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ 8);
56 render_ring_flush(struct intel_ring_buffer
*ring
,
57 u32 invalidate_domains
,
60 struct drm_device
*dev
= ring
->dev
;
67 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
69 * also flushed at 2d versus 3d pipeline switches.
73 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74 * MI_READ_FLUSH is set, and is always flushed on 965.
76 * I915_GEM_DOMAIN_COMMAND may not exist?
78 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79 * invalidated when MI_EXE_FLUSH is set.
81 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82 * invalidated with every MI_FLUSH.
86 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89 * are flushed at any MI_FLUSH.
92 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
93 if ((invalidate_domains
|flush_domains
) &
94 I915_GEM_DOMAIN_RENDER
)
95 cmd
&= ~MI_NO_WRITE_FLUSH
;
96 if (INTEL_INFO(dev
)->gen
< 4) {
98 * On the 965, the sampler cache always gets flushed
99 * and this bit is reserved.
101 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
102 cmd
|= MI_READ_FLUSH
;
104 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
107 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
108 (IS_G4X(dev
) || IS_GEN5(dev
)))
109 cmd
|= MI_INVALIDATE_ISP
;
111 ret
= intel_ring_begin(ring
, 2);
115 intel_ring_emit(ring
, cmd
);
116 intel_ring_emit(ring
, MI_NOOP
);
117 intel_ring_advance(ring
);
123 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124 * implementing two workarounds on gen6. From section 1.4.7.1
125 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
127 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128 * produced by non-pipelined state commands), software needs to first
129 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
132 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
135 * And the workaround for these two requires this workaround first:
137 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138 * BEFORE the pipe-control with a post-sync op and no write-cache
141 * And this last workaround is tricky because of the requirements on
142 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
145 * "1 of the following must also be set:
146 * - Render Target Cache Flush Enable ([12] of DW1)
147 * - Depth Cache Flush Enable ([0] of DW1)
148 * - Stall at Pixel Scoreboard ([1] of DW1)
149 * - Depth Stall ([13] of DW1)
150 * - Post-Sync Operation ([13] of DW1)
151 * - Notify Enable ([8] of DW1)"
153 * The cache flushes require the workaround flush that triggered this
154 * one, so we can't use it. Depth stall would trigger the same.
155 * Post-sync nonzero is what triggered this second workaround, so we
156 * can't use that one either. Notify enable is IRQs, which aren't
157 * really our business. That leaves only stall at scoreboard.
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
162 struct pipe_control
*pc
= ring
->private;
163 u32 scratch_addr
= pc
->gtt_offset
+ 128;
167 ret
= intel_ring_begin(ring
, 6);
171 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
172 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
173 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
174 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
175 intel_ring_emit(ring
, 0); /* low dword */
176 intel_ring_emit(ring
, 0); /* high dword */
177 intel_ring_emit(ring
, MI_NOOP
);
178 intel_ring_advance(ring
);
180 ret
= intel_ring_begin(ring
, 6);
184 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
185 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
186 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
187 intel_ring_emit(ring
, 0);
188 intel_ring_emit(ring
, 0);
189 intel_ring_emit(ring
, MI_NOOP
);
190 intel_ring_advance(ring
);
196 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
197 u32 invalidate_domains
, u32 flush_domains
)
200 struct pipe_control
*pc
= ring
->private;
201 u32 scratch_addr
= pc
->gtt_offset
+ 128;
204 /* Force SNB workarounds for PIPE_CONTROL flushes */
205 intel_emit_post_sync_nonzero_flush(ring
);
207 /* Just flush everything. Experiments have shown that reducing the
208 * number of bits based on the write domains has little performance
211 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
212 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
213 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
214 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
215 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
216 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
217 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
219 ret
= intel_ring_begin(ring
, 6);
223 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
224 intel_ring_emit(ring
, flags
);
225 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
226 intel_ring_emit(ring
, 0); /* lower dword */
227 intel_ring_emit(ring
, 0); /* uppwer dword */
228 intel_ring_emit(ring
, MI_NOOP
);
229 intel_ring_advance(ring
);
234 static void ring_write_tail(struct intel_ring_buffer
*ring
,
237 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
238 I915_WRITE_TAIL(ring
, value
);
241 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
243 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
244 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
245 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
247 return I915_READ(acthd_reg
);
250 static int init_ring_common(struct intel_ring_buffer
*ring
)
252 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
253 struct drm_i915_gem_object
*obj
= ring
->obj
;
256 /* Stop the ring if it's running. */
257 I915_WRITE_CTL(ring
, 0);
258 I915_WRITE_HEAD(ring
, 0);
259 ring
->write_tail(ring
, 0);
261 /* Initialize the ring. */
262 I915_WRITE_START(ring
, obj
->gtt_offset
);
263 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
265 /* G45 ring initialization fails to reset head to zero */
267 DRM_DEBUG_KMS("%s head not reset to zero "
268 "ctl %08x head %08x tail %08x start %08x\n",
271 I915_READ_HEAD(ring
),
272 I915_READ_TAIL(ring
),
273 I915_READ_START(ring
));
275 I915_WRITE_HEAD(ring
, 0);
277 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
278 DRM_ERROR("failed to set %s head to zero "
279 "ctl %08x head %08x tail %08x start %08x\n",
282 I915_READ_HEAD(ring
),
283 I915_READ_TAIL(ring
),
284 I915_READ_START(ring
));
289 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
292 /* If the head is still not zero, the ring is dead */
293 if ((I915_READ_CTL(ring
) & RING_VALID
) == 0 ||
294 I915_READ_START(ring
) != obj
->gtt_offset
||
295 (I915_READ_HEAD(ring
) & HEAD_ADDR
) != 0) {
296 DRM_ERROR("%s initialization failed "
297 "ctl %08x head %08x tail %08x start %08x\n",
300 I915_READ_HEAD(ring
),
301 I915_READ_TAIL(ring
),
302 I915_READ_START(ring
));
306 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
307 i915_kernel_lost_context(ring
->dev
);
309 ring
->head
= I915_READ_HEAD(ring
);
310 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
311 ring
->space
= ring_space(ring
);
318 init_pipe_control(struct intel_ring_buffer
*ring
)
320 struct pipe_control
*pc
;
321 struct drm_i915_gem_object
*obj
;
327 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
331 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
333 DRM_ERROR("Failed to allocate seqno page\n");
338 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
340 ret
= i915_gem_object_pin(obj
, 4096, true);
344 pc
->gtt_offset
= obj
->gtt_offset
;
345 pc
->cpu_page
= kmap(obj
->pages
[0]);
346 if (pc
->cpu_page
== NULL
)
354 i915_gem_object_unpin(obj
);
356 drm_gem_object_unreference(&obj
->base
);
363 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
365 struct pipe_control
*pc
= ring
->private;
366 struct drm_i915_gem_object
*obj
;
372 kunmap(obj
->pages
[0]);
373 i915_gem_object_unpin(obj
);
374 drm_gem_object_unreference(&obj
->base
);
377 ring
->private = NULL
;
380 static int init_render_ring(struct intel_ring_buffer
*ring
)
382 struct drm_device
*dev
= ring
->dev
;
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 int ret
= init_ring_common(ring
);
386 if (INTEL_INFO(dev
)->gen
> 3) {
387 int mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
388 I915_WRITE(MI_MODE
, mode
);
390 I915_WRITE(GFX_MODE_GEN7
,
391 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
392 GFX_MODE_ENABLE(GFX_REPLAY_MODE
));
395 if (INTEL_INFO(dev
)->gen
>= 5) {
396 ret
= init_pipe_control(ring
);
401 if (INTEL_INFO(dev
)->gen
>= 6) {
403 INSTPM_FORCE_ORDERING
<< 16 | INSTPM_FORCE_ORDERING
);
409 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
414 cleanup_pipe_control(ring
);
418 update_mboxes(struct intel_ring_buffer
*ring
,
422 intel_ring_emit(ring
, MI_SEMAPHORE_MBOX
|
423 MI_SEMAPHORE_GLOBAL_GTT
|
424 MI_SEMAPHORE_REGISTER
|
425 MI_SEMAPHORE_UPDATE
);
426 intel_ring_emit(ring
, seqno
);
427 intel_ring_emit(ring
, mmio_offset
);
431 * gen6_add_request - Update the semaphore mailbox registers
433 * @ring - ring that is adding a request
434 * @seqno - return seqno stuck into the ring
436 * Update the mailbox registers in the *other* rings with the current seqno.
437 * This acts like a signal in the canonical semaphore.
440 gen6_add_request(struct intel_ring_buffer
*ring
,
447 ret
= intel_ring_begin(ring
, 10);
451 mbox1_reg
= ring
->signal_mbox
[0];
452 mbox2_reg
= ring
->signal_mbox
[1];
454 *seqno
= i915_gem_next_request_seqno(ring
);
456 update_mboxes(ring
, *seqno
, mbox1_reg
);
457 update_mboxes(ring
, *seqno
, mbox2_reg
);
458 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
459 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
460 intel_ring_emit(ring
, *seqno
);
461 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
462 intel_ring_advance(ring
);
468 * intel_ring_sync - sync the waiter to the signaller on seqno
470 * @waiter - ring that is waiting
471 * @signaller - ring which has, or will signal
472 * @seqno - seqno which the waiter will block on
475 intel_ring_sync(struct intel_ring_buffer
*waiter
,
476 struct intel_ring_buffer
*signaller
,
481 u32 dw1
= MI_SEMAPHORE_MBOX
|
482 MI_SEMAPHORE_COMPARE
|
483 MI_SEMAPHORE_REGISTER
;
485 ret
= intel_ring_begin(waiter
, 4);
489 intel_ring_emit(waiter
, dw1
| signaller
->semaphore_register
[ring
]);
490 intel_ring_emit(waiter
, seqno
);
491 intel_ring_emit(waiter
, 0);
492 intel_ring_emit(waiter
, MI_NOOP
);
493 intel_ring_advance(waiter
);
498 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
500 render_ring_sync_to(struct intel_ring_buffer
*waiter
,
501 struct intel_ring_buffer
*signaller
,
504 WARN_ON(signaller
->semaphore_register
[RCS
] == MI_SEMAPHORE_SYNC_INVALID
);
505 return intel_ring_sync(waiter
,
511 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
513 gen6_bsd_ring_sync_to(struct intel_ring_buffer
*waiter
,
514 struct intel_ring_buffer
*signaller
,
517 WARN_ON(signaller
->semaphore_register
[VCS
] == MI_SEMAPHORE_SYNC_INVALID
);
518 return intel_ring_sync(waiter
,
524 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
526 gen6_blt_ring_sync_to(struct intel_ring_buffer
*waiter
,
527 struct intel_ring_buffer
*signaller
,
530 WARN_ON(signaller
->semaphore_register
[BCS
] == MI_SEMAPHORE_SYNC_INVALID
);
531 return intel_ring_sync(waiter
,
539 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
541 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
542 PIPE_CONTROL_DEPTH_STALL); \
543 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
544 intel_ring_emit(ring__, 0); \
545 intel_ring_emit(ring__, 0); \
549 pc_render_add_request(struct intel_ring_buffer
*ring
,
552 u32 seqno
= i915_gem_next_request_seqno(ring
);
553 struct pipe_control
*pc
= ring
->private;
554 u32 scratch_addr
= pc
->gtt_offset
+ 128;
557 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
558 * incoherent with writes to memory, i.e. completely fubar,
559 * so we need to use PIPE_NOTIFY instead.
561 * However, we also need to workaround the qword write
562 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
563 * memory before requesting an interrupt.
565 ret
= intel_ring_begin(ring
, 32);
569 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
570 PIPE_CONTROL_WRITE_FLUSH
|
571 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
572 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
573 intel_ring_emit(ring
, seqno
);
574 intel_ring_emit(ring
, 0);
575 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
576 scratch_addr
+= 128; /* write to separate cachelines */
577 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
579 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
581 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
583 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
585 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
587 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
588 PIPE_CONTROL_WRITE_FLUSH
|
589 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
590 PIPE_CONTROL_NOTIFY
);
591 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
592 intel_ring_emit(ring
, seqno
);
593 intel_ring_emit(ring
, 0);
594 intel_ring_advance(ring
);
601 render_ring_add_request(struct intel_ring_buffer
*ring
,
604 u32 seqno
= i915_gem_next_request_seqno(ring
);
607 ret
= intel_ring_begin(ring
, 4);
611 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
612 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
613 intel_ring_emit(ring
, seqno
);
614 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
615 intel_ring_advance(ring
);
622 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
)
624 struct drm_device
*dev
= ring
->dev
;
626 /* Workaround to force correct ordering between irq and seqno writes on
627 * ivb (and maybe also on snb) by reading from a CS register (like
628 * ACTHD) before reading the status page. */
629 if (IS_GEN6(dev
) || IS_GEN7(dev
))
630 intel_ring_get_active_head(ring
);
631 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
635 ring_get_seqno(struct intel_ring_buffer
*ring
)
637 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
641 pc_render_get_seqno(struct intel_ring_buffer
*ring
)
643 struct pipe_control
*pc
= ring
->private;
644 return pc
->cpu_page
[0];
648 ironlake_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
650 dev_priv
->gt_irq_mask
&= ~mask
;
651 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
656 ironlake_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
658 dev_priv
->gt_irq_mask
|= mask
;
659 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
664 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
666 dev_priv
->irq_mask
&= ~mask
;
667 I915_WRITE(IMR
, dev_priv
->irq_mask
);
672 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
674 dev_priv
->irq_mask
|= mask
;
675 I915_WRITE(IMR
, dev_priv
->irq_mask
);
680 render_ring_get_irq(struct intel_ring_buffer
*ring
)
682 struct drm_device
*dev
= ring
->dev
;
683 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
685 if (!dev
->irq_enabled
)
688 spin_lock(&ring
->irq_lock
);
689 if (ring
->irq_refcount
++ == 0) {
690 if (HAS_PCH_SPLIT(dev
))
691 ironlake_enable_irq(dev_priv
,
692 GT_PIPE_NOTIFY
| GT_USER_INTERRUPT
);
694 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
696 spin_unlock(&ring
->irq_lock
);
702 render_ring_put_irq(struct intel_ring_buffer
*ring
)
704 struct drm_device
*dev
= ring
->dev
;
705 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
707 spin_lock(&ring
->irq_lock
);
708 if (--ring
->irq_refcount
== 0) {
709 if (HAS_PCH_SPLIT(dev
))
710 ironlake_disable_irq(dev_priv
,
714 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
716 spin_unlock(&ring
->irq_lock
);
719 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
721 struct drm_device
*dev
= ring
->dev
;
722 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
725 /* The ring status page addresses are no longer next to the rest of
726 * the ring registers as of gen7.
731 mmio
= RENDER_HWS_PGA_GEN7
;
734 mmio
= BLT_HWS_PGA_GEN7
;
737 mmio
= BSD_HWS_PGA_GEN7
;
740 } else if (IS_GEN6(ring
->dev
)) {
741 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
743 mmio
= RING_HWS_PGA(ring
->mmio_base
);
746 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
751 bsd_ring_flush(struct intel_ring_buffer
*ring
,
752 u32 invalidate_domains
,
757 ret
= intel_ring_begin(ring
, 2);
761 intel_ring_emit(ring
, MI_FLUSH
);
762 intel_ring_emit(ring
, MI_NOOP
);
763 intel_ring_advance(ring
);
768 ring_add_request(struct intel_ring_buffer
*ring
,
774 ret
= intel_ring_begin(ring
, 4);
778 seqno
= i915_gem_next_request_seqno(ring
);
780 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
781 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
782 intel_ring_emit(ring
, seqno
);
783 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
784 intel_ring_advance(ring
);
791 gen6_ring_get_irq(struct intel_ring_buffer
*ring
, u32 gflag
, u32 rflag
)
793 struct drm_device
*dev
= ring
->dev
;
794 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
796 if (!dev
->irq_enabled
)
799 /* It looks like we need to prevent the gt from suspending while waiting
800 * for an notifiy irq, otherwise irqs seem to get lost on at least the
801 * blt/bsd rings on ivb. */
802 gen6_gt_force_wake_get(dev_priv
);
804 spin_lock(&ring
->irq_lock
);
805 if (ring
->irq_refcount
++ == 0) {
806 ring
->irq_mask
&= ~rflag
;
807 I915_WRITE_IMR(ring
, ring
->irq_mask
);
808 ironlake_enable_irq(dev_priv
, gflag
);
810 spin_unlock(&ring
->irq_lock
);
816 gen6_ring_put_irq(struct intel_ring_buffer
*ring
, u32 gflag
, u32 rflag
)
818 struct drm_device
*dev
= ring
->dev
;
819 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
821 spin_lock(&ring
->irq_lock
);
822 if (--ring
->irq_refcount
== 0) {
823 ring
->irq_mask
|= rflag
;
824 I915_WRITE_IMR(ring
, ring
->irq_mask
);
825 ironlake_disable_irq(dev_priv
, gflag
);
827 spin_unlock(&ring
->irq_lock
);
829 gen6_gt_force_wake_put(dev_priv
);
833 bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
835 struct drm_device
*dev
= ring
->dev
;
836 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
838 if (!dev
->irq_enabled
)
841 spin_lock(&ring
->irq_lock
);
842 if (ring
->irq_refcount
++ == 0) {
844 i915_enable_irq(dev_priv
, I915_BSD_USER_INTERRUPT
);
846 ironlake_enable_irq(dev_priv
, GT_BSD_USER_INTERRUPT
);
848 spin_unlock(&ring
->irq_lock
);
853 bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
855 struct drm_device
*dev
= ring
->dev
;
856 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
858 spin_lock(&ring
->irq_lock
);
859 if (--ring
->irq_refcount
== 0) {
861 i915_disable_irq(dev_priv
, I915_BSD_USER_INTERRUPT
);
863 ironlake_disable_irq(dev_priv
, GT_BSD_USER_INTERRUPT
);
865 spin_unlock(&ring
->irq_lock
);
869 ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
, u32 offset
, u32 length
)
873 ret
= intel_ring_begin(ring
, 2);
877 intel_ring_emit(ring
,
878 MI_BATCH_BUFFER_START
| (2 << 6) |
879 MI_BATCH_NON_SECURE_I965
);
880 intel_ring_emit(ring
, offset
);
881 intel_ring_advance(ring
);
887 render_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
890 struct drm_device
*dev
= ring
->dev
;
893 if (IS_I830(dev
) || IS_845G(dev
)) {
894 ret
= intel_ring_begin(ring
, 4);
898 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
899 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
900 intel_ring_emit(ring
, offset
+ len
- 8);
901 intel_ring_emit(ring
, 0);
903 ret
= intel_ring_begin(ring
, 2);
907 if (INTEL_INFO(dev
)->gen
>= 4) {
908 intel_ring_emit(ring
,
909 MI_BATCH_BUFFER_START
| (2 << 6) |
910 MI_BATCH_NON_SECURE_I965
);
911 intel_ring_emit(ring
, offset
);
913 intel_ring_emit(ring
,
914 MI_BATCH_BUFFER_START
| (2 << 6));
915 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
918 intel_ring_advance(ring
);
923 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
925 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
926 struct drm_i915_gem_object
*obj
;
928 obj
= ring
->status_page
.obj
;
932 kunmap(obj
->pages
[0]);
933 i915_gem_object_unpin(obj
);
934 drm_gem_object_unreference(&obj
->base
);
935 ring
->status_page
.obj
= NULL
;
937 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
940 static int init_status_page(struct intel_ring_buffer
*ring
)
942 struct drm_device
*dev
= ring
->dev
;
943 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
944 struct drm_i915_gem_object
*obj
;
947 obj
= i915_gem_alloc_object(dev
, 4096);
949 DRM_ERROR("Failed to allocate status page\n");
954 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
956 ret
= i915_gem_object_pin(obj
, 4096, true);
961 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
962 ring
->status_page
.page_addr
= kmap(obj
->pages
[0]);
963 if (ring
->status_page
.page_addr
== NULL
) {
964 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
967 ring
->status_page
.obj
= obj
;
968 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
970 intel_ring_setup_status_page(ring
);
971 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
972 ring
->name
, ring
->status_page
.gfx_addr
);
977 i915_gem_object_unpin(obj
);
979 drm_gem_object_unreference(&obj
->base
);
984 int intel_init_ring_buffer(struct drm_device
*dev
,
985 struct intel_ring_buffer
*ring
)
987 struct drm_i915_gem_object
*obj
;
991 INIT_LIST_HEAD(&ring
->active_list
);
992 INIT_LIST_HEAD(&ring
->request_list
);
993 INIT_LIST_HEAD(&ring
->gpu_write_list
);
995 init_waitqueue_head(&ring
->irq_queue
);
996 spin_lock_init(&ring
->irq_lock
);
999 if (I915_NEED_GFX_HWS(dev
)) {
1000 ret
= init_status_page(ring
);
1005 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1007 DRM_ERROR("Failed to allocate ringbuffer\n");
1014 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
1018 ring
->map
.size
= ring
->size
;
1019 ring
->map
.offset
= dev
->agp
->base
+ obj
->gtt_offset
;
1021 ring
->map
.flags
= 0;
1024 drm_core_ioremap_wc(&ring
->map
, dev
);
1025 if (ring
->map
.handle
== NULL
) {
1026 DRM_ERROR("Failed to map ringbuffer.\n");
1031 ring
->virtual_start
= ring
->map
.handle
;
1032 ret
= ring
->init(ring
);
1036 /* Workaround an erratum on the i830 which causes a hang if
1037 * the TAIL pointer points to within the last 2 cachelines
1040 ring
->effective_size
= ring
->size
;
1041 if (IS_I830(ring
->dev
))
1042 ring
->effective_size
-= 128;
1047 drm_core_ioremapfree(&ring
->map
, dev
);
1049 i915_gem_object_unpin(obj
);
1051 drm_gem_object_unreference(&obj
->base
);
1054 cleanup_status_page(ring
);
1058 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1060 struct drm_i915_private
*dev_priv
;
1063 if (ring
->obj
== NULL
)
1066 /* Disable the ring buffer. The ring must be idle at this point */
1067 dev_priv
= ring
->dev
->dev_private
;
1068 ret
= intel_wait_ring_idle(ring
);
1070 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1073 I915_WRITE_CTL(ring
, 0);
1075 drm_core_ioremapfree(&ring
->map
, ring
->dev
);
1077 i915_gem_object_unpin(ring
->obj
);
1078 drm_gem_object_unreference(&ring
->obj
->base
);
1082 ring
->cleanup(ring
);
1084 cleanup_status_page(ring
);
1087 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1090 int rem
= ring
->size
- ring
->tail
;
1092 if (ring
->space
< rem
) {
1093 int ret
= intel_wait_ring_buffer(ring
, rem
);
1098 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
1106 ring
->space
= ring_space(ring
);
1111 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1113 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1114 bool was_interruptible
;
1117 /* XXX As we have not yet audited all the paths to check that
1118 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1119 * allow us to be interruptible by a signal.
1121 was_interruptible
= dev_priv
->mm
.interruptible
;
1122 dev_priv
->mm
.interruptible
= false;
1124 ret
= i915_wait_request(ring
, seqno
, true);
1126 dev_priv
->mm
.interruptible
= was_interruptible
;
1131 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1133 struct drm_i915_gem_request
*request
;
1137 i915_gem_retire_requests_ring(ring
);
1139 if (ring
->last_retired_head
!= -1) {
1140 ring
->head
= ring
->last_retired_head
;
1141 ring
->last_retired_head
= -1;
1142 ring
->space
= ring_space(ring
);
1143 if (ring
->space
>= n
)
1147 list_for_each_entry(request
, &ring
->request_list
, list
) {
1150 if (request
->tail
== -1)
1153 space
= request
->tail
- (ring
->tail
+ 8);
1155 space
+= ring
->size
;
1157 seqno
= request
->seqno
;
1161 /* Consume this request in case we need more space than
1162 * is available and so need to prevent a race between
1163 * updating last_retired_head and direct reads of
1164 * I915_RING_HEAD. It also provides a nice sanity check.
1172 ret
= intel_ring_wait_seqno(ring
, seqno
);
1176 if (WARN_ON(ring
->last_retired_head
== -1))
1179 ring
->head
= ring
->last_retired_head
;
1180 ring
->last_retired_head
= -1;
1181 ring
->space
= ring_space(ring
);
1182 if (WARN_ON(ring
->space
< n
))
1188 int intel_wait_ring_buffer(struct intel_ring_buffer
*ring
, int n
)
1190 struct drm_device
*dev
= ring
->dev
;
1191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1195 ret
= intel_ring_wait_request(ring
, n
);
1199 trace_i915_ring_wait_begin(ring
);
1200 if (drm_core_check_feature(dev
, DRIVER_GEM
))
1201 /* With GEM the hangcheck timer should kick us out of the loop,
1202 * leaving it early runs the risk of corrupting GEM state (due
1203 * to running on almost untested codepaths). But on resume
1204 * timers don't work yet, so prevent a complete hang in that
1205 * case by choosing an insanely large timeout. */
1206 end
= jiffies
+ 60 * HZ
;
1208 end
= jiffies
+ 3 * HZ
;
1211 ring
->head
= I915_READ_HEAD(ring
);
1212 ring
->space
= ring_space(ring
);
1213 if (ring
->space
>= n
) {
1214 trace_i915_ring_wait_end(ring
);
1218 if (dev
->primary
->master
) {
1219 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1220 if (master_priv
->sarea_priv
)
1221 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1225 if (atomic_read(&dev_priv
->mm
.wedged
))
1227 } while (!time_after(jiffies
, end
));
1228 trace_i915_ring_wait_end(ring
);
1232 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1235 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1236 int n
= 4*num_dwords
;
1239 if (unlikely(atomic_read(&dev_priv
->mm
.wedged
)))
1242 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1243 ret
= intel_wrap_ring_buffer(ring
);
1248 if (unlikely(ring
->space
< n
)) {
1249 ret
= intel_wait_ring_buffer(ring
, n
);
1258 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1260 ring
->tail
&= ring
->size
- 1;
1261 ring
->write_tail(ring
, ring
->tail
);
1264 static const struct intel_ring_buffer render_ring
= {
1265 .name
= "render ring",
1267 .mmio_base
= RENDER_RING_BASE
,
1268 .size
= 32 * PAGE_SIZE
,
1269 .init
= init_render_ring
,
1270 .write_tail
= ring_write_tail
,
1271 .flush
= render_ring_flush
,
1272 .add_request
= render_ring_add_request
,
1273 .get_seqno
= ring_get_seqno
,
1274 .irq_get
= render_ring_get_irq
,
1275 .irq_put
= render_ring_put_irq
,
1276 .dispatch_execbuffer
= render_ring_dispatch_execbuffer
,
1277 .cleanup
= render_ring_cleanup
,
1278 .sync_to
= render_ring_sync_to
,
1279 .semaphore_register
= {MI_SEMAPHORE_SYNC_INVALID
,
1280 MI_SEMAPHORE_SYNC_RV
,
1281 MI_SEMAPHORE_SYNC_RB
},
1282 .signal_mbox
= {GEN6_VRSYNC
, GEN6_BRSYNC
},
1285 /* ring buffer for bit-stream decoder */
1287 static const struct intel_ring_buffer bsd_ring
= {
1290 .mmio_base
= BSD_RING_BASE
,
1291 .size
= 32 * PAGE_SIZE
,
1292 .init
= init_ring_common
,
1293 .write_tail
= ring_write_tail
,
1294 .flush
= bsd_ring_flush
,
1295 .add_request
= ring_add_request
,
1296 .get_seqno
= ring_get_seqno
,
1297 .irq_get
= bsd_ring_get_irq
,
1298 .irq_put
= bsd_ring_put_irq
,
1299 .dispatch_execbuffer
= ring_dispatch_execbuffer
,
1303 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1306 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1308 /* Every tail move must follow the sequence below */
1309 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1310 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1311 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE
);
1312 I915_WRITE(GEN6_BSD_RNCID
, 0x0);
1314 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1315 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR
) == 0,
1317 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1319 I915_WRITE_TAIL(ring
, value
);
1320 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1321 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1322 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE
);
1325 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1326 u32 invalidate
, u32 flush
)
1331 ret
= intel_ring_begin(ring
, 4);
1336 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1337 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
1338 intel_ring_emit(ring
, cmd
);
1339 intel_ring_emit(ring
, 0);
1340 intel_ring_emit(ring
, 0);
1341 intel_ring_emit(ring
, MI_NOOP
);
1342 intel_ring_advance(ring
);
1347 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1348 u32 offset
, u32 len
)
1352 ret
= intel_ring_begin(ring
, 2);
1356 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
);
1357 /* bit0-7 is the length on GEN6+ */
1358 intel_ring_emit(ring
, offset
);
1359 intel_ring_advance(ring
);
1365 gen6_render_ring_get_irq(struct intel_ring_buffer
*ring
)
1367 return gen6_ring_get_irq(ring
,
1369 GEN6_RENDER_USER_INTERRUPT
);
1373 gen6_render_ring_put_irq(struct intel_ring_buffer
*ring
)
1375 return gen6_ring_put_irq(ring
,
1377 GEN6_RENDER_USER_INTERRUPT
);
1381 gen6_bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
1383 return gen6_ring_get_irq(ring
,
1384 GT_GEN6_BSD_USER_INTERRUPT
,
1385 GEN6_BSD_USER_INTERRUPT
);
1389 gen6_bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
1391 return gen6_ring_put_irq(ring
,
1392 GT_GEN6_BSD_USER_INTERRUPT
,
1393 GEN6_BSD_USER_INTERRUPT
);
1396 /* ring buffer for Video Codec for Gen6+ */
1397 static const struct intel_ring_buffer gen6_bsd_ring
= {
1398 .name
= "gen6 bsd ring",
1400 .mmio_base
= GEN6_BSD_RING_BASE
,
1401 .size
= 32 * PAGE_SIZE
,
1402 .init
= init_ring_common
,
1403 .write_tail
= gen6_bsd_ring_write_tail
,
1404 .flush
= gen6_ring_flush
,
1405 .add_request
= gen6_add_request
,
1406 .get_seqno
= gen6_ring_get_seqno
,
1407 .irq_get
= gen6_bsd_ring_get_irq
,
1408 .irq_put
= gen6_bsd_ring_put_irq
,
1409 .dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
,
1410 .sync_to
= gen6_bsd_ring_sync_to
,
1411 .semaphore_register
= {MI_SEMAPHORE_SYNC_VR
,
1412 MI_SEMAPHORE_SYNC_INVALID
,
1413 MI_SEMAPHORE_SYNC_VB
},
1414 .signal_mbox
= {GEN6_RVSYNC
, GEN6_BVSYNC
},
1417 /* Blitter support (SandyBridge+) */
1420 blt_ring_get_irq(struct intel_ring_buffer
*ring
)
1422 return gen6_ring_get_irq(ring
,
1423 GT_BLT_USER_INTERRUPT
,
1424 GEN6_BLITTER_USER_INTERRUPT
);
1428 blt_ring_put_irq(struct intel_ring_buffer
*ring
)
1430 gen6_ring_put_irq(ring
,
1431 GT_BLT_USER_INTERRUPT
,
1432 GEN6_BLITTER_USER_INTERRUPT
);
1435 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1436 u32 invalidate
, u32 flush
)
1441 ret
= intel_ring_begin(ring
, 4);
1446 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1447 cmd
|= MI_INVALIDATE_TLB
;
1448 intel_ring_emit(ring
, cmd
);
1449 intel_ring_emit(ring
, 0);
1450 intel_ring_emit(ring
, 0);
1451 intel_ring_emit(ring
, MI_NOOP
);
1452 intel_ring_advance(ring
);
1456 static const struct intel_ring_buffer gen6_blt_ring
= {
1459 .mmio_base
= BLT_RING_BASE
,
1460 .size
= 32 * PAGE_SIZE
,
1461 .init
= init_ring_common
,
1462 .write_tail
= ring_write_tail
,
1463 .flush
= blt_ring_flush
,
1464 .add_request
= gen6_add_request
,
1465 .get_seqno
= gen6_ring_get_seqno
,
1466 .irq_get
= blt_ring_get_irq
,
1467 .irq_put
= blt_ring_put_irq
,
1468 .dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
,
1469 .sync_to
= gen6_blt_ring_sync_to
,
1470 .semaphore_register
= {MI_SEMAPHORE_SYNC_BR
,
1471 MI_SEMAPHORE_SYNC_BV
,
1472 MI_SEMAPHORE_SYNC_INVALID
},
1473 .signal_mbox
= {GEN6_RBSYNC
, GEN6_VBSYNC
},
1476 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1478 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1479 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1481 *ring
= render_ring
;
1482 if (INTEL_INFO(dev
)->gen
>= 6) {
1483 ring
->add_request
= gen6_add_request
;
1484 ring
->flush
= gen6_render_ring_flush
;
1485 ring
->irq_get
= gen6_render_ring_get_irq
;
1486 ring
->irq_put
= gen6_render_ring_put_irq
;
1487 ring
->get_seqno
= gen6_ring_get_seqno
;
1488 } else if (IS_GEN5(dev
)) {
1489 ring
->add_request
= pc_render_add_request
;
1490 ring
->get_seqno
= pc_render_get_seqno
;
1493 if (!I915_NEED_GFX_HWS(dev
)) {
1494 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1495 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1498 return intel_init_ring_buffer(dev
, ring
);
1501 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1503 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1504 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1506 *ring
= render_ring
;
1507 if (INTEL_INFO(dev
)->gen
>= 6) {
1508 ring
->add_request
= gen6_add_request
;
1509 ring
->irq_get
= gen6_render_ring_get_irq
;
1510 ring
->irq_put
= gen6_render_ring_put_irq
;
1511 } else if (IS_GEN5(dev
)) {
1512 ring
->add_request
= pc_render_add_request
;
1513 ring
->get_seqno
= pc_render_get_seqno
;
1516 if (!I915_NEED_GFX_HWS(dev
))
1517 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1520 INIT_LIST_HEAD(&ring
->active_list
);
1521 INIT_LIST_HEAD(&ring
->request_list
);
1522 INIT_LIST_HEAD(&ring
->gpu_write_list
);
1525 ring
->effective_size
= ring
->size
;
1526 if (IS_I830(ring
->dev
))
1527 ring
->effective_size
-= 128;
1529 ring
->map
.offset
= start
;
1530 ring
->map
.size
= size
;
1532 ring
->map
.flags
= 0;
1535 drm_core_ioremap_wc(&ring
->map
, dev
);
1536 if (ring
->map
.handle
== NULL
) {
1537 DRM_ERROR("can not ioremap virtual address for"
1542 ring
->virtual_start
= (void __force __iomem
*)ring
->map
.handle
;
1546 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1548 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1549 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1551 if (IS_GEN6(dev
) || IS_GEN7(dev
))
1552 *ring
= gen6_bsd_ring
;
1556 return intel_init_ring_buffer(dev
, ring
);
1559 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1561 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1562 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1564 *ring
= gen6_blt_ring
;
1566 return intel_init_ring_buffer(dev
, ring
);