2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
41 struct drm_i915_gem_object
*obj
;
42 volatile u32
*cpu_page
;
46 static inline int ring_space(struct intel_ring_buffer
*ring
)
48 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 struct pipe_control
*pc
= ring
->private;
179 u32 scratch_addr
= pc
->gtt_offset
+ 128;
183 ret
= intel_ring_begin(ring
, 6);
187 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
189 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
190 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
191 intel_ring_emit(ring
, 0); /* low dword */
192 intel_ring_emit(ring
, 0); /* high dword */
193 intel_ring_emit(ring
, MI_NOOP
);
194 intel_ring_advance(ring
);
196 ret
= intel_ring_begin(ring
, 6);
200 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
202 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, MI_NOOP
);
206 intel_ring_advance(ring
);
212 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
213 u32 invalidate_domains
, u32 flush_domains
)
216 struct pipe_control
*pc
= ring
->private;
217 u32 scratch_addr
= pc
->gtt_offset
+ 128;
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret
= intel_emit_post_sync_nonzero_flush(ring
);
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
230 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
231 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
236 flags
|= PIPE_CONTROL_CS_STALL
;
238 if (invalidate_domains
) {
239 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
240 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
244 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
246 * TLB invalidate requires a post-sync write.
248 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
251 ret
= intel_ring_begin(ring
, 4);
255 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring
, flags
);
257 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
258 intel_ring_emit(ring
, 0);
259 intel_ring_advance(ring
);
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
269 ret
= intel_ring_begin(ring
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
275 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
276 intel_ring_emit(ring
, 0);
277 intel_ring_emit(ring
, 0);
278 intel_ring_advance(ring
);
284 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
285 u32 invalidate_domains
, u32 flush_domains
)
288 struct pipe_control
*pc
= ring
->private;
289 u32 scratch_addr
= pc
->gtt_offset
+ 128;
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
300 flags
|= PIPE_CONTROL_CS_STALL
;
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
307 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
308 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
310 if (invalidate_domains
) {
311 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
312 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
313 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
314 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
315 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
316 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
318 * TLB invalidate requires a post-sync write.
320 flags
|= PIPE_CONTROL_QW_WRITE
;
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring
);
328 ret
= intel_ring_begin(ring
, 4);
332 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring
, flags
);
334 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
335 intel_ring_emit(ring
, 0);
336 intel_ring_advance(ring
);
341 static void ring_write_tail(struct intel_ring_buffer
*ring
,
344 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
345 I915_WRITE_TAIL(ring
, value
);
348 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
350 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
351 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
352 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
354 return I915_READ(acthd_reg
);
357 static int init_ring_common(struct intel_ring_buffer
*ring
)
359 struct drm_device
*dev
= ring
->dev
;
360 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
361 struct drm_i915_gem_object
*obj
= ring
->obj
;
365 if (HAS_FORCE_WAKE(dev
))
366 gen6_gt_force_wake_get(dev_priv
);
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring
, 0);
370 I915_WRITE_HEAD(ring
, 0);
371 ring
->write_tail(ring
, 0);
373 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
375 /* G45 ring initialization fails to reset head to zero */
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
381 I915_READ_HEAD(ring
),
382 I915_READ_TAIL(ring
),
383 I915_READ_START(ring
));
385 I915_WRITE_HEAD(ring
, 0);
387 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
392 I915_READ_HEAD(ring
),
393 I915_READ_TAIL(ring
),
394 I915_READ_START(ring
));
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring
, obj
->gtt_offset
);
404 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
409 I915_READ_START(ring
) == obj
->gtt_offset
&&
410 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
415 I915_READ_HEAD(ring
),
416 I915_READ_TAIL(ring
),
417 I915_READ_START(ring
));
422 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
423 i915_kernel_lost_context(ring
->dev
);
425 ring
->head
= I915_READ_HEAD(ring
);
426 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
427 ring
->space
= ring_space(ring
);
428 ring
->last_retired_head
= -1;
432 if (HAS_FORCE_WAKE(dev
))
433 gen6_gt_force_wake_put(dev_priv
);
439 init_pipe_control(struct intel_ring_buffer
*ring
)
441 struct pipe_control
*pc
;
442 struct drm_i915_gem_object
*obj
;
448 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
452 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
454 DRM_ERROR("Failed to allocate seqno page\n");
459 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
461 ret
= i915_gem_object_pin(obj
, 4096, true, false);
465 pc
->gtt_offset
= obj
->gtt_offset
;
466 pc
->cpu_page
= kmap(sg_page(obj
->pages
->sgl
));
467 if (pc
->cpu_page
== NULL
)
475 i915_gem_object_unpin(obj
);
477 drm_gem_object_unreference(&obj
->base
);
484 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
486 struct pipe_control
*pc
= ring
->private;
487 struct drm_i915_gem_object
*obj
;
494 kunmap(sg_page(obj
->pages
->sgl
));
495 i915_gem_object_unpin(obj
);
496 drm_gem_object_unreference(&obj
->base
);
499 ring
->private = NULL
;
502 static int init_render_ring(struct intel_ring_buffer
*ring
)
504 struct drm_device
*dev
= ring
->dev
;
505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
506 int ret
= init_ring_common(ring
);
508 if (INTEL_INFO(dev
)->gen
> 3) {
509 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
511 I915_WRITE(GFX_MODE_GEN7
,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
516 if (INTEL_INFO(dev
)->gen
>= 5) {
517 ret
= init_pipe_control(ring
);
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
528 I915_WRITE(CACHE_MODE_0
,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
535 ring
->itlb_before_ctx_switch
=
536 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
539 if (INTEL_INFO(dev
)->gen
>= 6)
540 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
542 if (HAS_L3_GPU_CACHE(dev
))
543 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
548 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
550 struct drm_device
*dev
= ring
->dev
;
555 if (HAS_BROKEN_CS_TLB(dev
))
556 drm_gem_object_unreference(to_gem_object(ring
->private));
558 cleanup_pipe_control(ring
);
562 update_mboxes(struct intel_ring_buffer
*ring
,
565 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
566 intel_ring_emit(ring
, mmio_offset
);
567 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
571 * gen6_add_request - Update the semaphore mailbox registers
573 * @ring - ring that is adding a request
574 * @seqno - return seqno stuck into the ring
576 * Update the mailbox registers in the *other* rings with the current seqno.
577 * This acts like a signal in the canonical semaphore.
580 gen6_add_request(struct intel_ring_buffer
*ring
)
586 ret
= intel_ring_begin(ring
, 10);
590 mbox1_reg
= ring
->signal_mbox
[0];
591 mbox2_reg
= ring
->signal_mbox
[1];
593 update_mboxes(ring
, mbox1_reg
);
594 update_mboxes(ring
, mbox2_reg
);
595 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
596 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
597 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
598 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
599 intel_ring_advance(ring
);
605 * intel_ring_sync - sync the waiter to the signaller on seqno
607 * @waiter - ring that is waiting
608 * @signaller - ring which has, or will signal
609 * @seqno - seqno which the waiter will block on
612 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
613 struct intel_ring_buffer
*signaller
,
617 u32 dw1
= MI_SEMAPHORE_MBOX
|
618 MI_SEMAPHORE_COMPARE
|
619 MI_SEMAPHORE_REGISTER
;
621 /* Throughout all of the GEM code, seqno passed implies our current
622 * seqno is >= the last seqno executed. However for hardware the
623 * comparison is strictly greater than.
627 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
628 MI_SEMAPHORE_SYNC_INVALID
);
630 ret
= intel_ring_begin(waiter
, 4);
634 intel_ring_emit(waiter
,
635 dw1
| signaller
->semaphore_register
[waiter
->id
]);
636 intel_ring_emit(waiter
, seqno
);
637 intel_ring_emit(waiter
, 0);
638 intel_ring_emit(waiter
, MI_NOOP
);
639 intel_ring_advance(waiter
);
644 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
646 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
647 PIPE_CONTROL_DEPTH_STALL); \
648 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
649 intel_ring_emit(ring__, 0); \
650 intel_ring_emit(ring__, 0); \
654 pc_render_add_request(struct intel_ring_buffer
*ring
)
656 struct pipe_control
*pc
= ring
->private;
657 u32 scratch_addr
= pc
->gtt_offset
+ 128;
660 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
661 * incoherent with writes to memory, i.e. completely fubar,
662 * so we need to use PIPE_NOTIFY instead.
664 * However, we also need to workaround the qword write
665 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
666 * memory before requesting an interrupt.
668 ret
= intel_ring_begin(ring
, 32);
672 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
673 PIPE_CONTROL_WRITE_FLUSH
|
674 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
675 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
676 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
677 intel_ring_emit(ring
, 0);
678 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
679 scratch_addr
+= 128; /* write to separate cachelines */
680 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
682 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
684 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
686 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
688 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
690 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
691 PIPE_CONTROL_WRITE_FLUSH
|
692 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
693 PIPE_CONTROL_NOTIFY
);
694 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
695 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
696 intel_ring_emit(ring
, 0);
697 intel_ring_advance(ring
);
703 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
705 /* Workaround to force correct ordering between irq and seqno writes on
706 * ivb (and maybe also on snb) by reading from a CS register (like
707 * ACTHD) before reading the status page. */
709 intel_ring_get_active_head(ring
);
710 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
714 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
716 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
720 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
722 struct pipe_control
*pc
= ring
->private;
723 return pc
->cpu_page
[0];
727 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
729 struct drm_device
*dev
= ring
->dev
;
730 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
733 if (!dev
->irq_enabled
)
736 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
737 if (ring
->irq_refcount
++ == 0) {
738 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
739 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
742 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
748 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
750 struct drm_device
*dev
= ring
->dev
;
751 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
754 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
755 if (--ring
->irq_refcount
== 0) {
756 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
757 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
760 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
764 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
766 struct drm_device
*dev
= ring
->dev
;
767 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
770 if (!dev
->irq_enabled
)
773 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
774 if (ring
->irq_refcount
++ == 0) {
775 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
776 I915_WRITE(IMR
, dev_priv
->irq_mask
);
779 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
785 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
787 struct drm_device
*dev
= ring
->dev
;
788 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
791 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
792 if (--ring
->irq_refcount
== 0) {
793 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
794 I915_WRITE(IMR
, dev_priv
->irq_mask
);
797 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
801 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
803 struct drm_device
*dev
= ring
->dev
;
804 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
807 if (!dev
->irq_enabled
)
810 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
811 if (ring
->irq_refcount
++ == 0) {
812 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
813 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
816 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
822 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
824 struct drm_device
*dev
= ring
->dev
;
825 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
828 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
829 if (--ring
->irq_refcount
== 0) {
830 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
831 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
834 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
837 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
839 struct drm_device
*dev
= ring
->dev
;
840 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
843 /* The ring status page addresses are no longer next to the rest of
844 * the ring registers as of gen7.
849 mmio
= RENDER_HWS_PGA_GEN7
;
852 mmio
= BLT_HWS_PGA_GEN7
;
855 mmio
= BSD_HWS_PGA_GEN7
;
858 } else if (IS_GEN6(ring
->dev
)) {
859 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
861 mmio
= RING_HWS_PGA(ring
->mmio_base
);
864 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
869 bsd_ring_flush(struct intel_ring_buffer
*ring
,
870 u32 invalidate_domains
,
875 ret
= intel_ring_begin(ring
, 2);
879 intel_ring_emit(ring
, MI_FLUSH
);
880 intel_ring_emit(ring
, MI_NOOP
);
881 intel_ring_advance(ring
);
886 i9xx_add_request(struct intel_ring_buffer
*ring
)
890 ret
= intel_ring_begin(ring
, 4);
894 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
895 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
896 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
897 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
898 intel_ring_advance(ring
);
904 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
906 struct drm_device
*dev
= ring
->dev
;
907 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
910 if (!dev
->irq_enabled
)
913 /* It looks like we need to prevent the gt from suspending while waiting
914 * for an notifiy irq, otherwise irqs seem to get lost on at least the
915 * blt/bsd rings on ivb. */
916 gen6_gt_force_wake_get(dev_priv
);
918 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
919 if (ring
->irq_refcount
++ == 0) {
920 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
921 I915_WRITE_IMR(ring
, ~(ring
->irq_enable_mask
|
922 GEN6_RENDER_L3_PARITY_ERROR
));
924 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
925 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
926 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
929 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
935 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
937 struct drm_device
*dev
= ring
->dev
;
938 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
941 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
942 if (--ring
->irq_refcount
== 0) {
943 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
944 I915_WRITE_IMR(ring
, ~GEN6_RENDER_L3_PARITY_ERROR
);
946 I915_WRITE_IMR(ring
, ~0);
947 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
948 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
951 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
953 gen6_gt_force_wake_put(dev_priv
);
957 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
958 u32 offset
, u32 length
,
963 ret
= intel_ring_begin(ring
, 2);
967 intel_ring_emit(ring
,
968 MI_BATCH_BUFFER_START
|
970 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
971 intel_ring_emit(ring
, offset
);
972 intel_ring_advance(ring
);
977 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
978 #define I830_BATCH_LIMIT (256*1024)
980 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
986 if (flags
& I915_DISPATCH_PINNED
) {
987 ret
= intel_ring_begin(ring
, 4);
991 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
992 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
993 intel_ring_emit(ring
, offset
+ len
- 8);
994 intel_ring_emit(ring
, MI_NOOP
);
995 intel_ring_advance(ring
);
997 struct drm_i915_gem_object
*obj
= ring
->private;
998 u32 cs_offset
= obj
->gtt_offset
;
1000 if (len
> I830_BATCH_LIMIT
)
1003 ret
= intel_ring_begin(ring
, 9+3);
1006 /* Blit the batch (which has now all relocs applied) to the stable batch
1007 * scratch bo area (so that the CS never stumbles over its tlb
1008 * invalidation bug) ... */
1009 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1010 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1011 XY_SRC_COPY_BLT_WRITE_RGB
);
1012 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1013 intel_ring_emit(ring
, 0);
1014 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1015 intel_ring_emit(ring
, cs_offset
);
1016 intel_ring_emit(ring
, 0);
1017 intel_ring_emit(ring
, 4096);
1018 intel_ring_emit(ring
, offset
);
1019 intel_ring_emit(ring
, MI_FLUSH
);
1021 /* ... and execute it. */
1022 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1023 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1024 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1025 intel_ring_advance(ring
);
1032 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1033 u32 offset
, u32 len
,
1038 ret
= intel_ring_begin(ring
, 2);
1042 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1043 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1044 intel_ring_advance(ring
);
1049 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1051 struct drm_i915_gem_object
*obj
;
1053 obj
= ring
->status_page
.obj
;
1057 kunmap(sg_page(obj
->pages
->sgl
));
1058 i915_gem_object_unpin(obj
);
1059 drm_gem_object_unreference(&obj
->base
);
1060 ring
->status_page
.obj
= NULL
;
1063 static int init_status_page(struct intel_ring_buffer
*ring
)
1065 struct drm_device
*dev
= ring
->dev
;
1066 struct drm_i915_gem_object
*obj
;
1069 obj
= i915_gem_alloc_object(dev
, 4096);
1071 DRM_ERROR("Failed to allocate status page\n");
1076 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1078 ret
= i915_gem_object_pin(obj
, 4096, true, false);
1083 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
1084 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1085 if (ring
->status_page
.page_addr
== NULL
) {
1089 ring
->status_page
.obj
= obj
;
1090 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1092 intel_ring_setup_status_page(ring
);
1093 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1094 ring
->name
, ring
->status_page
.gfx_addr
);
1099 i915_gem_object_unpin(obj
);
1101 drm_gem_object_unreference(&obj
->base
);
1106 static int init_phys_hws_pga(struct intel_ring_buffer
*ring
)
1108 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1111 if (!dev_priv
->status_page_dmah
) {
1112 dev_priv
->status_page_dmah
=
1113 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1114 if (!dev_priv
->status_page_dmah
)
1118 addr
= dev_priv
->status_page_dmah
->busaddr
;
1119 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
1120 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
1121 I915_WRITE(HWS_PGA
, addr
);
1123 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1124 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1129 static int intel_init_ring_buffer(struct drm_device
*dev
,
1130 struct intel_ring_buffer
*ring
)
1132 struct drm_i915_gem_object
*obj
;
1133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1137 INIT_LIST_HEAD(&ring
->active_list
);
1138 INIT_LIST_HEAD(&ring
->request_list
);
1139 ring
->size
= 32 * PAGE_SIZE
;
1140 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1142 init_waitqueue_head(&ring
->irq_queue
);
1144 if (I915_NEED_GFX_HWS(dev
)) {
1145 ret
= init_status_page(ring
);
1149 BUG_ON(ring
->id
!= RCS
);
1150 ret
= init_phys_hws_pga(ring
);
1155 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1157 DRM_ERROR("Failed to allocate ringbuffer\n");
1164 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true, false);
1168 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1172 ring
->virtual_start
=
1173 ioremap_wc(dev_priv
->mm
.gtt
->gma_bus_addr
+ obj
->gtt_offset
,
1175 if (ring
->virtual_start
== NULL
) {
1176 DRM_ERROR("Failed to map ringbuffer.\n");
1181 ret
= ring
->init(ring
);
1185 /* Workaround an erratum on the i830 which causes a hang if
1186 * the TAIL pointer points to within the last 2 cachelines
1189 ring
->effective_size
= ring
->size
;
1190 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1191 ring
->effective_size
-= 128;
1196 iounmap(ring
->virtual_start
);
1198 i915_gem_object_unpin(obj
);
1200 drm_gem_object_unreference(&obj
->base
);
1203 cleanup_status_page(ring
);
1207 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1209 struct drm_i915_private
*dev_priv
;
1212 if (ring
->obj
== NULL
)
1215 /* Disable the ring buffer. The ring must be idle at this point */
1216 dev_priv
= ring
->dev
->dev_private
;
1217 ret
= intel_ring_idle(ring
);
1219 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1222 I915_WRITE_CTL(ring
, 0);
1224 iounmap(ring
->virtual_start
);
1226 i915_gem_object_unpin(ring
->obj
);
1227 drm_gem_object_unreference(&ring
->obj
->base
);
1231 ring
->cleanup(ring
);
1233 cleanup_status_page(ring
);
1236 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1240 ret
= i915_wait_seqno(ring
, seqno
);
1242 i915_gem_retire_requests_ring(ring
);
1247 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1249 struct drm_i915_gem_request
*request
;
1253 i915_gem_retire_requests_ring(ring
);
1255 if (ring
->last_retired_head
!= -1) {
1256 ring
->head
= ring
->last_retired_head
;
1257 ring
->last_retired_head
= -1;
1258 ring
->space
= ring_space(ring
);
1259 if (ring
->space
>= n
)
1263 list_for_each_entry(request
, &ring
->request_list
, list
) {
1266 if (request
->tail
== -1)
1269 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1271 space
+= ring
->size
;
1273 seqno
= request
->seqno
;
1277 /* Consume this request in case we need more space than
1278 * is available and so need to prevent a race between
1279 * updating last_retired_head and direct reads of
1280 * I915_RING_HEAD. It also provides a nice sanity check.
1288 ret
= intel_ring_wait_seqno(ring
, seqno
);
1292 if (WARN_ON(ring
->last_retired_head
== -1))
1295 ring
->head
= ring
->last_retired_head
;
1296 ring
->last_retired_head
= -1;
1297 ring
->space
= ring_space(ring
);
1298 if (WARN_ON(ring
->space
< n
))
1304 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1306 struct drm_device
*dev
= ring
->dev
;
1307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1311 ret
= intel_ring_wait_request(ring
, n
);
1315 trace_i915_ring_wait_begin(ring
);
1316 /* With GEM the hangcheck timer should kick us out of the loop,
1317 * leaving it early runs the risk of corrupting GEM state (due
1318 * to running on almost untested codepaths). But on resume
1319 * timers don't work yet, so prevent a complete hang in that
1320 * case by choosing an insanely large timeout. */
1321 end
= jiffies
+ 60 * HZ
;
1324 ring
->head
= I915_READ_HEAD(ring
);
1325 ring
->space
= ring_space(ring
);
1326 if (ring
->space
>= n
) {
1327 trace_i915_ring_wait_end(ring
);
1331 if (dev
->primary
->master
) {
1332 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1333 if (master_priv
->sarea_priv
)
1334 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1339 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1342 } while (!time_after(jiffies
, end
));
1343 trace_i915_ring_wait_end(ring
);
1347 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1349 uint32_t __iomem
*virt
;
1350 int rem
= ring
->size
- ring
->tail
;
1352 if (ring
->space
< rem
) {
1353 int ret
= ring_wait_for_space(ring
, rem
);
1358 virt
= ring
->virtual_start
+ ring
->tail
;
1361 iowrite32(MI_NOOP
, virt
++);
1364 ring
->space
= ring_space(ring
);
1369 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1374 /* We need to add any requests required to flush the objects and ring */
1375 if (ring
->outstanding_lazy_request
) {
1376 ret
= i915_add_request(ring
, NULL
, NULL
);
1381 /* Wait upon the last request to be completed */
1382 if (list_empty(&ring
->request_list
))
1385 seqno
= list_entry(ring
->request_list
.prev
,
1386 struct drm_i915_gem_request
,
1389 return i915_wait_seqno(ring
, seqno
);
1393 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1395 if (ring
->outstanding_lazy_request
)
1398 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_request
);
1401 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1404 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1405 int n
= 4*num_dwords
;
1408 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
1412 /* Preallocate the olr before touching the ring */
1413 ret
= intel_ring_alloc_seqno(ring
);
1417 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1418 ret
= intel_wrap_ring_buffer(ring
);
1423 if (unlikely(ring
->space
< n
)) {
1424 ret
= ring_wait_for_space(ring
, n
);
1433 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1435 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1437 ring
->tail
&= ring
->size
- 1;
1438 if (dev_priv
->stop_rings
& intel_ring_flag(ring
))
1440 ring
->write_tail(ring
, ring
->tail
);
1444 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1447 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1449 /* Every tail move must follow the sequence below */
1451 /* Disable notification that the ring is IDLE. The GT
1452 * will then assume that it is busy and bring it out of rc6.
1454 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1455 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1457 /* Clear the context id. Here be magic! */
1458 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1460 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1461 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1462 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1464 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1466 /* Now that the ring is fully powered up, update the tail */
1467 I915_WRITE_TAIL(ring
, value
);
1468 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1470 /* Let the ring send IDLE messages to the GT again,
1471 * and so let it sleep to conserve power when idle.
1473 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1474 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1477 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1478 u32 invalidate
, u32 flush
)
1483 ret
= intel_ring_begin(ring
, 4);
1489 * Bspec vol 1c.5 - video engine command streamer:
1490 * "If ENABLED, all TLBs will be invalidated once the flush
1491 * operation is complete. This bit is only valid when the
1492 * Post-Sync Operation field is a value of 1h or 3h."
1494 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1495 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1496 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1497 intel_ring_emit(ring
, cmd
);
1498 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1499 intel_ring_emit(ring
, 0);
1500 intel_ring_emit(ring
, MI_NOOP
);
1501 intel_ring_advance(ring
);
1506 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1507 u32 offset
, u32 len
,
1512 ret
= intel_ring_begin(ring
, 2);
1516 intel_ring_emit(ring
,
1517 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1518 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1519 /* bit0-7 is the length on GEN6+ */
1520 intel_ring_emit(ring
, offset
);
1521 intel_ring_advance(ring
);
1527 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1528 u32 offset
, u32 len
,
1533 ret
= intel_ring_begin(ring
, 2);
1537 intel_ring_emit(ring
,
1538 MI_BATCH_BUFFER_START
|
1539 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1540 /* bit0-7 is the length on GEN6+ */
1541 intel_ring_emit(ring
, offset
);
1542 intel_ring_advance(ring
);
1547 /* Blitter support (SandyBridge+) */
1549 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1550 u32 invalidate
, u32 flush
)
1555 ret
= intel_ring_begin(ring
, 4);
1561 * Bspec vol 1c.3 - blitter engine command streamer:
1562 * "If ENABLED, all TLBs will be invalidated once the flush
1563 * operation is complete. This bit is only valid when the
1564 * Post-Sync Operation field is a value of 1h or 3h."
1566 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1567 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1568 MI_FLUSH_DW_OP_STOREDW
;
1569 intel_ring_emit(ring
, cmd
);
1570 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1571 intel_ring_emit(ring
, 0);
1572 intel_ring_emit(ring
, MI_NOOP
);
1573 intel_ring_advance(ring
);
1577 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1579 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1580 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1582 ring
->name
= "render ring";
1584 ring
->mmio_base
= RENDER_RING_BASE
;
1586 if (INTEL_INFO(dev
)->gen
>= 6) {
1587 ring
->add_request
= gen6_add_request
;
1588 ring
->flush
= gen7_render_ring_flush
;
1589 if (INTEL_INFO(dev
)->gen
== 6)
1590 ring
->flush
= gen6_render_ring_flush
;
1591 ring
->irq_get
= gen6_ring_get_irq
;
1592 ring
->irq_put
= gen6_ring_put_irq
;
1593 ring
->irq_enable_mask
= GT_USER_INTERRUPT
;
1594 ring
->get_seqno
= gen6_ring_get_seqno
;
1595 ring
->sync_to
= gen6_ring_sync
;
1596 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_INVALID
;
1597 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_RV
;
1598 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_RB
;
1599 ring
->signal_mbox
[0] = GEN6_VRSYNC
;
1600 ring
->signal_mbox
[1] = GEN6_BRSYNC
;
1601 } else if (IS_GEN5(dev
)) {
1602 ring
->add_request
= pc_render_add_request
;
1603 ring
->flush
= gen4_render_ring_flush
;
1604 ring
->get_seqno
= pc_render_get_seqno
;
1605 ring
->irq_get
= gen5_ring_get_irq
;
1606 ring
->irq_put
= gen5_ring_put_irq
;
1607 ring
->irq_enable_mask
= GT_USER_INTERRUPT
| GT_PIPE_NOTIFY
;
1609 ring
->add_request
= i9xx_add_request
;
1610 if (INTEL_INFO(dev
)->gen
< 4)
1611 ring
->flush
= gen2_render_ring_flush
;
1613 ring
->flush
= gen4_render_ring_flush
;
1614 ring
->get_seqno
= ring_get_seqno
;
1616 ring
->irq_get
= i8xx_ring_get_irq
;
1617 ring
->irq_put
= i8xx_ring_put_irq
;
1619 ring
->irq_get
= i9xx_ring_get_irq
;
1620 ring
->irq_put
= i9xx_ring_put_irq
;
1622 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1624 ring
->write_tail
= ring_write_tail
;
1625 if (IS_HASWELL(dev
))
1626 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1627 else if (INTEL_INFO(dev
)->gen
>= 6)
1628 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1629 else if (INTEL_INFO(dev
)->gen
>= 4)
1630 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1631 else if (IS_I830(dev
) || IS_845G(dev
))
1632 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1634 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1635 ring
->init
= init_render_ring
;
1636 ring
->cleanup
= render_ring_cleanup
;
1638 /* Workaround batchbuffer to combat CS tlb bug. */
1639 if (HAS_BROKEN_CS_TLB(dev
)) {
1640 struct drm_i915_gem_object
*obj
;
1643 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
1645 DRM_ERROR("Failed to allocate batch bo\n");
1649 ret
= i915_gem_object_pin(obj
, 0, true, false);
1651 drm_gem_object_unreference(&obj
->base
);
1652 DRM_ERROR("Failed to ping batch bo\n");
1656 ring
->private = obj
;
1659 return intel_init_ring_buffer(dev
, ring
);
1662 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1664 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1665 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1668 ring
->name
= "render ring";
1670 ring
->mmio_base
= RENDER_RING_BASE
;
1672 if (INTEL_INFO(dev
)->gen
>= 6) {
1673 /* non-kms not supported on gen6+ */
1677 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1678 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1679 * the special gen5 functions. */
1680 ring
->add_request
= i9xx_add_request
;
1681 if (INTEL_INFO(dev
)->gen
< 4)
1682 ring
->flush
= gen2_render_ring_flush
;
1684 ring
->flush
= gen4_render_ring_flush
;
1685 ring
->get_seqno
= ring_get_seqno
;
1687 ring
->irq_get
= i8xx_ring_get_irq
;
1688 ring
->irq_put
= i8xx_ring_put_irq
;
1690 ring
->irq_get
= i9xx_ring_get_irq
;
1691 ring
->irq_put
= i9xx_ring_put_irq
;
1693 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1694 ring
->write_tail
= ring_write_tail
;
1695 if (INTEL_INFO(dev
)->gen
>= 4)
1696 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1697 else if (IS_I830(dev
) || IS_845G(dev
))
1698 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1700 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1701 ring
->init
= init_render_ring
;
1702 ring
->cleanup
= render_ring_cleanup
;
1705 INIT_LIST_HEAD(&ring
->active_list
);
1706 INIT_LIST_HEAD(&ring
->request_list
);
1709 ring
->effective_size
= ring
->size
;
1710 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1711 ring
->effective_size
-= 128;
1713 ring
->virtual_start
= ioremap_wc(start
, size
);
1714 if (ring
->virtual_start
== NULL
) {
1715 DRM_ERROR("can not ioremap virtual address for"
1720 if (!I915_NEED_GFX_HWS(dev
)) {
1721 ret
= init_phys_hws_pga(ring
);
1729 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1731 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1732 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1734 ring
->name
= "bsd ring";
1737 ring
->write_tail
= ring_write_tail
;
1738 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1739 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1740 /* gen6 bsd needs a special wa for tail updates */
1742 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1743 ring
->flush
= gen6_ring_flush
;
1744 ring
->add_request
= gen6_add_request
;
1745 ring
->get_seqno
= gen6_ring_get_seqno
;
1746 ring
->irq_enable_mask
= GEN6_BSD_USER_INTERRUPT
;
1747 ring
->irq_get
= gen6_ring_get_irq
;
1748 ring
->irq_put
= gen6_ring_put_irq
;
1749 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1750 ring
->sync_to
= gen6_ring_sync
;
1751 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_VR
;
1752 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_INVALID
;
1753 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_VB
;
1754 ring
->signal_mbox
[0] = GEN6_RVSYNC
;
1755 ring
->signal_mbox
[1] = GEN6_BVSYNC
;
1757 ring
->mmio_base
= BSD_RING_BASE
;
1758 ring
->flush
= bsd_ring_flush
;
1759 ring
->add_request
= i9xx_add_request
;
1760 ring
->get_seqno
= ring_get_seqno
;
1762 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1763 ring
->irq_get
= gen5_ring_get_irq
;
1764 ring
->irq_put
= gen5_ring_put_irq
;
1766 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1767 ring
->irq_get
= i9xx_ring_get_irq
;
1768 ring
->irq_put
= i9xx_ring_put_irq
;
1770 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1772 ring
->init
= init_ring_common
;
1774 return intel_init_ring_buffer(dev
, ring
);
1777 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1779 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1780 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1782 ring
->name
= "blitter ring";
1785 ring
->mmio_base
= BLT_RING_BASE
;
1786 ring
->write_tail
= ring_write_tail
;
1787 ring
->flush
= blt_ring_flush
;
1788 ring
->add_request
= gen6_add_request
;
1789 ring
->get_seqno
= gen6_ring_get_seqno
;
1790 ring
->irq_enable_mask
= GEN6_BLITTER_USER_INTERRUPT
;
1791 ring
->irq_get
= gen6_ring_get_irq
;
1792 ring
->irq_put
= gen6_ring_put_irq
;
1793 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1794 ring
->sync_to
= gen6_ring_sync
;
1795 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_BR
;
1796 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_BV
;
1797 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_INVALID
;
1798 ring
->signal_mbox
[0] = GEN6_RBSYNC
;
1799 ring
->signal_mbox
[1] = GEN6_VBSYNC
;
1800 ring
->init
= init_ring_common
;
1802 return intel_init_ring_buffer(dev
, ring
);
1806 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
1810 if (!ring
->gpu_caches_dirty
)
1813 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1817 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
1819 ring
->gpu_caches_dirty
= false;
1824 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
1826 uint32_t flush_domains
;
1830 if (ring
->gpu_caches_dirty
)
1831 flush_domains
= I915_GEM_GPU_DOMAINS
;
1833 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1837 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
1839 ring
->gpu_caches_dirty
= false;