2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object
*obj
;
43 volatile u32
*cpu_page
;
47 static inline int ring_space(struct intel_ring_buffer
*ring
)
49 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ 8);
56 render_ring_flush(struct intel_ring_buffer
*ring
,
57 u32 invalidate_domains
,
60 struct drm_device
*dev
= ring
->dev
;
67 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
69 * also flushed at 2d versus 3d pipeline switches.
73 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74 * MI_READ_FLUSH is set, and is always flushed on 965.
76 * I915_GEM_DOMAIN_COMMAND may not exist?
78 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79 * invalidated when MI_EXE_FLUSH is set.
81 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82 * invalidated with every MI_FLUSH.
86 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89 * are flushed at any MI_FLUSH.
92 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
93 if ((invalidate_domains
|flush_domains
) &
94 I915_GEM_DOMAIN_RENDER
)
95 cmd
&= ~MI_NO_WRITE_FLUSH
;
96 if (INTEL_INFO(dev
)->gen
< 4) {
98 * On the 965, the sampler cache always gets flushed
99 * and this bit is reserved.
101 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
102 cmd
|= MI_READ_FLUSH
;
104 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
107 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
108 (IS_G4X(dev
) || IS_GEN5(dev
)))
109 cmd
|= MI_INVALIDATE_ISP
;
111 ret
= intel_ring_begin(ring
, 2);
115 intel_ring_emit(ring
, cmd
);
116 intel_ring_emit(ring
, MI_NOOP
);
117 intel_ring_advance(ring
);
123 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124 * implementing two workarounds on gen6. From section 1.4.7.1
125 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
127 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128 * produced by non-pipelined state commands), software needs to first
129 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
132 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
135 * And the workaround for these two requires this workaround first:
137 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138 * BEFORE the pipe-control with a post-sync op and no write-cache
141 * And this last workaround is tricky because of the requirements on
142 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
145 * "1 of the following must also be set:
146 * - Render Target Cache Flush Enable ([12] of DW1)
147 * - Depth Cache Flush Enable ([0] of DW1)
148 * - Stall at Pixel Scoreboard ([1] of DW1)
149 * - Depth Stall ([13] of DW1)
150 * - Post-Sync Operation ([13] of DW1)
151 * - Notify Enable ([8] of DW1)"
153 * The cache flushes require the workaround flush that triggered this
154 * one, so we can't use it. Depth stall would trigger the same.
155 * Post-sync nonzero is what triggered this second workaround, so we
156 * can't use that one either. Notify enable is IRQs, which aren't
157 * really our business. That leaves only stall at scoreboard.
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
162 struct pipe_control
*pc
= ring
->private;
163 u32 scratch_addr
= pc
->gtt_offset
+ 128;
167 ret
= intel_ring_begin(ring
, 6);
171 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
172 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
173 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
174 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
175 intel_ring_emit(ring
, 0); /* low dword */
176 intel_ring_emit(ring
, 0); /* high dword */
177 intel_ring_emit(ring
, MI_NOOP
);
178 intel_ring_advance(ring
);
180 ret
= intel_ring_begin(ring
, 6);
184 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
185 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
186 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
187 intel_ring_emit(ring
, 0);
188 intel_ring_emit(ring
, 0);
189 intel_ring_emit(ring
, MI_NOOP
);
190 intel_ring_advance(ring
);
196 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
197 u32 invalidate_domains
, u32 flush_domains
)
200 struct pipe_control
*pc
= ring
->private;
201 u32 scratch_addr
= pc
->gtt_offset
+ 128;
204 /* Force SNB workarounds for PIPE_CONTROL flushes */
205 intel_emit_post_sync_nonzero_flush(ring
);
207 /* Just flush everything. Experiments have shown that reducing the
208 * number of bits based on the write domains has little performance
211 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
212 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
213 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
214 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
215 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
216 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
217 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
219 ret
= intel_ring_begin(ring
, 6);
223 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
224 intel_ring_emit(ring
, flags
);
225 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
226 intel_ring_emit(ring
, 0); /* lower dword */
227 intel_ring_emit(ring
, 0); /* uppwer dword */
228 intel_ring_emit(ring
, MI_NOOP
);
229 intel_ring_advance(ring
);
234 static void ring_write_tail(struct intel_ring_buffer
*ring
,
237 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
238 I915_WRITE_TAIL(ring
, value
);
241 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
243 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
244 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
245 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
247 return I915_READ(acthd_reg
);
250 static int init_ring_common(struct intel_ring_buffer
*ring
)
252 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
253 struct drm_i915_gem_object
*obj
= ring
->obj
;
256 /* Stop the ring if it's running. */
257 I915_WRITE_CTL(ring
, 0);
258 I915_WRITE_HEAD(ring
, 0);
259 ring
->write_tail(ring
, 0);
261 /* Initialize the ring. */
262 I915_WRITE_START(ring
, obj
->gtt_offset
);
263 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
265 /* G45 ring initialization fails to reset head to zero */
267 DRM_DEBUG_KMS("%s head not reset to zero "
268 "ctl %08x head %08x tail %08x start %08x\n",
271 I915_READ_HEAD(ring
),
272 I915_READ_TAIL(ring
),
273 I915_READ_START(ring
));
275 I915_WRITE_HEAD(ring
, 0);
277 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
278 DRM_ERROR("failed to set %s head to zero "
279 "ctl %08x head %08x tail %08x start %08x\n",
282 I915_READ_HEAD(ring
),
283 I915_READ_TAIL(ring
),
284 I915_READ_START(ring
));
289 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
292 /* If the head is still not zero, the ring is dead */
293 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
294 I915_READ_START(ring
) == obj
->gtt_offset
&&
295 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
296 DRM_ERROR("%s initialization failed "
297 "ctl %08x head %08x tail %08x start %08x\n",
300 I915_READ_HEAD(ring
),
301 I915_READ_TAIL(ring
),
302 I915_READ_START(ring
));
306 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
307 i915_kernel_lost_context(ring
->dev
);
309 ring
->head
= I915_READ_HEAD(ring
);
310 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
311 ring
->space
= ring_space(ring
);
318 init_pipe_control(struct intel_ring_buffer
*ring
)
320 struct pipe_control
*pc
;
321 struct drm_i915_gem_object
*obj
;
327 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
331 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
333 DRM_ERROR("Failed to allocate seqno page\n");
338 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
340 ret
= i915_gem_object_pin(obj
, 4096, true);
344 pc
->gtt_offset
= obj
->gtt_offset
;
345 pc
->cpu_page
= kmap(obj
->pages
[0]);
346 if (pc
->cpu_page
== NULL
)
354 i915_gem_object_unpin(obj
);
356 drm_gem_object_unreference(&obj
->base
);
363 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
365 struct pipe_control
*pc
= ring
->private;
366 struct drm_i915_gem_object
*obj
;
372 kunmap(obj
->pages
[0]);
373 i915_gem_object_unpin(obj
);
374 drm_gem_object_unreference(&obj
->base
);
377 ring
->private = NULL
;
380 static int init_render_ring(struct intel_ring_buffer
*ring
)
382 struct drm_device
*dev
= ring
->dev
;
383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
384 int ret
= init_ring_common(ring
);
386 if (INTEL_INFO(dev
)->gen
> 3) {
387 int mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
388 I915_WRITE(MI_MODE
, mode
);
390 I915_WRITE(GFX_MODE_GEN7
,
391 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
392 GFX_MODE_ENABLE(GFX_REPLAY_MODE
));
395 if (INTEL_INFO(dev
)->gen
>= 5) {
396 ret
= init_pipe_control(ring
);
401 if (INTEL_INFO(dev
)->gen
>= 6) {
403 INSTPM_FORCE_ORDERING
<< 16 | INSTPM_FORCE_ORDERING
);
409 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
414 cleanup_pipe_control(ring
);
418 update_mboxes(struct intel_ring_buffer
*ring
,
422 intel_ring_emit(ring
, MI_SEMAPHORE_MBOX
|
423 MI_SEMAPHORE_GLOBAL_GTT
|
424 MI_SEMAPHORE_REGISTER
|
425 MI_SEMAPHORE_UPDATE
);
426 intel_ring_emit(ring
, seqno
);
427 intel_ring_emit(ring
, mmio_offset
);
431 * gen6_add_request - Update the semaphore mailbox registers
433 * @ring - ring that is adding a request
434 * @seqno - return seqno stuck into the ring
436 * Update the mailbox registers in the *other* rings with the current seqno.
437 * This acts like a signal in the canonical semaphore.
440 gen6_add_request(struct intel_ring_buffer
*ring
,
447 ret
= intel_ring_begin(ring
, 10);
451 mbox1_reg
= ring
->signal_mbox
[0];
452 mbox2_reg
= ring
->signal_mbox
[1];
454 *seqno
= i915_gem_next_request_seqno(ring
);
456 update_mboxes(ring
, *seqno
, mbox1_reg
);
457 update_mboxes(ring
, *seqno
, mbox2_reg
);
458 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
459 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
460 intel_ring_emit(ring
, *seqno
);
461 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
462 intel_ring_advance(ring
);
468 * intel_ring_sync - sync the waiter to the signaller on seqno
470 * @waiter - ring that is waiting
471 * @signaller - ring which has, or will signal
472 * @seqno - seqno which the waiter will block on
475 intel_ring_sync(struct intel_ring_buffer
*waiter
,
476 struct intel_ring_buffer
*signaller
,
481 u32 dw1
= MI_SEMAPHORE_MBOX
|
482 MI_SEMAPHORE_COMPARE
|
483 MI_SEMAPHORE_REGISTER
;
485 /* Throughout all of the GEM code, seqno passed implies our current
486 * seqno is >= the last seqno executed. However for hardware the
487 * comparison is strictly greater than.
491 ret
= intel_ring_begin(waiter
, 4);
495 intel_ring_emit(waiter
, dw1
| signaller
->semaphore_register
[ring
]);
496 intel_ring_emit(waiter
, seqno
);
497 intel_ring_emit(waiter
, 0);
498 intel_ring_emit(waiter
, MI_NOOP
);
499 intel_ring_advance(waiter
);
504 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
506 render_ring_sync_to(struct intel_ring_buffer
*waiter
,
507 struct intel_ring_buffer
*signaller
,
510 WARN_ON(signaller
->semaphore_register
[RCS
] == MI_SEMAPHORE_SYNC_INVALID
);
511 return intel_ring_sync(waiter
,
517 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
519 gen6_bsd_ring_sync_to(struct intel_ring_buffer
*waiter
,
520 struct intel_ring_buffer
*signaller
,
523 WARN_ON(signaller
->semaphore_register
[VCS
] == MI_SEMAPHORE_SYNC_INVALID
);
524 return intel_ring_sync(waiter
,
530 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
532 gen6_blt_ring_sync_to(struct intel_ring_buffer
*waiter
,
533 struct intel_ring_buffer
*signaller
,
536 WARN_ON(signaller
->semaphore_register
[BCS
] == MI_SEMAPHORE_SYNC_INVALID
);
537 return intel_ring_sync(waiter
,
545 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
547 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
548 PIPE_CONTROL_DEPTH_STALL); \
549 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
550 intel_ring_emit(ring__, 0); \
551 intel_ring_emit(ring__, 0); \
555 pc_render_add_request(struct intel_ring_buffer
*ring
,
558 u32 seqno
= i915_gem_next_request_seqno(ring
);
559 struct pipe_control
*pc
= ring
->private;
560 u32 scratch_addr
= pc
->gtt_offset
+ 128;
563 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
564 * incoherent with writes to memory, i.e. completely fubar,
565 * so we need to use PIPE_NOTIFY instead.
567 * However, we also need to workaround the qword write
568 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
569 * memory before requesting an interrupt.
571 ret
= intel_ring_begin(ring
, 32);
575 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
576 PIPE_CONTROL_WRITE_FLUSH
|
577 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
578 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
579 intel_ring_emit(ring
, seqno
);
580 intel_ring_emit(ring
, 0);
581 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
582 scratch_addr
+= 128; /* write to separate cachelines */
583 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
585 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
587 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
589 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
591 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
593 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
594 PIPE_CONTROL_WRITE_FLUSH
|
595 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
596 PIPE_CONTROL_NOTIFY
);
597 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
598 intel_ring_emit(ring
, seqno
);
599 intel_ring_emit(ring
, 0);
600 intel_ring_advance(ring
);
607 render_ring_add_request(struct intel_ring_buffer
*ring
,
610 u32 seqno
= i915_gem_next_request_seqno(ring
);
613 ret
= intel_ring_begin(ring
, 4);
617 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
618 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
619 intel_ring_emit(ring
, seqno
);
620 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
621 intel_ring_advance(ring
);
628 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
)
630 struct drm_device
*dev
= ring
->dev
;
632 /* Workaround to force correct ordering between irq and seqno writes on
633 * ivb (and maybe also on snb) by reading from a CS register (like
634 * ACTHD) before reading the status page. */
635 if (IS_GEN6(dev
) || IS_GEN7(dev
))
636 intel_ring_get_active_head(ring
);
637 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
641 ring_get_seqno(struct intel_ring_buffer
*ring
)
643 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
647 pc_render_get_seqno(struct intel_ring_buffer
*ring
)
649 struct pipe_control
*pc
= ring
->private;
650 return pc
->cpu_page
[0];
654 ironlake_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
656 dev_priv
->gt_irq_mask
&= ~mask
;
657 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
662 ironlake_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
664 dev_priv
->gt_irq_mask
|= mask
;
665 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
670 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
672 dev_priv
->irq_mask
&= ~mask
;
673 I915_WRITE(IMR
, dev_priv
->irq_mask
);
678 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
680 dev_priv
->irq_mask
|= mask
;
681 I915_WRITE(IMR
, dev_priv
->irq_mask
);
686 render_ring_get_irq(struct intel_ring_buffer
*ring
)
688 struct drm_device
*dev
= ring
->dev
;
689 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
691 if (!dev
->irq_enabled
)
694 spin_lock(&ring
->irq_lock
);
695 if (ring
->irq_refcount
++ == 0) {
696 if (INTEL_INFO(dev
)->gen
>= 5)
697 ironlake_enable_irq(dev_priv
,
698 GT_PIPE_NOTIFY
| GT_USER_INTERRUPT
);
700 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
702 spin_unlock(&ring
->irq_lock
);
708 render_ring_put_irq(struct intel_ring_buffer
*ring
)
710 struct drm_device
*dev
= ring
->dev
;
711 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
713 spin_lock(&ring
->irq_lock
);
714 if (--ring
->irq_refcount
== 0) {
715 if (INTEL_INFO(dev
)->gen
>= 5)
716 ironlake_disable_irq(dev_priv
,
720 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
722 spin_unlock(&ring
->irq_lock
);
725 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
727 struct drm_device
*dev
= ring
->dev
;
728 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
731 /* The ring status page addresses are no longer next to the rest of
732 * the ring registers as of gen7.
737 mmio
= RENDER_HWS_PGA_GEN7
;
740 mmio
= BLT_HWS_PGA_GEN7
;
743 mmio
= BSD_HWS_PGA_GEN7
;
746 } else if (IS_GEN6(ring
->dev
)) {
747 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
749 mmio
= RING_HWS_PGA(ring
->mmio_base
);
752 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
757 bsd_ring_flush(struct intel_ring_buffer
*ring
,
758 u32 invalidate_domains
,
763 ret
= intel_ring_begin(ring
, 2);
767 intel_ring_emit(ring
, MI_FLUSH
);
768 intel_ring_emit(ring
, MI_NOOP
);
769 intel_ring_advance(ring
);
774 ring_add_request(struct intel_ring_buffer
*ring
,
780 ret
= intel_ring_begin(ring
, 4);
784 seqno
= i915_gem_next_request_seqno(ring
);
786 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
787 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
788 intel_ring_emit(ring
, seqno
);
789 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
790 intel_ring_advance(ring
);
797 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
799 struct drm_device
*dev
= ring
->dev
;
800 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
802 if (!dev
->irq_enabled
)
805 /* It looks like we need to prevent the gt from suspending while waiting
806 * for an notifiy irq, otherwise irqs seem to get lost on at least the
807 * blt/bsd rings on ivb. */
808 gen6_gt_force_wake_get(dev_priv
);
810 spin_lock(&ring
->irq_lock
);
811 if (ring
->irq_refcount
++ == 0) {
812 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
813 ironlake_enable_irq(dev_priv
, ring
->irq_enable_mask
);
815 spin_unlock(&ring
->irq_lock
);
821 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
823 struct drm_device
*dev
= ring
->dev
;
824 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
826 spin_lock(&ring
->irq_lock
);
827 if (--ring
->irq_refcount
== 0) {
828 I915_WRITE_IMR(ring
, ~0);
829 ironlake_disable_irq(dev_priv
, ring
->irq_enable_mask
);
831 spin_unlock(&ring
->irq_lock
);
833 gen6_gt_force_wake_put(dev_priv
);
837 bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
839 struct drm_device
*dev
= ring
->dev
;
840 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
842 if (!dev
->irq_enabled
)
845 spin_lock(&ring
->irq_lock
);
846 if (ring
->irq_refcount
++ == 0) {
848 i915_enable_irq(dev_priv
, I915_BSD_USER_INTERRUPT
);
850 ironlake_enable_irq(dev_priv
, GT_BSD_USER_INTERRUPT
);
852 spin_unlock(&ring
->irq_lock
);
857 bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
859 struct drm_device
*dev
= ring
->dev
;
860 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
862 spin_lock(&ring
->irq_lock
);
863 if (--ring
->irq_refcount
== 0) {
865 i915_disable_irq(dev_priv
, I915_BSD_USER_INTERRUPT
);
867 ironlake_disable_irq(dev_priv
, GT_BSD_USER_INTERRUPT
);
869 spin_unlock(&ring
->irq_lock
);
873 ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
, u32 offset
, u32 length
)
877 ret
= intel_ring_begin(ring
, 2);
881 intel_ring_emit(ring
,
882 MI_BATCH_BUFFER_START
| (2 << 6) |
883 MI_BATCH_NON_SECURE_I965
);
884 intel_ring_emit(ring
, offset
);
885 intel_ring_advance(ring
);
891 render_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
894 struct drm_device
*dev
= ring
->dev
;
897 if (IS_I830(dev
) || IS_845G(dev
)) {
898 ret
= intel_ring_begin(ring
, 4);
902 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
903 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
904 intel_ring_emit(ring
, offset
+ len
- 8);
905 intel_ring_emit(ring
, 0);
907 ret
= intel_ring_begin(ring
, 2);
911 if (INTEL_INFO(dev
)->gen
>= 4) {
912 intel_ring_emit(ring
,
913 MI_BATCH_BUFFER_START
| (2 << 6) |
914 MI_BATCH_NON_SECURE_I965
);
915 intel_ring_emit(ring
, offset
);
917 intel_ring_emit(ring
,
918 MI_BATCH_BUFFER_START
| (2 << 6));
919 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
922 intel_ring_advance(ring
);
927 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
929 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
930 struct drm_i915_gem_object
*obj
;
932 obj
= ring
->status_page
.obj
;
936 kunmap(obj
->pages
[0]);
937 i915_gem_object_unpin(obj
);
938 drm_gem_object_unreference(&obj
->base
);
939 ring
->status_page
.obj
= NULL
;
941 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
944 static int init_status_page(struct intel_ring_buffer
*ring
)
946 struct drm_device
*dev
= ring
->dev
;
947 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
948 struct drm_i915_gem_object
*obj
;
951 obj
= i915_gem_alloc_object(dev
, 4096);
953 DRM_ERROR("Failed to allocate status page\n");
958 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
960 ret
= i915_gem_object_pin(obj
, 4096, true);
965 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
966 ring
->status_page
.page_addr
= kmap(obj
->pages
[0]);
967 if (ring
->status_page
.page_addr
== NULL
) {
968 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
971 ring
->status_page
.obj
= obj
;
972 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
974 intel_ring_setup_status_page(ring
);
975 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
976 ring
->name
, ring
->status_page
.gfx_addr
);
981 i915_gem_object_unpin(obj
);
983 drm_gem_object_unreference(&obj
->base
);
988 int intel_init_ring_buffer(struct drm_device
*dev
,
989 struct intel_ring_buffer
*ring
)
991 struct drm_i915_gem_object
*obj
;
995 INIT_LIST_HEAD(&ring
->active_list
);
996 INIT_LIST_HEAD(&ring
->request_list
);
997 INIT_LIST_HEAD(&ring
->gpu_write_list
);
998 ring
->size
= 32 * PAGE_SIZE
;
1000 init_waitqueue_head(&ring
->irq_queue
);
1001 spin_lock_init(&ring
->irq_lock
);
1003 if (I915_NEED_GFX_HWS(dev
)) {
1004 ret
= init_status_page(ring
);
1009 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1011 DRM_ERROR("Failed to allocate ringbuffer\n");
1018 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
1022 ring
->map
.size
= ring
->size
;
1023 ring
->map
.offset
= dev
->agp
->base
+ obj
->gtt_offset
;
1025 ring
->map
.flags
= 0;
1028 drm_core_ioremap_wc(&ring
->map
, dev
);
1029 if (ring
->map
.handle
== NULL
) {
1030 DRM_ERROR("Failed to map ringbuffer.\n");
1035 ring
->virtual_start
= ring
->map
.handle
;
1036 ret
= ring
->init(ring
);
1040 /* Workaround an erratum on the i830 which causes a hang if
1041 * the TAIL pointer points to within the last 2 cachelines
1044 ring
->effective_size
= ring
->size
;
1045 if (IS_I830(ring
->dev
))
1046 ring
->effective_size
-= 128;
1051 drm_core_ioremapfree(&ring
->map
, dev
);
1053 i915_gem_object_unpin(obj
);
1055 drm_gem_object_unreference(&obj
->base
);
1058 cleanup_status_page(ring
);
1062 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1064 struct drm_i915_private
*dev_priv
;
1067 if (ring
->obj
== NULL
)
1070 /* Disable the ring buffer. The ring must be idle at this point */
1071 dev_priv
= ring
->dev
->dev_private
;
1072 ret
= intel_wait_ring_idle(ring
);
1074 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1077 I915_WRITE_CTL(ring
, 0);
1079 drm_core_ioremapfree(&ring
->map
, ring
->dev
);
1081 i915_gem_object_unpin(ring
->obj
);
1082 drm_gem_object_unreference(&ring
->obj
->base
);
1086 ring
->cleanup(ring
);
1088 cleanup_status_page(ring
);
1091 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1094 int rem
= ring
->size
- ring
->tail
;
1096 if (ring
->space
< rem
) {
1097 int ret
= intel_wait_ring_buffer(ring
, rem
);
1102 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
1110 ring
->space
= ring_space(ring
);
1115 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1117 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1118 bool was_interruptible
;
1121 /* XXX As we have not yet audited all the paths to check that
1122 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1123 * allow us to be interruptible by a signal.
1125 was_interruptible
= dev_priv
->mm
.interruptible
;
1126 dev_priv
->mm
.interruptible
= false;
1128 ret
= i915_wait_request(ring
, seqno
, true);
1130 dev_priv
->mm
.interruptible
= was_interruptible
;
1135 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1137 struct drm_i915_gem_request
*request
;
1141 i915_gem_retire_requests_ring(ring
);
1143 if (ring
->last_retired_head
!= -1) {
1144 ring
->head
= ring
->last_retired_head
;
1145 ring
->last_retired_head
= -1;
1146 ring
->space
= ring_space(ring
);
1147 if (ring
->space
>= n
)
1151 list_for_each_entry(request
, &ring
->request_list
, list
) {
1154 if (request
->tail
== -1)
1157 space
= request
->tail
- (ring
->tail
+ 8);
1159 space
+= ring
->size
;
1161 seqno
= request
->seqno
;
1165 /* Consume this request in case we need more space than
1166 * is available and so need to prevent a race between
1167 * updating last_retired_head and direct reads of
1168 * I915_RING_HEAD. It also provides a nice sanity check.
1176 ret
= intel_ring_wait_seqno(ring
, seqno
);
1180 if (WARN_ON(ring
->last_retired_head
== -1))
1183 ring
->head
= ring
->last_retired_head
;
1184 ring
->last_retired_head
= -1;
1185 ring
->space
= ring_space(ring
);
1186 if (WARN_ON(ring
->space
< n
))
1192 int intel_wait_ring_buffer(struct intel_ring_buffer
*ring
, int n
)
1194 struct drm_device
*dev
= ring
->dev
;
1195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1199 ret
= intel_ring_wait_request(ring
, n
);
1203 trace_i915_ring_wait_begin(ring
);
1204 if (drm_core_check_feature(dev
, DRIVER_GEM
))
1205 /* With GEM the hangcheck timer should kick us out of the loop,
1206 * leaving it early runs the risk of corrupting GEM state (due
1207 * to running on almost untested codepaths). But on resume
1208 * timers don't work yet, so prevent a complete hang in that
1209 * case by choosing an insanely large timeout. */
1210 end
= jiffies
+ 60 * HZ
;
1212 end
= jiffies
+ 3 * HZ
;
1215 ring
->head
= I915_READ_HEAD(ring
);
1216 ring
->space
= ring_space(ring
);
1217 if (ring
->space
>= n
) {
1218 trace_i915_ring_wait_end(ring
);
1222 if (dev
->primary
->master
) {
1223 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1224 if (master_priv
->sarea_priv
)
1225 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1229 if (atomic_read(&dev_priv
->mm
.wedged
))
1231 } while (!time_after(jiffies
, end
));
1232 trace_i915_ring_wait_end(ring
);
1236 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1239 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1240 int n
= 4*num_dwords
;
1243 if (unlikely(atomic_read(&dev_priv
->mm
.wedged
)))
1246 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1247 ret
= intel_wrap_ring_buffer(ring
);
1252 if (unlikely(ring
->space
< n
)) {
1253 ret
= intel_wait_ring_buffer(ring
, n
);
1262 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1264 ring
->tail
&= ring
->size
- 1;
1265 ring
->write_tail(ring
, ring
->tail
);
1269 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1272 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1274 /* Every tail move must follow the sequence below */
1275 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1276 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1277 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE
);
1278 I915_WRITE(GEN6_BSD_RNCID
, 0x0);
1280 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1281 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR
) == 0,
1283 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1285 I915_WRITE_TAIL(ring
, value
);
1286 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1287 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1288 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE
);
1291 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1292 u32 invalidate
, u32 flush
)
1297 ret
= intel_ring_begin(ring
, 4);
1302 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1303 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
1304 intel_ring_emit(ring
, cmd
);
1305 intel_ring_emit(ring
, 0);
1306 intel_ring_emit(ring
, 0);
1307 intel_ring_emit(ring
, MI_NOOP
);
1308 intel_ring_advance(ring
);
1313 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1314 u32 offset
, u32 len
)
1318 ret
= intel_ring_begin(ring
, 2);
1322 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
);
1323 /* bit0-7 is the length on GEN6+ */
1324 intel_ring_emit(ring
, offset
);
1325 intel_ring_advance(ring
);
1330 /* Blitter support (SandyBridge+) */
1332 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1333 u32 invalidate
, u32 flush
)
1338 ret
= intel_ring_begin(ring
, 4);
1343 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1344 cmd
|= MI_INVALIDATE_TLB
;
1345 intel_ring_emit(ring
, cmd
);
1346 intel_ring_emit(ring
, 0);
1347 intel_ring_emit(ring
, 0);
1348 intel_ring_emit(ring
, MI_NOOP
);
1349 intel_ring_advance(ring
);
1353 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1356 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1358 ring
->name
= "render ring";
1360 ring
->mmio_base
= RENDER_RING_BASE
;
1362 if (INTEL_INFO(dev
)->gen
>= 6) {
1363 ring
->add_request
= gen6_add_request
;
1364 ring
->flush
= gen6_render_ring_flush
;
1365 ring
->irq_get
= gen6_ring_get_irq
;
1366 ring
->irq_put
= gen6_ring_put_irq
;
1367 ring
->irq_enable_mask
= GT_USER_INTERRUPT
;
1368 ring
->get_seqno
= gen6_ring_get_seqno
;
1369 ring
->sync_to
= render_ring_sync_to
;
1370 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_INVALID
;
1371 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_RV
;
1372 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_RB
;
1373 ring
->signal_mbox
[0] = GEN6_VRSYNC
;
1374 ring
->signal_mbox
[1] = GEN6_BRSYNC
;
1375 } else if (IS_GEN5(dev
)) {
1376 ring
->add_request
= pc_render_add_request
;
1377 ring
->flush
= render_ring_flush
;
1378 ring
->get_seqno
= pc_render_get_seqno
;
1379 ring
->irq_get
= render_ring_get_irq
;
1380 ring
->irq_put
= render_ring_put_irq
;
1382 ring
->add_request
= render_ring_add_request
;
1383 ring
->flush
= render_ring_flush
;
1384 ring
->get_seqno
= ring_get_seqno
;
1385 ring
->irq_get
= render_ring_get_irq
;
1386 ring
->irq_put
= render_ring_put_irq
;
1388 ring
->write_tail
= ring_write_tail
;
1389 ring
->dispatch_execbuffer
= render_ring_dispatch_execbuffer
;
1390 ring
->init
= init_render_ring
;
1391 ring
->cleanup
= render_ring_cleanup
;
1394 if (!I915_NEED_GFX_HWS(dev
)) {
1395 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1396 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1399 return intel_init_ring_buffer(dev
, ring
);
1402 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1404 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1405 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1407 ring
->name
= "render ring";
1409 ring
->mmio_base
= RENDER_RING_BASE
;
1411 if (INTEL_INFO(dev
)->gen
>= 6) {
1412 /* non-kms not supported on gen6+ */
1414 } else if (IS_GEN5(dev
)) {
1415 ring
->add_request
= pc_render_add_request
;
1416 ring
->flush
= render_ring_flush
;
1417 ring
->get_seqno
= pc_render_get_seqno
;
1418 ring
->irq_get
= render_ring_get_irq
;
1419 ring
->irq_put
= render_ring_put_irq
;
1421 ring
->add_request
= render_ring_add_request
;
1422 ring
->flush
= render_ring_flush
;
1423 ring
->get_seqno
= ring_get_seqno
;
1424 ring
->irq_get
= render_ring_get_irq
;
1425 ring
->irq_put
= render_ring_put_irq
;
1427 ring
->write_tail
= ring_write_tail
;
1428 ring
->dispatch_execbuffer
= render_ring_dispatch_execbuffer
;
1429 ring
->init
= init_render_ring
;
1430 ring
->cleanup
= render_ring_cleanup
;
1432 if (!I915_NEED_GFX_HWS(dev
))
1433 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1436 INIT_LIST_HEAD(&ring
->active_list
);
1437 INIT_LIST_HEAD(&ring
->request_list
);
1438 INIT_LIST_HEAD(&ring
->gpu_write_list
);
1441 ring
->effective_size
= ring
->size
;
1442 if (IS_I830(ring
->dev
))
1443 ring
->effective_size
-= 128;
1445 ring
->map
.offset
= start
;
1446 ring
->map
.size
= size
;
1448 ring
->map
.flags
= 0;
1451 drm_core_ioremap_wc(&ring
->map
, dev
);
1452 if (ring
->map
.handle
== NULL
) {
1453 DRM_ERROR("can not ioremap virtual address for"
1458 ring
->virtual_start
= (void __force __iomem
*)ring
->map
.handle
;
1462 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1464 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1465 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1467 ring
->name
= "bsd ring";
1470 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1471 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1472 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1473 ring
->flush
= gen6_ring_flush
;
1474 ring
->add_request
= gen6_add_request
;
1475 ring
->get_seqno
= gen6_ring_get_seqno
;
1476 ring
->irq_enable_mask
= GEN6_BSD_USER_INTERRUPT
;
1477 ring
->irq_get
= gen6_ring_get_irq
;
1478 ring
->irq_put
= gen6_ring_put_irq
;
1479 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1480 ring
->sync_to
= gen6_bsd_ring_sync_to
;
1481 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_VR
;
1482 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_INVALID
;
1483 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_VB
;
1484 ring
->signal_mbox
[0] = GEN6_RVSYNC
;
1485 ring
->signal_mbox
[1] = GEN6_BVSYNC
;
1487 ring
->mmio_base
= BSD_RING_BASE
;
1488 ring
->write_tail
= ring_write_tail
;
1489 ring
->flush
= bsd_ring_flush
;
1490 ring
->add_request
= ring_add_request
;
1491 ring
->get_seqno
= ring_get_seqno
;
1492 ring
->irq_get
= bsd_ring_get_irq
;
1493 ring
->irq_put
= bsd_ring_put_irq
;
1494 ring
->dispatch_execbuffer
= ring_dispatch_execbuffer
;
1496 ring
->init
= init_ring_common
;
1499 return intel_init_ring_buffer(dev
, ring
);
1502 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1504 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1505 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1507 ring
->name
= "blitter ring";
1510 ring
->mmio_base
= BLT_RING_BASE
;
1511 ring
->write_tail
= ring_write_tail
;
1512 ring
->flush
= blt_ring_flush
;
1513 ring
->add_request
= gen6_add_request
;
1514 ring
->get_seqno
= gen6_ring_get_seqno
;
1515 ring
->irq_enable_mask
= GEN6_BLITTER_USER_INTERRUPT
;
1516 ring
->irq_get
= gen6_ring_get_irq
;
1517 ring
->irq_put
= gen6_ring_put_irq
;
1518 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1519 ring
->sync_to
= gen6_blt_ring_sync_to
;
1520 ring
->semaphore_register
[0] = MI_SEMAPHORE_SYNC_BR
;
1521 ring
->semaphore_register
[1] = MI_SEMAPHORE_SYNC_BV
;
1522 ring
->semaphore_register
[2] = MI_SEMAPHORE_SYNC_INVALID
;
1523 ring
->signal_mbox
[0] = GEN6_RBSYNC
;
1524 ring
->signal_mbox
[1] = GEN6_VBSYNC
;
1525 ring
->init
= init_ring_common
;
1527 return intel_init_ring_buffer(dev
, ring
);