projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Introduce ring set_seqno
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 /*
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
39 */
40 struct pipe_control {
41 struct drm_i915_gem_object *obj;
42 volatile u32 *cpu_page;
43 u32 gtt_offset;
44 };
45
46 static inline int ring_space(struct intel_ring_buffer *ring)
47 {
48 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
49 if (space < 0)
50 space += ring->size;
51 return space;
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 struct pipe_control *pc = ring->private;
179 u32 scratch_addr = pc->gtt_offset + 128;
180 int ret;
181
182
183 ret = intel_ring_begin(ring, 6);
184 if (ret)
185 return ret;
186
187 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
189 PIPE_CONTROL_STALL_AT_SCOREBOARD);
190 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
191 intel_ring_emit(ring, 0); /* low dword */
192 intel_ring_emit(ring, 0); /* high dword */
193 intel_ring_emit(ring, MI_NOOP);
194 intel_ring_advance(ring);
195
196 ret = intel_ring_begin(ring, 6);
197 if (ret)
198 return ret;
199
200 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
202 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, MI_NOOP);
206 intel_ring_advance(ring);
207
208 return 0;
209 }
210
211 static int
212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
213 u32 invalidate_domains, u32 flush_domains)
214 {
215 u32 flags = 0;
216 struct pipe_control *pc = ring->private;
217 u32 scratch_addr = pc->gtt_offset + 128;
218 int ret;
219
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret = intel_emit_post_sync_nonzero_flush(ring);
222 if (ret)
223 return ret;
224
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
227 * impact.
228 */
229 if (flush_domains) {
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 /*
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
235 */
236 flags |= PIPE_CONTROL_CS_STALL;
237 }
238 if (invalidate_domains) {
239 flags |= PIPE_CONTROL_TLB_INVALIDATE;
240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
245 /*
246 * TLB invalidate requires a post-sync write.
247 */
248 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
249 }
250
251 ret = intel_ring_begin(ring, 4);
252 if (ret)
253 return ret;
254
255 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring, flags);
257 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
258 intel_ring_emit(ring, 0);
259 intel_ring_advance(ring);
260
261 return 0;
262 }
263
264 static int
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
266 {
267 int ret;
268
269 ret = intel_ring_begin(ring, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
275 PIPE_CONTROL_STALL_AT_SCOREBOARD);
276 intel_ring_emit(ring, 0);
277 intel_ring_emit(ring, 0);
278 intel_ring_advance(ring);
279
280 return 0;
281 }
282
283 static int
284 gen7_render_ring_flush(struct intel_ring_buffer *ring,
285 u32 invalidate_domains, u32 flush_domains)
286 {
287 u32 flags = 0;
288 struct pipe_control *pc = ring->private;
289 u32 scratch_addr = pc->gtt_offset + 128;
290 int ret;
291
292 /*
293 * Ensure that any following seqno writes only happen when the render
294 * cache is indeed flushed.
295 *
296 * Workaround: 4th PIPE_CONTROL command (except the ones with only
297 * read-cache invalidate bits set) must have the CS_STALL bit set. We
298 * don't try to be clever and just set it unconditionally.
299 */
300 flags |= PIPE_CONTROL_CS_STALL;
301
302 /* Just flush everything. Experiments have shown that reducing the
303 * number of bits based on the write domains has little performance
304 * impact.
305 */
306 if (flush_domains) {
307 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
308 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
309 }
310 if (invalidate_domains) {
311 flags |= PIPE_CONTROL_TLB_INVALIDATE;
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
317 /*
318 * TLB invalidate requires a post-sync write.
319 */
320 flags |= PIPE_CONTROL_QW_WRITE;
321
322 /* Workaround: we must issue a pipe_control with CS-stall bit
323 * set before a pipe_control command that has the state cache
324 * invalidate bit set. */
325 gen7_render_ring_cs_stall_wa(ring);
326 }
327
328 ret = intel_ring_begin(ring, 4);
329 if (ret)
330 return ret;
331
332 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
333 intel_ring_emit(ring, flags);
334 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
335 intel_ring_emit(ring, 0);
336 intel_ring_advance(ring);
337
338 return 0;
339 }
340
341 static void ring_write_tail(struct intel_ring_buffer *ring,
342 u32 value)
343 {
344 drm_i915_private_t *dev_priv = ring->dev->dev_private;
345 I915_WRITE_TAIL(ring, value);
346 }
347
348 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
349 {
350 drm_i915_private_t *dev_priv = ring->dev->dev_private;
351 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
352 RING_ACTHD(ring->mmio_base) : ACTHD;
353
354 return I915_READ(acthd_reg);
355 }
356
357 static int init_ring_common(struct intel_ring_buffer *ring)
358 {
359 struct drm_device *dev = ring->dev;
360 drm_i915_private_t *dev_priv = dev->dev_private;
361 struct drm_i915_gem_object *obj = ring->obj;
362 int ret = 0;
363 u32 head;
364
365 if (HAS_FORCE_WAKE(dev))
366 gen6_gt_force_wake_get(dev_priv);
367
368 /* Stop the ring if it's running. */
369 I915_WRITE_CTL(ring, 0);
370 I915_WRITE_HEAD(ring, 0);
371 ring->write_tail(ring, 0);
372
373 head = I915_READ_HEAD(ring) & HEAD_ADDR;
374
375 /* G45 ring initialization fails to reset head to zero */
376 if (head != 0) {
377 DRM_DEBUG_KMS("%s head not reset to zero "
378 "ctl %08x head %08x tail %08x start %08x\n",
379 ring->name,
380 I915_READ_CTL(ring),
381 I915_READ_HEAD(ring),
382 I915_READ_TAIL(ring),
383 I915_READ_START(ring));
384
385 I915_WRITE_HEAD(ring, 0);
386
387 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
388 DRM_ERROR("failed to set %s head to zero "
389 "ctl %08x head %08x tail %08x start %08x\n",
390 ring->name,
391 I915_READ_CTL(ring),
392 I915_READ_HEAD(ring),
393 I915_READ_TAIL(ring),
394 I915_READ_START(ring));
395 }
396 }
397
398 /* Initialize the ring. This must happen _after_ we've cleared the ring
399 * registers with the above sequence (the readback of the HEAD registers
400 * also enforces ordering), otherwise the hw might lose the new ring
401 * register values. */
402 I915_WRITE_START(ring, obj->gtt_offset);
403 I915_WRITE_CTL(ring,
404 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
405 | RING_VALID);
406
407 /* If the head is still not zero, the ring is dead */
408 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
409 I915_READ_START(ring) == obj->gtt_offset &&
410 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
411 DRM_ERROR("%s initialization failed "
412 "ctl %08x head %08x tail %08x start %08x\n",
413 ring->name,
414 I915_READ_CTL(ring),
415 I915_READ_HEAD(ring),
416 I915_READ_TAIL(ring),
417 I915_READ_START(ring));
418 ret = -EIO;
419 goto out;
420 }
421
422 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
423 i915_kernel_lost_context(ring->dev);
424 else {
425 ring->head = I915_READ_HEAD(ring);
426 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
427 ring->space = ring_space(ring);
428 ring->last_retired_head = -1;
429 }
430
431 out:
432 if (HAS_FORCE_WAKE(dev))
433 gen6_gt_force_wake_put(dev_priv);
434
435 return ret;
436 }
437
438 static int
439 init_pipe_control(struct intel_ring_buffer *ring)
440 {
441 struct pipe_control *pc;
442 struct drm_i915_gem_object *obj;
443 int ret;
444
445 if (ring->private)
446 return 0;
447
448 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
449 if (!pc)
450 return -ENOMEM;
451
452 obj = i915_gem_alloc_object(ring->dev, 4096);
453 if (obj == NULL) {
454 DRM_ERROR("Failed to allocate seqno page\n");
455 ret = -ENOMEM;
456 goto err;
457 }
458
459 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
460
461 ret = i915_gem_object_pin(obj, 4096, true, false);
462 if (ret)
463 goto err_unref;
464
465 pc->gtt_offset = obj->gtt_offset;
466 pc->cpu_page = kmap(sg_page(obj->pages->sgl));
467 if (pc->cpu_page == NULL)
468 goto err_unpin;
469
470 pc->obj = obj;
471 ring->private = pc;
472 return 0;
473
474 err_unpin:
475 i915_gem_object_unpin(obj);
476 err_unref:
477 drm_gem_object_unreference(&obj->base);
478 err:
479 kfree(pc);
480 return ret;
481 }
482
483 static void
484 cleanup_pipe_control(struct intel_ring_buffer *ring)
485 {
486 struct pipe_control *pc = ring->private;
487 struct drm_i915_gem_object *obj;
488
489 if (!ring->private)
490 return;
491
492 obj = pc->obj;
493
494 kunmap(sg_page(obj->pages->sgl));
495 i915_gem_object_unpin(obj);
496 drm_gem_object_unreference(&obj->base);
497
498 kfree(pc);
499 ring->private = NULL;
500 }
501
502 static int init_render_ring(struct intel_ring_buffer *ring)
503 {
504 struct drm_device *dev = ring->dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
506 int ret = init_ring_common(ring);
507
508 if (INTEL_INFO(dev)->gen > 3) {
509 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
510 if (IS_GEN7(dev))
511 I915_WRITE(GFX_MODE_GEN7,
512 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
513 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
514 }
515
516 if (INTEL_INFO(dev)->gen >= 5) {
517 ret = init_pipe_control(ring);
518 if (ret)
519 return ret;
520 }
521
522 if (IS_GEN6(dev)) {
523 /* From the Sandybridge PRM, volume 1 part 3, page 24:
524 * "If this bit is set, STCunit will have LRA as replacement
525 * policy. [...] This bit must be reset. LRA replacement
526 * policy is not supported."
527 */
528 I915_WRITE(CACHE_MODE_0,
529 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
530
531 /* This is not explicitly set for GEN6, so read the register.
532 * see intel_ring_mi_set_context() for why we care.
533 * TODO: consider explicitly setting the bit for GEN5
534 */
535 ring->itlb_before_ctx_switch =
536 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
537 }
538
539 if (INTEL_INFO(dev)->gen >= 6)
540 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
541
542 if (HAS_L3_GPU_CACHE(dev))
543 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
544
545 return ret;
546 }
547
548 static void render_ring_cleanup(struct intel_ring_buffer *ring)
549 {
550 if (!ring->private)
551 return;
552
553 cleanup_pipe_control(ring);
554 }
555
556 static void
557 update_mboxes(struct intel_ring_buffer *ring,
558 u32 mmio_offset)
559 {
560 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
561 intel_ring_emit(ring, mmio_offset);
562 intel_ring_emit(ring, ring->outstanding_lazy_request);
563 }
564
565 /**
566 * gen6_add_request - Update the semaphore mailbox registers
567 *
568 * @ring - ring that is adding a request
569 * @seqno - return seqno stuck into the ring
570 *
571 * Update the mailbox registers in the *other* rings with the current seqno.
572 * This acts like a signal in the canonical semaphore.
573 */
574 static int
575 gen6_add_request(struct intel_ring_buffer *ring)
576 {
577 u32 mbox1_reg;
578 u32 mbox2_reg;
579 int ret;
580
581 ret = intel_ring_begin(ring, 10);
582 if (ret)
583 return ret;
584
585 mbox1_reg = ring->signal_mbox[0];
586 mbox2_reg = ring->signal_mbox[1];
587
588 update_mboxes(ring, mbox1_reg);
589 update_mboxes(ring, mbox2_reg);
590 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
591 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
592 intel_ring_emit(ring, ring->outstanding_lazy_request);
593 intel_ring_emit(ring, MI_USER_INTERRUPT);
594 intel_ring_advance(ring);
595
596 return 0;
597 }
598
599 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
600 u32 seqno)
601 {
602 struct drm_i915_private *dev_priv = dev->dev_private;
603 return dev_priv->last_seqno < seqno;
604 }
605
606 /**
607 * intel_ring_sync - sync the waiter to the signaller on seqno
608 *
609 * @waiter - ring that is waiting
610 * @signaller - ring which has, or will signal
611 * @seqno - seqno which the waiter will block on
612 */
613 static int
614 gen6_ring_sync(struct intel_ring_buffer *waiter,
615 struct intel_ring_buffer *signaller,
616 u32 seqno)
617 {
618 int ret;
619 u32 dw1 = MI_SEMAPHORE_MBOX |
620 MI_SEMAPHORE_COMPARE |
621 MI_SEMAPHORE_REGISTER;
622
623 /* Throughout all of the GEM code, seqno passed implies our current
624 * seqno is >= the last seqno executed. However for hardware the
625 * comparison is strictly greater than.
626 */
627 seqno -= 1;
628
629 WARN_ON(signaller->semaphore_register[waiter->id] ==
630 MI_SEMAPHORE_SYNC_INVALID);
631
632 ret = intel_ring_begin(waiter, 4);
633 if (ret)
634 return ret;
635
636 /* If seqno wrap happened, omit the wait with no-ops */
637 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
638 intel_ring_emit(waiter,
639 dw1 |
640 signaller->semaphore_register[waiter->id]);
641 intel_ring_emit(waiter, seqno);
642 intel_ring_emit(waiter, 0);
643 intel_ring_emit(waiter, MI_NOOP);
644 } else {
645 intel_ring_emit(waiter, MI_NOOP);
646 intel_ring_emit(waiter, MI_NOOP);
647 intel_ring_emit(waiter, MI_NOOP);
648 intel_ring_emit(waiter, MI_NOOP);
649 }
650 intel_ring_advance(waiter);
651
652 return 0;
653 }
654
655 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
656 do { \
657 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
658 PIPE_CONTROL_DEPTH_STALL); \
659 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
660 intel_ring_emit(ring__, 0); \
661 intel_ring_emit(ring__, 0); \
662 } while (0)
663
664 static int
665 pc_render_add_request(struct intel_ring_buffer *ring)
666 {
667 struct pipe_control *pc = ring->private;
668 u32 scratch_addr = pc->gtt_offset + 128;
669 int ret;
670
671 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
672 * incoherent with writes to memory, i.e. completely fubar,
673 * so we need to use PIPE_NOTIFY instead.
674 *
675 * However, we also need to workaround the qword write
676 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
677 * memory before requesting an interrupt.
678 */
679 ret = intel_ring_begin(ring, 32);
680 if (ret)
681 return ret;
682
683 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
684 PIPE_CONTROL_WRITE_FLUSH |
685 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
686 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
687 intel_ring_emit(ring, ring->outstanding_lazy_request);
688 intel_ring_emit(ring, 0);
689 PIPE_CONTROL_FLUSH(ring, scratch_addr);
690 scratch_addr += 128; /* write to separate cachelines */
691 PIPE_CONTROL_FLUSH(ring, scratch_addr);
692 scratch_addr += 128;
693 PIPE_CONTROL_FLUSH(ring, scratch_addr);
694 scratch_addr += 128;
695 PIPE_CONTROL_FLUSH(ring, scratch_addr);
696 scratch_addr += 128;
697 PIPE_CONTROL_FLUSH(ring, scratch_addr);
698 scratch_addr += 128;
699 PIPE_CONTROL_FLUSH(ring, scratch_addr);
700
701 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
702 PIPE_CONTROL_WRITE_FLUSH |
703 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
704 PIPE_CONTROL_NOTIFY);
705 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
706 intel_ring_emit(ring, ring->outstanding_lazy_request);
707 intel_ring_emit(ring, 0);
708 intel_ring_advance(ring);
709
710 return 0;
711 }
712
713 static u32
714 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
715 {
716 /* Workaround to force correct ordering between irq and seqno writes on
717 * ivb (and maybe also on snb) by reading from a CS register (like
718 * ACTHD) before reading the status page. */
719 if (!lazy_coherency)
720 intel_ring_get_active_head(ring);
721 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
722 }
723
724 static u32
725 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
726 {
727 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
728 }
729
730 static void
731 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
732 {
733 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
734 }
735
736 static u32
737 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
738 {
739 struct pipe_control *pc = ring->private;
740 return pc->cpu_page[0];
741 }
742
743 static void
744 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
745 {
746 struct pipe_control *pc = ring->private;
747 pc->cpu_page[0] = seqno;
748 }
749
750 static bool
751 gen5_ring_get_irq(struct intel_ring_buffer *ring)
752 {
753 struct drm_device *dev = ring->dev;
754 drm_i915_private_t *dev_priv = dev->dev_private;
755 unsigned long flags;
756
757 if (!dev->irq_enabled)
758 return false;
759
760 spin_lock_irqsave(&dev_priv->irq_lock, flags);
761 if (ring->irq_refcount++ == 0) {
762 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
763 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
764 POSTING_READ(GTIMR);
765 }
766 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
767
768 return true;
769 }
770
771 static void
772 gen5_ring_put_irq(struct intel_ring_buffer *ring)
773 {
774 struct drm_device *dev = ring->dev;
775 drm_i915_private_t *dev_priv = dev->dev_private;
776 unsigned long flags;
777
778 spin_lock_irqsave(&dev_priv->irq_lock, flags);
779 if (--ring->irq_refcount == 0) {
780 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
781 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
782 POSTING_READ(GTIMR);
783 }
784 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
785 }
786
787 static bool
788 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
789 {
790 struct drm_device *dev = ring->dev;
791 drm_i915_private_t *dev_priv = dev->dev_private;
792 unsigned long flags;
793
794 if (!dev->irq_enabled)
795 return false;
796
797 spin_lock_irqsave(&dev_priv->irq_lock, flags);
798 if (ring->irq_refcount++ == 0) {
799 dev_priv->irq_mask &= ~ring->irq_enable_mask;
800 I915_WRITE(IMR, dev_priv->irq_mask);
801 POSTING_READ(IMR);
802 }
803 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
804
805 return true;
806 }
807
808 static void
809 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
810 {
811 struct drm_device *dev = ring->dev;
812 drm_i915_private_t *dev_priv = dev->dev_private;
813 unsigned long flags;
814
815 spin_lock_irqsave(&dev_priv->irq_lock, flags);
816 if (--ring->irq_refcount == 0) {
817 dev_priv->irq_mask |= ring->irq_enable_mask;
818 I915_WRITE(IMR, dev_priv->irq_mask);
819 POSTING_READ(IMR);
820 }
821 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
822 }
823
824 static bool
825 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
826 {
827 struct drm_device *dev = ring->dev;
828 drm_i915_private_t *dev_priv = dev->dev_private;
829 unsigned long flags;
830
831 if (!dev->irq_enabled)
832 return false;
833
834 spin_lock_irqsave(&dev_priv->irq_lock, flags);
835 if (ring->irq_refcount++ == 0) {
836 dev_priv->irq_mask &= ~ring->irq_enable_mask;
837 I915_WRITE16(IMR, dev_priv->irq_mask);
838 POSTING_READ16(IMR);
839 }
840 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
841
842 return true;
843 }
844
845 static void
846 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
847 {
848 struct drm_device *dev = ring->dev;
849 drm_i915_private_t *dev_priv = dev->dev_private;
850 unsigned long flags;
851
852 spin_lock_irqsave(&dev_priv->irq_lock, flags);
853 if (--ring->irq_refcount == 0) {
854 dev_priv->irq_mask |= ring->irq_enable_mask;
855 I915_WRITE16(IMR, dev_priv->irq_mask);
856 POSTING_READ16(IMR);
857 }
858 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
859 }
860
861 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
862 {
863 struct drm_device *dev = ring->dev;
864 drm_i915_private_t *dev_priv = ring->dev->dev_private;
865 u32 mmio = 0;
866
867 /* The ring status page addresses are no longer next to the rest of
868 * the ring registers as of gen7.
869 */
870 if (IS_GEN7(dev)) {
871 switch (ring->id) {
872 case RCS:
873 mmio = RENDER_HWS_PGA_GEN7;
874 break;
875 case BCS:
876 mmio = BLT_HWS_PGA_GEN7;
877 break;
878 case VCS:
879 mmio = BSD_HWS_PGA_GEN7;
880 break;
881 }
882 } else if (IS_GEN6(ring->dev)) {
883 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
884 } else {
885 mmio = RING_HWS_PGA(ring->mmio_base);
886 }
887
888 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
889 POSTING_READ(mmio);
890 }
891
892 static int
893 bsd_ring_flush(struct intel_ring_buffer *ring,
894 u32 invalidate_domains,
895 u32 flush_domains)
896 {
897 int ret;
898
899 ret = intel_ring_begin(ring, 2);
900 if (ret)
901 return ret;
902
903 intel_ring_emit(ring, MI_FLUSH);
904 intel_ring_emit(ring, MI_NOOP);
905 intel_ring_advance(ring);
906 return 0;
907 }
908
909 static int
910 i9xx_add_request(struct intel_ring_buffer *ring)
911 {
912 int ret;
913
914 ret = intel_ring_begin(ring, 4);
915 if (ret)
916 return ret;
917
918 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
919 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
920 intel_ring_emit(ring, ring->outstanding_lazy_request);
921 intel_ring_emit(ring, MI_USER_INTERRUPT);
922 intel_ring_advance(ring);
923
924 return 0;
925 }
926
927 static bool
928 gen6_ring_get_irq(struct intel_ring_buffer *ring)
929 {
930 struct drm_device *dev = ring->dev;
931 drm_i915_private_t *dev_priv = dev->dev_private;
932 unsigned long flags;
933
934 if (!dev->irq_enabled)
935 return false;
936
937 /* It looks like we need to prevent the gt from suspending while waiting
938 * for an notifiy irq, otherwise irqs seem to get lost on at least the
939 * blt/bsd rings on ivb. */
940 gen6_gt_force_wake_get(dev_priv);
941
942 spin_lock_irqsave(&dev_priv->irq_lock, flags);
943 if (ring->irq_refcount++ == 0) {
944 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
945 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
946 GEN6_RENDER_L3_PARITY_ERROR));
947 else
948 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
949 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
950 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
951 POSTING_READ(GTIMR);
952 }
953 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
954
955 return true;
956 }
957
958 static void
959 gen6_ring_put_irq(struct intel_ring_buffer *ring)
960 {
961 struct drm_device *dev = ring->dev;
962 drm_i915_private_t *dev_priv = dev->dev_private;
963 unsigned long flags;
964
965 spin_lock_irqsave(&dev_priv->irq_lock, flags);
966 if (--ring->irq_refcount == 0) {
967 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
968 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
969 else
970 I915_WRITE_IMR(ring, ~0);
971 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
972 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
973 POSTING_READ(GTIMR);
974 }
975 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
976
977 gen6_gt_force_wake_put(dev_priv);
978 }
979
980 static int
981 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
982 u32 offset, u32 length,
983 unsigned flags)
984 {
985 int ret;
986
987 ret = intel_ring_begin(ring, 2);
988 if (ret)
989 return ret;
990
991 intel_ring_emit(ring,
992 MI_BATCH_BUFFER_START |
993 MI_BATCH_GTT |
994 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
995 intel_ring_emit(ring, offset);
996 intel_ring_advance(ring);
997
998 return 0;
999 }
1000
1001 static int
1002 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1003 u32 offset, u32 len,
1004 unsigned flags)
1005 {
1006 int ret;
1007
1008 ret = intel_ring_begin(ring, 4);
1009 if (ret)
1010 return ret;
1011
1012 intel_ring_emit(ring, MI_BATCH_BUFFER);
1013 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1014 intel_ring_emit(ring, offset + len - 8);
1015 intel_ring_emit(ring, 0);
1016 intel_ring_advance(ring);
1017
1018 return 0;
1019 }
1020
1021 static int
1022 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1023 u32 offset, u32 len,
1024 unsigned flags)
1025 {
1026 int ret;
1027
1028 ret = intel_ring_begin(ring, 2);
1029 if (ret)
1030 return ret;
1031
1032 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1033 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1034 intel_ring_advance(ring);
1035
1036 return 0;
1037 }
1038
1039 static void cleanup_status_page(struct intel_ring_buffer *ring)
1040 {
1041 struct drm_i915_gem_object *obj;
1042
1043 obj = ring->status_page.obj;
1044 if (obj == NULL)
1045 return;
1046
1047 kunmap(sg_page(obj->pages->sgl));
1048 i915_gem_object_unpin(obj);
1049 drm_gem_object_unreference(&obj->base);
1050 ring->status_page.obj = NULL;
1051 }
1052
1053 static int init_status_page(struct intel_ring_buffer *ring)
1054 {
1055 struct drm_device *dev = ring->dev;
1056 struct drm_i915_gem_object *obj;
1057 int ret;
1058
1059 obj = i915_gem_alloc_object(dev, 4096);
1060 if (obj == NULL) {
1061 DRM_ERROR("Failed to allocate status page\n");
1062 ret = -ENOMEM;
1063 goto err;
1064 }
1065
1066 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1067
1068 ret = i915_gem_object_pin(obj, 4096, true, false);
1069 if (ret != 0) {
1070 goto err_unref;
1071 }
1072
1073 ring->status_page.gfx_addr = obj->gtt_offset;
1074 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1075 if (ring->status_page.page_addr == NULL) {
1076 ret = -ENOMEM;
1077 goto err_unpin;
1078 }
1079 ring->status_page.obj = obj;
1080 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1081
1082 intel_ring_setup_status_page(ring);
1083 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1084 ring->name, ring->status_page.gfx_addr);
1085
1086 return 0;
1087
1088 err_unpin:
1089 i915_gem_object_unpin(obj);
1090 err_unref:
1091 drm_gem_object_unreference(&obj->base);
1092 err:
1093 return ret;
1094 }
1095
1096 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1097 {
1098 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1099 u32 addr;
1100
1101 if (!dev_priv->status_page_dmah) {
1102 dev_priv->status_page_dmah =
1103 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1104 if (!dev_priv->status_page_dmah)
1105 return -ENOMEM;
1106 }
1107
1108 addr = dev_priv->status_page_dmah->busaddr;
1109 if (INTEL_INFO(ring->dev)->gen >= 4)
1110 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1111 I915_WRITE(HWS_PGA, addr);
1112
1113 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1114 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1115
1116 return 0;
1117 }
1118
1119 static int intel_init_ring_buffer(struct drm_device *dev,
1120 struct intel_ring_buffer *ring)
1121 {
1122 struct drm_i915_gem_object *obj;
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1124 int ret;
1125
1126 ring->dev = dev;
1127 INIT_LIST_HEAD(&ring->active_list);
1128 INIT_LIST_HEAD(&ring->request_list);
1129 ring->size = 32 * PAGE_SIZE;
1130 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1131
1132 init_waitqueue_head(&ring->irq_queue);
1133
1134 if (I915_NEED_GFX_HWS(dev)) {
1135 ret = init_status_page(ring);
1136 if (ret)
1137 return ret;
1138 } else {
1139 BUG_ON(ring->id != RCS);
1140 ret = init_phys_hws_pga(ring);
1141 if (ret)
1142 return ret;
1143 }
1144
1145 obj = NULL;
1146 if (!HAS_LLC(dev))
1147 obj = i915_gem_object_create_stolen(dev, ring->size);
1148 if (obj == NULL)
1149 obj = i915_gem_alloc_object(dev, ring->size);
1150 if (obj == NULL) {
1151 DRM_ERROR("Failed to allocate ringbuffer\n");
1152 ret = -ENOMEM;
1153 goto err_hws;
1154 }
1155
1156 ring->obj = obj;
1157
1158 ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1159 if (ret)
1160 goto err_unref;
1161
1162 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1163 if (ret)
1164 goto err_unpin;
1165
1166 ring->virtual_start =
1167 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1168 ring->size);
1169 if (ring->virtual_start == NULL) {
1170 DRM_ERROR("Failed to map ringbuffer.\n");
1171 ret = -EINVAL;
1172 goto err_unpin;
1173 }
1174
1175 ret = ring->init(ring);
1176 if (ret)
1177 goto err_unmap;
1178
1179 /* Workaround an erratum on the i830 which causes a hang if
1180 * the TAIL pointer points to within the last 2 cachelines
1181 * of the buffer.
1182 */
1183 ring->effective_size = ring->size;
1184 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1185 ring->effective_size -= 128;
1186
1187 return 0;
1188
1189 err_unmap:
1190 iounmap(ring->virtual_start);
1191 err_unpin:
1192 i915_gem_object_unpin(obj);
1193 err_unref:
1194 drm_gem_object_unreference(&obj->base);
1195 ring->obj = NULL;
1196 err_hws:
1197 cleanup_status_page(ring);
1198 return ret;
1199 }
1200
1201 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1202 {
1203 struct drm_i915_private *dev_priv;
1204 int ret;
1205
1206 if (ring->obj == NULL)
1207 return;
1208
1209 /* Disable the ring buffer. The ring must be idle at this point */
1210 dev_priv = ring->dev->dev_private;
1211 ret = intel_ring_idle(ring);
1212 if (ret)
1213 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1214 ring->name, ret);
1215
1216 I915_WRITE_CTL(ring, 0);
1217
1218 iounmap(ring->virtual_start);
1219
1220 i915_gem_object_unpin(ring->obj);
1221 drm_gem_object_unreference(&ring->obj->base);
1222 ring->obj = NULL;
1223
1224 if (ring->cleanup)
1225 ring->cleanup(ring);
1226
1227 cleanup_status_page(ring);
1228 }
1229
1230 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1231 {
1232 int ret;
1233
1234 ret = i915_wait_seqno(ring, seqno);
1235 if (!ret)
1236 i915_gem_retire_requests_ring(ring);
1237
1238 return ret;
1239 }
1240
1241 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1242 {
1243 struct drm_i915_gem_request *request;
1244 u32 seqno = 0;
1245 int ret;
1246
1247 i915_gem_retire_requests_ring(ring);
1248
1249 if (ring->last_retired_head != -1) {
1250 ring->head = ring->last_retired_head;
1251 ring->last_retired_head = -1;
1252 ring->space = ring_space(ring);
1253 if (ring->space >= n)
1254 return 0;
1255 }
1256
1257 list_for_each_entry(request, &ring->request_list, list) {
1258 int space;
1259
1260 if (request->tail == -1)
1261 continue;
1262
1263 space = request->tail - (ring->tail + 8);
1264 if (space < 0)
1265 space += ring->size;
1266 if (space >= n) {
1267 seqno = request->seqno;
1268 break;
1269 }
1270
1271 /* Consume this request in case we need more space than
1272 * is available and so need to prevent a race between
1273 * updating last_retired_head and direct reads of
1274 * I915_RING_HEAD. It also provides a nice sanity check.
1275 */
1276 request->tail = -1;
1277 }
1278
1279 if (seqno == 0)
1280 return -ENOSPC;
1281
1282 ret = intel_ring_wait_seqno(ring, seqno);
1283 if (ret)
1284 return ret;
1285
1286 if (WARN_ON(ring->last_retired_head == -1))
1287 return -ENOSPC;
1288
1289 ring->head = ring->last_retired_head;
1290 ring->last_retired_head = -1;
1291 ring->space = ring_space(ring);
1292 if (WARN_ON(ring->space < n))
1293 return -ENOSPC;
1294
1295 return 0;
1296 }
1297
1298 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1299 {
1300 struct drm_device *dev = ring->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 unsigned long end;
1303 int ret;
1304
1305 ret = intel_ring_wait_request(ring, n);
1306 if (ret != -ENOSPC)
1307 return ret;
1308
1309 trace_i915_ring_wait_begin(ring);
1310 /* With GEM the hangcheck timer should kick us out of the loop,
1311 * leaving it early runs the risk of corrupting GEM state (due
1312 * to running on almost untested codepaths). But on resume
1313 * timers don't work yet, so prevent a complete hang in that
1314 * case by choosing an insanely large timeout. */
1315 end = jiffies + 60 * HZ;
1316
1317 do {
1318 ring->head = I915_READ_HEAD(ring);
1319 ring->space = ring_space(ring);
1320 if (ring->space >= n) {
1321 trace_i915_ring_wait_end(ring);
1322 return 0;
1323 }
1324
1325 if (dev->primary->master) {
1326 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1327 if (master_priv->sarea_priv)
1328 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1329 }
1330
1331 msleep(1);
1332
1333 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1334 if (ret)
1335 return ret;
1336 } while (!time_after(jiffies, end));
1337 trace_i915_ring_wait_end(ring);
1338 return -EBUSY;
1339 }
1340
1341 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1342 {
1343 uint32_t __iomem *virt;
1344 int rem = ring->size - ring->tail;
1345
1346 if (ring->space < rem) {
1347 int ret = ring_wait_for_space(ring, rem);
1348 if (ret)
1349 return ret;
1350 }
1351
1352 virt = ring->virtual_start + ring->tail;
1353 rem /= 4;
1354 while (rem--)
1355 iowrite32(MI_NOOP, virt++);
1356
1357 ring->tail = 0;
1358 ring->space = ring_space(ring);
1359
1360 return 0;
1361 }
1362
1363 int intel_ring_idle(struct intel_ring_buffer *ring)
1364 {
1365 u32 seqno;
1366 int ret;
1367
1368 /* We need to add any requests required to flush the objects and ring */
1369 if (ring->outstanding_lazy_request) {
1370 ret = i915_add_request(ring, NULL, NULL);
1371 if (ret)
1372 return ret;
1373 }
1374
1375 /* Wait upon the last request to be completed */
1376 if (list_empty(&ring->request_list))
1377 return 0;
1378
1379 seqno = list_entry(ring->request_list.prev,
1380 struct drm_i915_gem_request,
1381 list)->seqno;
1382
1383 return i915_wait_seqno(ring, seqno);
1384 }
1385
1386 static int
1387 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1388 {
1389 if (ring->outstanding_lazy_request)
1390 return 0;
1391
1392 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1393 }
1394
1395 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1396 int bytes)
1397 {
1398 int ret;
1399
1400 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1401 ret = intel_wrap_ring_buffer(ring);
1402 if (unlikely(ret))
1403 return ret;
1404 }
1405
1406 if (unlikely(ring->space < bytes)) {
1407 ret = ring_wait_for_space(ring, bytes);
1408 if (unlikely(ret))
1409 return ret;
1410 }
1411
1412 ring->space -= bytes;
1413 return 0;
1414 }
1415
1416 int intel_ring_begin(struct intel_ring_buffer *ring,
1417 int num_dwords)
1418 {
1419 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1420 int ret;
1421
1422 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1423 if (ret)
1424 return ret;
1425
1426 /* Preallocate the olr before touching the ring */
1427 ret = intel_ring_alloc_seqno(ring);
1428 if (ret)
1429 return ret;
1430
1431 return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1432 }
1433
1434 int intel_ring_handle_seqno_wrap(struct intel_ring_buffer *ring)
1435 {
1436 int ret;
1437
1438 BUG_ON(ring->outstanding_lazy_request);
1439
1440 if (INTEL_INFO(ring->dev)->gen < 6)
1441 return 0;
1442
1443 ret = __intel_ring_begin(ring, 6 * sizeof(uint32_t));
1444 if (ret)
1445 return ret;
1446
1447 /* Leaving a stale, pre-wrap seqno behind in the mboxes will result in
1448 * post-wrap semaphore waits completing immediately. Clear them. */
1449 update_mboxes(ring, ring->signal_mbox[0]);
1450 update_mboxes(ring, ring->signal_mbox[1]);
1451 intel_ring_advance(ring);
1452
1453 return 0;
1454 }
1455
1456 void intel_ring_advance(struct intel_ring_buffer *ring)
1457 {
1458 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1459
1460 ring->tail &= ring->size - 1;
1461 if (dev_priv->stop_rings & intel_ring_flag(ring))
1462 return;
1463 ring->write_tail(ring, ring->tail);
1464 }
1465
1466
1467 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1468 u32 value)
1469 {
1470 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1471
1472 /* Every tail move must follow the sequence below */
1473
1474 /* Disable notification that the ring is IDLE. The GT
1475 * will then assume that it is busy and bring it out of rc6.
1476 */
1477 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1478 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1479
1480 /* Clear the context id. Here be magic! */
1481 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1482
1483 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1484 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1485 GEN6_BSD_SLEEP_INDICATOR) == 0,
1486 50))
1487 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1488
1489 /* Now that the ring is fully powered up, update the tail */
1490 I915_WRITE_TAIL(ring, value);
1491 POSTING_READ(RING_TAIL(ring->mmio_base));
1492
1493 /* Let the ring send IDLE messages to the GT again,
1494 * and so let it sleep to conserve power when idle.
1495 */
1496 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1497 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1498 }
1499
1500 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1501 u32 invalidate, u32 flush)
1502 {
1503 uint32_t cmd;
1504 int ret;
1505
1506 ret = intel_ring_begin(ring, 4);
1507 if (ret)
1508 return ret;
1509
1510 cmd = MI_FLUSH_DW;
1511 /*
1512 * Bspec vol 1c.5 - video engine command streamer:
1513 * "If ENABLED, all TLBs will be invalidated once the flush
1514 * operation is complete. This bit is only valid when the
1515 * Post-Sync Operation field is a value of 1h or 3h."
1516 */
1517 if (invalidate & I915_GEM_GPU_DOMAINS)
1518 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1519 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1520 intel_ring_emit(ring, cmd);
1521 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1522 intel_ring_emit(ring, 0);
1523 intel_ring_emit(ring, MI_NOOP);
1524 intel_ring_advance(ring);
1525 return 0;
1526 }
1527
1528 static int
1529 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1530 u32 offset, u32 len,
1531 unsigned flags)
1532 {
1533 int ret;
1534
1535 ret = intel_ring_begin(ring, 2);
1536 if (ret)
1537 return ret;
1538
1539 intel_ring_emit(ring,
1540 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1541 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1542 /* bit0-7 is the length on GEN6+ */
1543 intel_ring_emit(ring, offset);
1544 intel_ring_advance(ring);
1545
1546 return 0;
1547 }
1548
1549 static int
1550 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1551 u32 offset, u32 len,
1552 unsigned flags)
1553 {
1554 int ret;
1555
1556 ret = intel_ring_begin(ring, 2);
1557 if (ret)
1558 return ret;
1559
1560 intel_ring_emit(ring,
1561 MI_BATCH_BUFFER_START |
1562 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1563 /* bit0-7 is the length on GEN6+ */
1564 intel_ring_emit(ring, offset);
1565 intel_ring_advance(ring);
1566
1567 return 0;
1568 }
1569
1570 /* Blitter support (SandyBridge+) */
1571
1572 static int blt_ring_flush(struct intel_ring_buffer *ring,
1573 u32 invalidate, u32 flush)
1574 {
1575 uint32_t cmd;
1576 int ret;
1577
1578 ret = intel_ring_begin(ring, 4);
1579 if (ret)
1580 return ret;
1581
1582 cmd = MI_FLUSH_DW;
1583 /*
1584 * Bspec vol 1c.3 - blitter engine command streamer:
1585 * "If ENABLED, all TLBs will be invalidated once the flush
1586 * operation is complete. This bit is only valid when the
1587 * Post-Sync Operation field is a value of 1h or 3h."
1588 */
1589 if (invalidate & I915_GEM_DOMAIN_RENDER)
1590 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1591 MI_FLUSH_DW_OP_STOREDW;
1592 intel_ring_emit(ring, cmd);
1593 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1594 intel_ring_emit(ring, 0);
1595 intel_ring_emit(ring, MI_NOOP);
1596 intel_ring_advance(ring);
1597 return 0;
1598 }
1599
1600 int intel_init_render_ring_buffer(struct drm_device *dev)
1601 {
1602 drm_i915_private_t *dev_priv = dev->dev_private;
1603 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1604
1605 ring->name = "render ring";
1606 ring->id = RCS;
1607 ring->mmio_base = RENDER_RING_BASE;
1608
1609 if (INTEL_INFO(dev)->gen >= 6) {
1610 ring->add_request = gen6_add_request;
1611 ring->flush = gen7_render_ring_flush;
1612 if (INTEL_INFO(dev)->gen == 6)
1613 ring->flush = gen6_render_ring_flush;
1614 ring->irq_get = gen6_ring_get_irq;
1615 ring->irq_put = gen6_ring_put_irq;
1616 ring->irq_enable_mask = GT_USER_INTERRUPT;
1617 ring->get_seqno = gen6_ring_get_seqno;
1618 ring->set_seqno = ring_set_seqno;
1619 ring->sync_to = gen6_ring_sync;
1620 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1621 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1622 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1623 ring->signal_mbox[0] = GEN6_VRSYNC;
1624 ring->signal_mbox[1] = GEN6_BRSYNC;
1625 } else if (IS_GEN5(dev)) {
1626 ring->add_request = pc_render_add_request;
1627 ring->flush = gen4_render_ring_flush;
1628 ring->get_seqno = pc_render_get_seqno;
1629 ring->set_seqno = pc_render_set_seqno;
1630 ring->irq_get = gen5_ring_get_irq;
1631 ring->irq_put = gen5_ring_put_irq;
1632 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1633 } else {
1634 ring->add_request = i9xx_add_request;
1635 if (INTEL_INFO(dev)->gen < 4)
1636 ring->flush = gen2_render_ring_flush;
1637 else
1638 ring->flush = gen4_render_ring_flush;
1639 ring->get_seqno = ring_get_seqno;
1640 ring->set_seqno = ring_set_seqno;
1641 if (IS_GEN2(dev)) {
1642 ring->irq_get = i8xx_ring_get_irq;
1643 ring->irq_put = i8xx_ring_put_irq;
1644 } else {
1645 ring->irq_get = i9xx_ring_get_irq;
1646 ring->irq_put = i9xx_ring_put_irq;
1647 }
1648 ring->irq_enable_mask = I915_USER_INTERRUPT;
1649 }
1650 ring->write_tail = ring_write_tail;
1651 if (IS_HASWELL(dev))
1652 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1653 else if (INTEL_INFO(dev)->gen >= 6)
1654 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1655 else if (INTEL_INFO(dev)->gen >= 4)
1656 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1657 else if (IS_I830(dev) || IS_845G(dev))
1658 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1659 else
1660 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1661 ring->init = init_render_ring;
1662 ring->cleanup = render_ring_cleanup;
1663
1664 return intel_init_ring_buffer(dev, ring);
1665 }
1666
1667 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1668 {
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1670 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1671 int ret;
1672
1673 ring->name = "render ring";
1674 ring->id = RCS;
1675 ring->mmio_base = RENDER_RING_BASE;
1676
1677 if (INTEL_INFO(dev)->gen >= 6) {
1678 /* non-kms not supported on gen6+ */
1679 return -ENODEV;
1680 }
1681
1682 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1683 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1684 * the special gen5 functions. */
1685 ring->add_request = i9xx_add_request;
1686 if (INTEL_INFO(dev)->gen < 4)
1687 ring->flush = gen2_render_ring_flush;
1688 else
1689 ring->flush = gen4_render_ring_flush;
1690 ring->get_seqno = ring_get_seqno;
1691 ring->set_seqno = ring_set_seqno;
1692 if (IS_GEN2(dev)) {
1693 ring->irq_get = i8xx_ring_get_irq;
1694 ring->irq_put = i8xx_ring_put_irq;
1695 } else {
1696 ring->irq_get = i9xx_ring_get_irq;
1697 ring->irq_put = i9xx_ring_put_irq;
1698 }
1699 ring->irq_enable_mask = I915_USER_INTERRUPT;
1700 ring->write_tail = ring_write_tail;
1701 if (INTEL_INFO(dev)->gen >= 4)
1702 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1703 else if (IS_I830(dev) || IS_845G(dev))
1704 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1705 else
1706 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1707 ring->init = init_render_ring;
1708 ring->cleanup = render_ring_cleanup;
1709
1710 ring->dev = dev;
1711 INIT_LIST_HEAD(&ring->active_list);
1712 INIT_LIST_HEAD(&ring->request_list);
1713
1714 ring->size = size;
1715 ring->effective_size = ring->size;
1716 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1717 ring->effective_size -= 128;
1718
1719 ring->virtual_start = ioremap_wc(start, size);
1720 if (ring->virtual_start == NULL) {
1721 DRM_ERROR("can not ioremap virtual address for"
1722 " ring buffer\n");
1723 return -ENOMEM;
1724 }
1725
1726 if (!I915_NEED_GFX_HWS(dev)) {
1727 ret = init_phys_hws_pga(ring);
1728 if (ret)
1729 return ret;
1730 }
1731
1732 return 0;
1733 }
1734
1735 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1736 {
1737 drm_i915_private_t *dev_priv = dev->dev_private;
1738 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1739
1740 ring->name = "bsd ring";
1741 ring->id = VCS;
1742
1743 ring->write_tail = ring_write_tail;
1744 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1745 ring->mmio_base = GEN6_BSD_RING_BASE;
1746 /* gen6 bsd needs a special wa for tail updates */
1747 if (IS_GEN6(dev))
1748 ring->write_tail = gen6_bsd_ring_write_tail;
1749 ring->flush = gen6_ring_flush;
1750 ring->add_request = gen6_add_request;
1751 ring->get_seqno = gen6_ring_get_seqno;
1752 ring->set_seqno = ring_set_seqno;
1753 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1754 ring->irq_get = gen6_ring_get_irq;
1755 ring->irq_put = gen6_ring_put_irq;
1756 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1757 ring->sync_to = gen6_ring_sync;
1758 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1759 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1760 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1761 ring->signal_mbox[0] = GEN6_RVSYNC;
1762 ring->signal_mbox[1] = GEN6_BVSYNC;
1763 } else {
1764 ring->mmio_base = BSD_RING_BASE;
1765 ring->flush = bsd_ring_flush;
1766 ring->add_request = i9xx_add_request;
1767 ring->get_seqno = ring_get_seqno;
1768 ring->set_seqno = ring_set_seqno;
1769 if (IS_GEN5(dev)) {
1770 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1771 ring->irq_get = gen5_ring_get_irq;
1772 ring->irq_put = gen5_ring_put_irq;
1773 } else {
1774 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1775 ring->irq_get = i9xx_ring_get_irq;
1776 ring->irq_put = i9xx_ring_put_irq;
1777 }
1778 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1779 }
1780 ring->init = init_ring_common;
1781
1782 return intel_init_ring_buffer(dev, ring);
1783 }
1784
1785 int intel_init_blt_ring_buffer(struct drm_device *dev)
1786 {
1787 drm_i915_private_t *dev_priv = dev->dev_private;
1788 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1789
1790 ring->name = "blitter ring";
1791 ring->id = BCS;
1792
1793 ring->mmio_base = BLT_RING_BASE;
1794 ring->write_tail = ring_write_tail;
1795 ring->flush = blt_ring_flush;
1796 ring->add_request = gen6_add_request;
1797 ring->get_seqno = gen6_ring_get_seqno;
1798 ring->set_seqno = ring_set_seqno;
1799 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1800 ring->irq_get = gen6_ring_get_irq;
1801 ring->irq_put = gen6_ring_put_irq;
1802 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1803 ring->sync_to = gen6_ring_sync;
1804 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1805 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1806 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1807 ring->signal_mbox[0] = GEN6_RBSYNC;
1808 ring->signal_mbox[1] = GEN6_VBSYNC;
1809 ring->init = init_ring_common;
1810
1811 return intel_init_ring_buffer(dev, ring);
1812 }
1813
1814 int
1815 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
1816 {
1817 int ret;
1818
1819 if (!ring->gpu_caches_dirty)
1820 return 0;
1821
1822 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
1823 if (ret)
1824 return ret;
1825
1826 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
1827
1828 ring->gpu_caches_dirty = false;
1829 return 0;
1830 }
1831
1832 int
1833 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
1834 {
1835 uint32_t flush_domains;
1836 int ret;
1837
1838 flush_domains = 0;
1839 if (ring->gpu_caches_dirty)
1840 flush_domains = I915_GEM_GPU_DOMAINS;
1841
1842 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1843 if (ret)
1844 return ret;
1845
1846 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
1847
1848 ring->gpu_caches_dirty = false;
1849 return 0;
1850 }
Linux kernel - Deliverables
This page took 0.093151 seconds and 6 git commands to generate.