2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 * 965+ support PIPE_CONTROL commands, which provide finer grained control
38 * over cache flushing.
41 struct drm_i915_gem_object
*obj
;
42 volatile u32
*cpu_page
;
46 static inline int ring_space(struct intel_ring_buffer
*ring
)
48 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 struct pipe_control
*pc
= ring
->private;
179 u32 scratch_addr
= pc
->gtt_offset
+ 128;
183 ret
= intel_ring_begin(ring
, 6);
187 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
188 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
189 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
190 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
191 intel_ring_emit(ring
, 0); /* low dword */
192 intel_ring_emit(ring
, 0); /* high dword */
193 intel_ring_emit(ring
, MI_NOOP
);
194 intel_ring_advance(ring
);
196 ret
= intel_ring_begin(ring
, 6);
200 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
201 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
202 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, 0);
205 intel_ring_emit(ring
, MI_NOOP
);
206 intel_ring_advance(ring
);
212 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
213 u32 invalidate_domains
, u32 flush_domains
)
216 struct pipe_control
*pc
= ring
->private;
217 u32 scratch_addr
= pc
->gtt_offset
+ 128;
220 /* Force SNB workarounds for PIPE_CONTROL flushes */
221 ret
= intel_emit_post_sync_nonzero_flush(ring
);
225 /* Just flush everything. Experiments have shown that reducing the
226 * number of bits based on the write domains has little performance
230 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
231 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
233 * Ensure that any following seqno writes only happen
234 * when the render cache is indeed flushed.
236 flags
|= PIPE_CONTROL_CS_STALL
;
238 if (invalidate_domains
) {
239 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
240 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
244 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
246 * TLB invalidate requires a post-sync write.
248 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
251 ret
= intel_ring_begin(ring
, 4);
255 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
256 intel_ring_emit(ring
, flags
);
257 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
258 intel_ring_emit(ring
, 0);
259 intel_ring_advance(ring
);
265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
269 ret
= intel_ring_begin(ring
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
275 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
276 intel_ring_emit(ring
, 0);
277 intel_ring_emit(ring
, 0);
278 intel_ring_advance(ring
);
283 static int gen7_ring_fbc_flush(struct intel_ring_buffer
*ring
, u32 value
)
287 if (!ring
->fbc_dirty
)
290 ret
= intel_ring_begin(ring
, 4);
293 intel_ring_emit(ring
, MI_NOOP
);
294 /* WaFbcNukeOn3DBlt:ivb/hsw */
295 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
296 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
297 intel_ring_emit(ring
, value
);
298 intel_ring_advance(ring
);
300 ring
->fbc_dirty
= false;
305 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
306 u32 invalidate_domains
, u32 flush_domains
)
309 struct pipe_control
*pc
= ring
->private;
310 u32 scratch_addr
= pc
->gtt_offset
+ 128;
314 * Ensure that any following seqno writes only happen when the render
315 * cache is indeed flushed.
317 * Workaround: 4th PIPE_CONTROL command (except the ones with only
318 * read-cache invalidate bits set) must have the CS_STALL bit set. We
319 * don't try to be clever and just set it unconditionally.
321 flags
|= PIPE_CONTROL_CS_STALL
;
323 /* Just flush everything. Experiments have shown that reducing the
324 * number of bits based on the write domains has little performance
328 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
329 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
331 if (invalidate_domains
) {
332 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
333 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
334 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
335 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
336 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
337 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
339 * TLB invalidate requires a post-sync write.
341 flags
|= PIPE_CONTROL_QW_WRITE
;
342 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
344 /* Workaround: we must issue a pipe_control with CS-stall bit
345 * set before a pipe_control command that has the state cache
346 * invalidate bit set. */
347 gen7_render_ring_cs_stall_wa(ring
);
350 ret
= intel_ring_begin(ring
, 4);
354 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
355 intel_ring_emit(ring
, flags
);
356 intel_ring_emit(ring
, scratch_addr
);
357 intel_ring_emit(ring
, 0);
358 intel_ring_advance(ring
);
361 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
366 static void ring_write_tail(struct intel_ring_buffer
*ring
,
369 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
370 I915_WRITE_TAIL(ring
, value
);
373 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
375 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
376 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
377 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
379 return I915_READ(acthd_reg
);
382 static void ring_setup_phys_status_page(struct intel_ring_buffer
*ring
)
384 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
387 addr
= dev_priv
->status_page_dmah
->busaddr
;
388 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
389 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
390 I915_WRITE(HWS_PGA
, addr
);
393 static int init_ring_common(struct intel_ring_buffer
*ring
)
395 struct drm_device
*dev
= ring
->dev
;
396 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
397 struct drm_i915_gem_object
*obj
= ring
->obj
;
401 if (HAS_FORCE_WAKE(dev
))
402 gen6_gt_force_wake_get(dev_priv
);
404 if (I915_NEED_GFX_HWS(dev
))
405 intel_ring_setup_status_page(ring
);
407 ring_setup_phys_status_page(ring
);
409 /* Stop the ring if it's running. */
410 I915_WRITE_CTL(ring
, 0);
411 I915_WRITE_HEAD(ring
, 0);
412 ring
->write_tail(ring
, 0);
414 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
416 /* G45 ring initialization fails to reset head to zero */
418 DRM_DEBUG_KMS("%s head not reset to zero "
419 "ctl %08x head %08x tail %08x start %08x\n",
422 I915_READ_HEAD(ring
),
423 I915_READ_TAIL(ring
),
424 I915_READ_START(ring
));
426 I915_WRITE_HEAD(ring
, 0);
428 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
429 DRM_ERROR("failed to set %s head to zero "
430 "ctl %08x head %08x tail %08x start %08x\n",
433 I915_READ_HEAD(ring
),
434 I915_READ_TAIL(ring
),
435 I915_READ_START(ring
));
439 /* Initialize the ring. This must happen _after_ we've cleared the ring
440 * registers with the above sequence (the readback of the HEAD registers
441 * also enforces ordering), otherwise the hw might lose the new ring
442 * register values. */
443 I915_WRITE_START(ring
, obj
->gtt_offset
);
445 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
448 /* If the head is still not zero, the ring is dead */
449 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
450 I915_READ_START(ring
) == obj
->gtt_offset
&&
451 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
452 DRM_ERROR("%s initialization failed "
453 "ctl %08x head %08x tail %08x start %08x\n",
456 I915_READ_HEAD(ring
),
457 I915_READ_TAIL(ring
),
458 I915_READ_START(ring
));
463 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
464 i915_kernel_lost_context(ring
->dev
);
466 ring
->head
= I915_READ_HEAD(ring
);
467 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
468 ring
->space
= ring_space(ring
);
469 ring
->last_retired_head
= -1;
472 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
475 if (HAS_FORCE_WAKE(dev
))
476 gen6_gt_force_wake_put(dev_priv
);
482 init_pipe_control(struct intel_ring_buffer
*ring
)
484 struct pipe_control
*pc
;
485 struct drm_i915_gem_object
*obj
;
491 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
495 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
497 DRM_ERROR("Failed to allocate seqno page\n");
502 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
504 ret
= i915_gem_object_pin(obj
, 4096, true, false);
508 pc
->gtt_offset
= obj
->gtt_offset
;
509 pc
->cpu_page
= kmap(sg_page(obj
->pages
->sgl
));
510 if (pc
->cpu_page
== NULL
) {
515 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
516 ring
->name
, pc
->gtt_offset
);
523 i915_gem_object_unpin(obj
);
525 drm_gem_object_unreference(&obj
->base
);
532 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
534 struct pipe_control
*pc
= ring
->private;
535 struct drm_i915_gem_object
*obj
;
539 kunmap(sg_page(obj
->pages
->sgl
));
540 i915_gem_object_unpin(obj
);
541 drm_gem_object_unreference(&obj
->base
);
546 static int init_render_ring(struct intel_ring_buffer
*ring
)
548 struct drm_device
*dev
= ring
->dev
;
549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
550 int ret
= init_ring_common(ring
);
552 if (INTEL_INFO(dev
)->gen
> 3)
553 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
555 /* We need to disable the AsyncFlip performance optimisations in order
556 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
557 * programmed to '1' on all products.
559 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
561 if (INTEL_INFO(dev
)->gen
>= 6)
562 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
564 /* Required for the hardware to program scanline values for waiting */
565 if (INTEL_INFO(dev
)->gen
== 6)
567 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS
));
570 I915_WRITE(GFX_MODE_GEN7
,
571 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
572 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
574 if (INTEL_INFO(dev
)->gen
>= 5) {
575 ret
= init_pipe_control(ring
);
581 /* From the Sandybridge PRM, volume 1 part 3, page 24:
582 * "If this bit is set, STCunit will have LRA as replacement
583 * policy. [...] This bit must be reset. LRA replacement
584 * policy is not supported."
586 I915_WRITE(CACHE_MODE_0
,
587 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
589 /* This is not explicitly set for GEN6, so read the register.
590 * see intel_ring_mi_set_context() for why we care.
591 * TODO: consider explicitly setting the bit for GEN5
593 ring
->itlb_before_ctx_switch
=
594 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
597 if (INTEL_INFO(dev
)->gen
>= 6)
598 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
600 if (HAS_L3_GPU_CACHE(dev
))
601 I915_WRITE_IMR(ring
, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
606 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
608 struct drm_device
*dev
= ring
->dev
;
613 if (HAS_BROKEN_CS_TLB(dev
))
614 drm_gem_object_unreference(to_gem_object(ring
->private));
616 if (INTEL_INFO(dev
)->gen
>= 5)
617 cleanup_pipe_control(ring
);
619 ring
->private = NULL
;
623 update_mboxes(struct intel_ring_buffer
*ring
,
626 /* NB: In order to be able to do semaphore MBOX updates for varying number
627 * of rings, it's easiest if we round up each individual update to a
628 * multiple of 2 (since ring updates must always be a multiple of 2)
629 * even though the actual update only requires 3 dwords.
631 #define MBOX_UPDATE_DWORDS 4
632 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
633 intel_ring_emit(ring
, mmio_offset
);
634 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
635 intel_ring_emit(ring
, MI_NOOP
);
639 * gen6_add_request - Update the semaphore mailbox registers
641 * @ring - ring that is adding a request
642 * @seqno - return seqno stuck into the ring
644 * Update the mailbox registers in the *other* rings with the current seqno.
645 * This acts like a signal in the canonical semaphore.
648 gen6_add_request(struct intel_ring_buffer
*ring
)
650 struct drm_device
*dev
= ring
->dev
;
651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
652 struct intel_ring_buffer
*useless
;
655 ret
= intel_ring_begin(ring
, ((I915_NUM_RINGS
-1) *
656 MBOX_UPDATE_DWORDS
) +
660 #undef MBOX_UPDATE_DWORDS
662 for_each_ring(useless
, dev_priv
, i
) {
663 u32 mbox_reg
= ring
->signal_mbox
[i
];
664 if (mbox_reg
!= GEN6_NOSYNC
)
665 update_mboxes(ring
, mbox_reg
);
668 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
669 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
670 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
671 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
672 intel_ring_advance(ring
);
677 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
681 return dev_priv
->last_seqno
< seqno
;
685 * intel_ring_sync - sync the waiter to the signaller on seqno
687 * @waiter - ring that is waiting
688 * @signaller - ring which has, or will signal
689 * @seqno - seqno which the waiter will block on
692 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
693 struct intel_ring_buffer
*signaller
,
697 u32 dw1
= MI_SEMAPHORE_MBOX
|
698 MI_SEMAPHORE_COMPARE
|
699 MI_SEMAPHORE_REGISTER
;
701 /* Throughout all of the GEM code, seqno passed implies our current
702 * seqno is >= the last seqno executed. However for hardware the
703 * comparison is strictly greater than.
707 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
708 MI_SEMAPHORE_SYNC_INVALID
);
710 ret
= intel_ring_begin(waiter
, 4);
714 /* If seqno wrap happened, omit the wait with no-ops */
715 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
716 intel_ring_emit(waiter
,
718 signaller
->semaphore_register
[waiter
->id
]);
719 intel_ring_emit(waiter
, seqno
);
720 intel_ring_emit(waiter
, 0);
721 intel_ring_emit(waiter
, MI_NOOP
);
723 intel_ring_emit(waiter
, MI_NOOP
);
724 intel_ring_emit(waiter
, MI_NOOP
);
725 intel_ring_emit(waiter
, MI_NOOP
);
726 intel_ring_emit(waiter
, MI_NOOP
);
728 intel_ring_advance(waiter
);
733 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
735 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
736 PIPE_CONTROL_DEPTH_STALL); \
737 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
738 intel_ring_emit(ring__, 0); \
739 intel_ring_emit(ring__, 0); \
743 pc_render_add_request(struct intel_ring_buffer
*ring
)
745 struct pipe_control
*pc
= ring
->private;
746 u32 scratch_addr
= pc
->gtt_offset
+ 128;
749 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
750 * incoherent with writes to memory, i.e. completely fubar,
751 * so we need to use PIPE_NOTIFY instead.
753 * However, we also need to workaround the qword write
754 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
755 * memory before requesting an interrupt.
757 ret
= intel_ring_begin(ring
, 32);
761 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
762 PIPE_CONTROL_WRITE_FLUSH
|
763 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
764 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
765 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
766 intel_ring_emit(ring
, 0);
767 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
768 scratch_addr
+= 128; /* write to separate cachelines */
769 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
771 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
773 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
775 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
777 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
779 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
780 PIPE_CONTROL_WRITE_FLUSH
|
781 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
782 PIPE_CONTROL_NOTIFY
);
783 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
784 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
785 intel_ring_emit(ring
, 0);
786 intel_ring_advance(ring
);
792 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
794 /* Workaround to force correct ordering between irq and seqno writes on
795 * ivb (and maybe also on snb) by reading from a CS register (like
796 * ACTHD) before reading the status page. */
798 intel_ring_get_active_head(ring
);
799 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
803 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
805 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
809 ring_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
811 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
815 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
817 struct pipe_control
*pc
= ring
->private;
818 return pc
->cpu_page
[0];
822 pc_render_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
824 struct pipe_control
*pc
= ring
->private;
825 pc
->cpu_page
[0] = seqno
;
829 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
831 struct drm_device
*dev
= ring
->dev
;
832 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
835 if (!dev
->irq_enabled
)
838 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
839 if (ring
->irq_refcount
.gt
++ == 0) {
840 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
841 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
844 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
850 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
852 struct drm_device
*dev
= ring
->dev
;
853 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
856 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
857 if (--ring
->irq_refcount
.gt
== 0) {
858 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
859 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
862 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
866 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
868 struct drm_device
*dev
= ring
->dev
;
869 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
872 if (!dev
->irq_enabled
)
875 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
876 if (ring
->irq_refcount
.gt
++ == 0) {
877 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
878 I915_WRITE(IMR
, dev_priv
->irq_mask
);
881 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
887 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
889 struct drm_device
*dev
= ring
->dev
;
890 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
893 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
894 if (--ring
->irq_refcount
.gt
== 0) {
895 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
896 I915_WRITE(IMR
, dev_priv
->irq_mask
);
899 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
903 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
905 struct drm_device
*dev
= ring
->dev
;
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
909 if (!dev
->irq_enabled
)
912 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
913 if (ring
->irq_refcount
.gt
++ == 0) {
914 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
915 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
918 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
924 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
926 struct drm_device
*dev
= ring
->dev
;
927 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
930 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
931 if (--ring
->irq_refcount
.gt
== 0) {
932 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
933 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
936 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
939 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
941 struct drm_device
*dev
= ring
->dev
;
942 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
945 /* The ring status page addresses are no longer next to the rest of
946 * the ring registers as of gen7.
951 mmio
= RENDER_HWS_PGA_GEN7
;
954 mmio
= BLT_HWS_PGA_GEN7
;
957 mmio
= BSD_HWS_PGA_GEN7
;
960 mmio
= VEBOX_HWS_PGA_GEN7
;
963 } else if (IS_GEN6(ring
->dev
)) {
964 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
966 mmio
= RING_HWS_PGA(ring
->mmio_base
);
969 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
974 bsd_ring_flush(struct intel_ring_buffer
*ring
,
975 u32 invalidate_domains
,
980 ret
= intel_ring_begin(ring
, 2);
984 intel_ring_emit(ring
, MI_FLUSH
);
985 intel_ring_emit(ring
, MI_NOOP
);
986 intel_ring_advance(ring
);
991 i9xx_add_request(struct intel_ring_buffer
*ring
)
995 ret
= intel_ring_begin(ring
, 4);
999 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1000 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1001 intel_ring_emit(ring
, ring
->outstanding_lazy_request
);
1002 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1003 intel_ring_advance(ring
);
1009 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
1011 struct drm_device
*dev
= ring
->dev
;
1012 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1013 unsigned long flags
;
1015 if (!dev
->irq_enabled
)
1018 /* It looks like we need to prevent the gt from suspending while waiting
1019 * for an notifiy irq, otherwise irqs seem to get lost on at least the
1020 * blt/bsd rings on ivb. */
1021 gen6_gt_force_wake_get(dev_priv
);
1023 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1024 if (ring
->irq_refcount
.gt
++ == 0) {
1025 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
1026 I915_WRITE_IMR(ring
,
1027 ~(ring
->irq_enable_mask
|
1028 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1030 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1031 dev_priv
->gt_irq_mask
&= ~ring
->irq_enable_mask
;
1032 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1033 POSTING_READ(GTIMR
);
1035 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1041 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
1043 struct drm_device
*dev
= ring
->dev
;
1044 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1045 unsigned long flags
;
1047 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1048 if (--ring
->irq_refcount
.gt
== 0) {
1049 if (HAS_L3_GPU_CACHE(dev
) && ring
->id
== RCS
)
1050 I915_WRITE_IMR(ring
,
1051 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1053 I915_WRITE_IMR(ring
, ~0);
1054 dev_priv
->gt_irq_mask
|= ring
->irq_enable_mask
;
1055 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
1056 POSTING_READ(GTIMR
);
1058 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1060 gen6_gt_force_wake_put(dev_priv
);
1064 hsw_vebox_get_irq(struct intel_ring_buffer
*ring
)
1066 struct drm_device
*dev
= ring
->dev
;
1067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1068 unsigned long flags
;
1070 if (!dev
->irq_enabled
)
1073 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
1074 if (ring
->irq_refcount
.pm
++ == 0) {
1075 u32 pm_imr
= I915_READ(GEN6_PMIMR
);
1076 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1077 I915_WRITE(GEN6_PMIMR
, pm_imr
& ~ring
->irq_enable_mask
);
1078 POSTING_READ(GEN6_PMIMR
);
1080 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
1086 hsw_vebox_put_irq(struct intel_ring_buffer
*ring
)
1088 struct drm_device
*dev
= ring
->dev
;
1089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1090 unsigned long flags
;
1092 if (!dev
->irq_enabled
)
1095 spin_lock_irqsave(&dev_priv
->rps
.lock
, flags
);
1096 if (--ring
->irq_refcount
.pm
== 0) {
1097 u32 pm_imr
= I915_READ(GEN6_PMIMR
);
1098 I915_WRITE_IMR(ring
, ~0);
1099 I915_WRITE(GEN6_PMIMR
, pm_imr
| ring
->irq_enable_mask
);
1100 POSTING_READ(GEN6_PMIMR
);
1102 spin_unlock_irqrestore(&dev_priv
->rps
.lock
, flags
);
1106 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1107 u32 offset
, u32 length
,
1112 ret
= intel_ring_begin(ring
, 2);
1116 intel_ring_emit(ring
,
1117 MI_BATCH_BUFFER_START
|
1119 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1120 intel_ring_emit(ring
, offset
);
1121 intel_ring_advance(ring
);
1126 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1127 #define I830_BATCH_LIMIT (256*1024)
1129 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1130 u32 offset
, u32 len
,
1135 if (flags
& I915_DISPATCH_PINNED
) {
1136 ret
= intel_ring_begin(ring
, 4);
1140 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1141 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1142 intel_ring_emit(ring
, offset
+ len
- 8);
1143 intel_ring_emit(ring
, MI_NOOP
);
1144 intel_ring_advance(ring
);
1146 struct drm_i915_gem_object
*obj
= ring
->private;
1147 u32 cs_offset
= obj
->gtt_offset
;
1149 if (len
> I830_BATCH_LIMIT
)
1152 ret
= intel_ring_begin(ring
, 9+3);
1155 /* Blit the batch (which has now all relocs applied) to the stable batch
1156 * scratch bo area (so that the CS never stumbles over its tlb
1157 * invalidation bug) ... */
1158 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1159 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1160 XY_SRC_COPY_BLT_WRITE_RGB
);
1161 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1162 intel_ring_emit(ring
, 0);
1163 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1164 intel_ring_emit(ring
, cs_offset
);
1165 intel_ring_emit(ring
, 0);
1166 intel_ring_emit(ring
, 4096);
1167 intel_ring_emit(ring
, offset
);
1168 intel_ring_emit(ring
, MI_FLUSH
);
1170 /* ... and execute it. */
1171 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1172 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1173 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1174 intel_ring_advance(ring
);
1181 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1182 u32 offset
, u32 len
,
1187 ret
= intel_ring_begin(ring
, 2);
1191 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1192 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1193 intel_ring_advance(ring
);
1198 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1200 struct drm_i915_gem_object
*obj
;
1202 obj
= ring
->status_page
.obj
;
1206 kunmap(sg_page(obj
->pages
->sgl
));
1207 i915_gem_object_unpin(obj
);
1208 drm_gem_object_unreference(&obj
->base
);
1209 ring
->status_page
.obj
= NULL
;
1212 static int init_status_page(struct intel_ring_buffer
*ring
)
1214 struct drm_device
*dev
= ring
->dev
;
1215 struct drm_i915_gem_object
*obj
;
1218 obj
= i915_gem_alloc_object(dev
, 4096);
1220 DRM_ERROR("Failed to allocate status page\n");
1225 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1227 ret
= i915_gem_object_pin(obj
, 4096, true, false);
1232 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
1233 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1234 if (ring
->status_page
.page_addr
== NULL
) {
1238 ring
->status_page
.obj
= obj
;
1239 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1241 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1242 ring
->name
, ring
->status_page
.gfx_addr
);
1247 i915_gem_object_unpin(obj
);
1249 drm_gem_object_unreference(&obj
->base
);
1254 static int init_phys_status_page(struct intel_ring_buffer
*ring
)
1256 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1258 if (!dev_priv
->status_page_dmah
) {
1259 dev_priv
->status_page_dmah
=
1260 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1261 if (!dev_priv
->status_page_dmah
)
1265 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1266 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1271 static int intel_init_ring_buffer(struct drm_device
*dev
,
1272 struct intel_ring_buffer
*ring
)
1274 struct drm_i915_gem_object
*obj
;
1275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1279 INIT_LIST_HEAD(&ring
->active_list
);
1280 INIT_LIST_HEAD(&ring
->request_list
);
1281 ring
->size
= 32 * PAGE_SIZE
;
1282 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1284 init_waitqueue_head(&ring
->irq_queue
);
1286 if (I915_NEED_GFX_HWS(dev
)) {
1287 ret
= init_status_page(ring
);
1291 BUG_ON(ring
->id
!= RCS
);
1292 ret
= init_phys_status_page(ring
);
1299 obj
= i915_gem_object_create_stolen(dev
, ring
->size
);
1301 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1303 DRM_ERROR("Failed to allocate ringbuffer\n");
1310 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true, false);
1314 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1318 ring
->virtual_start
=
1319 ioremap_wc(dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
,
1321 if (ring
->virtual_start
== NULL
) {
1322 DRM_ERROR("Failed to map ringbuffer.\n");
1327 ret
= ring
->init(ring
);
1331 /* Workaround an erratum on the i830 which causes a hang if
1332 * the TAIL pointer points to within the last 2 cachelines
1335 ring
->effective_size
= ring
->size
;
1336 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1337 ring
->effective_size
-= 128;
1342 iounmap(ring
->virtual_start
);
1344 i915_gem_object_unpin(obj
);
1346 drm_gem_object_unreference(&obj
->base
);
1349 cleanup_status_page(ring
);
1353 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1355 struct drm_i915_private
*dev_priv
;
1358 if (ring
->obj
== NULL
)
1361 /* Disable the ring buffer. The ring must be idle at this point */
1362 dev_priv
= ring
->dev
->dev_private
;
1363 ret
= intel_ring_idle(ring
);
1365 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1368 I915_WRITE_CTL(ring
, 0);
1370 iounmap(ring
->virtual_start
);
1372 i915_gem_object_unpin(ring
->obj
);
1373 drm_gem_object_unreference(&ring
->obj
->base
);
1377 ring
->cleanup(ring
);
1379 cleanup_status_page(ring
);
1382 static int intel_ring_wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1386 ret
= i915_wait_seqno(ring
, seqno
);
1388 i915_gem_retire_requests_ring(ring
);
1393 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1395 struct drm_i915_gem_request
*request
;
1399 i915_gem_retire_requests_ring(ring
);
1401 if (ring
->last_retired_head
!= -1) {
1402 ring
->head
= ring
->last_retired_head
;
1403 ring
->last_retired_head
= -1;
1404 ring
->space
= ring_space(ring
);
1405 if (ring
->space
>= n
)
1409 list_for_each_entry(request
, &ring
->request_list
, list
) {
1412 if (request
->tail
== -1)
1415 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1417 space
+= ring
->size
;
1419 seqno
= request
->seqno
;
1423 /* Consume this request in case we need more space than
1424 * is available and so need to prevent a race between
1425 * updating last_retired_head and direct reads of
1426 * I915_RING_HEAD. It also provides a nice sanity check.
1434 ret
= intel_ring_wait_seqno(ring
, seqno
);
1438 if (WARN_ON(ring
->last_retired_head
== -1))
1441 ring
->head
= ring
->last_retired_head
;
1442 ring
->last_retired_head
= -1;
1443 ring
->space
= ring_space(ring
);
1444 if (WARN_ON(ring
->space
< n
))
1450 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1452 struct drm_device
*dev
= ring
->dev
;
1453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1457 ret
= intel_ring_wait_request(ring
, n
);
1461 trace_i915_ring_wait_begin(ring
);
1462 /* With GEM the hangcheck timer should kick us out of the loop,
1463 * leaving it early runs the risk of corrupting GEM state (due
1464 * to running on almost untested codepaths). But on resume
1465 * timers don't work yet, so prevent a complete hang in that
1466 * case by choosing an insanely large timeout. */
1467 end
= jiffies
+ 60 * HZ
;
1470 ring
->head
= I915_READ_HEAD(ring
);
1471 ring
->space
= ring_space(ring
);
1472 if (ring
->space
>= n
) {
1473 trace_i915_ring_wait_end(ring
);
1477 if (dev
->primary
->master
) {
1478 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1479 if (master_priv
->sarea_priv
)
1480 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1485 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1486 dev_priv
->mm
.interruptible
);
1489 } while (!time_after(jiffies
, end
));
1490 trace_i915_ring_wait_end(ring
);
1494 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1496 uint32_t __iomem
*virt
;
1497 int rem
= ring
->size
- ring
->tail
;
1499 if (ring
->space
< rem
) {
1500 int ret
= ring_wait_for_space(ring
, rem
);
1505 virt
= ring
->virtual_start
+ ring
->tail
;
1508 iowrite32(MI_NOOP
, virt
++);
1511 ring
->space
= ring_space(ring
);
1516 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1521 /* We need to add any requests required to flush the objects and ring */
1522 if (ring
->outstanding_lazy_request
) {
1523 ret
= i915_add_request(ring
, NULL
);
1528 /* Wait upon the last request to be completed */
1529 if (list_empty(&ring
->request_list
))
1532 seqno
= list_entry(ring
->request_list
.prev
,
1533 struct drm_i915_gem_request
,
1536 return i915_wait_seqno(ring
, seqno
);
1540 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1542 if (ring
->outstanding_lazy_request
)
1545 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_request
);
1548 static int __intel_ring_begin(struct intel_ring_buffer
*ring
,
1553 if (unlikely(ring
->tail
+ bytes
> ring
->effective_size
)) {
1554 ret
= intel_wrap_ring_buffer(ring
);
1559 if (unlikely(ring
->space
< bytes
)) {
1560 ret
= ring_wait_for_space(ring
, bytes
);
1565 ring
->space
-= bytes
;
1569 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1572 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1575 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1576 dev_priv
->mm
.interruptible
);
1580 /* Preallocate the olr before touching the ring */
1581 ret
= intel_ring_alloc_seqno(ring
);
1585 return __intel_ring_begin(ring
, num_dwords
* sizeof(uint32_t));
1588 void intel_ring_init_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1590 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1592 BUG_ON(ring
->outstanding_lazy_request
);
1594 if (INTEL_INFO(ring
->dev
)->gen
>= 6) {
1595 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
1596 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
1599 ring
->set_seqno(ring
, seqno
);
1600 ring
->hangcheck
.seqno
= seqno
;
1603 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1605 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1607 ring
->tail
&= ring
->size
- 1;
1608 if (dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
))
1610 ring
->write_tail(ring
, ring
->tail
);
1614 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1617 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1619 /* Every tail move must follow the sequence below */
1621 /* Disable notification that the ring is IDLE. The GT
1622 * will then assume that it is busy and bring it out of rc6.
1624 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1625 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1627 /* Clear the context id. Here be magic! */
1628 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1630 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1631 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1632 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1634 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1636 /* Now that the ring is fully powered up, update the tail */
1637 I915_WRITE_TAIL(ring
, value
);
1638 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1640 /* Let the ring send IDLE messages to the GT again,
1641 * and so let it sleep to conserve power when idle.
1643 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1644 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1647 static int gen6_bsd_ring_flush(struct intel_ring_buffer
*ring
,
1648 u32 invalidate
, u32 flush
)
1653 ret
= intel_ring_begin(ring
, 4);
1659 * Bspec vol 1c.5 - video engine command streamer:
1660 * "If ENABLED, all TLBs will be invalidated once the flush
1661 * operation is complete. This bit is only valid when the
1662 * Post-Sync Operation field is a value of 1h or 3h."
1664 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1665 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1666 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1667 intel_ring_emit(ring
, cmd
);
1668 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1669 intel_ring_emit(ring
, 0);
1670 intel_ring_emit(ring
, MI_NOOP
);
1671 intel_ring_advance(ring
);
1676 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1677 u32 offset
, u32 len
,
1682 ret
= intel_ring_begin(ring
, 2);
1686 intel_ring_emit(ring
,
1687 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1688 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1689 /* bit0-7 is the length on GEN6+ */
1690 intel_ring_emit(ring
, offset
);
1691 intel_ring_advance(ring
);
1697 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1698 u32 offset
, u32 len
,
1703 ret
= intel_ring_begin(ring
, 2);
1707 intel_ring_emit(ring
,
1708 MI_BATCH_BUFFER_START
|
1709 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1710 /* bit0-7 is the length on GEN6+ */
1711 intel_ring_emit(ring
, offset
);
1712 intel_ring_advance(ring
);
1717 /* Blitter support (SandyBridge+) */
1719 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1720 u32 invalidate
, u32 flush
)
1722 struct drm_device
*dev
= ring
->dev
;
1726 ret
= intel_ring_begin(ring
, 4);
1732 * Bspec vol 1c.3 - blitter engine command streamer:
1733 * "If ENABLED, all TLBs will be invalidated once the flush
1734 * operation is complete. This bit is only valid when the
1735 * Post-Sync Operation field is a value of 1h or 3h."
1737 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1738 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1739 MI_FLUSH_DW_OP_STOREDW
;
1740 intel_ring_emit(ring
, cmd
);
1741 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1742 intel_ring_emit(ring
, 0);
1743 intel_ring_emit(ring
, MI_NOOP
);
1744 intel_ring_advance(ring
);
1746 if (IS_GEN7(dev
) && flush
)
1747 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
1752 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1754 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1755 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1757 ring
->name
= "render ring";
1759 ring
->mmio_base
= RENDER_RING_BASE
;
1761 if (INTEL_INFO(dev
)->gen
>= 6) {
1762 ring
->add_request
= gen6_add_request
;
1763 ring
->flush
= gen7_render_ring_flush
;
1764 if (INTEL_INFO(dev
)->gen
== 6)
1765 ring
->flush
= gen6_render_ring_flush
;
1766 ring
->irq_get
= gen6_ring_get_irq
;
1767 ring
->irq_put
= gen6_ring_put_irq
;
1768 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
1769 ring
->get_seqno
= gen6_ring_get_seqno
;
1770 ring
->set_seqno
= ring_set_seqno
;
1771 ring
->sync_to
= gen6_ring_sync
;
1772 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1773 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
1774 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
1775 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
1776 ring
->signal_mbox
[RCS
] = GEN6_NOSYNC
;
1777 ring
->signal_mbox
[VCS
] = GEN6_VRSYNC
;
1778 ring
->signal_mbox
[BCS
] = GEN6_BRSYNC
;
1779 ring
->signal_mbox
[VECS
] = GEN6_VERSYNC
;
1780 } else if (IS_GEN5(dev
)) {
1781 ring
->add_request
= pc_render_add_request
;
1782 ring
->flush
= gen4_render_ring_flush
;
1783 ring
->get_seqno
= pc_render_get_seqno
;
1784 ring
->set_seqno
= pc_render_set_seqno
;
1785 ring
->irq_get
= gen5_ring_get_irq
;
1786 ring
->irq_put
= gen5_ring_put_irq
;
1787 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
1788 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
1790 ring
->add_request
= i9xx_add_request
;
1791 if (INTEL_INFO(dev
)->gen
< 4)
1792 ring
->flush
= gen2_render_ring_flush
;
1794 ring
->flush
= gen4_render_ring_flush
;
1795 ring
->get_seqno
= ring_get_seqno
;
1796 ring
->set_seqno
= ring_set_seqno
;
1798 ring
->irq_get
= i8xx_ring_get_irq
;
1799 ring
->irq_put
= i8xx_ring_put_irq
;
1801 ring
->irq_get
= i9xx_ring_get_irq
;
1802 ring
->irq_put
= i9xx_ring_put_irq
;
1804 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1806 ring
->write_tail
= ring_write_tail
;
1807 if (IS_HASWELL(dev
))
1808 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1809 else if (INTEL_INFO(dev
)->gen
>= 6)
1810 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1811 else if (INTEL_INFO(dev
)->gen
>= 4)
1812 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1813 else if (IS_I830(dev
) || IS_845G(dev
))
1814 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1816 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1817 ring
->init
= init_render_ring
;
1818 ring
->cleanup
= render_ring_cleanup
;
1820 /* Workaround batchbuffer to combat CS tlb bug. */
1821 if (HAS_BROKEN_CS_TLB(dev
)) {
1822 struct drm_i915_gem_object
*obj
;
1825 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
1827 DRM_ERROR("Failed to allocate batch bo\n");
1831 ret
= i915_gem_object_pin(obj
, 0, true, false);
1833 drm_gem_object_unreference(&obj
->base
);
1834 DRM_ERROR("Failed to ping batch bo\n");
1838 ring
->private = obj
;
1841 return intel_init_ring_buffer(dev
, ring
);
1844 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1846 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1847 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1850 ring
->name
= "render ring";
1852 ring
->mmio_base
= RENDER_RING_BASE
;
1854 if (INTEL_INFO(dev
)->gen
>= 6) {
1855 /* non-kms not supported on gen6+ */
1859 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1860 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1861 * the special gen5 functions. */
1862 ring
->add_request
= i9xx_add_request
;
1863 if (INTEL_INFO(dev
)->gen
< 4)
1864 ring
->flush
= gen2_render_ring_flush
;
1866 ring
->flush
= gen4_render_ring_flush
;
1867 ring
->get_seqno
= ring_get_seqno
;
1868 ring
->set_seqno
= ring_set_seqno
;
1870 ring
->irq_get
= i8xx_ring_get_irq
;
1871 ring
->irq_put
= i8xx_ring_put_irq
;
1873 ring
->irq_get
= i9xx_ring_get_irq
;
1874 ring
->irq_put
= i9xx_ring_put_irq
;
1876 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1877 ring
->write_tail
= ring_write_tail
;
1878 if (INTEL_INFO(dev
)->gen
>= 4)
1879 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1880 else if (IS_I830(dev
) || IS_845G(dev
))
1881 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1883 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1884 ring
->init
= init_render_ring
;
1885 ring
->cleanup
= render_ring_cleanup
;
1888 INIT_LIST_HEAD(&ring
->active_list
);
1889 INIT_LIST_HEAD(&ring
->request_list
);
1892 ring
->effective_size
= ring
->size
;
1893 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1894 ring
->effective_size
-= 128;
1896 ring
->virtual_start
= ioremap_wc(start
, size
);
1897 if (ring
->virtual_start
== NULL
) {
1898 DRM_ERROR("can not ioremap virtual address for"
1903 if (!I915_NEED_GFX_HWS(dev
)) {
1904 ret
= init_phys_status_page(ring
);
1912 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1914 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1915 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1917 ring
->name
= "bsd ring";
1920 ring
->write_tail
= ring_write_tail
;
1921 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1922 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
1923 /* gen6 bsd needs a special wa for tail updates */
1925 ring
->write_tail
= gen6_bsd_ring_write_tail
;
1926 ring
->flush
= gen6_bsd_ring_flush
;
1927 ring
->add_request
= gen6_add_request
;
1928 ring
->get_seqno
= gen6_ring_get_seqno
;
1929 ring
->set_seqno
= ring_set_seqno
;
1930 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
1931 ring
->irq_get
= gen6_ring_get_irq
;
1932 ring
->irq_put
= gen6_ring_put_irq
;
1933 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1934 ring
->sync_to
= gen6_ring_sync
;
1935 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
1936 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1937 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
1938 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
1939 ring
->signal_mbox
[RCS
] = GEN6_RVSYNC
;
1940 ring
->signal_mbox
[VCS
] = GEN6_NOSYNC
;
1941 ring
->signal_mbox
[BCS
] = GEN6_BVSYNC
;
1942 ring
->signal_mbox
[VECS
] = GEN6_VEVSYNC
;
1944 ring
->mmio_base
= BSD_RING_BASE
;
1945 ring
->flush
= bsd_ring_flush
;
1946 ring
->add_request
= i9xx_add_request
;
1947 ring
->get_seqno
= ring_get_seqno
;
1948 ring
->set_seqno
= ring_set_seqno
;
1950 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
1951 ring
->irq_get
= gen5_ring_get_irq
;
1952 ring
->irq_put
= gen5_ring_put_irq
;
1954 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
1955 ring
->irq_get
= i9xx_ring_get_irq
;
1956 ring
->irq_put
= i9xx_ring_put_irq
;
1958 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1960 ring
->init
= init_ring_common
;
1962 return intel_init_ring_buffer(dev
, ring
);
1965 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1967 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1968 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1970 ring
->name
= "blitter ring";
1973 ring
->mmio_base
= BLT_RING_BASE
;
1974 ring
->write_tail
= ring_write_tail
;
1975 ring
->flush
= gen6_ring_flush
;
1976 ring
->add_request
= gen6_add_request
;
1977 ring
->get_seqno
= gen6_ring_get_seqno
;
1978 ring
->set_seqno
= ring_set_seqno
;
1979 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
1980 ring
->irq_get
= gen6_ring_get_irq
;
1981 ring
->irq_put
= gen6_ring_put_irq
;
1982 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1983 ring
->sync_to
= gen6_ring_sync
;
1984 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
1985 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
1986 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1987 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
1988 ring
->signal_mbox
[RCS
] = GEN6_RBSYNC
;
1989 ring
->signal_mbox
[VCS
] = GEN6_VBSYNC
;
1990 ring
->signal_mbox
[BCS
] = GEN6_NOSYNC
;
1991 ring
->signal_mbox
[VECS
] = GEN6_VEBSYNC
;
1992 ring
->init
= init_ring_common
;
1994 return intel_init_ring_buffer(dev
, ring
);
1997 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
1999 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2000 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VECS
];
2002 ring
->name
= "video enhancement ring";
2005 ring
->mmio_base
= VEBOX_RING_BASE
;
2006 ring
->write_tail
= ring_write_tail
;
2007 ring
->flush
= gen6_ring_flush
;
2008 ring
->add_request
= gen6_add_request
;
2009 ring
->get_seqno
= gen6_ring_get_seqno
;
2010 ring
->set_seqno
= ring_set_seqno
;
2011 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
|
2012 PM_VEBOX_CS_ERROR_INTERRUPT
;
2013 ring
->irq_get
= hsw_vebox_get_irq
;
2014 ring
->irq_put
= hsw_vebox_put_irq
;
2015 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2016 ring
->sync_to
= gen6_ring_sync
;
2017 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2018 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2019 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2020 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2021 ring
->signal_mbox
[RCS
] = GEN6_RVESYNC
;
2022 ring
->signal_mbox
[VCS
] = GEN6_VVESYNC
;
2023 ring
->signal_mbox
[BCS
] = GEN6_BVESYNC
;
2024 ring
->signal_mbox
[VECS
] = GEN6_NOSYNC
;
2025 ring
->init
= init_ring_common
;
2027 return intel_init_ring_buffer(dev
, ring
);
2031 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
2035 if (!ring
->gpu_caches_dirty
)
2038 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2042 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2044 ring
->gpu_caches_dirty
= false;
2049 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
2051 uint32_t flush_domains
;
2055 if (ring
->gpu_caches_dirty
)
2056 flush_domains
= I915_GEM_GPU_DOMAINS
;
2058 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2062 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2064 ring
->gpu_caches_dirty
= false;