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Merge branch 'fixes_for-3.6' into fixes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
40 */
41 struct pipe_control {
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
44 u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50 if (space < 0)
51 space += ring->size;
52 return space;
53 }
54
55 static int
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
58 u32 flush_domains)
59 {
60 u32 cmd;
61 int ret;
62
63 cmd = MI_FLUSH;
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
66
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
68 cmd |= MI_READ_FLUSH;
69
70 ret = intel_ring_begin(ring, 2);
71 if (ret)
72 return ret;
73
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
77
78 return 0;
79 }
80
81 static int
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
84 u32 flush_domains)
85 {
86 struct drm_device *dev = ring->dev;
87 u32 cmd;
88 int ret;
89
90 /*
91 * read/write caches:
92 *
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
96 *
97 * read-only caches:
98 *
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
101 *
102 * I915_GEM_DOMAIN_COMMAND may not exist?
103 *
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
106 *
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
109 *
110 * TLBs:
111 *
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
116 */
117
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
122 cmd |= MI_EXE_FLUSH;
123
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
127
128 ret = intel_ring_begin(ring, 2);
129 if (ret)
130 return ret;
131
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
135
136 return 0;
137 }
138
139 /**
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 *
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * 0.
148 *
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 *
152 * And the workaround for these two requires this workaround first:
153 *
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * flushes.
157 *
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * volume 2 part 1:
161 *
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
169 *
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
175 */
176 static int
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
178 {
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
181 int ret;
182
183
184 ret = intel_ring_begin(ring, 6);
185 if (ret)
186 return ret;
187
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
196
197 ret = intel_ring_begin(ring, 6);
198 if (ret)
199 return ret;
200
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
208
209 return 0;
210 }
211
212 static int
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
215 {
216 u32 flags = 0;
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
219 int ret;
220
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 ret = intel_emit_post_sync_nonzero_flush(ring);
223 if (ret)
224 return ret;
225
226 /* Just flush everything. Experiments have shown that reducing the
227 * number of bits based on the write domains has little performance
228 * impact.
229 */
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
231 flags |= PIPE_CONTROL_TLB_INVALIDATE;
232 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
235 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
236 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
237 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
238 /*
239 * Ensure that any following seqno writes only happen when the render
240 * cache is indeed flushed (but only if the caller actually wants that).
241 */
242 if (flush_domains)
243 flags |= PIPE_CONTROL_CS_STALL;
244
245 ret = intel_ring_begin(ring, 6);
246 if (ret)
247 return ret;
248
249 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
250 intel_ring_emit(ring, flags);
251 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
252 intel_ring_emit(ring, 0); /* lower dword */
253 intel_ring_emit(ring, 0); /* uppwer dword */
254 intel_ring_emit(ring, MI_NOOP);
255 intel_ring_advance(ring);
256
257 return 0;
258 }
259
260 static void ring_write_tail(struct intel_ring_buffer *ring,
261 u32 value)
262 {
263 drm_i915_private_t *dev_priv = ring->dev->dev_private;
264 I915_WRITE_TAIL(ring, value);
265 }
266
267 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
268 {
269 drm_i915_private_t *dev_priv = ring->dev->dev_private;
270 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
271 RING_ACTHD(ring->mmio_base) : ACTHD;
272
273 return I915_READ(acthd_reg);
274 }
275
276 static int init_ring_common(struct intel_ring_buffer *ring)
277 {
278 struct drm_device *dev = ring->dev;
279 drm_i915_private_t *dev_priv = dev->dev_private;
280 struct drm_i915_gem_object *obj = ring->obj;
281 int ret = 0;
282 u32 head;
283
284 if (HAS_FORCE_WAKE(dev))
285 gen6_gt_force_wake_get(dev_priv);
286
287 /* Stop the ring if it's running. */
288 I915_WRITE_CTL(ring, 0);
289 I915_WRITE_HEAD(ring, 0);
290 ring->write_tail(ring, 0);
291
292 /* Initialize the ring. */
293 I915_WRITE_START(ring, obj->gtt_offset);
294 head = I915_READ_HEAD(ring) & HEAD_ADDR;
295
296 /* G45 ring initialization fails to reset head to zero */
297 if (head != 0) {
298 DRM_DEBUG_KMS("%s head not reset to zero "
299 "ctl %08x head %08x tail %08x start %08x\n",
300 ring->name,
301 I915_READ_CTL(ring),
302 I915_READ_HEAD(ring),
303 I915_READ_TAIL(ring),
304 I915_READ_START(ring));
305
306 I915_WRITE_HEAD(ring, 0);
307
308 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
309 DRM_ERROR("failed to set %s head to zero "
310 "ctl %08x head %08x tail %08x start %08x\n",
311 ring->name,
312 I915_READ_CTL(ring),
313 I915_READ_HEAD(ring),
314 I915_READ_TAIL(ring),
315 I915_READ_START(ring));
316 }
317 }
318
319 I915_WRITE_CTL(ring,
320 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
321 | RING_VALID);
322
323 /* If the head is still not zero, the ring is dead */
324 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
325 I915_READ_START(ring) == obj->gtt_offset &&
326 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
327 DRM_ERROR("%s initialization failed "
328 "ctl %08x head %08x tail %08x start %08x\n",
329 ring->name,
330 I915_READ_CTL(ring),
331 I915_READ_HEAD(ring),
332 I915_READ_TAIL(ring),
333 I915_READ_START(ring));
334 ret = -EIO;
335 goto out;
336 }
337
338 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
339 i915_kernel_lost_context(ring->dev);
340 else {
341 ring->head = I915_READ_HEAD(ring);
342 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
343 ring->space = ring_space(ring);
344 ring->last_retired_head = -1;
345 }
346
347 out:
348 if (HAS_FORCE_WAKE(dev))
349 gen6_gt_force_wake_put(dev_priv);
350
351 return ret;
352 }
353
354 static int
355 init_pipe_control(struct intel_ring_buffer *ring)
356 {
357 struct pipe_control *pc;
358 struct drm_i915_gem_object *obj;
359 int ret;
360
361 if (ring->private)
362 return 0;
363
364 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
365 if (!pc)
366 return -ENOMEM;
367
368 obj = i915_gem_alloc_object(ring->dev, 4096);
369 if (obj == NULL) {
370 DRM_ERROR("Failed to allocate seqno page\n");
371 ret = -ENOMEM;
372 goto err;
373 }
374
375 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
376
377 ret = i915_gem_object_pin(obj, 4096, true);
378 if (ret)
379 goto err_unref;
380
381 pc->gtt_offset = obj->gtt_offset;
382 pc->cpu_page = kmap(obj->pages[0]);
383 if (pc->cpu_page == NULL)
384 goto err_unpin;
385
386 pc->obj = obj;
387 ring->private = pc;
388 return 0;
389
390 err_unpin:
391 i915_gem_object_unpin(obj);
392 err_unref:
393 drm_gem_object_unreference(&obj->base);
394 err:
395 kfree(pc);
396 return ret;
397 }
398
399 static void
400 cleanup_pipe_control(struct intel_ring_buffer *ring)
401 {
402 struct pipe_control *pc = ring->private;
403 struct drm_i915_gem_object *obj;
404
405 if (!ring->private)
406 return;
407
408 obj = pc->obj;
409 kunmap(obj->pages[0]);
410 i915_gem_object_unpin(obj);
411 drm_gem_object_unreference(&obj->base);
412
413 kfree(pc);
414 ring->private = NULL;
415 }
416
417 static int init_render_ring(struct intel_ring_buffer *ring)
418 {
419 struct drm_device *dev = ring->dev;
420 struct drm_i915_private *dev_priv = dev->dev_private;
421 int ret = init_ring_common(ring);
422
423 if (INTEL_INFO(dev)->gen > 3) {
424 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
425 if (IS_GEN7(dev))
426 I915_WRITE(GFX_MODE_GEN7,
427 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
428 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
429 }
430
431 if (INTEL_INFO(dev)->gen >= 5) {
432 ret = init_pipe_control(ring);
433 if (ret)
434 return ret;
435 }
436
437 if (IS_GEN6(dev)) {
438 /* From the Sandybridge PRM, volume 1 part 3, page 24:
439 * "If this bit is set, STCunit will have LRA as replacement
440 * policy. [...] This bit must be reset. LRA replacement
441 * policy is not supported."
442 */
443 I915_WRITE(CACHE_MODE_0,
444 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
445
446 /* This is not explicitly set for GEN6, so read the register.
447 * see intel_ring_mi_set_context() for why we care.
448 * TODO: consider explicitly setting the bit for GEN5
449 */
450 ring->itlb_before_ctx_switch =
451 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
452 }
453
454 if (INTEL_INFO(dev)->gen >= 6)
455 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
456
457 if (IS_IVYBRIDGE(dev))
458 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
459
460 return ret;
461 }
462
463 static void render_ring_cleanup(struct intel_ring_buffer *ring)
464 {
465 if (!ring->private)
466 return;
467
468 cleanup_pipe_control(ring);
469 }
470
471 static void
472 update_mboxes(struct intel_ring_buffer *ring,
473 u32 seqno,
474 u32 mmio_offset)
475 {
476 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
477 MI_SEMAPHORE_GLOBAL_GTT |
478 MI_SEMAPHORE_REGISTER |
479 MI_SEMAPHORE_UPDATE);
480 intel_ring_emit(ring, seqno);
481 intel_ring_emit(ring, mmio_offset);
482 }
483
484 /**
485 * gen6_add_request - Update the semaphore mailbox registers
486 *
487 * @ring - ring that is adding a request
488 * @seqno - return seqno stuck into the ring
489 *
490 * Update the mailbox registers in the *other* rings with the current seqno.
491 * This acts like a signal in the canonical semaphore.
492 */
493 static int
494 gen6_add_request(struct intel_ring_buffer *ring,
495 u32 *seqno)
496 {
497 u32 mbox1_reg;
498 u32 mbox2_reg;
499 int ret;
500
501 ret = intel_ring_begin(ring, 10);
502 if (ret)
503 return ret;
504
505 mbox1_reg = ring->signal_mbox[0];
506 mbox2_reg = ring->signal_mbox[1];
507
508 *seqno = i915_gem_next_request_seqno(ring);
509
510 update_mboxes(ring, *seqno, mbox1_reg);
511 update_mboxes(ring, *seqno, mbox2_reg);
512 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
513 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
514 intel_ring_emit(ring, *seqno);
515 intel_ring_emit(ring, MI_USER_INTERRUPT);
516 intel_ring_advance(ring);
517
518 return 0;
519 }
520
521 /**
522 * intel_ring_sync - sync the waiter to the signaller on seqno
523 *
524 * @waiter - ring that is waiting
525 * @signaller - ring which has, or will signal
526 * @seqno - seqno which the waiter will block on
527 */
528 static int
529 gen6_ring_sync(struct intel_ring_buffer *waiter,
530 struct intel_ring_buffer *signaller,
531 u32 seqno)
532 {
533 int ret;
534 u32 dw1 = MI_SEMAPHORE_MBOX |
535 MI_SEMAPHORE_COMPARE |
536 MI_SEMAPHORE_REGISTER;
537
538 /* Throughout all of the GEM code, seqno passed implies our current
539 * seqno is >= the last seqno executed. However for hardware the
540 * comparison is strictly greater than.
541 */
542 seqno -= 1;
543
544 WARN_ON(signaller->semaphore_register[waiter->id] ==
545 MI_SEMAPHORE_SYNC_INVALID);
546
547 ret = intel_ring_begin(waiter, 4);
548 if (ret)
549 return ret;
550
551 intel_ring_emit(waiter,
552 dw1 | signaller->semaphore_register[waiter->id]);
553 intel_ring_emit(waiter, seqno);
554 intel_ring_emit(waiter, 0);
555 intel_ring_emit(waiter, MI_NOOP);
556 intel_ring_advance(waiter);
557
558 return 0;
559 }
560
561 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
562 do { \
563 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
564 PIPE_CONTROL_DEPTH_STALL); \
565 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
566 intel_ring_emit(ring__, 0); \
567 intel_ring_emit(ring__, 0); \
568 } while (0)
569
570 static int
571 pc_render_add_request(struct intel_ring_buffer *ring,
572 u32 *result)
573 {
574 u32 seqno = i915_gem_next_request_seqno(ring);
575 struct pipe_control *pc = ring->private;
576 u32 scratch_addr = pc->gtt_offset + 128;
577 int ret;
578
579 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
580 * incoherent with writes to memory, i.e. completely fubar,
581 * so we need to use PIPE_NOTIFY instead.
582 *
583 * However, we also need to workaround the qword write
584 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
585 * memory before requesting an interrupt.
586 */
587 ret = intel_ring_begin(ring, 32);
588 if (ret)
589 return ret;
590
591 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
592 PIPE_CONTROL_WRITE_FLUSH |
593 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
594 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
595 intel_ring_emit(ring, seqno);
596 intel_ring_emit(ring, 0);
597 PIPE_CONTROL_FLUSH(ring, scratch_addr);
598 scratch_addr += 128; /* write to separate cachelines */
599 PIPE_CONTROL_FLUSH(ring, scratch_addr);
600 scratch_addr += 128;
601 PIPE_CONTROL_FLUSH(ring, scratch_addr);
602 scratch_addr += 128;
603 PIPE_CONTROL_FLUSH(ring, scratch_addr);
604 scratch_addr += 128;
605 PIPE_CONTROL_FLUSH(ring, scratch_addr);
606 scratch_addr += 128;
607 PIPE_CONTROL_FLUSH(ring, scratch_addr);
608
609 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
610 PIPE_CONTROL_WRITE_FLUSH |
611 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
612 PIPE_CONTROL_NOTIFY);
613 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
614 intel_ring_emit(ring, seqno);
615 intel_ring_emit(ring, 0);
616 intel_ring_advance(ring);
617
618 *result = seqno;
619 return 0;
620 }
621
622 static u32
623 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
624 {
625 struct drm_device *dev = ring->dev;
626
627 /* Workaround to force correct ordering between irq and seqno writes on
628 * ivb (and maybe also on snb) by reading from a CS register (like
629 * ACTHD) before reading the status page. */
630 if (IS_GEN6(dev) || IS_GEN7(dev))
631 intel_ring_get_active_head(ring);
632 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
633 }
634
635 static u32
636 ring_get_seqno(struct intel_ring_buffer *ring)
637 {
638 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
639 }
640
641 static u32
642 pc_render_get_seqno(struct intel_ring_buffer *ring)
643 {
644 struct pipe_control *pc = ring->private;
645 return pc->cpu_page[0];
646 }
647
648 static bool
649 gen5_ring_get_irq(struct intel_ring_buffer *ring)
650 {
651 struct drm_device *dev = ring->dev;
652 drm_i915_private_t *dev_priv = dev->dev_private;
653 unsigned long flags;
654
655 if (!dev->irq_enabled)
656 return false;
657
658 spin_lock_irqsave(&dev_priv->irq_lock, flags);
659 if (ring->irq_refcount++ == 0) {
660 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
661 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
662 POSTING_READ(GTIMR);
663 }
664 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
665
666 return true;
667 }
668
669 static void
670 gen5_ring_put_irq(struct intel_ring_buffer *ring)
671 {
672 struct drm_device *dev = ring->dev;
673 drm_i915_private_t *dev_priv = dev->dev_private;
674 unsigned long flags;
675
676 spin_lock_irqsave(&dev_priv->irq_lock, flags);
677 if (--ring->irq_refcount == 0) {
678 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
679 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
680 POSTING_READ(GTIMR);
681 }
682 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
683 }
684
685 static bool
686 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
687 {
688 struct drm_device *dev = ring->dev;
689 drm_i915_private_t *dev_priv = dev->dev_private;
690 unsigned long flags;
691
692 if (!dev->irq_enabled)
693 return false;
694
695 spin_lock_irqsave(&dev_priv->irq_lock, flags);
696 if (ring->irq_refcount++ == 0) {
697 dev_priv->irq_mask &= ~ring->irq_enable_mask;
698 I915_WRITE(IMR, dev_priv->irq_mask);
699 POSTING_READ(IMR);
700 }
701 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
702
703 return true;
704 }
705
706 static void
707 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
708 {
709 struct drm_device *dev = ring->dev;
710 drm_i915_private_t *dev_priv = dev->dev_private;
711 unsigned long flags;
712
713 spin_lock_irqsave(&dev_priv->irq_lock, flags);
714 if (--ring->irq_refcount == 0) {
715 dev_priv->irq_mask |= ring->irq_enable_mask;
716 I915_WRITE(IMR, dev_priv->irq_mask);
717 POSTING_READ(IMR);
718 }
719 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
720 }
721
722 static bool
723 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
724 {
725 struct drm_device *dev = ring->dev;
726 drm_i915_private_t *dev_priv = dev->dev_private;
727 unsigned long flags;
728
729 if (!dev->irq_enabled)
730 return false;
731
732 spin_lock_irqsave(&dev_priv->irq_lock, flags);
733 if (ring->irq_refcount++ == 0) {
734 dev_priv->irq_mask &= ~ring->irq_enable_mask;
735 I915_WRITE16(IMR, dev_priv->irq_mask);
736 POSTING_READ16(IMR);
737 }
738 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
739
740 return true;
741 }
742
743 static void
744 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
745 {
746 struct drm_device *dev = ring->dev;
747 drm_i915_private_t *dev_priv = dev->dev_private;
748 unsigned long flags;
749
750 spin_lock_irqsave(&dev_priv->irq_lock, flags);
751 if (--ring->irq_refcount == 0) {
752 dev_priv->irq_mask |= ring->irq_enable_mask;
753 I915_WRITE16(IMR, dev_priv->irq_mask);
754 POSTING_READ16(IMR);
755 }
756 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
757 }
758
759 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
760 {
761 struct drm_device *dev = ring->dev;
762 drm_i915_private_t *dev_priv = ring->dev->dev_private;
763 u32 mmio = 0;
764
765 /* The ring status page addresses are no longer next to the rest of
766 * the ring registers as of gen7.
767 */
768 if (IS_GEN7(dev)) {
769 switch (ring->id) {
770 case RCS:
771 mmio = RENDER_HWS_PGA_GEN7;
772 break;
773 case BCS:
774 mmio = BLT_HWS_PGA_GEN7;
775 break;
776 case VCS:
777 mmio = BSD_HWS_PGA_GEN7;
778 break;
779 }
780 } else if (IS_GEN6(ring->dev)) {
781 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
782 } else {
783 mmio = RING_HWS_PGA(ring->mmio_base);
784 }
785
786 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
787 POSTING_READ(mmio);
788 }
789
790 static int
791 bsd_ring_flush(struct intel_ring_buffer *ring,
792 u32 invalidate_domains,
793 u32 flush_domains)
794 {
795 int ret;
796
797 ret = intel_ring_begin(ring, 2);
798 if (ret)
799 return ret;
800
801 intel_ring_emit(ring, MI_FLUSH);
802 intel_ring_emit(ring, MI_NOOP);
803 intel_ring_advance(ring);
804 return 0;
805 }
806
807 static int
808 i9xx_add_request(struct intel_ring_buffer *ring,
809 u32 *result)
810 {
811 u32 seqno;
812 int ret;
813
814 ret = intel_ring_begin(ring, 4);
815 if (ret)
816 return ret;
817
818 seqno = i915_gem_next_request_seqno(ring);
819
820 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
821 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
822 intel_ring_emit(ring, seqno);
823 intel_ring_emit(ring, MI_USER_INTERRUPT);
824 intel_ring_advance(ring);
825
826 *result = seqno;
827 return 0;
828 }
829
830 static bool
831 gen6_ring_get_irq(struct intel_ring_buffer *ring)
832 {
833 struct drm_device *dev = ring->dev;
834 drm_i915_private_t *dev_priv = dev->dev_private;
835 unsigned long flags;
836
837 if (!dev->irq_enabled)
838 return false;
839
840 /* It looks like we need to prevent the gt from suspending while waiting
841 * for an notifiy irq, otherwise irqs seem to get lost on at least the
842 * blt/bsd rings on ivb. */
843 gen6_gt_force_wake_get(dev_priv);
844
845 spin_lock_irqsave(&dev_priv->irq_lock, flags);
846 if (ring->irq_refcount++ == 0) {
847 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
848 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
849 GEN6_RENDER_L3_PARITY_ERROR));
850 else
851 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
852 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
853 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
854 POSTING_READ(GTIMR);
855 }
856 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
857
858 return true;
859 }
860
861 static void
862 gen6_ring_put_irq(struct intel_ring_buffer *ring)
863 {
864 struct drm_device *dev = ring->dev;
865 drm_i915_private_t *dev_priv = dev->dev_private;
866 unsigned long flags;
867
868 spin_lock_irqsave(&dev_priv->irq_lock, flags);
869 if (--ring->irq_refcount == 0) {
870 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
871 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
872 else
873 I915_WRITE_IMR(ring, ~0);
874 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
875 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
876 POSTING_READ(GTIMR);
877 }
878 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
879
880 gen6_gt_force_wake_put(dev_priv);
881 }
882
883 static int
884 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
885 {
886 int ret;
887
888 ret = intel_ring_begin(ring, 2);
889 if (ret)
890 return ret;
891
892 intel_ring_emit(ring,
893 MI_BATCH_BUFFER_START |
894 MI_BATCH_GTT |
895 MI_BATCH_NON_SECURE_I965);
896 intel_ring_emit(ring, offset);
897 intel_ring_advance(ring);
898
899 return 0;
900 }
901
902 static int
903 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
904 u32 offset, u32 len)
905 {
906 int ret;
907
908 ret = intel_ring_begin(ring, 4);
909 if (ret)
910 return ret;
911
912 intel_ring_emit(ring, MI_BATCH_BUFFER);
913 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
914 intel_ring_emit(ring, offset + len - 8);
915 intel_ring_emit(ring, 0);
916 intel_ring_advance(ring);
917
918 return 0;
919 }
920
921 static int
922 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
923 u32 offset, u32 len)
924 {
925 int ret;
926
927 ret = intel_ring_begin(ring, 2);
928 if (ret)
929 return ret;
930
931 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
932 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
933 intel_ring_advance(ring);
934
935 return 0;
936 }
937
938 static void cleanup_status_page(struct intel_ring_buffer *ring)
939 {
940 struct drm_i915_gem_object *obj;
941
942 obj = ring->status_page.obj;
943 if (obj == NULL)
944 return;
945
946 kunmap(obj->pages[0]);
947 i915_gem_object_unpin(obj);
948 drm_gem_object_unreference(&obj->base);
949 ring->status_page.obj = NULL;
950 }
951
952 static int init_status_page(struct intel_ring_buffer *ring)
953 {
954 struct drm_device *dev = ring->dev;
955 struct drm_i915_gem_object *obj;
956 int ret;
957
958 obj = i915_gem_alloc_object(dev, 4096);
959 if (obj == NULL) {
960 DRM_ERROR("Failed to allocate status page\n");
961 ret = -ENOMEM;
962 goto err;
963 }
964
965 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
966
967 ret = i915_gem_object_pin(obj, 4096, true);
968 if (ret != 0) {
969 goto err_unref;
970 }
971
972 ring->status_page.gfx_addr = obj->gtt_offset;
973 ring->status_page.page_addr = kmap(obj->pages[0]);
974 if (ring->status_page.page_addr == NULL) {
975 ret = -ENOMEM;
976 goto err_unpin;
977 }
978 ring->status_page.obj = obj;
979 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
980
981 intel_ring_setup_status_page(ring);
982 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
983 ring->name, ring->status_page.gfx_addr);
984
985 return 0;
986
987 err_unpin:
988 i915_gem_object_unpin(obj);
989 err_unref:
990 drm_gem_object_unreference(&obj->base);
991 err:
992 return ret;
993 }
994
995 static int intel_init_ring_buffer(struct drm_device *dev,
996 struct intel_ring_buffer *ring)
997 {
998 struct drm_i915_gem_object *obj;
999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 int ret;
1001
1002 ring->dev = dev;
1003 INIT_LIST_HEAD(&ring->active_list);
1004 INIT_LIST_HEAD(&ring->request_list);
1005 INIT_LIST_HEAD(&ring->gpu_write_list);
1006 ring->size = 32 * PAGE_SIZE;
1007
1008 init_waitqueue_head(&ring->irq_queue);
1009
1010 if (I915_NEED_GFX_HWS(dev)) {
1011 ret = init_status_page(ring);
1012 if (ret)
1013 return ret;
1014 }
1015
1016 obj = i915_gem_alloc_object(dev, ring->size);
1017 if (obj == NULL) {
1018 DRM_ERROR("Failed to allocate ringbuffer\n");
1019 ret = -ENOMEM;
1020 goto err_hws;
1021 }
1022
1023 ring->obj = obj;
1024
1025 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1026 if (ret)
1027 goto err_unref;
1028
1029 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1030 if (ret)
1031 goto err_unpin;
1032
1033 ring->virtual_start =
1034 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1035 ring->size);
1036 if (ring->virtual_start == NULL) {
1037 DRM_ERROR("Failed to map ringbuffer.\n");
1038 ret = -EINVAL;
1039 goto err_unpin;
1040 }
1041
1042 ret = ring->init(ring);
1043 if (ret)
1044 goto err_unmap;
1045
1046 /* Workaround an erratum on the i830 which causes a hang if
1047 * the TAIL pointer points to within the last 2 cachelines
1048 * of the buffer.
1049 */
1050 ring->effective_size = ring->size;
1051 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1052 ring->effective_size -= 128;
1053
1054 return 0;
1055
1056 err_unmap:
1057 iounmap(ring->virtual_start);
1058 err_unpin:
1059 i915_gem_object_unpin(obj);
1060 err_unref:
1061 drm_gem_object_unreference(&obj->base);
1062 ring->obj = NULL;
1063 err_hws:
1064 cleanup_status_page(ring);
1065 return ret;
1066 }
1067
1068 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1069 {
1070 struct drm_i915_private *dev_priv;
1071 int ret;
1072
1073 if (ring->obj == NULL)
1074 return;
1075
1076 /* Disable the ring buffer. The ring must be idle at this point */
1077 dev_priv = ring->dev->dev_private;
1078 ret = intel_wait_ring_idle(ring);
1079 if (ret)
1080 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1081 ring->name, ret);
1082
1083 I915_WRITE_CTL(ring, 0);
1084
1085 iounmap(ring->virtual_start);
1086
1087 i915_gem_object_unpin(ring->obj);
1088 drm_gem_object_unreference(&ring->obj->base);
1089 ring->obj = NULL;
1090
1091 if (ring->cleanup)
1092 ring->cleanup(ring);
1093
1094 cleanup_status_page(ring);
1095 }
1096
1097 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1098 {
1099 uint32_t __iomem *virt;
1100 int rem = ring->size - ring->tail;
1101
1102 if (ring->space < rem) {
1103 int ret = intel_wait_ring_buffer(ring, rem);
1104 if (ret)
1105 return ret;
1106 }
1107
1108 virt = ring->virtual_start + ring->tail;
1109 rem /= 4;
1110 while (rem--)
1111 iowrite32(MI_NOOP, virt++);
1112
1113 ring->tail = 0;
1114 ring->space = ring_space(ring);
1115
1116 return 0;
1117 }
1118
1119 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1120 {
1121 int ret;
1122
1123 ret = i915_wait_seqno(ring, seqno);
1124 if (!ret)
1125 i915_gem_retire_requests_ring(ring);
1126
1127 return ret;
1128 }
1129
1130 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1131 {
1132 struct drm_i915_gem_request *request;
1133 u32 seqno = 0;
1134 int ret;
1135
1136 i915_gem_retire_requests_ring(ring);
1137
1138 if (ring->last_retired_head != -1) {
1139 ring->head = ring->last_retired_head;
1140 ring->last_retired_head = -1;
1141 ring->space = ring_space(ring);
1142 if (ring->space >= n)
1143 return 0;
1144 }
1145
1146 list_for_each_entry(request, &ring->request_list, list) {
1147 int space;
1148
1149 if (request->tail == -1)
1150 continue;
1151
1152 space = request->tail - (ring->tail + 8);
1153 if (space < 0)
1154 space += ring->size;
1155 if (space >= n) {
1156 seqno = request->seqno;
1157 break;
1158 }
1159
1160 /* Consume this request in case we need more space than
1161 * is available and so need to prevent a race between
1162 * updating last_retired_head and direct reads of
1163 * I915_RING_HEAD. It also provides a nice sanity check.
1164 */
1165 request->tail = -1;
1166 }
1167
1168 if (seqno == 0)
1169 return -ENOSPC;
1170
1171 ret = intel_ring_wait_seqno(ring, seqno);
1172 if (ret)
1173 return ret;
1174
1175 if (WARN_ON(ring->last_retired_head == -1))
1176 return -ENOSPC;
1177
1178 ring->head = ring->last_retired_head;
1179 ring->last_retired_head = -1;
1180 ring->space = ring_space(ring);
1181 if (WARN_ON(ring->space < n))
1182 return -ENOSPC;
1183
1184 return 0;
1185 }
1186
1187 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1188 {
1189 struct drm_device *dev = ring->dev;
1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 unsigned long end;
1192 int ret;
1193
1194 ret = intel_ring_wait_request(ring, n);
1195 if (ret != -ENOSPC)
1196 return ret;
1197
1198 trace_i915_ring_wait_begin(ring);
1199 /* With GEM the hangcheck timer should kick us out of the loop,
1200 * leaving it early runs the risk of corrupting GEM state (due
1201 * to running on almost untested codepaths). But on resume
1202 * timers don't work yet, so prevent a complete hang in that
1203 * case by choosing an insanely large timeout. */
1204 end = jiffies + 60 * HZ;
1205
1206 do {
1207 ring->head = I915_READ_HEAD(ring);
1208 ring->space = ring_space(ring);
1209 if (ring->space >= n) {
1210 trace_i915_ring_wait_end(ring);
1211 return 0;
1212 }
1213
1214 if (dev->primary->master) {
1215 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1216 if (master_priv->sarea_priv)
1217 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1218 }
1219
1220 msleep(1);
1221
1222 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1223 if (ret)
1224 return ret;
1225 } while (!time_after(jiffies, end));
1226 trace_i915_ring_wait_end(ring);
1227 return -EBUSY;
1228 }
1229
1230 int intel_ring_begin(struct intel_ring_buffer *ring,
1231 int num_dwords)
1232 {
1233 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1234 int n = 4*num_dwords;
1235 int ret;
1236
1237 ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1238 if (ret)
1239 return ret;
1240
1241 if (unlikely(ring->tail + n > ring->effective_size)) {
1242 ret = intel_wrap_ring_buffer(ring);
1243 if (unlikely(ret))
1244 return ret;
1245 }
1246
1247 if (unlikely(ring->space < n)) {
1248 ret = intel_wait_ring_buffer(ring, n);
1249 if (unlikely(ret))
1250 return ret;
1251 }
1252
1253 ring->space -= n;
1254 return 0;
1255 }
1256
1257 void intel_ring_advance(struct intel_ring_buffer *ring)
1258 {
1259 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1260
1261 ring->tail &= ring->size - 1;
1262 if (dev_priv->stop_rings & intel_ring_flag(ring))
1263 return;
1264 ring->write_tail(ring, ring->tail);
1265 }
1266
1267
1268 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1269 u32 value)
1270 {
1271 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1272
1273 /* Every tail move must follow the sequence below */
1274
1275 /* Disable notification that the ring is IDLE. The GT
1276 * will then assume that it is busy and bring it out of rc6.
1277 */
1278 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1279 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1280
1281 /* Clear the context id. Here be magic! */
1282 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1283
1284 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1285 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1286 GEN6_BSD_SLEEP_INDICATOR) == 0,
1287 50))
1288 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1289
1290 /* Now that the ring is fully powered up, update the tail */
1291 I915_WRITE_TAIL(ring, value);
1292 POSTING_READ(RING_TAIL(ring->mmio_base));
1293
1294 /* Let the ring send IDLE messages to the GT again,
1295 * and so let it sleep to conserve power when idle.
1296 */
1297 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1298 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1299 }
1300
1301 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1302 u32 invalidate, u32 flush)
1303 {
1304 uint32_t cmd;
1305 int ret;
1306
1307 ret = intel_ring_begin(ring, 4);
1308 if (ret)
1309 return ret;
1310
1311 cmd = MI_FLUSH_DW;
1312 if (invalidate & I915_GEM_GPU_DOMAINS)
1313 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1314 intel_ring_emit(ring, cmd);
1315 intel_ring_emit(ring, 0);
1316 intel_ring_emit(ring, 0);
1317 intel_ring_emit(ring, MI_NOOP);
1318 intel_ring_advance(ring);
1319 return 0;
1320 }
1321
1322 static int
1323 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1324 u32 offset, u32 len)
1325 {
1326 int ret;
1327
1328 ret = intel_ring_begin(ring, 2);
1329 if (ret)
1330 return ret;
1331
1332 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1333 /* bit0-7 is the length on GEN6+ */
1334 intel_ring_emit(ring, offset);
1335 intel_ring_advance(ring);
1336
1337 return 0;
1338 }
1339
1340 /* Blitter support (SandyBridge+) */
1341
1342 static int blt_ring_flush(struct intel_ring_buffer *ring,
1343 u32 invalidate, u32 flush)
1344 {
1345 uint32_t cmd;
1346 int ret;
1347
1348 ret = intel_ring_begin(ring, 4);
1349 if (ret)
1350 return ret;
1351
1352 cmd = MI_FLUSH_DW;
1353 if (invalidate & I915_GEM_DOMAIN_RENDER)
1354 cmd |= MI_INVALIDATE_TLB;
1355 intel_ring_emit(ring, cmd);
1356 intel_ring_emit(ring, 0);
1357 intel_ring_emit(ring, 0);
1358 intel_ring_emit(ring, MI_NOOP);
1359 intel_ring_advance(ring);
1360 return 0;
1361 }
1362
1363 int intel_init_render_ring_buffer(struct drm_device *dev)
1364 {
1365 drm_i915_private_t *dev_priv = dev->dev_private;
1366 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1367
1368 ring->name = "render ring";
1369 ring->id = RCS;
1370 ring->mmio_base = RENDER_RING_BASE;
1371
1372 if (INTEL_INFO(dev)->gen >= 6) {
1373 ring->add_request = gen6_add_request;
1374 ring->flush = gen6_render_ring_flush;
1375 ring->irq_get = gen6_ring_get_irq;
1376 ring->irq_put = gen6_ring_put_irq;
1377 ring->irq_enable_mask = GT_USER_INTERRUPT;
1378 ring->get_seqno = gen6_ring_get_seqno;
1379 ring->sync_to = gen6_ring_sync;
1380 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1381 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1382 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1383 ring->signal_mbox[0] = GEN6_VRSYNC;
1384 ring->signal_mbox[1] = GEN6_BRSYNC;
1385 } else if (IS_GEN5(dev)) {
1386 ring->add_request = pc_render_add_request;
1387 ring->flush = gen4_render_ring_flush;
1388 ring->get_seqno = pc_render_get_seqno;
1389 ring->irq_get = gen5_ring_get_irq;
1390 ring->irq_put = gen5_ring_put_irq;
1391 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1392 } else {
1393 ring->add_request = i9xx_add_request;
1394 if (INTEL_INFO(dev)->gen < 4)
1395 ring->flush = gen2_render_ring_flush;
1396 else
1397 ring->flush = gen4_render_ring_flush;
1398 ring->get_seqno = ring_get_seqno;
1399 if (IS_GEN2(dev)) {
1400 ring->irq_get = i8xx_ring_get_irq;
1401 ring->irq_put = i8xx_ring_put_irq;
1402 } else {
1403 ring->irq_get = i9xx_ring_get_irq;
1404 ring->irq_put = i9xx_ring_put_irq;
1405 }
1406 ring->irq_enable_mask = I915_USER_INTERRUPT;
1407 }
1408 ring->write_tail = ring_write_tail;
1409 if (INTEL_INFO(dev)->gen >= 6)
1410 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1411 else if (INTEL_INFO(dev)->gen >= 4)
1412 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1413 else if (IS_I830(dev) || IS_845G(dev))
1414 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1415 else
1416 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1417 ring->init = init_render_ring;
1418 ring->cleanup = render_ring_cleanup;
1419
1420
1421 if (!I915_NEED_GFX_HWS(dev)) {
1422 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1423 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1424 }
1425
1426 return intel_init_ring_buffer(dev, ring);
1427 }
1428
1429 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1430 {
1431 drm_i915_private_t *dev_priv = dev->dev_private;
1432 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1433
1434 ring->name = "render ring";
1435 ring->id = RCS;
1436 ring->mmio_base = RENDER_RING_BASE;
1437
1438 if (INTEL_INFO(dev)->gen >= 6) {
1439 /* non-kms not supported on gen6+ */
1440 return -ENODEV;
1441 }
1442
1443 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1444 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1445 * the special gen5 functions. */
1446 ring->add_request = i9xx_add_request;
1447 if (INTEL_INFO(dev)->gen < 4)
1448 ring->flush = gen2_render_ring_flush;
1449 else
1450 ring->flush = gen4_render_ring_flush;
1451 ring->get_seqno = ring_get_seqno;
1452 if (IS_GEN2(dev)) {
1453 ring->irq_get = i8xx_ring_get_irq;
1454 ring->irq_put = i8xx_ring_put_irq;
1455 } else {
1456 ring->irq_get = i9xx_ring_get_irq;
1457 ring->irq_put = i9xx_ring_put_irq;
1458 }
1459 ring->irq_enable_mask = I915_USER_INTERRUPT;
1460 ring->write_tail = ring_write_tail;
1461 if (INTEL_INFO(dev)->gen >= 4)
1462 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1463 else if (IS_I830(dev) || IS_845G(dev))
1464 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1465 else
1466 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1467 ring->init = init_render_ring;
1468 ring->cleanup = render_ring_cleanup;
1469
1470 if (!I915_NEED_GFX_HWS(dev))
1471 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1472
1473 ring->dev = dev;
1474 INIT_LIST_HEAD(&ring->active_list);
1475 INIT_LIST_HEAD(&ring->request_list);
1476 INIT_LIST_HEAD(&ring->gpu_write_list);
1477
1478 ring->size = size;
1479 ring->effective_size = ring->size;
1480 if (IS_I830(ring->dev))
1481 ring->effective_size -= 128;
1482
1483 ring->virtual_start = ioremap_wc(start, size);
1484 if (ring->virtual_start == NULL) {
1485 DRM_ERROR("can not ioremap virtual address for"
1486 " ring buffer\n");
1487 return -ENOMEM;
1488 }
1489
1490 return 0;
1491 }
1492
1493 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1494 {
1495 drm_i915_private_t *dev_priv = dev->dev_private;
1496 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1497
1498 ring->name = "bsd ring";
1499 ring->id = VCS;
1500
1501 ring->write_tail = ring_write_tail;
1502 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1503 ring->mmio_base = GEN6_BSD_RING_BASE;
1504 /* gen6 bsd needs a special wa for tail updates */
1505 if (IS_GEN6(dev))
1506 ring->write_tail = gen6_bsd_ring_write_tail;
1507 ring->flush = gen6_ring_flush;
1508 ring->add_request = gen6_add_request;
1509 ring->get_seqno = gen6_ring_get_seqno;
1510 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1511 ring->irq_get = gen6_ring_get_irq;
1512 ring->irq_put = gen6_ring_put_irq;
1513 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1514 ring->sync_to = gen6_ring_sync;
1515 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1516 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1517 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1518 ring->signal_mbox[0] = GEN6_RVSYNC;
1519 ring->signal_mbox[1] = GEN6_BVSYNC;
1520 } else {
1521 ring->mmio_base = BSD_RING_BASE;
1522 ring->flush = bsd_ring_flush;
1523 ring->add_request = i9xx_add_request;
1524 ring->get_seqno = ring_get_seqno;
1525 if (IS_GEN5(dev)) {
1526 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1527 ring->irq_get = gen5_ring_get_irq;
1528 ring->irq_put = gen5_ring_put_irq;
1529 } else {
1530 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1531 ring->irq_get = i9xx_ring_get_irq;
1532 ring->irq_put = i9xx_ring_put_irq;
1533 }
1534 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1535 }
1536 ring->init = init_ring_common;
1537
1538
1539 return intel_init_ring_buffer(dev, ring);
1540 }
1541
1542 int intel_init_blt_ring_buffer(struct drm_device *dev)
1543 {
1544 drm_i915_private_t *dev_priv = dev->dev_private;
1545 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1546
1547 ring->name = "blitter ring";
1548 ring->id = BCS;
1549
1550 ring->mmio_base = BLT_RING_BASE;
1551 ring->write_tail = ring_write_tail;
1552 ring->flush = blt_ring_flush;
1553 ring->add_request = gen6_add_request;
1554 ring->get_seqno = gen6_ring_get_seqno;
1555 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1556 ring->irq_get = gen6_ring_get_irq;
1557 ring->irq_put = gen6_ring_put_irq;
1558 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1559 ring->sync_to = gen6_ring_sync;
1560 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1561 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1562 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1563 ring->signal_mbox[0] = GEN6_RBSYNC;
1564 ring->signal_mbox[1] = GEN6_VBSYNC;
1565 ring->init = init_ring_common;
1566
1567 return intel_init_ring_buffer(dev, ring);
1568 }
Linux kernel - Deliverables
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