1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
5 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
6 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
7 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
9 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
10 * cacheline, the Head Pointer must not be greater than the Tail
13 #define I915_RING_FREE_SPACE 64
15 struct intel_hw_status_page
{
17 unsigned int gfx_addr
;
18 struct drm_i915_gem_object
*obj
;
21 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
22 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
24 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
25 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
27 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
28 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
30 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
31 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
33 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
34 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
36 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
37 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
39 enum intel_ring_hangcheck_action
{
47 #define HANGCHECK_SCORE_RING_HUNG 31
49 struct intel_ring_hangcheck
{
53 enum intel_ring_hangcheck_action action
;
57 struct intel_ring_buffer
{
66 #define I915_NUM_RINGS 5
67 #define LAST_USER_RING (VECS + 1)
69 void __iomem
*virtual_start
;
70 struct drm_device
*dev
;
71 struct drm_i915_gem_object
*obj
;
78 struct intel_hw_status_page status_page
;
80 /** We track the position of the requests in the ring buffer, and
81 * when each is retired we increment last_retired_head as the GPU
82 * must have finished processing the request and so we know we
83 * can advance the ringbuffer up to that position.
85 * last_retired_head is set to -1 after the value is consumed so
86 * we can detect new retirements.
88 u32 last_retired_head
;
90 unsigned irq_refcount
; /* protected by dev_priv->irq_lock */
91 u32 irq_enable_mask
; /* bitmask to enable ring interrupt */
93 u32 sync_seqno
[I915_NUM_RINGS
-1];
94 bool __must_check (*irq_get
)(struct intel_ring_buffer
*ring
);
95 void (*irq_put
)(struct intel_ring_buffer
*ring
);
97 int (*init
)(struct intel_ring_buffer
*ring
);
99 void (*write_tail
)(struct intel_ring_buffer
*ring
,
101 int __must_check (*flush
)(struct intel_ring_buffer
*ring
,
102 u32 invalidate_domains
,
104 int (*add_request
)(struct intel_ring_buffer
*ring
);
105 /* Some chipsets are not quite as coherent as advertised and need
106 * an expensive kick to force a true read of the up-to-date seqno.
107 * However, the up-to-date seqno is not always required and the last
108 * seen value is good enough. Note that the seqno will always be
109 * monotonic, even if not coherent.
111 u32 (*get_seqno
)(struct intel_ring_buffer
*ring
,
112 bool lazy_coherency
);
113 void (*set_seqno
)(struct intel_ring_buffer
*ring
,
115 int (*dispatch_execbuffer
)(struct intel_ring_buffer
*ring
,
116 u32 offset
, u32 length
,
118 #define I915_DISPATCH_SECURE 0x1
119 #define I915_DISPATCH_PINNED 0x2
120 void (*cleanup
)(struct intel_ring_buffer
*ring
);
121 int (*sync_to
)(struct intel_ring_buffer
*ring
,
122 struct intel_ring_buffer
*to
,
125 /* our mbox written by others */
126 u32 semaphore_register
[I915_NUM_RINGS
];
127 /* mboxes this ring signals to */
128 u32 signal_mbox
[I915_NUM_RINGS
];
131 * List of objects currently involved in rendering from the
134 * Includes buffers having the contents of their GPU caches
135 * flushed, not necessarily primitives. last_rendering_seqno
136 * represents when the rendering involved will be completed.
138 * A reference is held on the buffer while on this list.
140 struct list_head active_list
;
143 * List of breadcrumbs associated with GPU requests currently
146 struct list_head request_list
;
149 * Do we have some not yet emitted requests outstanding?
151 struct drm_i915_gem_request
*preallocated_lazy_request
;
152 u32 outstanding_lazy_seqno
;
153 bool gpu_caches_dirty
;
156 wait_queue_head_t irq_queue
;
158 struct i915_hw_context
*default_context
;
159 struct i915_hw_context
*last_context
;
161 struct intel_ring_hangcheck hangcheck
;
164 struct drm_i915_gem_object
*obj
;
166 volatile u32
*cpu_page
;
170 * Tables of commands the command parser needs to know about
173 const struct drm_i915_cmd_table
*cmd_tables
;
177 * Table of registers allowed in commands that read/write registers.
179 const u32
*reg_table
;
183 * Table of registers allowed in commands that read/write registers, but
184 * only from the DRM master.
186 const u32
*master_reg_table
;
187 int master_reg_count
;
190 * Returns the bitmask for the length field of the specified command.
191 * Return 0 for an unrecognized/invalid command.
193 * If the command parser finds an entry for a command in the ring's
194 * cmd_tables, it gets the command's length based on the table entry.
195 * If not, it calls this function to determine the per-ring length field
196 * encoding for the command (i.e. certain opcode ranges use certain bits
197 * to encode the command length in the header).
199 u32 (*get_cmd_length_mask
)(u32 cmd_header
);
203 intel_ring_initialized(struct intel_ring_buffer
*ring
)
205 return ring
->obj
!= NULL
;
208 static inline unsigned
209 intel_ring_flag(struct intel_ring_buffer
*ring
)
211 return 1 << ring
->id
;
215 intel_ring_sync_index(struct intel_ring_buffer
*ring
,
216 struct intel_ring_buffer
*other
)
221 * cs -> 0 = vcs, 1 = bcs
222 * vcs -> 0 = bcs, 1 = cs,
223 * bcs -> 0 = cs, 1 = vcs.
226 idx
= (other
- ring
) - 1;
228 idx
+= I915_NUM_RINGS
;
234 intel_read_status_page(struct intel_ring_buffer
*ring
,
237 /* Ensure that the compiler doesn't optimize away the load. */
239 return ring
->status_page
.page_addr
[reg
];
243 intel_write_status_page(struct intel_ring_buffer
*ring
,
246 ring
->status_page
.page_addr
[reg
] = value
;
250 * Reads a dword out of the status page, which is written to from the command
251 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
254 * The following dwords have a reserved meaning:
255 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
256 * 0x04: ring 0 head pointer
257 * 0x05: ring 1 head pointer (915-class)
258 * 0x06: ring 2 head pointer (915-class)
259 * 0x10-0x1b: Context status DWords (GM45)
260 * 0x1f: Last written status offset. (GM45)
262 * The area from dword 0x20 to 0x3ff is available for driver usage.
264 #define I915_GEM_HWS_INDEX 0x20
265 #define I915_GEM_HWS_SCRATCH_INDEX 0x30
266 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
268 void intel_stop_ring_buffer(struct intel_ring_buffer
*ring
);
269 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
);
271 int __must_check
intel_ring_begin(struct intel_ring_buffer
*ring
, int n
);
272 int __must_check
intel_ring_cacheline_align(struct intel_ring_buffer
*ring
);
273 static inline void intel_ring_emit(struct intel_ring_buffer
*ring
,
276 iowrite32(data
, ring
->virtual_start
+ ring
->tail
);
279 static inline void intel_ring_advance(struct intel_ring_buffer
*ring
)
281 ring
->tail
&= ring
->size
- 1;
283 void __intel_ring_advance(struct intel_ring_buffer
*ring
);
285 int __must_check
intel_ring_idle(struct intel_ring_buffer
*ring
);
286 void intel_ring_init_seqno(struct intel_ring_buffer
*ring
, u32 seqno
);
287 int intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
);
288 int intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
);
290 int intel_init_render_ring_buffer(struct drm_device
*dev
);
291 int intel_init_bsd_ring_buffer(struct drm_device
*dev
);
292 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
);
293 int intel_init_blt_ring_buffer(struct drm_device
*dev
);
294 int intel_init_vebox_ring_buffer(struct drm_device
*dev
);
296 u64
intel_ring_get_active_head(struct intel_ring_buffer
*ring
);
297 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
);
299 static inline u32
intel_ring_get_tail(struct intel_ring_buffer
*ring
)
304 static inline u32
intel_ring_get_seqno(struct intel_ring_buffer
*ring
)
306 BUG_ON(ring
->outstanding_lazy_seqno
== 0);
307 return ring
->outstanding_lazy_seqno
;
310 static inline void i915_trace_irq_get(struct intel_ring_buffer
*ring
, u32 seqno
)
312 if (ring
->trace_irq_seqno
== 0 && ring
->irq_get(ring
))
313 ring
->trace_irq_seqno
= seqno
;
317 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
);
319 #endif /* _INTEL_RINGBUFFER_H_ */