1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
6 #define I915_CMD_HASH_ORDER 9
9 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
10 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
11 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
13 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
14 * cacheline, the Head Pointer must not be greater than the Tail
17 #define I915_RING_FREE_SPACE 64
19 struct intel_hw_status_page
{
21 unsigned int gfx_addr
;
22 struct drm_i915_gem_object
*obj
;
25 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
26 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
28 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
29 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
31 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
32 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
34 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
35 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
37 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
38 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
40 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
41 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
43 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
44 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
46 #define i915_semaphore_seqno_size sizeof(uint64_t)
47 #define GEN8_SIGNAL_OFFSET(__ring, to) \
48 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
49 ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
50 (i915_semaphore_seqno_size * (to)))
52 #define GEN8_WAIT_OFFSET(__ring, from) \
53 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
54 ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
55 (i915_semaphore_seqno_size * (__ring)->id))
57 #define GEN8_RING_SEMAPHORE_INIT do { \
58 if (!dev_priv->semaphore_obj) { \
61 ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
62 ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
63 ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
64 ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
65 ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
66 ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
69 enum intel_ring_hangcheck_action
{
73 HANGCHECK_ACTIVE_LOOP
,
78 #define HANGCHECK_SCORE_RING_HUNG 31
80 struct intel_ring_hangcheck
{
85 enum intel_ring_hangcheck_action action
;
89 struct intel_ringbuffer
{
90 struct drm_i915_gem_object
*obj
;
91 void __iomem
*virtual_start
;
93 struct intel_engine_cs
*ring
;
101 /** We track the position of the requests in the ring buffer, and
102 * when each is retired we increment last_retired_head as the GPU
103 * must have finished processing the request and so we know we
104 * can advance the ringbuffer up to that position.
106 * last_retired_head is set to -1 after the value is consumed so
107 * we can detect new retirements.
109 u32 last_retired_head
;
112 struct intel_engine_cs
{
121 #define I915_NUM_RINGS 5
122 #define LAST_USER_RING (VECS + 1)
124 struct drm_device
*dev
;
125 struct intel_ringbuffer
*buffer
;
127 struct intel_hw_status_page status_page
;
129 unsigned irq_refcount
; /* protected by dev_priv->irq_lock */
130 u32 irq_enable_mask
; /* bitmask to enable ring interrupt */
132 bool __must_check (*irq_get
)(struct intel_engine_cs
*ring
);
133 void (*irq_put
)(struct intel_engine_cs
*ring
);
135 int (*init
)(struct intel_engine_cs
*ring
);
137 void (*write_tail
)(struct intel_engine_cs
*ring
,
139 int __must_check (*flush
)(struct intel_engine_cs
*ring
,
140 u32 invalidate_domains
,
142 int (*add_request
)(struct intel_engine_cs
*ring
);
143 /* Some chipsets are not quite as coherent as advertised and need
144 * an expensive kick to force a true read of the up-to-date seqno.
145 * However, the up-to-date seqno is not always required and the last
146 * seen value is good enough. Note that the seqno will always be
147 * monotonic, even if not coherent.
149 u32 (*get_seqno
)(struct intel_engine_cs
*ring
,
150 bool lazy_coherency
);
151 void (*set_seqno
)(struct intel_engine_cs
*ring
,
153 int (*dispatch_execbuffer
)(struct intel_engine_cs
*ring
,
154 u64 offset
, u32 length
,
156 #define I915_DISPATCH_SECURE 0x1
157 #define I915_DISPATCH_PINNED 0x2
158 void (*cleanup
)(struct intel_engine_cs
*ring
);
160 /* GEN8 signal/wait table - never trust comments!
161 * signal to signal to signal to signal to signal to
162 * RCS VCS BCS VECS VCS2
163 * --------------------------------------------------------------------
164 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
165 * |-------------------------------------------------------------------
166 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
167 * |-------------------------------------------------------------------
168 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
169 * |-------------------------------------------------------------------
170 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
171 * |-------------------------------------------------------------------
172 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
173 * |-------------------------------------------------------------------
176 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
177 * ie. transpose of g(x, y)
179 * sync from sync from sync from sync from sync from
180 * RCS VCS BCS VECS VCS2
181 * --------------------------------------------------------------------
182 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
183 * |-------------------------------------------------------------------
184 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
185 * |-------------------------------------------------------------------
186 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
187 * |-------------------------------------------------------------------
188 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
189 * |-------------------------------------------------------------------
190 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
191 * |-------------------------------------------------------------------
194 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
195 * ie. transpose of f(x, y)
198 u32 sync_seqno
[I915_NUM_RINGS
-1];
202 /* our mbox written by others */
203 u32 wait
[I915_NUM_RINGS
];
204 /* mboxes this ring signals to */
205 u32 signal
[I915_NUM_RINGS
];
207 u64 signal_ggtt
[I915_NUM_RINGS
];
211 int (*sync_to
)(struct intel_engine_cs
*ring
,
212 struct intel_engine_cs
*to
,
214 int (*signal
)(struct intel_engine_cs
*signaller
,
215 /* num_dwords needed by caller */
216 unsigned int num_dwords
);
220 * List of objects currently involved in rendering from the
223 * Includes buffers having the contents of their GPU caches
224 * flushed, not necessarily primitives. last_rendering_seqno
225 * represents when the rendering involved will be completed.
227 * A reference is held on the buffer while on this list.
229 struct list_head active_list
;
232 * List of breadcrumbs associated with GPU requests currently
235 struct list_head request_list
;
238 * Do we have some not yet emitted requests outstanding?
240 struct drm_i915_gem_request
*preallocated_lazy_request
;
241 u32 outstanding_lazy_seqno
;
242 bool gpu_caches_dirty
;
245 wait_queue_head_t irq_queue
;
247 struct intel_context
*default_context
;
248 struct intel_context
*last_context
;
250 struct intel_ring_hangcheck hangcheck
;
253 struct drm_i915_gem_object
*obj
;
255 volatile u32
*cpu_page
;
258 bool needs_cmd_parser
;
261 * Table of commands the command parser needs to know about
264 DECLARE_HASHTABLE(cmd_hash
, I915_CMD_HASH_ORDER
);
267 * Table of registers allowed in commands that read/write registers.
269 const u32
*reg_table
;
273 * Table of registers allowed in commands that read/write registers, but
274 * only from the DRM master.
276 const u32
*master_reg_table
;
277 int master_reg_count
;
280 * Returns the bitmask for the length field of the specified command.
281 * Return 0 for an unrecognized/invalid command.
283 * If the command parser finds an entry for a command in the ring's
284 * cmd_tables, it gets the command's length based on the table entry.
285 * If not, it calls this function to determine the per-ring length field
286 * encoding for the command (i.e. certain opcode ranges use certain bits
287 * to encode the command length in the header).
289 u32 (*get_cmd_length_mask
)(u32 cmd_header
);
292 bool intel_ring_initialized(struct intel_engine_cs
*ring
);
294 static inline unsigned
295 intel_ring_flag(struct intel_engine_cs
*ring
)
297 return 1 << ring
->id
;
301 intel_ring_sync_index(struct intel_engine_cs
*ring
,
302 struct intel_engine_cs
*other
)
307 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
308 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
309 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
310 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
311 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
314 idx
= (other
- ring
) - 1;
316 idx
+= I915_NUM_RINGS
;
322 intel_read_status_page(struct intel_engine_cs
*ring
,
325 /* Ensure that the compiler doesn't optimize away the load. */
327 return ring
->status_page
.page_addr
[reg
];
331 intel_write_status_page(struct intel_engine_cs
*ring
,
334 ring
->status_page
.page_addr
[reg
] = value
;
338 * Reads a dword out of the status page, which is written to from the command
339 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
342 * The following dwords have a reserved meaning:
343 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
344 * 0x04: ring 0 head pointer
345 * 0x05: ring 1 head pointer (915-class)
346 * 0x06: ring 2 head pointer (915-class)
347 * 0x10-0x1b: Context status DWords (GM45)
348 * 0x1f: Last written status offset. (GM45)
350 * The area from dword 0x20 to 0x3ff is available for driver usage.
352 #define I915_GEM_HWS_INDEX 0x20
353 #define I915_GEM_HWS_SCRATCH_INDEX 0x30
354 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
356 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
);
357 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
358 struct intel_ringbuffer
*ringbuf
);
360 void intel_stop_ring_buffer(struct intel_engine_cs
*ring
);
361 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
);
363 int __must_check
intel_ring_begin(struct intel_engine_cs
*ring
, int n
);
364 int __must_check
intel_ring_cacheline_align(struct intel_engine_cs
*ring
);
365 static inline void intel_ring_emit(struct intel_engine_cs
*ring
,
368 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
369 iowrite32(data
, ringbuf
->virtual_start
+ ringbuf
->tail
);
372 static inline void intel_ring_advance(struct intel_engine_cs
*ring
)
374 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
375 ringbuf
->tail
&= ringbuf
->size
- 1;
377 void __intel_ring_advance(struct intel_engine_cs
*ring
);
379 int __must_check
intel_ring_idle(struct intel_engine_cs
*ring
);
380 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
);
381 int intel_ring_flush_all_caches(struct intel_engine_cs
*ring
);
382 int intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
);
384 void intel_fini_pipe_control(struct intel_engine_cs
*ring
);
385 int intel_init_pipe_control(struct intel_engine_cs
*ring
);
387 int intel_init_render_ring_buffer(struct drm_device
*dev
);
388 int intel_init_bsd_ring_buffer(struct drm_device
*dev
);
389 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
);
390 int intel_init_blt_ring_buffer(struct drm_device
*dev
);
391 int intel_init_vebox_ring_buffer(struct drm_device
*dev
);
393 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
);
394 void intel_ring_setup_status_page(struct intel_engine_cs
*ring
);
396 static inline u32
intel_ring_get_tail(struct intel_ringbuffer
*ringbuf
)
398 return ringbuf
->tail
;
401 static inline u32
intel_ring_get_seqno(struct intel_engine_cs
*ring
)
403 BUG_ON(ring
->outstanding_lazy_seqno
== 0);
404 return ring
->outstanding_lazy_seqno
;
407 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
, u32 seqno
)
409 if (ring
->trace_irq_seqno
== 0 && ring
->irq_get(ring
))
410 ring
->trace_irq_seqno
= seqno
;
414 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
);
416 #endif /* _INTEL_RINGBUFFER_H_ */