drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 enum {
   5     RCS = 0x0,
   6     VCS,
   7     BCS,
   8     I915_NUM_RINGS,
   9 };
  10
  11 struct  intel_hw_status_page {
  12         u32     __iomem *page_addr;
  13         unsigned int    gfx_addr;
  14         struct          drm_i915_gem_object *obj;
  15 };
  16
  17 #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
  18
  19 #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
  20 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  21
  22 #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
  23 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  24
  25 #define I915_READ_HEAD(ring)  I915_RING_READ(RING_HEAD((ring)->mmio_base))
  26 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  27
  28 #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
  29 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  30
  31 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  32 #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
  33
  34 #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
  35 #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
  36 #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
  37
  38 struct  intel_ring_buffer {
  39         const char      *name;
  40         enum intel_ring_id {
  41                 RING_RENDER = 0x1,
  42                 RING_BSD = 0x2,
  43                 RING_BLT = 0x4,
  44         } id;
  45         u32             mmio_base;
  46         void            *virtual_start;
  47         struct          drm_device *dev;
  48         struct          drm_i915_gem_object *obj;
  49
  50         u32             head;
  51         u32             tail;
  52         int             space;
  53         int             size;
  54         int             effective_size;
  55         struct intel_hw_status_page status_page;
  56
  57         spinlock_t      irq_lock;
  58         u32             irq_refcount;
  59         u32             irq_mask;
  60         u32             irq_seqno;              /* last seq seem at irq time */
  61         u32             waiting_seqno;
  62         u32             sync_seqno[I915_NUM_RINGS-1];
  63         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  64         void            (*irq_put)(struct intel_ring_buffer *ring);
  65
  66         int             (*init)(struct intel_ring_buffer *ring);
  67
  68         void            (*write_tail)(struct intel_ring_buffer *ring,
  69                                       u32 value);
  70         int __must_check (*flush)(struct intel_ring_buffer *ring,
  71                                   u32   invalidate_domains,
  72                                   u32   flush_domains);
  73         int             (*add_request)(struct intel_ring_buffer *ring,
  74                                        u32 *seqno);
  75         u32             (*get_seqno)(struct intel_ring_buffer *ring);
  76         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  77                                                u32 offset, u32 length);
  78         void            (*cleanup)(struct intel_ring_buffer *ring);
  79
  80         /**
  81          * List of objects currently involved in rendering from the
  82          * ringbuffer.
  83          *
  84          * Includes buffers having the contents of their GPU caches
  85          * flushed, not necessarily primitives.  last_rendering_seqno
  86          * represents when the rendering involved will be completed.
  87          *
  88          * A reference is held on the buffer while on this list.
  89          */
  90         struct list_head active_list;
  91
  92         /**
  93          * List of breadcrumbs associated with GPU requests currently
  94          * outstanding.
  95          */
  96         struct list_head request_list;
  97
  98         /**
  99          * List of objects currently pending a GPU write flush.
 100          *
 101          * All elements on this list will belong to either the
 102          * active_list or flushing_list, last_rendering_seqno can
 103          * be used to differentiate between the two elements.
 104          */
 105         struct list_head gpu_write_list;
 106
 107         /**
 108          * Do we have some not yet emitted requests outstanding?
 109          */
 110         u32 outstanding_lazy_request;
 111
 112         wait_queue_head_t irq_queue;
 113         drm_local_map_t map;
 114
 115         void *private;
 116 };
 117
 118 static inline u32
 119 intel_ring_sync_index(struct intel_ring_buffer *ring,
 120                       struct intel_ring_buffer *other)
 121 {
 122         int idx;
 123
 124         /*
 125          * cs -> 0 = vcs, 1 = bcs
 126          * vcs -> 0 = bcs, 1 = cs,
 127          * bcs -> 0 = cs, 1 = vcs.
 128          */
 129
 130         idx = (other - ring) - 1;
 131         if (idx < 0)
 132                 idx += I915_NUM_RINGS;
 133
 134         return idx;
 135 }
 136
 137 static inline u32
 138 intel_read_status_page(struct intel_ring_buffer *ring,
 139                        int reg)
 140 {
 141         return ioread32(ring->status_page.page_addr + reg);
 142 }
 143
 144 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 145 int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
 146 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 147
 148 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 149                                    u32 data)
 150 {
 151         iowrite32(data, ring->virtual_start + ring->tail);
 152         ring->tail += 4;
 153 }
 154
 155 void intel_ring_advance(struct intel_ring_buffer *ring);
 156
 157 u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
 158 int intel_ring_sync(struct intel_ring_buffer *ring,
 159                     struct intel_ring_buffer *to,
 160                     u32 seqno);
 161
 162 int intel_init_render_ring_buffer(struct drm_device *dev);
 163 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 164 int intel_init_blt_ring_buffer(struct drm_device *dev);
 165
 166 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 167 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 168
 169 /* DRI warts */
 170 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 171
 172 #endif /* _INTEL_RINGBUFFER_H_ */