drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 struct  intel_hw_status_page {
   5         void            *page_addr;
   6         unsigned int    gfx_addr;
   7         struct          drm_gem_object *obj;
   8 };
   9
  10 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base))
  11 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
  12 #define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base))
  13 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
  14 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base))
  15 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
  16 #define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base))
  17 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
  18
  19 struct drm_i915_gem_execbuffer2;
  20 struct  intel_ring_buffer {
  21         const char      *name;
  22         enum intel_ring_id {
  23                 RING_RENDER = 0x1,
  24                 RING_BSD = 0x2,
  25                 RING_BLT = 0x4,
  26         } id;
  27         u32             mmio_base;
  28         unsigned long   size;
  29         void            *virtual_start;
  30         struct          drm_device *dev;
  31         struct          drm_gem_object *gem_object;
  32
  33         unsigned int    head;
  34         unsigned int    tail;
  35         int             space;
  36         struct intel_hw_status_page status_page;
  37
  38         u32             irq_gem_seqno;          /* last seq seem at irq time */
  39         u32             waiting_gem_seqno;
  40         int             user_irq_refcount;
  41         void            (*user_irq_get)(struct drm_device *dev,
  42                         struct intel_ring_buffer *ring);
  43         void            (*user_irq_put)(struct drm_device *dev,
  44                         struct intel_ring_buffer *ring);
  45
  46         int             (*init)(struct drm_device *dev,
  47                         struct intel_ring_buffer *ring);
  48
  49         void            (*set_tail)(struct drm_device *dev,
  50                                     struct intel_ring_buffer *ring,
  51                                     u32 value);
  52         void            (*flush)(struct drm_device *dev,
  53                         struct intel_ring_buffer *ring,
  54                         u32     invalidate_domains,
  55                         u32     flush_domains);
  56         u32             (*add_request)(struct drm_device *dev,
  57                         struct intel_ring_buffer *ring,
  58                         u32 flush_domains);
  59         u32             (*get_seqno)(struct drm_device *dev,
  60                                      struct intel_ring_buffer *ring);
  61         int             (*dispatch_gem_execbuffer)(struct drm_device *dev,
  62                         struct intel_ring_buffer *ring,
  63                         struct drm_i915_gem_execbuffer2 *exec,
  64                         struct drm_clip_rect *cliprects,
  65                         uint64_t exec_offset);
  66
  67         /**
  68          * List of objects currently involved in rendering from the
  69          * ringbuffer.
  70          *
  71          * Includes buffers having the contents of their GPU caches
  72          * flushed, not necessarily primitives.  last_rendering_seqno
  73          * represents when the rendering involved will be completed.
  74          *
  75          * A reference is held on the buffer while on this list.
  76          */
  77         struct list_head active_list;
  78
  79         /**
  80          * List of breadcrumbs associated with GPU requests currently
  81          * outstanding.
  82          */
  83         struct list_head request_list;
  84
  85         /**
  86          * Do we have some not yet emitted requests outstanding?
  87          */
  88         bool outstanding_lazy_request;
  89
  90         wait_queue_head_t irq_queue;
  91         drm_local_map_t map;
  92 };
  93
  94 static inline u32
  95 intel_read_status_page(struct intel_ring_buffer *ring,
  96                 int reg)
  97 {
  98         u32 *regs = ring->status_page.page_addr;
  99         return regs[reg];
 100 }
 101
 102 int intel_init_ring_buffer(struct drm_device *dev,
 103                            struct intel_ring_buffer *ring);
 104 void intel_cleanup_ring_buffer(struct drm_device *dev,
 105                                struct intel_ring_buffer *ring);
 106 int intel_wait_ring_buffer(struct drm_device *dev,
 107                            struct intel_ring_buffer *ring, int n);
 108 void intel_ring_begin(struct drm_device *dev,
 109                       struct intel_ring_buffer *ring, int n);
 110
 111 static inline void intel_ring_emit(struct drm_device *dev,
 112                                    struct intel_ring_buffer *ring,
 113                                    unsigned int data)
 114 {
 115         unsigned int *virt = ring->virtual_start + ring->tail;
 116         *virt = data;
 117         ring->tail += 4;
 118 }
 119
 120 void intel_ring_advance(struct drm_device *dev,
 121                 struct intel_ring_buffer *ring);
 122
 123 u32 intel_ring_get_seqno(struct drm_device *dev,
 124                 struct intel_ring_buffer *ring);
 125
 126 int intel_init_render_ring_buffer(struct drm_device *dev);
 127 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 128 int intel_init_blt_ring_buffer(struct drm_device *dev);
 129
 130 u32 intel_ring_get_active_head(struct drm_device *dev,
 131                                struct intel_ring_buffer *ring);
 132 void intel_ring_setup_status_page(struct drm_device *dev,
 133                                   struct intel_ring_buffer *ring);
 134
 135 #endif /* _INTEL_RINGBUFFER_H_ */