drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 enum {
   5     RCS = 0x0,
   6     VCS,
   7     BCS,
   8     I915_NUM_RINGS,
   9 };
  10
  11 struct  intel_hw_status_page {
  12         u32     __iomem *page_addr;
  13         unsigned int    gfx_addr;
  14         struct          drm_i915_gem_object *obj;
  15 };
  16
  17 #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
  18
  19 #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
  20 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  21
  22 #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
  23 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  24
  25 #define I915_READ_HEAD(ring)  I915_RING_READ(RING_HEAD((ring)->mmio_base))
  26 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  27
  28 #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
  29 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  30
  31 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  32 #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
  33
  34 #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
  35 #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
  36 #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
  37
  38 struct  intel_ring_buffer {
  39         const char      *name;
  40         enum intel_ring_id {
  41                 RING_RENDER = 0x1,
  42                 RING_BSD = 0x2,
  43                 RING_BLT = 0x4,
  44         } id;
  45         u32             mmio_base;
  46         void            __iomem *virtual_start;
  47         struct          drm_device *dev;
  48         struct          drm_i915_gem_object *obj;
  49
  50         u32             head;
  51         u32             tail;
  52         int             space;
  53         int             size;
  54         int             effective_size;
  55         struct intel_hw_status_page status_page;
  56
  57         spinlock_t      irq_lock;
  58         u32             irq_refcount;
  59         u32             irq_mask;
  60         u32             irq_seqno;              /* last seq seem at irq time */
  61         u32             trace_irq_seqno;
  62         u32             waiting_seqno;
  63         u32             sync_seqno[I915_NUM_RINGS-1];
  64         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  65         void            (*irq_put)(struct intel_ring_buffer *ring);
  66
  67         int             (*init)(struct intel_ring_buffer *ring);
  68
  69         void            (*write_tail)(struct intel_ring_buffer *ring,
  70                                       u32 value);
  71         int __must_check (*flush)(struct intel_ring_buffer *ring,
  72                                   u32   invalidate_domains,
  73                                   u32   flush_domains);
  74         int             (*add_request)(struct intel_ring_buffer *ring,
  75                                        u32 *seqno);
  76         u32             (*get_seqno)(struct intel_ring_buffer *ring);
  77         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  78                                                u32 offset, u32 length);
  79         void            (*cleanup)(struct intel_ring_buffer *ring);
  80
  81         /**
  82          * List of objects currently involved in rendering from the
  83          * ringbuffer.
  84          *
  85          * Includes buffers having the contents of their GPU caches
  86          * flushed, not necessarily primitives.  last_rendering_seqno
  87          * represents when the rendering involved will be completed.
  88          *
  89          * A reference is held on the buffer while on this list.
  90          */
  91         struct list_head active_list;
  92
  93         /**
  94          * List of breadcrumbs associated with GPU requests currently
  95          * outstanding.
  96          */
  97         struct list_head request_list;
  98
  99         /**
 100          * List of objects currently pending a GPU write flush.
 101          *
 102          * All elements on this list will belong to either the
 103          * active_list or flushing_list, last_rendering_seqno can
 104          * be used to differentiate between the two elements.
 105          */
 106         struct list_head gpu_write_list;
 107
 108         /**
 109          * Do we have some not yet emitted requests outstanding?
 110          */
 111         u32 outstanding_lazy_request;
 112
 113         wait_queue_head_t irq_queue;
 114         drm_local_map_t map;
 115
 116         void *private;
 117 };
 118
 119 static inline u32
 120 intel_ring_sync_index(struct intel_ring_buffer *ring,
 121                       struct intel_ring_buffer *other)
 122 {
 123         int idx;
 124
 125         /*
 126          * cs -> 0 = vcs, 1 = bcs
 127          * vcs -> 0 = bcs, 1 = cs,
 128          * bcs -> 0 = cs, 1 = vcs.
 129          */
 130
 131         idx = (other - ring) - 1;
 132         if (idx < 0)
 133                 idx += I915_NUM_RINGS;
 134
 135         return idx;
 136 }
 137
 138 static inline u32
 139 intel_read_status_page(struct intel_ring_buffer *ring,
 140                        int reg)
 141 {
 142         return ioread32(ring->status_page.page_addr + reg);
 143 }
 144
 145 /**
 146  * Reads a dword out of the status page, which is written to from the command
 147  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 148  * MI_STORE_DATA_IMM.
 149  *
 150  * The following dwords have a reserved meaning:
 151  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 152  * 0x04: ring 0 head pointer
 153  * 0x05: ring 1 head pointer (915-class)
 154  * 0x06: ring 2 head pointer (915-class)
 155  * 0x10-0x1b: Context status DWords (GM45)
 156  * 0x1f: Last written status offset. (GM45)
 157  *
 158  * The area from dword 0x20 to 0x3ff is available for driver usage.
 159  */
 160 #define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg)
 161 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 162 #define I915_GEM_HWS_INDEX              0x20
 163 #define I915_BREADCRUMB_INDEX           0x21
 164
 165 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 166 int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
 167 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 168
 169 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 170                                    u32 data)
 171 {
 172         iowrite32(data, ring->virtual_start + ring->tail);
 173         ring->tail += 4;
 174 }
 175
 176 void intel_ring_advance(struct intel_ring_buffer *ring);
 177
 178 u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
 179 int intel_ring_sync(struct intel_ring_buffer *ring,
 180                     struct intel_ring_buffer *to,
 181                     u32 seqno);
 182
 183 int intel_init_render_ring_buffer(struct drm_device *dev);
 184 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 185 int intel_init_blt_ring_buffer(struct drm_device *dev);
 186
 187 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 188 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 189
 190 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 191 {
 192         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 193                 ring->trace_irq_seqno = seqno;
 194 }
 195
 196 /* DRI warts */
 197 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 198
 199 #endif /* _INTEL_RINGBUFFER_H_ */