drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 /*
   5  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
   6  * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
   7  * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
   8  *
   9  * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
  10  * cacheline, the Head Pointer must not be greater than the Tail
  11  * Pointer."
  12  */
  13 #define I915_RING_FREE_SPACE 64
  14
  15 struct  intel_hw_status_page {
  16         u32             *page_addr;
  17         unsigned int    gfx_addr;
  18         struct          drm_i915_gem_object *obj;
  19 };
  20
  21 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  22 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  23
  24 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  25 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  26
  27 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  28 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  29
  30 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  31 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  32
  33 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  34 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  35
  36 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
  37 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
  38 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
  39
  40 struct intel_ring_hangcheck {
  41         u32 seqno;
  42         u32 acthd;
  43         int score;
  44 };
  45
  46 struct  intel_ring_buffer {
  47         const char      *name;
  48         enum intel_ring_id {
  49                 RCS = 0x0,
  50                 VCS,
  51                 BCS,
  52                 VECS,
  53         } id;
  54 #define I915_NUM_RINGS 4
  55         u32             mmio_base;
  56         void            __iomem *virtual_start;
  57         struct          drm_device *dev;
  58         struct          drm_i915_gem_object *obj;
  59
  60         u32             head;
  61         u32             tail;
  62         int             space;
  63         int             size;
  64         int             effective_size;
  65         struct intel_hw_status_page status_page;
  66
  67         /** We track the position of the requests in the ring buffer, and
  68          * when each is retired we increment last_retired_head as the GPU
  69          * must have finished processing the request and so we know we
  70          * can advance the ringbuffer up to that position.
  71          *
  72          * last_retired_head is set to -1 after the value is consumed so
  73          * we can detect new retirements.
  74          */
  75         u32             last_retired_head;
  76
  77         struct {
  78                 u32     gt; /*  protected by dev_priv->irq_lock */
  79                 u32     pm; /*  protected by dev_priv->rps.lock (sucks) */
  80         } irq_refcount;
  81         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
  82         u32             trace_irq_seqno;
  83         u32             sync_seqno[I915_NUM_RINGS-1];
  84         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  85         void            (*irq_put)(struct intel_ring_buffer *ring);
  86
  87         int             (*init)(struct intel_ring_buffer *ring);
  88
  89         void            (*write_tail)(struct intel_ring_buffer *ring,
  90                                       u32 value);
  91         int __must_check (*flush)(struct intel_ring_buffer *ring,
  92                                   u32   invalidate_domains,
  93                                   u32   flush_domains);
  94         int             (*add_request)(struct intel_ring_buffer *ring);
  95         /* Some chipsets are not quite as coherent as advertised and need
  96          * an expensive kick to force a true read of the up-to-date seqno.
  97          * However, the up-to-date seqno is not always required and the last
  98          * seen value is good enough. Note that the seqno will always be
  99          * monotonic, even if not coherent.
 100          */
 101         u32             (*get_seqno)(struct intel_ring_buffer *ring,
 102                                      bool lazy_coherency);
 103         void            (*set_seqno)(struct intel_ring_buffer *ring,
 104                                      u32 seqno);
 105         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
 106                                                u32 offset, u32 length,
 107                                                unsigned flags);
 108 #define I915_DISPATCH_SECURE 0x1
 109 #define I915_DISPATCH_PINNED 0x2
 110         void            (*cleanup)(struct intel_ring_buffer *ring);
 111         int             (*sync_to)(struct intel_ring_buffer *ring,
 112                                    struct intel_ring_buffer *to,
 113                                    u32 seqno);
 114
 115         /* our mbox written by others */
 116         u32             semaphore_register[I915_NUM_RINGS];
 117         /* mboxes this ring signals to */
 118         u32             signal_mbox[I915_NUM_RINGS];
 119
 120         /**
 121          * List of objects currently involved in rendering from the
 122          * ringbuffer.
 123          *
 124          * Includes buffers having the contents of their GPU caches
 125          * flushed, not necessarily primitives.  last_rendering_seqno
 126          * represents when the rendering involved will be completed.
 127          *
 128          * A reference is held on the buffer while on this list.
 129          */
 130         struct list_head active_list;
 131
 132         /**
 133          * List of breadcrumbs associated with GPU requests currently
 134          * outstanding.
 135          */
 136         struct list_head request_list;
 137
 138         /**
 139          * Do we have some not yet emitted requests outstanding?
 140          */
 141         u32 outstanding_lazy_request;
 142         bool gpu_caches_dirty;
 143         bool fbc_dirty;
 144
 145         wait_queue_head_t irq_queue;
 146
 147         /**
 148          * Do an explicit TLB flush before MI_SET_CONTEXT
 149          */
 150         bool itlb_before_ctx_switch;
 151         struct i915_hw_context *default_context;
 152         struct i915_hw_context *last_context;
 153
 154         struct intel_ring_hangcheck hangcheck;
 155
 156         void *private;
 157 };
 158
 159 static inline bool
 160 intel_ring_initialized(struct intel_ring_buffer *ring)
 161 {
 162         return ring->obj != NULL;
 163 }
 164
 165 static inline unsigned
 166 intel_ring_flag(struct intel_ring_buffer *ring)
 167 {
 168         return 1 << ring->id;
 169 }
 170
 171 static inline u32
 172 intel_ring_sync_index(struct intel_ring_buffer *ring,
 173                       struct intel_ring_buffer *other)
 174 {
 175         int idx;
 176
 177         /*
 178          * cs -> 0 = vcs, 1 = bcs
 179          * vcs -> 0 = bcs, 1 = cs,
 180          * bcs -> 0 = cs, 1 = vcs.
 181          */
 182
 183         idx = (other - ring) - 1;
 184         if (idx < 0)
 185                 idx += I915_NUM_RINGS;
 186
 187         return idx;
 188 }
 189
 190 static inline u32
 191 intel_read_status_page(struct intel_ring_buffer *ring,
 192                        int reg)
 193 {
 194         /* Ensure that the compiler doesn't optimize away the load. */
 195         barrier();
 196         return ring->status_page.page_addr[reg];
 197 }
 198
 199 static inline void
 200 intel_write_status_page(struct intel_ring_buffer *ring,
 201                         int reg, u32 value)
 202 {
 203         ring->status_page.page_addr[reg] = value;
 204 }
 205
 206 /**
 207  * Reads a dword out of the status page, which is written to from the command
 208  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 209  * MI_STORE_DATA_IMM.
 210  *
 211  * The following dwords have a reserved meaning:
 212  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 213  * 0x04: ring 0 head pointer
 214  * 0x05: ring 1 head pointer (915-class)
 215  * 0x06: ring 2 head pointer (915-class)
 216  * 0x10-0x1b: Context status DWords (GM45)
 217  * 0x1f: Last written status offset. (GM45)
 218  *
 219  * The area from dword 0x20 to 0x3ff is available for driver usage.
 220  */
 221 #define I915_GEM_HWS_INDEX              0x20
 222 #define I915_GEM_HWS_SCRATCH_INDEX      0x30
 223 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 224
 225 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 226
 227 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 228 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 229                                    u32 data)
 230 {
 231         iowrite32(data, ring->virtual_start + ring->tail);
 232         ring->tail += 4;
 233 }
 234 void intel_ring_advance(struct intel_ring_buffer *ring);
 235 int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
 236 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
 237 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
 238 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 239
 240 int intel_init_render_ring_buffer(struct drm_device *dev);
 241 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 242 int intel_init_blt_ring_buffer(struct drm_device *dev);
 243 int intel_init_vebox_ring_buffer(struct drm_device *dev);
 244
 245 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 246 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 247
 248 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
 249 {
 250         return ring->tail;
 251 }
 252
 253 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
 254 {
 255         BUG_ON(ring->outstanding_lazy_request == 0);
 256         return ring->outstanding_lazy_request;
 257 }
 258
 259 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 260 {
 261         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 262                 ring->trace_irq_seqno = seqno;
 263 }
 264
 265 /* DRI warts */
 266 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 267
 268 #endif /* _INTEL_RINGBUFFER_H_ */