drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 #include <linux/hashtable.h>
   5
   6 #define I915_CMD_HASH_ORDER 9
   7
   8 /*
   9  * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
  10  * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
  11  * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
  12  *
  13  * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
  14  * cacheline, the Head Pointer must not be greater than the Tail
  15  * Pointer."
  16  */
  17 #define I915_RING_FREE_SPACE 64
  18
  19 struct  intel_hw_status_page {
  20         u32             *page_addr;
  21         unsigned int    gfx_addr;
  22         struct          drm_i915_gem_object *obj;
  23 };
  24
  25 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  26 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  27
  28 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  29 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  30
  31 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  32 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  33
  34 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  35 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  36
  37 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  38 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  39
  40 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
  41 #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
  42
  43 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
  44  * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
  45  */
  46 #define i915_semaphore_seqno_size sizeof(uint64_t)
  47 #define GEN8_SIGNAL_OFFSET(__ring, to)                       \
  48         (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
  49         ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) +   \
  50         (i915_semaphore_seqno_size * (to)))
  51
  52 #define GEN8_WAIT_OFFSET(__ring, from)                       \
  53         (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
  54         ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
  55         (i915_semaphore_seqno_size * (__ring)->id))
  56
  57 #define GEN8_RING_SEMAPHORE_INIT do { \
  58         if (!dev_priv->semaphore_obj) { \
  59                 break; \
  60         } \
  61         ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
  62         ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
  63         ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
  64         ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
  65         ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
  66         ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
  67         } while(0)
  68
  69 enum intel_ring_hangcheck_action {
  70         HANGCHECK_IDLE = 0,
  71         HANGCHECK_WAIT,
  72         HANGCHECK_ACTIVE,
  73         HANGCHECK_ACTIVE_LOOP,
  74         HANGCHECK_KICK,
  75         HANGCHECK_HUNG,
  76 };
  77
  78 #define HANGCHECK_SCORE_RING_HUNG 31
  79
  80 struct intel_ring_hangcheck {
  81         u64 acthd;
  82         u64 max_acthd;
  83         u32 seqno;
  84         int score;
  85         enum intel_ring_hangcheck_action action;
  86         int deadlock;
  87 };
  88
  89 struct intel_ringbuffer {
  90         struct drm_i915_gem_object *obj;
  91         void __iomem *virtual_start;
  92
  93         struct intel_engine_cs *ring;
  94
  95         u32 head;
  96         u32 tail;
  97         int space;
  98         int size;
  99         int effective_size;
 100
 101         /** We track the position of the requests in the ring buffer, and
 102          * when each is retired we increment last_retired_head as the GPU
 103          * must have finished processing the request and so we know we
 104          * can advance the ringbuffer up to that position.
 105          *
 106          * last_retired_head is set to -1 after the value is consumed so
 107          * we can detect new retirements.
 108          */
 109         u32 last_retired_head;
 110 };
 111
 112 struct  intel_engine_cs {
 113         const char      *name;
 114         enum intel_ring_id {
 115                 RCS = 0x0,
 116                 VCS,
 117                 BCS,
 118                 VECS,
 119                 VCS2
 120         } id;
 121 #define I915_NUM_RINGS 5
 122 #define LAST_USER_RING (VECS + 1)
 123         u32             mmio_base;
 124         struct          drm_device *dev;
 125         struct intel_ringbuffer *buffer;
 126
 127         struct intel_hw_status_page status_page;
 128
 129         unsigned irq_refcount; /* protected by dev_priv->irq_lock */
 130         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
 131         u32             trace_irq_seqno;
 132         bool __must_check (*irq_get)(struct intel_engine_cs *ring);
 133         void            (*irq_put)(struct intel_engine_cs *ring);
 134
 135         int             (*init)(struct intel_engine_cs *ring);
 136
 137         void            (*write_tail)(struct intel_engine_cs *ring,
 138                                       u32 value);
 139         int __must_check (*flush)(struct intel_engine_cs *ring,
 140                                   u32   invalidate_domains,
 141                                   u32   flush_domains);
 142         int             (*add_request)(struct intel_engine_cs *ring);
 143         /* Some chipsets are not quite as coherent as advertised and need
 144          * an expensive kick to force a true read of the up-to-date seqno.
 145          * However, the up-to-date seqno is not always required and the last
 146          * seen value is good enough. Note that the seqno will always be
 147          * monotonic, even if not coherent.
 148          */
 149         u32             (*get_seqno)(struct intel_engine_cs *ring,
 150                                      bool lazy_coherency);
 151         void            (*set_seqno)(struct intel_engine_cs *ring,
 152                                      u32 seqno);
 153         int             (*dispatch_execbuffer)(struct intel_engine_cs *ring,
 154                                                u64 offset, u32 length,
 155                                                unsigned flags);
 156 #define I915_DISPATCH_SECURE 0x1
 157 #define I915_DISPATCH_PINNED 0x2
 158         void            (*cleanup)(struct intel_engine_cs *ring);
 159
 160         /* GEN8 signal/wait table - never trust comments!
 161          *        signal to     signal to    signal to   signal to      signal to
 162          *          RCS            VCS          BCS        VECS          VCS2
 163          *      --------------------------------------------------------------------
 164          *  RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
 165          *      |-------------------------------------------------------------------
 166          *  VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
 167          *      |-------------------------------------------------------------------
 168          *  BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
 169          *      |-------------------------------------------------------------------
 170          * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) |  NOP (0x90) | VCS2 (0x98) |
 171          *      |-------------------------------------------------------------------
 172          * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP  (0xc0) |
 173          *      |-------------------------------------------------------------------
 174          *
 175          * Generalization:
 176          *  f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
 177          *  ie. transpose of g(x, y)
 178          *
 179          *       sync from      sync from    sync from    sync from     sync from
 180          *          RCS            VCS          BCS        VECS          VCS2
 181          *      --------------------------------------------------------------------
 182          *  RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
 183          *      |-------------------------------------------------------------------
 184          *  VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
 185          *      |-------------------------------------------------------------------
 186          *  BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
 187          *      |-------------------------------------------------------------------
 188          * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) |  NOP (0x90) | VCS2 (0xb8) |
 189          *      |-------------------------------------------------------------------
 190          * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) |  NOP (0xc0) |
 191          *      |-------------------------------------------------------------------
 192          *
 193          * Generalization:
 194          *  g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
 195          *  ie. transpose of f(x, y)
 196          */
 197         struct {
 198                 u32     sync_seqno[I915_NUM_RINGS-1];
 199
 200                 union {
 201                         struct {
 202                                 /* our mbox written by others */
 203                                 u32             wait[I915_NUM_RINGS];
 204                                 /* mboxes this ring signals to */
 205                                 u32             signal[I915_NUM_RINGS];
 206                         } mbox;
 207                         u64             signal_ggtt[I915_NUM_RINGS];
 208                 };
 209
 210                 /* AKA wait() */
 211                 int     (*sync_to)(struct intel_engine_cs *ring,
 212                                    struct intel_engine_cs *to,
 213                                    u32 seqno);
 214                 int     (*signal)(struct intel_engine_cs *signaller,
 215                                   /* num_dwords needed by caller */
 216                                   unsigned int num_dwords);
 217         } semaphore;
 218
 219         /**
 220          * List of objects currently involved in rendering from the
 221          * ringbuffer.
 222          *
 223          * Includes buffers having the contents of their GPU caches
 224          * flushed, not necessarily primitives.  last_rendering_seqno
 225          * represents when the rendering involved will be completed.
 226          *
 227          * A reference is held on the buffer while on this list.
 228          */
 229         struct list_head active_list;
 230
 231         /**
 232          * List of breadcrumbs associated with GPU requests currently
 233          * outstanding.
 234          */
 235         struct list_head request_list;
 236
 237         /**
 238          * Do we have some not yet emitted requests outstanding?
 239          */
 240         struct drm_i915_gem_request *preallocated_lazy_request;
 241         u32 outstanding_lazy_seqno;
 242         bool gpu_caches_dirty;
 243         bool fbc_dirty;
 244
 245         wait_queue_head_t irq_queue;
 246
 247         struct intel_context *default_context;
 248         struct intel_context *last_context;
 249
 250         struct intel_ring_hangcheck hangcheck;
 251
 252         struct {
 253                 struct drm_i915_gem_object *obj;
 254                 u32 gtt_offset;
 255                 volatile u32 *cpu_page;
 256         } scratch;
 257
 258         bool needs_cmd_parser;
 259
 260         /*
 261          * Table of commands the command parser needs to know about
 262          * for this ring.
 263          */
 264         DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
 265
 266         /*
 267          * Table of registers allowed in commands that read/write registers.
 268          */
 269         const u32 *reg_table;
 270         int reg_count;
 271
 272         /*
 273          * Table of registers allowed in commands that read/write registers, but
 274          * only from the DRM master.
 275          */
 276         const u32 *master_reg_table;
 277         int master_reg_count;
 278
 279         /*
 280          * Returns the bitmask for the length field of the specified command.
 281          * Return 0 for an unrecognized/invalid command.
 282          *
 283          * If the command parser finds an entry for a command in the ring's
 284          * cmd_tables, it gets the command's length based on the table entry.
 285          * If not, it calls this function to determine the per-ring length field
 286          * encoding for the command (i.e. certain opcode ranges use certain bits
 287          * to encode the command length in the header).
 288          */
 289         u32 (*get_cmd_length_mask)(u32 cmd_header);
 290 };
 291
 292 bool intel_ring_initialized(struct intel_engine_cs *ring);
 293
 294 static inline unsigned
 295 intel_ring_flag(struct intel_engine_cs *ring)
 296 {
 297         return 1 << ring->id;
 298 }
 299
 300 static inline u32
 301 intel_ring_sync_index(struct intel_engine_cs *ring,
 302                       struct intel_engine_cs *other)
 303 {
 304         int idx;
 305
 306         /*
 307          * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
 308          * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
 309          * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
 310          * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
 311          * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
 312          */
 313
 314         idx = (other - ring) - 1;
 315         if (idx < 0)
 316                 idx += I915_NUM_RINGS;
 317
 318         return idx;
 319 }
 320
 321 static inline u32
 322 intel_read_status_page(struct intel_engine_cs *ring,
 323                        int reg)
 324 {
 325         /* Ensure that the compiler doesn't optimize away the load. */
 326         barrier();
 327         return ring->status_page.page_addr[reg];
 328 }
 329
 330 static inline void
 331 intel_write_status_page(struct intel_engine_cs *ring,
 332                         int reg, u32 value)
 333 {
 334         ring->status_page.page_addr[reg] = value;
 335 }
 336
 337 /**
 338  * Reads a dword out of the status page, which is written to from the command
 339  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 340  * MI_STORE_DATA_IMM.
 341  *
 342  * The following dwords have a reserved meaning:
 343  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 344  * 0x04: ring 0 head pointer
 345  * 0x05: ring 1 head pointer (915-class)
 346  * 0x06: ring 2 head pointer (915-class)
 347  * 0x10-0x1b: Context status DWords (GM45)
 348  * 0x1f: Last written status offset. (GM45)
 349  *
 350  * The area from dword 0x20 to 0x3ff is available for driver usage.
 351  */
 352 #define I915_GEM_HWS_INDEX              0x20
 353 #define I915_GEM_HWS_SCRATCH_INDEX      0x30
 354 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 355
 356 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
 357 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
 358                                struct intel_ringbuffer *ringbuf);
 359
 360 void intel_stop_ring_buffer(struct intel_engine_cs *ring);
 361 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
 362
 363 int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
 364 int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
 365 static inline void intel_ring_emit(struct intel_engine_cs *ring,
 366                                    u32 data)
 367 {
 368         struct intel_ringbuffer *ringbuf = ring->buffer;
 369         iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
 370         ringbuf->tail += 4;
 371 }
 372 static inline void intel_ring_advance(struct intel_engine_cs *ring)
 373 {
 374         struct intel_ringbuffer *ringbuf = ring->buffer;
 375         ringbuf->tail &= ringbuf->size - 1;
 376 }
 377 void __intel_ring_advance(struct intel_engine_cs *ring);
 378
 379 int __must_check intel_ring_idle(struct intel_engine_cs *ring);
 380 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
 381 int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
 382 int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
 383
 384 int intel_init_render_ring_buffer(struct drm_device *dev);
 385 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 386 int intel_init_bsd2_ring_buffer(struct drm_device *dev);
 387 int intel_init_blt_ring_buffer(struct drm_device *dev);
 388 int intel_init_vebox_ring_buffer(struct drm_device *dev);
 389
 390 u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
 391 void intel_ring_setup_status_page(struct intel_engine_cs *ring);
 392
 393 static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
 394 {
 395         return ringbuf->tail;
 396 }
 397
 398 static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
 399 {
 400         BUG_ON(ring->outstanding_lazy_seqno == 0);
 401         return ring->outstanding_lazy_seqno;
 402 }
 403
 404 static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
 405 {
 406         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 407                 ring->trace_irq_seqno = seqno;
 408 }
 409
 410 /* DRI warts */
 411 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 412
 413 #endif /* _INTEL_RINGBUFFER_H_ */