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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
1 /*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
31
32 #include "i915_drv.h"
33 #include "intel_drv.h"
34
35 /**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
52 #define GEN9_ENABLE_DC5(dev) 0
53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
54
55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
56 for (i = 0; \
57 i < (power_domains)->power_well_count && \
58 ((power_well) = &(power_domains)->power_wells[i]); \
59 i++) \
60 if ((power_well)->domains & (domain_mask))
61
62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63 for (i = (power_domains)->power_well_count - 1; \
64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
65 i--) \
66 if ((power_well)->domains & (domain_mask))
67
68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
69 int power_well_id);
70
71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
72 struct i915_power_well *power_well)
73 {
74 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
75 power_well->ops->enable(dev_priv, power_well);
76 power_well->hw_enabled = true;
77 }
78
79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
80 struct i915_power_well *power_well)
81 {
82 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
83 power_well->hw_enabled = false;
84 power_well->ops->disable(dev_priv, power_well);
85 }
86
87 /*
88 * We should only use the power well if we explicitly asked the hardware to
89 * enable it, so check if it's enabled and also check if we've requested it to
90 * be enabled.
91 */
92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
93 struct i915_power_well *power_well)
94 {
95 return I915_READ(HSW_PWR_WELL_DRIVER) ==
96 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
97 }
98
99 /**
100 * __intel_display_power_is_enabled - unlocked check for a power domain
101 * @dev_priv: i915 device instance
102 * @domain: power domain to check
103 *
104 * This is the unlocked version of intel_display_power_is_enabled() and should
105 * only be used from error capture and recovery code where deadlocks are
106 * possible.
107 *
108 * Returns:
109 * True when the power domain is enabled, false otherwise.
110 */
111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
112 enum intel_display_power_domain domain)
113 {
114 struct i915_power_domains *power_domains;
115 struct i915_power_well *power_well;
116 bool is_enabled;
117 int i;
118
119 if (dev_priv->pm.suspended)
120 return false;
121
122 power_domains = &dev_priv->power_domains;
123
124 is_enabled = true;
125
126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
127 if (power_well->always_on)
128 continue;
129
130 if (!power_well->hw_enabled) {
131 is_enabled = false;
132 break;
133 }
134 }
135
136 return is_enabled;
137 }
138
139 /**
140 * intel_display_power_is_enabled - check for a power domain
141 * @dev_priv: i915 device instance
142 * @domain: power domain to check
143 *
144 * This function can be used to check the hw power domain state. It is mostly
145 * used in hardware state readout functions. Everywhere else code should rely
146 * upon explicit power domain reference counting to ensure that the hardware
147 * block is powered up before accessing it.
148 *
149 * Callers must hold the relevant modesetting locks to ensure that concurrent
150 * threads can't disable the power well while the caller tries to read a few
151 * registers.
152 *
153 * Returns:
154 * True when the power domain is enabled, false otherwise.
155 */
156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
157 enum intel_display_power_domain domain)
158 {
159 struct i915_power_domains *power_domains;
160 bool ret;
161
162 power_domains = &dev_priv->power_domains;
163
164 mutex_lock(&power_domains->lock);
165 ret = __intel_display_power_is_enabled(dev_priv, domain);
166 mutex_unlock(&power_domains->lock);
167
168 return ret;
169 }
170
171 /**
172 * intel_display_set_init_power - set the initial power domain state
173 * @dev_priv: i915 device instance
174 * @enable: whether to enable or disable the initial power domain state
175 *
176 * For simplicity our driver load/unload and system suspend/resume code assumes
177 * that all power domains are always enabled. This functions controls the state
178 * of this little hack. While the initial power domain state is enabled runtime
179 * pm is effectively disabled.
180 */
181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
182 bool enable)
183 {
184 if (dev_priv->power_domains.init_power_on == enable)
185 return;
186
187 if (enable)
188 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
189 else
190 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
191
192 dev_priv->power_domains.init_power_on = enable;
193 }
194
195 /*
196 * Starting with Haswell, we have a "Power Down Well" that can be turned off
197 * when not needed anymore. We have 4 registers that can request the power well
198 * to be enabled, and it will only be disabled if none of the registers is
199 * requesting it to be enabled.
200 */
201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
202 {
203 struct drm_device *dev = dev_priv->dev;
204
205 /*
206 * After we re-enable the power well, if we touch VGA register 0x3d5
207 * we'll get unclaimed register interrupts. This stops after we write
208 * anything to the VGA MSR register. The vgacon module uses this
209 * register all the time, so if we unbind our driver and, as a
210 * consequence, bind vgacon, we'll get stuck in an infinite loop at
211 * console_unlock(). So make here we touch the VGA MSR register, making
212 * sure vgacon can keep working normally without triggering interrupts
213 * and error messages.
214 */
215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
216 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
217 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
218
219 if (IS_BROADWELL(dev))
220 gen8_irq_power_well_post_enable(dev_priv,
221 1 << PIPE_C | 1 << PIPE_B);
222 }
223
224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
225 struct i915_power_well *power_well)
226 {
227 struct drm_device *dev = dev_priv->dev;
228
229 /*
230 * After we re-enable the power well, if we touch VGA register 0x3d5
231 * we'll get unclaimed register interrupts. This stops after we write
232 * anything to the VGA MSR register. The vgacon module uses this
233 * register all the time, so if we unbind our driver and, as a
234 * consequence, bind vgacon, we'll get stuck in an infinite loop at
235 * console_unlock(). So make here we touch the VGA MSR register, making
236 * sure vgacon can keep working normally without triggering interrupts
237 * and error messages.
238 */
239 if (power_well->data == SKL_DISP_PW_2) {
240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
241 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
242 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
243
244 gen8_irq_power_well_post_enable(dev_priv,
245 1 << PIPE_C | 1 << PIPE_B);
246 }
247
248 if (power_well->data == SKL_DISP_PW_1) {
249 if (!dev_priv->power_domains.initializing)
250 intel_prepare_ddi(dev);
251 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
252 }
253 }
254
255 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
256 struct i915_power_well *power_well, bool enable)
257 {
258 bool is_enabled, enable_requested;
259 uint32_t tmp;
260
261 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
262 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
263 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
264
265 if (enable) {
266 if (!enable_requested)
267 I915_WRITE(HSW_PWR_WELL_DRIVER,
268 HSW_PWR_WELL_ENABLE_REQUEST);
269
270 if (!is_enabled) {
271 DRM_DEBUG_KMS("Enabling power well\n");
272 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
273 HSW_PWR_WELL_STATE_ENABLED), 20))
274 DRM_ERROR("Timeout enabling power well\n");
275 hsw_power_well_post_enable(dev_priv);
276 }
277
278 } else {
279 if (enable_requested) {
280 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
281 POSTING_READ(HSW_PWR_WELL_DRIVER);
282 DRM_DEBUG_KMS("Requesting to disable the power well\n");
283 }
284 }
285 }
286
287 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
288 BIT(POWER_DOMAIN_TRANSCODER_A) | \
289 BIT(POWER_DOMAIN_PIPE_B) | \
290 BIT(POWER_DOMAIN_TRANSCODER_B) | \
291 BIT(POWER_DOMAIN_PIPE_C) | \
292 BIT(POWER_DOMAIN_TRANSCODER_C) | \
293 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
294 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
295 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
297 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
298 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
299 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
300 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
301 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
302 BIT(POWER_DOMAIN_AUX_B) | \
303 BIT(POWER_DOMAIN_AUX_C) | \
304 BIT(POWER_DOMAIN_AUX_D) | \
305 BIT(POWER_DOMAIN_AUDIO) | \
306 BIT(POWER_DOMAIN_VGA) | \
307 BIT(POWER_DOMAIN_INIT))
308 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
309 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
310 BIT(POWER_DOMAIN_PLLS) | \
311 BIT(POWER_DOMAIN_PIPE_A) | \
312 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
313 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
314 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
315 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
316 BIT(POWER_DOMAIN_AUX_A) | \
317 BIT(POWER_DOMAIN_INIT))
318 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
319 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
320 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
321 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
322 BIT(POWER_DOMAIN_INIT))
323 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
324 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
325 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
326 BIT(POWER_DOMAIN_INIT))
327 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
328 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
329 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
330 BIT(POWER_DOMAIN_INIT))
331 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
332 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
333 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
334 BIT(POWER_DOMAIN_INIT))
335 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
336 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
337 BIT(POWER_DOMAIN_PLLS) | \
338 BIT(POWER_DOMAIN_INIT))
339 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
340 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
341 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
342 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
343 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
344 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
345 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
346 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
347 BIT(POWER_DOMAIN_INIT))
348
349 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
350 BIT(POWER_DOMAIN_TRANSCODER_A) | \
351 BIT(POWER_DOMAIN_PIPE_B) | \
352 BIT(POWER_DOMAIN_TRANSCODER_B) | \
353 BIT(POWER_DOMAIN_PIPE_C) | \
354 BIT(POWER_DOMAIN_TRANSCODER_C) | \
355 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
356 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
357 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
358 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
359 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
360 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
361 BIT(POWER_DOMAIN_AUX_B) | \
362 BIT(POWER_DOMAIN_AUX_C) | \
363 BIT(POWER_DOMAIN_AUDIO) | \
364 BIT(POWER_DOMAIN_VGA) | \
365 BIT(POWER_DOMAIN_INIT))
366 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
367 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
368 BIT(POWER_DOMAIN_PIPE_A) | \
369 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
370 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
371 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
372 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
373 BIT(POWER_DOMAIN_AUX_A) | \
374 BIT(POWER_DOMAIN_PLLS) | \
375 BIT(POWER_DOMAIN_INIT))
376 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
377 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
378 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
379 BIT(POWER_DOMAIN_INIT))
380
381 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
382 {
383 struct drm_device *dev = dev_priv->dev;
384
385 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
386 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
387 "DC9 already programmed to be enabled.\n");
388 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
389 "DC5 still not disabled to enable DC9.\n");
390 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
391 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
392
393 /*
394 * TODO: check for the following to verify the conditions to enter DC9
395 * state are satisfied:
396 * 1] Check relevant display engine registers to verify if mode set
397 * disable sequence was followed.
398 * 2] Check if display uninitialize sequence is initialized.
399 */
400 }
401
402 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
403 {
404 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
405 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
406 "DC9 already programmed to be disabled.\n");
407 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
408 "DC5 still not disabled.\n");
409
410 /*
411 * TODO: check for the following to verify DC9 state was indeed
412 * entered before programming to disable it:
413 * 1] Check relevant display engine registers to verify if mode
414 * set disable sequence was followed.
415 * 2] Check if display uninitialize sequence is initialized.
416 */
417 }
418
419 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
420 {
421 uint32_t val;
422
423 assert_can_enable_dc9(dev_priv);
424
425 DRM_DEBUG_KMS("Enabling DC9\n");
426
427 val = I915_READ(DC_STATE_EN);
428 val |= DC_STATE_EN_DC9;
429 I915_WRITE(DC_STATE_EN, val);
430 POSTING_READ(DC_STATE_EN);
431 }
432
433 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
434 {
435 uint32_t val;
436
437 assert_can_disable_dc9(dev_priv);
438
439 DRM_DEBUG_KMS("Disabling DC9\n");
440
441 val = I915_READ(DC_STATE_EN);
442 val &= ~DC_STATE_EN_DC9;
443 I915_WRITE(DC_STATE_EN, val);
444 POSTING_READ(DC_STATE_EN);
445 }
446
447 static void gen9_set_dc_state_debugmask_memory_up(
448 struct drm_i915_private *dev_priv)
449 {
450 uint32_t val;
451
452 /* The below bit doesn't need to be cleared ever afterwards */
453 val = I915_READ(DC_STATE_DEBUG);
454 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
455 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
456 I915_WRITE(DC_STATE_DEBUG, val);
457 POSTING_READ(DC_STATE_DEBUG);
458 }
459 }
460
461 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
462 {
463 struct drm_device *dev = dev_priv->dev;
464 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
465 SKL_DISP_PW_2);
466
467 WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
468 WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
469 WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
470
471 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
472 "DC5 already programmed to be enabled.\n");
473 WARN(dev_priv->pm.suspended,
474 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
475
476 assert_csr_loaded(dev_priv);
477 }
478
479 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
480 {
481 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
482 SKL_DISP_PW_2);
483 /*
484 * During initialization, the firmware may not be loaded yet.
485 * We still want to make sure that the DC enabling flag is cleared.
486 */
487 if (dev_priv->power_domains.initializing)
488 return;
489
490 WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
491 WARN(dev_priv->pm.suspended,
492 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
493 }
494
495 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
496 {
497 uint32_t val;
498
499 assert_can_enable_dc5(dev_priv);
500
501 DRM_DEBUG_KMS("Enabling DC5\n");
502
503 gen9_set_dc_state_debugmask_memory_up(dev_priv);
504
505 val = I915_READ(DC_STATE_EN);
506 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
507 val |= DC_STATE_EN_UPTO_DC5;
508 I915_WRITE(DC_STATE_EN, val);
509 POSTING_READ(DC_STATE_EN);
510 }
511
512 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
513 {
514 uint32_t val;
515
516 assert_can_disable_dc5(dev_priv);
517
518 DRM_DEBUG_KMS("Disabling DC5\n");
519
520 val = I915_READ(DC_STATE_EN);
521 val &= ~DC_STATE_EN_UPTO_DC5;
522 I915_WRITE(DC_STATE_EN, val);
523 POSTING_READ(DC_STATE_EN);
524 }
525
526 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
527 {
528 struct drm_device *dev = dev_priv->dev;
529
530 WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
531 WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
532 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
533 "Backlight is not disabled.\n");
534 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
535 "DC6 already programmed to be enabled.\n");
536
537 assert_csr_loaded(dev_priv);
538 }
539
540 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
541 {
542 /*
543 * During initialization, the firmware may not be loaded yet.
544 * We still want to make sure that the DC enabling flag is cleared.
545 */
546 if (dev_priv->power_domains.initializing)
547 return;
548
549 assert_csr_loaded(dev_priv);
550 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
551 "DC6 already programmed to be disabled.\n");
552 }
553
554 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
555 {
556 uint32_t val;
557
558 assert_can_enable_dc6(dev_priv);
559
560 DRM_DEBUG_KMS("Enabling DC6\n");
561
562 gen9_set_dc_state_debugmask_memory_up(dev_priv);
563
564 val = I915_READ(DC_STATE_EN);
565 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
566 val |= DC_STATE_EN_UPTO_DC6;
567 I915_WRITE(DC_STATE_EN, val);
568 POSTING_READ(DC_STATE_EN);
569 }
570
571 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
572 {
573 uint32_t val;
574
575 assert_can_disable_dc6(dev_priv);
576
577 DRM_DEBUG_KMS("Disabling DC6\n");
578
579 val = I915_READ(DC_STATE_EN);
580 val &= ~DC_STATE_EN_UPTO_DC6;
581 I915_WRITE(DC_STATE_EN, val);
582 POSTING_READ(DC_STATE_EN);
583 }
584
585 static void skl_set_power_well(struct drm_i915_private *dev_priv,
586 struct i915_power_well *power_well, bool enable)
587 {
588 struct drm_device *dev = dev_priv->dev;
589 uint32_t tmp, fuse_status;
590 uint32_t req_mask, state_mask;
591 bool is_enabled, enable_requested, check_fuse_status = false;
592
593 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
594 fuse_status = I915_READ(SKL_FUSE_STATUS);
595
596 switch (power_well->data) {
597 case SKL_DISP_PW_1:
598 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
599 SKL_FUSE_PG0_DIST_STATUS), 1)) {
600 DRM_ERROR("PG0 not enabled\n");
601 return;
602 }
603 break;
604 case SKL_DISP_PW_2:
605 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
606 DRM_ERROR("PG1 in disabled state\n");
607 return;
608 }
609 break;
610 case SKL_DISP_PW_DDI_A_E:
611 case SKL_DISP_PW_DDI_B:
612 case SKL_DISP_PW_DDI_C:
613 case SKL_DISP_PW_DDI_D:
614 case SKL_DISP_PW_MISC_IO:
615 break;
616 default:
617 WARN(1, "Unknown power well %lu\n", power_well->data);
618 return;
619 }
620
621 req_mask = SKL_POWER_WELL_REQ(power_well->data);
622 enable_requested = tmp & req_mask;
623 state_mask = SKL_POWER_WELL_STATE(power_well->data);
624 is_enabled = tmp & state_mask;
625
626 if (enable) {
627 if (!enable_requested) {
628 WARN((tmp & state_mask) &&
629 !I915_READ(HSW_PWR_WELL_BIOS),
630 "Invalid for power well status to be enabled, unless done by the BIOS, \
631 when request is to disable!\n");
632 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
633 power_well->data == SKL_DISP_PW_2) {
634 if (SKL_ENABLE_DC6(dev)) {
635 skl_disable_dc6(dev_priv);
636 /*
637 * DDI buffer programming unnecessary during driver-load/resume
638 * as it's already done during modeset initialization then.
639 * It's also invalid here as encoder list is still uninitialized.
640 */
641 if (!dev_priv->power_domains.initializing)
642 intel_prepare_ddi(dev);
643 } else {
644 gen9_disable_dc5(dev_priv);
645 }
646 }
647 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
648 }
649
650 if (!is_enabled) {
651 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
652 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
653 state_mask), 1))
654 DRM_ERROR("%s enable timeout\n",
655 power_well->name);
656 check_fuse_status = true;
657 }
658 } else {
659 if (enable_requested) {
660 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
661 POSTING_READ(HSW_PWR_WELL_DRIVER);
662 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
663
664 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
665 power_well->data == SKL_DISP_PW_2) {
666 enum csr_state state;
667 /* TODO: wait for a completion event or
668 * similar here instead of busy
669 * waiting using wait_for function.
670 */
671 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
672 FW_UNINITIALIZED, 1000);
673 if (state != FW_LOADED)
674 DRM_ERROR("CSR firmware not ready (%d)\n",
675 state);
676 else
677 if (SKL_ENABLE_DC6(dev))
678 skl_enable_dc6(dev_priv);
679 else
680 gen9_enable_dc5(dev_priv);
681 }
682 }
683 }
684
685 if (check_fuse_status) {
686 if (power_well->data == SKL_DISP_PW_1) {
687 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
688 SKL_FUSE_PG1_DIST_STATUS), 1))
689 DRM_ERROR("PG1 distributing status timeout\n");
690 } else if (power_well->data == SKL_DISP_PW_2) {
691 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
692 SKL_FUSE_PG2_DIST_STATUS), 1))
693 DRM_ERROR("PG2 distributing status timeout\n");
694 }
695 }
696
697 if (enable && !is_enabled)
698 skl_power_well_post_enable(dev_priv, power_well);
699 }
700
701 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
702 struct i915_power_well *power_well)
703 {
704 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
705
706 /*
707 * We're taking over the BIOS, so clear any requests made by it since
708 * the driver is in charge now.
709 */
710 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
711 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
712 }
713
714 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
715 struct i915_power_well *power_well)
716 {
717 hsw_set_power_well(dev_priv, power_well, true);
718 }
719
720 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
721 struct i915_power_well *power_well)
722 {
723 hsw_set_power_well(dev_priv, power_well, false);
724 }
725
726 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
727 struct i915_power_well *power_well)
728 {
729 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
730 SKL_POWER_WELL_STATE(power_well->data);
731
732 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
733 }
734
735 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
736 struct i915_power_well *power_well)
737 {
738 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
739
740 /* Clear any request made by BIOS as driver is taking over */
741 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
742 }
743
744 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
745 struct i915_power_well *power_well)
746 {
747 skl_set_power_well(dev_priv, power_well, true);
748 }
749
750 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
751 struct i915_power_well *power_well)
752 {
753 skl_set_power_well(dev_priv, power_well, false);
754 }
755
756 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
757 struct i915_power_well *power_well)
758 {
759 }
760
761 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
762 struct i915_power_well *power_well)
763 {
764 return true;
765 }
766
767 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
768 struct i915_power_well *power_well, bool enable)
769 {
770 enum punit_power_well power_well_id = power_well->data;
771 u32 mask;
772 u32 state;
773 u32 ctrl;
774
775 mask = PUNIT_PWRGT_MASK(power_well_id);
776 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
777 PUNIT_PWRGT_PWR_GATE(power_well_id);
778
779 mutex_lock(&dev_priv->rps.hw_lock);
780
781 #define COND \
782 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
783
784 if (COND)
785 goto out;
786
787 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
788 ctrl &= ~mask;
789 ctrl |= state;
790 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
791
792 if (wait_for(COND, 100))
793 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
794 state,
795 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
796
797 #undef COND
798
799 out:
800 mutex_unlock(&dev_priv->rps.hw_lock);
801 }
802
803 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
804 struct i915_power_well *power_well)
805 {
806 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
807 }
808
809 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
810 struct i915_power_well *power_well)
811 {
812 vlv_set_power_well(dev_priv, power_well, true);
813 }
814
815 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
816 struct i915_power_well *power_well)
817 {
818 vlv_set_power_well(dev_priv, power_well, false);
819 }
820
821 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
822 struct i915_power_well *power_well)
823 {
824 int power_well_id = power_well->data;
825 bool enabled = false;
826 u32 mask;
827 u32 state;
828 u32 ctrl;
829
830 mask = PUNIT_PWRGT_MASK(power_well_id);
831 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
832
833 mutex_lock(&dev_priv->rps.hw_lock);
834
835 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
836 /*
837 * We only ever set the power-on and power-gate states, anything
838 * else is unexpected.
839 */
840 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
841 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
842 if (state == ctrl)
843 enabled = true;
844
845 /*
846 * A transient state at this point would mean some unexpected party
847 * is poking at the power controls too.
848 */
849 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
850 WARN_ON(ctrl != state);
851
852 mutex_unlock(&dev_priv->rps.hw_lock);
853
854 return enabled;
855 }
856
857 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
858 {
859
860 spin_lock_irq(&dev_priv->irq_lock);
861 valleyview_enable_display_irqs(dev_priv);
862 spin_unlock_irq(&dev_priv->irq_lock);
863
864 /*
865 * During driver initialization/resume we can avoid restoring the
866 * part of the HW/SW state that will be inited anyway explicitly.
867 */
868 if (dev_priv->power_domains.initializing)
869 return;
870
871 intel_hpd_init(dev_priv);
872
873 i915_redisable_vga_power_on(dev_priv->dev);
874 }
875
876 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
877 {
878 spin_lock_irq(&dev_priv->irq_lock);
879 valleyview_disable_display_irqs(dev_priv);
880 spin_unlock_irq(&dev_priv->irq_lock);
881
882 vlv_power_sequencer_reset(dev_priv);
883 }
884
885 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
886 struct i915_power_well *power_well)
887 {
888 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
889
890 vlv_set_power_well(dev_priv, power_well, true);
891
892 vlv_display_power_well_init(dev_priv);
893 }
894
895 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
896 struct i915_power_well *power_well)
897 {
898 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
899
900 vlv_display_power_well_deinit(dev_priv);
901
902 vlv_set_power_well(dev_priv, power_well, false);
903 }
904
905 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
906 struct i915_power_well *power_well)
907 {
908 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
909
910 /*
911 * Enable the CRI clock source so we can get at the
912 * display and the reference clock for VGA
913 * hotplug / manual detection.
914 */
915 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
916 DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
917 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
918
919 vlv_set_power_well(dev_priv, power_well, true);
920
921 /*
922 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
923 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
924 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
925 * b. The other bits such as sfr settings / modesel may all
926 * be set to 0.
927 *
928 * This should only be done on init and resume from S3 with
929 * both PLLs disabled, or we risk losing DPIO and PLL
930 * synchronization.
931 */
932 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
933 }
934
935 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
936 struct i915_power_well *power_well)
937 {
938 enum pipe pipe;
939
940 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
941
942 for_each_pipe(dev_priv, pipe)
943 assert_pll_disabled(dev_priv, pipe);
944
945 /* Assert common reset */
946 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
947
948 vlv_set_power_well(dev_priv, power_well, false);
949 }
950
951 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
952 struct i915_power_well *power_well)
953 {
954 enum dpio_phy phy;
955
956 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
957 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
958
959 /*
960 * Enable the CRI clock source so we can get at the
961 * display and the reference clock for VGA
962 * hotplug / manual detection.
963 */
964 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
965 phy = DPIO_PHY0;
966 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
967 DPLL_REF_CLK_ENABLE_VLV);
968 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | DPLL_VGA_MODE_DIS |
969 DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
970 } else {
971 phy = DPIO_PHY1;
972 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | DPLL_VGA_MODE_DIS |
973 DPLL_REF_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
974 }
975 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
976 vlv_set_power_well(dev_priv, power_well, true);
977
978 /* Poll for phypwrgood signal */
979 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
980 DRM_ERROR("Display PHY %d is not power up\n", phy);
981
982 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
983 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
984 }
985
986 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
987 struct i915_power_well *power_well)
988 {
989 enum dpio_phy phy;
990
991 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
992 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
993
994 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
995 phy = DPIO_PHY0;
996 assert_pll_disabled(dev_priv, PIPE_A);
997 assert_pll_disabled(dev_priv, PIPE_B);
998 } else {
999 phy = DPIO_PHY1;
1000 assert_pll_disabled(dev_priv, PIPE_C);
1001 }
1002
1003 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1004 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1005
1006 vlv_set_power_well(dev_priv, power_well, false);
1007 }
1008
1009 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1010 struct i915_power_well *power_well)
1011 {
1012 enum pipe pipe = power_well->data;
1013 bool enabled;
1014 u32 state, ctrl;
1015
1016 mutex_lock(&dev_priv->rps.hw_lock);
1017
1018 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1019 /*
1020 * We only ever set the power-on and power-gate states, anything
1021 * else is unexpected.
1022 */
1023 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1024 enabled = state == DP_SSS_PWR_ON(pipe);
1025
1026 /*
1027 * A transient state at this point would mean some unexpected party
1028 * is poking at the power controls too.
1029 */
1030 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1031 WARN_ON(ctrl << 16 != state);
1032
1033 mutex_unlock(&dev_priv->rps.hw_lock);
1034
1035 return enabled;
1036 }
1037
1038 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1039 struct i915_power_well *power_well,
1040 bool enable)
1041 {
1042 enum pipe pipe = power_well->data;
1043 u32 state;
1044 u32 ctrl;
1045
1046 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1047
1048 mutex_lock(&dev_priv->rps.hw_lock);
1049
1050 #define COND \
1051 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1052
1053 if (COND)
1054 goto out;
1055
1056 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1057 ctrl &= ~DP_SSC_MASK(pipe);
1058 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1059 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1060
1061 if (wait_for(COND, 100))
1062 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1063 state,
1064 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1065
1066 #undef COND
1067
1068 out:
1069 mutex_unlock(&dev_priv->rps.hw_lock);
1070 }
1071
1072 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1073 struct i915_power_well *power_well)
1074 {
1075 WARN_ON_ONCE(power_well->data != PIPE_A);
1076
1077 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1078 }
1079
1080 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1081 struct i915_power_well *power_well)
1082 {
1083 WARN_ON_ONCE(power_well->data != PIPE_A);
1084
1085 chv_set_pipe_power_well(dev_priv, power_well, true);
1086
1087 vlv_display_power_well_init(dev_priv);
1088 }
1089
1090 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1091 struct i915_power_well *power_well)
1092 {
1093 WARN_ON_ONCE(power_well->data != PIPE_A);
1094
1095 vlv_display_power_well_deinit(dev_priv);
1096
1097 chv_set_pipe_power_well(dev_priv, power_well, false);
1098 }
1099
1100 /**
1101 * intel_display_power_get - grab a power domain reference
1102 * @dev_priv: i915 device instance
1103 * @domain: power domain to reference
1104 *
1105 * This function grabs a power domain reference for @domain and ensures that the
1106 * power domain and all its parents are powered up. Therefore users should only
1107 * grab a reference to the innermost power domain they need.
1108 *
1109 * Any power domain reference obtained by this function must have a symmetric
1110 * call to intel_display_power_put() to release the reference again.
1111 */
1112 void intel_display_power_get(struct drm_i915_private *dev_priv,
1113 enum intel_display_power_domain domain)
1114 {
1115 struct i915_power_domains *power_domains;
1116 struct i915_power_well *power_well;
1117 int i;
1118
1119 intel_runtime_pm_get(dev_priv);
1120
1121 power_domains = &dev_priv->power_domains;
1122
1123 mutex_lock(&power_domains->lock);
1124
1125 for_each_power_well(i, power_well, BIT(domain), power_domains) {
1126 if (!power_well->count++)
1127 intel_power_well_enable(dev_priv, power_well);
1128 }
1129
1130 power_domains->domain_use_count[domain]++;
1131
1132 mutex_unlock(&power_domains->lock);
1133 }
1134
1135 /**
1136 * intel_display_power_put - release a power domain reference
1137 * @dev_priv: i915 device instance
1138 * @domain: power domain to reference
1139 *
1140 * This function drops the power domain reference obtained by
1141 * intel_display_power_get() and might power down the corresponding hardware
1142 * block right away if this is the last reference.
1143 */
1144 void intel_display_power_put(struct drm_i915_private *dev_priv,
1145 enum intel_display_power_domain domain)
1146 {
1147 struct i915_power_domains *power_domains;
1148 struct i915_power_well *power_well;
1149 int i;
1150
1151 power_domains = &dev_priv->power_domains;
1152
1153 mutex_lock(&power_domains->lock);
1154
1155 WARN_ON(!power_domains->domain_use_count[domain]);
1156 power_domains->domain_use_count[domain]--;
1157
1158 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1159 WARN_ON(!power_well->count);
1160
1161 if (!--power_well->count && i915.disable_power_well)
1162 intel_power_well_disable(dev_priv, power_well);
1163 }
1164
1165 mutex_unlock(&power_domains->lock);
1166
1167 intel_runtime_pm_put(dev_priv);
1168 }
1169
1170 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1171
1172 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1173 BIT(POWER_DOMAIN_PIPE_A) | \
1174 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1175 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
1176 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
1177 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1178 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1179 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1180 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1181 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1182 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1183 BIT(POWER_DOMAIN_PORT_CRT) | \
1184 BIT(POWER_DOMAIN_PLLS) | \
1185 BIT(POWER_DOMAIN_AUX_A) | \
1186 BIT(POWER_DOMAIN_AUX_B) | \
1187 BIT(POWER_DOMAIN_AUX_C) | \
1188 BIT(POWER_DOMAIN_AUX_D) | \
1189 BIT(POWER_DOMAIN_INIT))
1190 #define HSW_DISPLAY_POWER_DOMAINS ( \
1191 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1192 BIT(POWER_DOMAIN_INIT))
1193
1194 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1195 HSW_ALWAYS_ON_POWER_DOMAINS | \
1196 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1197 #define BDW_DISPLAY_POWER_DOMAINS ( \
1198 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1199 BIT(POWER_DOMAIN_INIT))
1200
1201 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1202 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1203
1204 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1205 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1206 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1207 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1208 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1209 BIT(POWER_DOMAIN_PORT_CRT) | \
1210 BIT(POWER_DOMAIN_AUX_B) | \
1211 BIT(POWER_DOMAIN_AUX_C) | \
1212 BIT(POWER_DOMAIN_INIT))
1213
1214 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1215 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1216 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1217 BIT(POWER_DOMAIN_AUX_B) | \
1218 BIT(POWER_DOMAIN_INIT))
1219
1220 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1221 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1222 BIT(POWER_DOMAIN_AUX_B) | \
1223 BIT(POWER_DOMAIN_INIT))
1224
1225 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1226 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1227 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1228 BIT(POWER_DOMAIN_AUX_C) | \
1229 BIT(POWER_DOMAIN_INIT))
1230
1231 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1232 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1233 BIT(POWER_DOMAIN_AUX_C) | \
1234 BIT(POWER_DOMAIN_INIT))
1235
1236 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1237 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1238 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1239 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1240 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1241 BIT(POWER_DOMAIN_AUX_B) | \
1242 BIT(POWER_DOMAIN_AUX_C) | \
1243 BIT(POWER_DOMAIN_INIT))
1244
1245 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1246 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1247 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1248 BIT(POWER_DOMAIN_AUX_D) | \
1249 BIT(POWER_DOMAIN_INIT))
1250
1251 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1252 .sync_hw = i9xx_always_on_power_well_noop,
1253 .enable = i9xx_always_on_power_well_noop,
1254 .disable = i9xx_always_on_power_well_noop,
1255 .is_enabled = i9xx_always_on_power_well_enabled,
1256 };
1257
1258 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1259 .sync_hw = chv_pipe_power_well_sync_hw,
1260 .enable = chv_pipe_power_well_enable,
1261 .disable = chv_pipe_power_well_disable,
1262 .is_enabled = chv_pipe_power_well_enabled,
1263 };
1264
1265 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1266 .sync_hw = vlv_power_well_sync_hw,
1267 .enable = chv_dpio_cmn_power_well_enable,
1268 .disable = chv_dpio_cmn_power_well_disable,
1269 .is_enabled = vlv_power_well_enabled,
1270 };
1271
1272 static struct i915_power_well i9xx_always_on_power_well[] = {
1273 {
1274 .name = "always-on",
1275 .always_on = 1,
1276 .domains = POWER_DOMAIN_MASK,
1277 .ops = &i9xx_always_on_power_well_ops,
1278 },
1279 };
1280
1281 static const struct i915_power_well_ops hsw_power_well_ops = {
1282 .sync_hw = hsw_power_well_sync_hw,
1283 .enable = hsw_power_well_enable,
1284 .disable = hsw_power_well_disable,
1285 .is_enabled = hsw_power_well_enabled,
1286 };
1287
1288 static const struct i915_power_well_ops skl_power_well_ops = {
1289 .sync_hw = skl_power_well_sync_hw,
1290 .enable = skl_power_well_enable,
1291 .disable = skl_power_well_disable,
1292 .is_enabled = skl_power_well_enabled,
1293 };
1294
1295 static struct i915_power_well hsw_power_wells[] = {
1296 {
1297 .name = "always-on",
1298 .always_on = 1,
1299 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1300 .ops = &i9xx_always_on_power_well_ops,
1301 },
1302 {
1303 .name = "display",
1304 .domains = HSW_DISPLAY_POWER_DOMAINS,
1305 .ops = &hsw_power_well_ops,
1306 },
1307 };
1308
1309 static struct i915_power_well bdw_power_wells[] = {
1310 {
1311 .name = "always-on",
1312 .always_on = 1,
1313 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1314 .ops = &i9xx_always_on_power_well_ops,
1315 },
1316 {
1317 .name = "display",
1318 .domains = BDW_DISPLAY_POWER_DOMAINS,
1319 .ops = &hsw_power_well_ops,
1320 },
1321 };
1322
1323 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1324 .sync_hw = vlv_power_well_sync_hw,
1325 .enable = vlv_display_power_well_enable,
1326 .disable = vlv_display_power_well_disable,
1327 .is_enabled = vlv_power_well_enabled,
1328 };
1329
1330 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1331 .sync_hw = vlv_power_well_sync_hw,
1332 .enable = vlv_dpio_cmn_power_well_enable,
1333 .disable = vlv_dpio_cmn_power_well_disable,
1334 .is_enabled = vlv_power_well_enabled,
1335 };
1336
1337 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1338 .sync_hw = vlv_power_well_sync_hw,
1339 .enable = vlv_power_well_enable,
1340 .disable = vlv_power_well_disable,
1341 .is_enabled = vlv_power_well_enabled,
1342 };
1343
1344 static struct i915_power_well vlv_power_wells[] = {
1345 {
1346 .name = "always-on",
1347 .always_on = 1,
1348 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1349 .ops = &i9xx_always_on_power_well_ops,
1350 },
1351 {
1352 .name = "display",
1353 .domains = VLV_DISPLAY_POWER_DOMAINS,
1354 .data = PUNIT_POWER_WELL_DISP2D,
1355 .ops = &vlv_display_power_well_ops,
1356 },
1357 {
1358 .name = "dpio-tx-b-01",
1359 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1360 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1361 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1362 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1363 .ops = &vlv_dpio_power_well_ops,
1364 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1365 },
1366 {
1367 .name = "dpio-tx-b-23",
1368 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1369 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1370 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1371 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1372 .ops = &vlv_dpio_power_well_ops,
1373 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1374 },
1375 {
1376 .name = "dpio-tx-c-01",
1377 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1378 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1379 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1380 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1381 .ops = &vlv_dpio_power_well_ops,
1382 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1383 },
1384 {
1385 .name = "dpio-tx-c-23",
1386 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1387 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1388 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1389 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1390 .ops = &vlv_dpio_power_well_ops,
1391 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1392 },
1393 {
1394 .name = "dpio-common",
1395 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1396 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1397 .ops = &vlv_dpio_cmn_power_well_ops,
1398 },
1399 };
1400
1401 static struct i915_power_well chv_power_wells[] = {
1402 {
1403 .name = "always-on",
1404 .always_on = 1,
1405 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1406 .ops = &i9xx_always_on_power_well_ops,
1407 },
1408 {
1409 .name = "display",
1410 /*
1411 * Pipe A power well is the new disp2d well. Pipe B and C
1412 * power wells don't actually exist. Pipe A power well is
1413 * required for any pipe to work.
1414 */
1415 .domains = VLV_DISPLAY_POWER_DOMAINS,
1416 .data = PIPE_A,
1417 .ops = &chv_pipe_power_well_ops,
1418 },
1419 {
1420 .name = "dpio-common-bc",
1421 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1422 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1423 .ops = &chv_dpio_cmn_power_well_ops,
1424 },
1425 {
1426 .name = "dpio-common-d",
1427 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1428 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1429 .ops = &chv_dpio_cmn_power_well_ops,
1430 },
1431 };
1432
1433 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1434 int power_well_id)
1435 {
1436 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1437 struct i915_power_well *power_well;
1438 int i;
1439
1440 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1441 if (power_well->data == power_well_id)
1442 return power_well;
1443 }
1444
1445 return NULL;
1446 }
1447
1448 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1449 int power_well_id)
1450 {
1451 struct i915_power_well *power_well;
1452 bool ret;
1453
1454 power_well = lookup_power_well(dev_priv, power_well_id);
1455 ret = power_well->ops->is_enabled(dev_priv, power_well);
1456
1457 return ret;
1458 }
1459
1460 static struct i915_power_well skl_power_wells[] = {
1461 {
1462 .name = "always-on",
1463 .always_on = 1,
1464 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1465 .ops = &i9xx_always_on_power_well_ops,
1466 },
1467 {
1468 .name = "power well 1",
1469 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1470 .ops = &skl_power_well_ops,
1471 .data = SKL_DISP_PW_1,
1472 },
1473 {
1474 .name = "MISC IO power well",
1475 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1476 .ops = &skl_power_well_ops,
1477 .data = SKL_DISP_PW_MISC_IO,
1478 },
1479 {
1480 .name = "power well 2",
1481 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1482 .ops = &skl_power_well_ops,
1483 .data = SKL_DISP_PW_2,
1484 },
1485 {
1486 .name = "DDI A/E power well",
1487 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1488 .ops = &skl_power_well_ops,
1489 .data = SKL_DISP_PW_DDI_A_E,
1490 },
1491 {
1492 .name = "DDI B power well",
1493 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1494 .ops = &skl_power_well_ops,
1495 .data = SKL_DISP_PW_DDI_B,
1496 },
1497 {
1498 .name = "DDI C power well",
1499 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1500 .ops = &skl_power_well_ops,
1501 .data = SKL_DISP_PW_DDI_C,
1502 },
1503 {
1504 .name = "DDI D power well",
1505 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1506 .ops = &skl_power_well_ops,
1507 .data = SKL_DISP_PW_DDI_D,
1508 },
1509 };
1510
1511 static struct i915_power_well bxt_power_wells[] = {
1512 {
1513 .name = "always-on",
1514 .always_on = 1,
1515 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1516 .ops = &i9xx_always_on_power_well_ops,
1517 },
1518 {
1519 .name = "power well 1",
1520 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1521 .ops = &skl_power_well_ops,
1522 .data = SKL_DISP_PW_1,
1523 },
1524 {
1525 .name = "power well 2",
1526 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1527 .ops = &skl_power_well_ops,
1528 .data = SKL_DISP_PW_2,
1529 }
1530 };
1531
1532 #define set_power_wells(power_domains, __power_wells) ({ \
1533 (power_domains)->power_wells = (__power_wells); \
1534 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1535 })
1536
1537 /**
1538 * intel_power_domains_init - initializes the power domain structures
1539 * @dev_priv: i915 device instance
1540 *
1541 * Initializes the power domain structures for @dev_priv depending upon the
1542 * supported platform.
1543 */
1544 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1545 {
1546 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1547
1548 mutex_init(&power_domains->lock);
1549
1550 /*
1551 * The enabling order will be from lower to higher indexed wells,
1552 * the disabling order is reversed.
1553 */
1554 if (IS_HASWELL(dev_priv->dev)) {
1555 set_power_wells(power_domains, hsw_power_wells);
1556 } else if (IS_BROADWELL(dev_priv->dev)) {
1557 set_power_wells(power_domains, bdw_power_wells);
1558 } else if (IS_SKYLAKE(dev_priv->dev)) {
1559 set_power_wells(power_domains, skl_power_wells);
1560 } else if (IS_BROXTON(dev_priv->dev)) {
1561 set_power_wells(power_domains, bxt_power_wells);
1562 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1563 set_power_wells(power_domains, chv_power_wells);
1564 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1565 set_power_wells(power_domains, vlv_power_wells);
1566 } else {
1567 set_power_wells(power_domains, i9xx_always_on_power_well);
1568 }
1569
1570 return 0;
1571 }
1572
1573 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1574 {
1575 struct drm_device *dev = dev_priv->dev;
1576 struct device *device = &dev->pdev->dev;
1577
1578 if (!HAS_RUNTIME_PM(dev))
1579 return;
1580
1581 if (!intel_enable_rc6(dev))
1582 return;
1583
1584 /* Make sure we're not suspended first. */
1585 pm_runtime_get_sync(device);
1586 pm_runtime_disable(device);
1587 }
1588
1589 /**
1590 * intel_power_domains_fini - finalizes the power domain structures
1591 * @dev_priv: i915 device instance
1592 *
1593 * Finalizes the power domain structures for @dev_priv depending upon the
1594 * supported platform. This function also disables runtime pm and ensures that
1595 * the device stays powered up so that the driver can be reloaded.
1596 */
1597 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1598 {
1599 intel_runtime_pm_disable(dev_priv);
1600
1601 /* The i915.ko module is still not prepared to be loaded when
1602 * the power well is not enabled, so just enable it in case
1603 * we're going to unload/reload. */
1604 intel_display_set_init_power(dev_priv, true);
1605 }
1606
1607 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1608 {
1609 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1610 struct i915_power_well *power_well;
1611 int i;
1612
1613 mutex_lock(&power_domains->lock);
1614 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1615 power_well->ops->sync_hw(dev_priv, power_well);
1616 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1617 power_well);
1618 }
1619 mutex_unlock(&power_domains->lock);
1620 }
1621
1622 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1623 {
1624 struct i915_power_well *cmn_bc =
1625 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1626 struct i915_power_well *cmn_d =
1627 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1628
1629 /*
1630 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1631 * workaround never ever read DISPLAY_PHY_CONTROL, and
1632 * instead maintain a shadow copy ourselves. Use the actual
1633 * power well state to reconstruct the expected initial
1634 * value.
1635 */
1636 dev_priv->chv_phy_control =
1637 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1638 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1639 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) |
1640 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) |
1641 PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0);
1642 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc))
1643 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1644 if (cmn_d->ops->is_enabled(dev_priv, cmn_d))
1645 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1646 }
1647
1648 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1649 {
1650 struct i915_power_well *cmn =
1651 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1652 struct i915_power_well *disp2d =
1653 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1654
1655 /* If the display might be already active skip this */
1656 if (cmn->ops->is_enabled(dev_priv, cmn) &&
1657 disp2d->ops->is_enabled(dev_priv, disp2d) &&
1658 I915_READ(DPIO_CTL) & DPIO_CMNRST)
1659 return;
1660
1661 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1662
1663 /* cmnlane needs DPLL registers */
1664 disp2d->ops->enable(dev_priv, disp2d);
1665
1666 /*
1667 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1668 * Need to assert and de-assert PHY SB reset by gating the
1669 * common lane power, then un-gating it.
1670 * Simply ungating isn't enough to reset the PHY enough to get
1671 * ports and lanes running.
1672 */
1673 cmn->ops->disable(dev_priv, cmn);
1674 }
1675
1676 /**
1677 * intel_power_domains_init_hw - initialize hardware power domain state
1678 * @dev_priv: i915 device instance
1679 *
1680 * This function initializes the hardware power domain state and enables all
1681 * power domains using intel_display_set_init_power().
1682 */
1683 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1684 {
1685 struct drm_device *dev = dev_priv->dev;
1686 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1687
1688 power_domains->initializing = true;
1689
1690 if (IS_CHERRYVIEW(dev)) {
1691 chv_phy_control_init(dev_priv);
1692 } else if (IS_VALLEYVIEW(dev)) {
1693 mutex_lock(&power_domains->lock);
1694 vlv_cmnlane_wa(dev_priv);
1695 mutex_unlock(&power_domains->lock);
1696 }
1697
1698 /* For now, we need the power well to be always enabled. */
1699 intel_display_set_init_power(dev_priv, true);
1700 intel_power_domains_resume(dev_priv);
1701 power_domains->initializing = false;
1702 }
1703
1704 /**
1705 * intel_aux_display_runtime_get - grab an auxiliary power domain reference
1706 * @dev_priv: i915 device instance
1707 *
1708 * This function grabs a power domain reference for the auxiliary power domain
1709 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1710 * parents are powered up. Therefore users should only grab a reference to the
1711 * innermost power domain they need.
1712 *
1713 * Any power domain reference obtained by this function must have a symmetric
1714 * call to intel_aux_display_runtime_put() to release the reference again.
1715 */
1716 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
1717 {
1718 intel_runtime_pm_get(dev_priv);
1719 }
1720
1721 /**
1722 * intel_aux_display_runtime_put - release an auxiliary power domain reference
1723 * @dev_priv: i915 device instance
1724 *
1725 * This function drops the auxiliary power domain reference obtained by
1726 * intel_aux_display_runtime_get() and might power down the corresponding
1727 * hardware block right away if this is the last reference.
1728 */
1729 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
1730 {
1731 intel_runtime_pm_put(dev_priv);
1732 }
1733
1734 /**
1735 * intel_runtime_pm_get - grab a runtime pm reference
1736 * @dev_priv: i915 device instance
1737 *
1738 * This function grabs a device-level runtime pm reference (mostly used for GEM
1739 * code to ensure the GTT or GT is on) and ensures that it is powered up.
1740 *
1741 * Any runtime pm reference obtained by this function must have a symmetric
1742 * call to intel_runtime_pm_put() to release the reference again.
1743 */
1744 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
1745 {
1746 struct drm_device *dev = dev_priv->dev;
1747 struct device *device = &dev->pdev->dev;
1748
1749 if (!HAS_RUNTIME_PM(dev))
1750 return;
1751
1752 pm_runtime_get_sync(device);
1753 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
1754 }
1755
1756 /**
1757 * intel_runtime_pm_get_noresume - grab a runtime pm reference
1758 * @dev_priv: i915 device instance
1759 *
1760 * This function grabs a device-level runtime pm reference (mostly used for GEM
1761 * code to ensure the GTT or GT is on).
1762 *
1763 * It will _not_ power up the device but instead only check that it's powered
1764 * on. Therefore it is only valid to call this functions from contexts where
1765 * the device is known to be powered up and where trying to power it up would
1766 * result in hilarity and deadlocks. That pretty much means only the system
1767 * suspend/resume code where this is used to grab runtime pm references for
1768 * delayed setup down in work items.
1769 *
1770 * Any runtime pm reference obtained by this function must have a symmetric
1771 * call to intel_runtime_pm_put() to release the reference again.
1772 */
1773 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
1774 {
1775 struct drm_device *dev = dev_priv->dev;
1776 struct device *device = &dev->pdev->dev;
1777
1778 if (!HAS_RUNTIME_PM(dev))
1779 return;
1780
1781 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
1782 pm_runtime_get_noresume(device);
1783 }
1784
1785 /**
1786 * intel_runtime_pm_put - release a runtime pm reference
1787 * @dev_priv: i915 device instance
1788 *
1789 * This function drops the device-level runtime pm reference obtained by
1790 * intel_runtime_pm_get() and might power down the corresponding
1791 * hardware block right away if this is the last reference.
1792 */
1793 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
1794 {
1795 struct drm_device *dev = dev_priv->dev;
1796 struct device *device = &dev->pdev->dev;
1797
1798 if (!HAS_RUNTIME_PM(dev))
1799 return;
1800
1801 pm_runtime_mark_last_busy(device);
1802 pm_runtime_put_autosuspend(device);
1803 }
1804
1805 /**
1806 * intel_runtime_pm_enable - enable runtime pm
1807 * @dev_priv: i915 device instance
1808 *
1809 * This function enables runtime pm at the end of the driver load sequence.
1810 *
1811 * Note that this function does currently not enable runtime pm for the
1812 * subordinate display power domains. That is only done on the first modeset
1813 * using intel_display_set_init_power().
1814 */
1815 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
1816 {
1817 struct drm_device *dev = dev_priv->dev;
1818 struct device *device = &dev->pdev->dev;
1819
1820 if (!HAS_RUNTIME_PM(dev))
1821 return;
1822
1823 pm_runtime_set_active(device);
1824
1825 /*
1826 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1827 * requirement.
1828 */
1829 if (!intel_enable_rc6(dev)) {
1830 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1831 return;
1832 }
1833
1834 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
1835 pm_runtime_mark_last_busy(device);
1836 pm_runtime_use_autosuspend(device);
1837
1838 pm_runtime_put_autosuspend(device);
1839 }
1840
Linux kernel - Deliverables
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