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drm/i915: Enable querying offset of UV plane with intel_plane_obj_offset
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
1 /*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
31
32 #include "i915_drv.h"
33 #include "intel_drv.h"
34
35 /**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
52 #define GEN9_ENABLE_DC5(dev) 0
53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
54
55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
56 for (i = 0; \
57 i < (power_domains)->power_well_count && \
58 ((power_well) = &(power_domains)->power_wells[i]); \
59 i++) \
60 if ((power_well)->domains & (domain_mask))
61
62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63 for (i = (power_domains)->power_well_count - 1; \
64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
65 i--) \
66 if ((power_well)->domains & (domain_mask))
67
68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
69 int power_well_id);
70
71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
72 struct i915_power_well *power_well)
73 {
74 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
75 power_well->ops->enable(dev_priv, power_well);
76 power_well->hw_enabled = true;
77 }
78
79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
80 struct i915_power_well *power_well)
81 {
82 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
83 power_well->hw_enabled = false;
84 power_well->ops->disable(dev_priv, power_well);
85 }
86
87 /*
88 * We should only use the power well if we explicitly asked the hardware to
89 * enable it, so check if it's enabled and also check if we've requested it to
90 * be enabled.
91 */
92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
93 struct i915_power_well *power_well)
94 {
95 return I915_READ(HSW_PWR_WELL_DRIVER) ==
96 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
97 }
98
99 /**
100 * __intel_display_power_is_enabled - unlocked check for a power domain
101 * @dev_priv: i915 device instance
102 * @domain: power domain to check
103 *
104 * This is the unlocked version of intel_display_power_is_enabled() and should
105 * only be used from error capture and recovery code where deadlocks are
106 * possible.
107 *
108 * Returns:
109 * True when the power domain is enabled, false otherwise.
110 */
111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
112 enum intel_display_power_domain domain)
113 {
114 struct i915_power_domains *power_domains;
115 struct i915_power_well *power_well;
116 bool is_enabled;
117 int i;
118
119 if (dev_priv->pm.suspended)
120 return false;
121
122 power_domains = &dev_priv->power_domains;
123
124 is_enabled = true;
125
126 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
127 if (power_well->always_on)
128 continue;
129
130 if (!power_well->hw_enabled) {
131 is_enabled = false;
132 break;
133 }
134 }
135
136 return is_enabled;
137 }
138
139 /**
140 * intel_display_power_is_enabled - check for a power domain
141 * @dev_priv: i915 device instance
142 * @domain: power domain to check
143 *
144 * This function can be used to check the hw power domain state. It is mostly
145 * used in hardware state readout functions. Everywhere else code should rely
146 * upon explicit power domain reference counting to ensure that the hardware
147 * block is powered up before accessing it.
148 *
149 * Callers must hold the relevant modesetting locks to ensure that concurrent
150 * threads can't disable the power well while the caller tries to read a few
151 * registers.
152 *
153 * Returns:
154 * True when the power domain is enabled, false otherwise.
155 */
156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
157 enum intel_display_power_domain domain)
158 {
159 struct i915_power_domains *power_domains;
160 bool ret;
161
162 power_domains = &dev_priv->power_domains;
163
164 mutex_lock(&power_domains->lock);
165 ret = __intel_display_power_is_enabled(dev_priv, domain);
166 mutex_unlock(&power_domains->lock);
167
168 return ret;
169 }
170
171 /**
172 * intel_display_set_init_power - set the initial power domain state
173 * @dev_priv: i915 device instance
174 * @enable: whether to enable or disable the initial power domain state
175 *
176 * For simplicity our driver load/unload and system suspend/resume code assumes
177 * that all power domains are always enabled. This functions controls the state
178 * of this little hack. While the initial power domain state is enabled runtime
179 * pm is effectively disabled.
180 */
181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
182 bool enable)
183 {
184 if (dev_priv->power_domains.init_power_on == enable)
185 return;
186
187 if (enable)
188 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
189 else
190 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
191
192 dev_priv->power_domains.init_power_on = enable;
193 }
194
195 /*
196 * Starting with Haswell, we have a "Power Down Well" that can be turned off
197 * when not needed anymore. We have 4 registers that can request the power well
198 * to be enabled, and it will only be disabled if none of the registers is
199 * requesting it to be enabled.
200 */
201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
202 {
203 struct drm_device *dev = dev_priv->dev;
204
205 /*
206 * After we re-enable the power well, if we touch VGA register 0x3d5
207 * we'll get unclaimed register interrupts. This stops after we write
208 * anything to the VGA MSR register. The vgacon module uses this
209 * register all the time, so if we unbind our driver and, as a
210 * consequence, bind vgacon, we'll get stuck in an infinite loop at
211 * console_unlock(). So make here we touch the VGA MSR register, making
212 * sure vgacon can keep working normally without triggering interrupts
213 * and error messages.
214 */
215 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
216 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
217 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
218
219 if (IS_BROADWELL(dev))
220 gen8_irq_power_well_post_enable(dev_priv,
221 1 << PIPE_C | 1 << PIPE_B);
222 }
223
224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
225 struct i915_power_well *power_well)
226 {
227 struct drm_device *dev = dev_priv->dev;
228
229 /*
230 * After we re-enable the power well, if we touch VGA register 0x3d5
231 * we'll get unclaimed register interrupts. This stops after we write
232 * anything to the VGA MSR register. The vgacon module uses this
233 * register all the time, so if we unbind our driver and, as a
234 * consequence, bind vgacon, we'll get stuck in an infinite loop at
235 * console_unlock(). So make here we touch the VGA MSR register, making
236 * sure vgacon can keep working normally without triggering interrupts
237 * and error messages.
238 */
239 if (power_well->data == SKL_DISP_PW_2) {
240 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
241 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
242 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
243
244 gen8_irq_power_well_post_enable(dev_priv,
245 1 << PIPE_C | 1 << PIPE_B);
246 }
247
248 if (power_well->data == SKL_DISP_PW_1) {
249 intel_prepare_ddi(dev);
250 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
251 }
252 }
253
254 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
255 struct i915_power_well *power_well, bool enable)
256 {
257 bool is_enabled, enable_requested;
258 uint32_t tmp;
259
260 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
261 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
262 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
263
264 if (enable) {
265 if (!enable_requested)
266 I915_WRITE(HSW_PWR_WELL_DRIVER,
267 HSW_PWR_WELL_ENABLE_REQUEST);
268
269 if (!is_enabled) {
270 DRM_DEBUG_KMS("Enabling power well\n");
271 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
272 HSW_PWR_WELL_STATE_ENABLED), 20))
273 DRM_ERROR("Timeout enabling power well\n");
274 hsw_power_well_post_enable(dev_priv);
275 }
276
277 } else {
278 if (enable_requested) {
279 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
280 POSTING_READ(HSW_PWR_WELL_DRIVER);
281 DRM_DEBUG_KMS("Requesting to disable the power well\n");
282 }
283 }
284 }
285
286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
287 BIT(POWER_DOMAIN_TRANSCODER_A) | \
288 BIT(POWER_DOMAIN_PIPE_B) | \
289 BIT(POWER_DOMAIN_TRANSCODER_B) | \
290 BIT(POWER_DOMAIN_PIPE_C) | \
291 BIT(POWER_DOMAIN_TRANSCODER_C) | \
292 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
293 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
294 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
295 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
296 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
297 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
298 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
299 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
300 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
301 BIT(POWER_DOMAIN_AUX_B) | \
302 BIT(POWER_DOMAIN_AUX_C) | \
303 BIT(POWER_DOMAIN_AUX_D) | \
304 BIT(POWER_DOMAIN_AUDIO) | \
305 BIT(POWER_DOMAIN_VGA) | \
306 BIT(POWER_DOMAIN_INIT))
307 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
308 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
309 BIT(POWER_DOMAIN_PLLS) | \
310 BIT(POWER_DOMAIN_PIPE_A) | \
311 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
312 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
313 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
314 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
315 BIT(POWER_DOMAIN_AUX_A) | \
316 BIT(POWER_DOMAIN_INIT))
317 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
318 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
319 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
320 BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
321 BIT(POWER_DOMAIN_INIT))
322 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
323 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
324 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
325 BIT(POWER_DOMAIN_INIT))
326 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
327 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
328 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
329 BIT(POWER_DOMAIN_INIT))
330 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
331 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
332 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
333 BIT(POWER_DOMAIN_INIT))
334 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
335 SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
336 BIT(POWER_DOMAIN_PLLS) | \
337 BIT(POWER_DOMAIN_INIT))
338 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
339 (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
340 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
341 SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
342 SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
343 SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
344 SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
345 SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
346 BIT(POWER_DOMAIN_INIT))
347
348 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
349 BIT(POWER_DOMAIN_TRANSCODER_A) | \
350 BIT(POWER_DOMAIN_PIPE_B) | \
351 BIT(POWER_DOMAIN_TRANSCODER_B) | \
352 BIT(POWER_DOMAIN_PIPE_C) | \
353 BIT(POWER_DOMAIN_TRANSCODER_C) | \
354 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
355 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
356 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
357 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
358 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
359 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
360 BIT(POWER_DOMAIN_AUX_B) | \
361 BIT(POWER_DOMAIN_AUX_C) | \
362 BIT(POWER_DOMAIN_AUDIO) | \
363 BIT(POWER_DOMAIN_VGA) | \
364 BIT(POWER_DOMAIN_INIT))
365 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
366 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
367 BIT(POWER_DOMAIN_PIPE_A) | \
368 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
369 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
370 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
371 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
372 BIT(POWER_DOMAIN_AUX_A) | \
373 BIT(POWER_DOMAIN_PLLS) | \
374 BIT(POWER_DOMAIN_INIT))
375 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
376 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
377 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
378 BIT(POWER_DOMAIN_INIT))
379
380 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
381 {
382 struct drm_device *dev = dev_priv->dev;
383
384 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
385 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
386 "DC9 already programmed to be enabled.\n");
387 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
388 "DC5 still not disabled to enable DC9.\n");
389 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
390 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
391
392 /*
393 * TODO: check for the following to verify the conditions to enter DC9
394 * state are satisfied:
395 * 1] Check relevant display engine registers to verify if mode set
396 * disable sequence was followed.
397 * 2] Check if display uninitialize sequence is initialized.
398 */
399 }
400
401 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
402 {
403 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
404 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
405 "DC9 already programmed to be disabled.\n");
406 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
407 "DC5 still not disabled.\n");
408
409 /*
410 * TODO: check for the following to verify DC9 state was indeed
411 * entered before programming to disable it:
412 * 1] Check relevant display engine registers to verify if mode
413 * set disable sequence was followed.
414 * 2] Check if display uninitialize sequence is initialized.
415 */
416 }
417
418 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
419 {
420 uint32_t val;
421
422 assert_can_enable_dc9(dev_priv);
423
424 DRM_DEBUG_KMS("Enabling DC9\n");
425
426 val = I915_READ(DC_STATE_EN);
427 val |= DC_STATE_EN_DC9;
428 I915_WRITE(DC_STATE_EN, val);
429 POSTING_READ(DC_STATE_EN);
430 }
431
432 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
433 {
434 uint32_t val;
435
436 assert_can_disable_dc9(dev_priv);
437
438 DRM_DEBUG_KMS("Disabling DC9\n");
439
440 val = I915_READ(DC_STATE_EN);
441 val &= ~DC_STATE_EN_DC9;
442 I915_WRITE(DC_STATE_EN, val);
443 POSTING_READ(DC_STATE_EN);
444 }
445
446 static void gen9_set_dc_state_debugmask_memory_up(
447 struct drm_i915_private *dev_priv)
448 {
449 uint32_t val;
450
451 /* The below bit doesn't need to be cleared ever afterwards */
452 val = I915_READ(DC_STATE_DEBUG);
453 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
454 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
455 I915_WRITE(DC_STATE_DEBUG, val);
456 POSTING_READ(DC_STATE_DEBUG);
457 }
458 }
459
460 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
461 {
462 struct drm_device *dev = dev_priv->dev;
463 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
464 SKL_DISP_PW_2);
465
466 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
467 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
468 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
469
470 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
471 "DC5 already programmed to be enabled.\n");
472 WARN_ONCE(dev_priv->pm.suspended,
473 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
474
475 assert_csr_loaded(dev_priv);
476 }
477
478 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
479 {
480 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
481 SKL_DISP_PW_2);
482 /*
483 * During initialization, the firmware may not be loaded yet.
484 * We still want to make sure that the DC enabling flag is cleared.
485 */
486 if (dev_priv->power_domains.initializing)
487 return;
488
489 WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
490 WARN_ONCE(dev_priv->pm.suspended,
491 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
492 }
493
494 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
495 {
496 uint32_t val;
497
498 assert_can_enable_dc5(dev_priv);
499
500 DRM_DEBUG_KMS("Enabling DC5\n");
501
502 gen9_set_dc_state_debugmask_memory_up(dev_priv);
503
504 val = I915_READ(DC_STATE_EN);
505 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
506 val |= DC_STATE_EN_UPTO_DC5;
507 I915_WRITE(DC_STATE_EN, val);
508 POSTING_READ(DC_STATE_EN);
509 }
510
511 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
512 {
513 uint32_t val;
514
515 assert_can_disable_dc5(dev_priv);
516
517 DRM_DEBUG_KMS("Disabling DC5\n");
518
519 val = I915_READ(DC_STATE_EN);
520 val &= ~DC_STATE_EN_UPTO_DC5;
521 I915_WRITE(DC_STATE_EN, val);
522 POSTING_READ(DC_STATE_EN);
523 }
524
525 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
526 {
527 struct drm_device *dev = dev_priv->dev;
528
529 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
530 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
531 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
532 "Backlight is not disabled.\n");
533 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
534 "DC6 already programmed to be enabled.\n");
535
536 assert_csr_loaded(dev_priv);
537 }
538
539 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
540 {
541 /*
542 * During initialization, the firmware may not be loaded yet.
543 * We still want to make sure that the DC enabling flag is cleared.
544 */
545 if (dev_priv->power_domains.initializing)
546 return;
547
548 assert_csr_loaded(dev_priv);
549 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
550 "DC6 already programmed to be disabled.\n");
551 }
552
553 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
554 {
555 uint32_t val;
556
557 assert_can_enable_dc6(dev_priv);
558
559 DRM_DEBUG_KMS("Enabling DC6\n");
560
561 gen9_set_dc_state_debugmask_memory_up(dev_priv);
562
563 val = I915_READ(DC_STATE_EN);
564 val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
565 val |= DC_STATE_EN_UPTO_DC6;
566 I915_WRITE(DC_STATE_EN, val);
567 POSTING_READ(DC_STATE_EN);
568 }
569
570 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
571 {
572 uint32_t val;
573
574 assert_can_disable_dc6(dev_priv);
575
576 DRM_DEBUG_KMS("Disabling DC6\n");
577
578 val = I915_READ(DC_STATE_EN);
579 val &= ~DC_STATE_EN_UPTO_DC6;
580 I915_WRITE(DC_STATE_EN, val);
581 POSTING_READ(DC_STATE_EN);
582 }
583
584 static void skl_set_power_well(struct drm_i915_private *dev_priv,
585 struct i915_power_well *power_well, bool enable)
586 {
587 struct drm_device *dev = dev_priv->dev;
588 uint32_t tmp, fuse_status;
589 uint32_t req_mask, state_mask;
590 bool is_enabled, enable_requested, check_fuse_status = false;
591
592 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
593 fuse_status = I915_READ(SKL_FUSE_STATUS);
594
595 switch (power_well->data) {
596 case SKL_DISP_PW_1:
597 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
598 SKL_FUSE_PG0_DIST_STATUS), 1)) {
599 DRM_ERROR("PG0 not enabled\n");
600 return;
601 }
602 break;
603 case SKL_DISP_PW_2:
604 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
605 DRM_ERROR("PG1 in disabled state\n");
606 return;
607 }
608 break;
609 case SKL_DISP_PW_DDI_A_E:
610 case SKL_DISP_PW_DDI_B:
611 case SKL_DISP_PW_DDI_C:
612 case SKL_DISP_PW_DDI_D:
613 case SKL_DISP_PW_MISC_IO:
614 break;
615 default:
616 WARN(1, "Unknown power well %lu\n", power_well->data);
617 return;
618 }
619
620 req_mask = SKL_POWER_WELL_REQ(power_well->data);
621 enable_requested = tmp & req_mask;
622 state_mask = SKL_POWER_WELL_STATE(power_well->data);
623 is_enabled = tmp & state_mask;
624
625 if (enable) {
626 if (!enable_requested) {
627 WARN((tmp & state_mask) &&
628 !I915_READ(HSW_PWR_WELL_BIOS),
629 "Invalid for power well status to be enabled, unless done by the BIOS, \
630 when request is to disable!\n");
631 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
632 power_well->data == SKL_DISP_PW_2) {
633 if (SKL_ENABLE_DC6(dev)) {
634 skl_disable_dc6(dev_priv);
635 /*
636 * DDI buffer programming unnecessary during driver-load/resume
637 * as it's already done during modeset initialization then.
638 * It's also invalid here as encoder list is still uninitialized.
639 */
640 if (!dev_priv->power_domains.initializing)
641 intel_prepare_ddi(dev);
642 } else {
643 gen9_disable_dc5(dev_priv);
644 }
645 }
646 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
647 }
648
649 if (!is_enabled) {
650 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
651 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
652 state_mask), 1))
653 DRM_ERROR("%s enable timeout\n",
654 power_well->name);
655 check_fuse_status = true;
656 }
657 } else {
658 if (enable_requested) {
659 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
660 POSTING_READ(HSW_PWR_WELL_DRIVER);
661 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
662
663 if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
664 power_well->data == SKL_DISP_PW_2) {
665 enum csr_state state;
666 /* TODO: wait for a completion event or
667 * similar here instead of busy
668 * waiting using wait_for function.
669 */
670 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
671 FW_UNINITIALIZED, 1000);
672 if (state != FW_LOADED)
673 DRM_DEBUG("CSR firmware not ready (%d)\n",
674 state);
675 else
676 if (SKL_ENABLE_DC6(dev))
677 skl_enable_dc6(dev_priv);
678 else
679 gen9_enable_dc5(dev_priv);
680 }
681 }
682 }
683
684 if (check_fuse_status) {
685 if (power_well->data == SKL_DISP_PW_1) {
686 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
687 SKL_FUSE_PG1_DIST_STATUS), 1))
688 DRM_ERROR("PG1 distributing status timeout\n");
689 } else if (power_well->data == SKL_DISP_PW_2) {
690 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
691 SKL_FUSE_PG2_DIST_STATUS), 1))
692 DRM_ERROR("PG2 distributing status timeout\n");
693 }
694 }
695
696 if (enable && !is_enabled)
697 skl_power_well_post_enable(dev_priv, power_well);
698 }
699
700 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
701 struct i915_power_well *power_well)
702 {
703 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
704
705 /*
706 * We're taking over the BIOS, so clear any requests made by it since
707 * the driver is in charge now.
708 */
709 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
710 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
711 }
712
713 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
714 struct i915_power_well *power_well)
715 {
716 hsw_set_power_well(dev_priv, power_well, true);
717 }
718
719 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
720 struct i915_power_well *power_well)
721 {
722 hsw_set_power_well(dev_priv, power_well, false);
723 }
724
725 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
726 struct i915_power_well *power_well)
727 {
728 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
729 SKL_POWER_WELL_STATE(power_well->data);
730
731 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
732 }
733
734 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
735 struct i915_power_well *power_well)
736 {
737 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
738
739 /* Clear any request made by BIOS as driver is taking over */
740 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
741 }
742
743 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
744 struct i915_power_well *power_well)
745 {
746 skl_set_power_well(dev_priv, power_well, true);
747 }
748
749 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
750 struct i915_power_well *power_well)
751 {
752 skl_set_power_well(dev_priv, power_well, false);
753 }
754
755 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
756 struct i915_power_well *power_well)
757 {
758 }
759
760 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
761 struct i915_power_well *power_well)
762 {
763 return true;
764 }
765
766 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
767 struct i915_power_well *power_well, bool enable)
768 {
769 enum punit_power_well power_well_id = power_well->data;
770 u32 mask;
771 u32 state;
772 u32 ctrl;
773
774 mask = PUNIT_PWRGT_MASK(power_well_id);
775 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
776 PUNIT_PWRGT_PWR_GATE(power_well_id);
777
778 mutex_lock(&dev_priv->rps.hw_lock);
779
780 #define COND \
781 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
782
783 if (COND)
784 goto out;
785
786 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
787 ctrl &= ~mask;
788 ctrl |= state;
789 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
790
791 if (wait_for(COND, 100))
792 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
793 state,
794 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
795
796 #undef COND
797
798 out:
799 mutex_unlock(&dev_priv->rps.hw_lock);
800 }
801
802 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
803 struct i915_power_well *power_well)
804 {
805 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
806 }
807
808 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
809 struct i915_power_well *power_well)
810 {
811 vlv_set_power_well(dev_priv, power_well, true);
812 }
813
814 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
815 struct i915_power_well *power_well)
816 {
817 vlv_set_power_well(dev_priv, power_well, false);
818 }
819
820 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
821 struct i915_power_well *power_well)
822 {
823 int power_well_id = power_well->data;
824 bool enabled = false;
825 u32 mask;
826 u32 state;
827 u32 ctrl;
828
829 mask = PUNIT_PWRGT_MASK(power_well_id);
830 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
831
832 mutex_lock(&dev_priv->rps.hw_lock);
833
834 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
835 /*
836 * We only ever set the power-on and power-gate states, anything
837 * else is unexpected.
838 */
839 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
840 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
841 if (state == ctrl)
842 enabled = true;
843
844 /*
845 * A transient state at this point would mean some unexpected party
846 * is poking at the power controls too.
847 */
848 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
849 WARN_ON(ctrl != state);
850
851 mutex_unlock(&dev_priv->rps.hw_lock);
852
853 return enabled;
854 }
855
856 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
857 {
858 enum pipe pipe;
859
860 /*
861 * Enable the CRI clock source so we can get at the
862 * display and the reference clock for VGA
863 * hotplug / manual detection. Supposedly DSI also
864 * needs the ref clock up and running.
865 *
866 * CHV DPLL B/C have some issues if VGA mode is enabled.
867 */
868 for_each_pipe(dev_priv->dev, pipe) {
869 u32 val = I915_READ(DPLL(pipe));
870
871 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
872 if (pipe != PIPE_A)
873 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
874
875 I915_WRITE(DPLL(pipe), val);
876 }
877
878 spin_lock_irq(&dev_priv->irq_lock);
879 valleyview_enable_display_irqs(dev_priv);
880 spin_unlock_irq(&dev_priv->irq_lock);
881
882 /*
883 * During driver initialization/resume we can avoid restoring the
884 * part of the HW/SW state that will be inited anyway explicitly.
885 */
886 if (dev_priv->power_domains.initializing)
887 return;
888
889 intel_hpd_init(dev_priv);
890
891 i915_redisable_vga_power_on(dev_priv->dev);
892 }
893
894 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
895 {
896 spin_lock_irq(&dev_priv->irq_lock);
897 valleyview_disable_display_irqs(dev_priv);
898 spin_unlock_irq(&dev_priv->irq_lock);
899
900 vlv_power_sequencer_reset(dev_priv);
901 }
902
903 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
904 struct i915_power_well *power_well)
905 {
906 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
907
908 vlv_set_power_well(dev_priv, power_well, true);
909
910 vlv_display_power_well_init(dev_priv);
911 }
912
913 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
914 struct i915_power_well *power_well)
915 {
916 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
917
918 vlv_display_power_well_deinit(dev_priv);
919
920 vlv_set_power_well(dev_priv, power_well, false);
921 }
922
923 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
924 struct i915_power_well *power_well)
925 {
926 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
927
928 /* since ref/cri clock was enabled */
929 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
930
931 vlv_set_power_well(dev_priv, power_well, true);
932
933 /*
934 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
935 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
936 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
937 * b. The other bits such as sfr settings / modesel may all
938 * be set to 0.
939 *
940 * This should only be done on init and resume from S3 with
941 * both PLLs disabled, or we risk losing DPIO and PLL
942 * synchronization.
943 */
944 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
945 }
946
947 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
948 struct i915_power_well *power_well)
949 {
950 enum pipe pipe;
951
952 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
953
954 for_each_pipe(dev_priv, pipe)
955 assert_pll_disabled(dev_priv, pipe);
956
957 /* Assert common reset */
958 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
959
960 vlv_set_power_well(dev_priv, power_well, false);
961 }
962
963 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
964
965 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
966 int power_well_id)
967 {
968 struct i915_power_domains *power_domains = &dev_priv->power_domains;
969 struct i915_power_well *power_well;
970 int i;
971
972 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
973 if (power_well->data == power_well_id)
974 return power_well;
975 }
976
977 return NULL;
978 }
979
980 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
981
982 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
983 {
984 struct i915_power_well *cmn_bc =
985 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
986 struct i915_power_well *cmn_d =
987 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
988 u32 phy_control = dev_priv->chv_phy_control;
989 u32 phy_status = 0;
990 u32 tmp;
991
992 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
993 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
994
995 /* this assumes override is only used to enable lanes */
996 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
997 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
998
999 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1000 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1001
1002 /* CL1 is on whenever anything is on in either channel */
1003 if (BITS_SET(phy_control,
1004 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1005 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1006 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1007
1008 /*
1009 * The DPLLB check accounts for the pipe B + port A usage
1010 * with CL2 powered up but all the lanes in the second channel
1011 * powered down.
1012 */
1013 if (BITS_SET(phy_control,
1014 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1015 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1016 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1017
1018 if (BITS_SET(phy_control,
1019 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1020 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1021 if (BITS_SET(phy_control,
1022 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1023 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1024
1025 if (BITS_SET(phy_control,
1026 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1027 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1028 if (BITS_SET(phy_control,
1029 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1030 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1031 }
1032
1033 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1034 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1035
1036 /* this assumes override is only used to enable lanes */
1037 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1038 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1039
1040 if (BITS_SET(phy_control,
1041 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1042 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1043
1044 if (BITS_SET(phy_control,
1045 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1046 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1047 if (BITS_SET(phy_control,
1048 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1049 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1050 }
1051
1052 /*
1053 * The PHY may be busy with some initial calibration and whatnot,
1054 * so the power state can take a while to actually change.
1055 */
1056 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS)) == phy_status, 10))
1057 WARN(phy_status != tmp,
1058 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1059 tmp, phy_status, dev_priv->chv_phy_control);
1060 }
1061
1062 #undef BITS_SET
1063
1064 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1065 struct i915_power_well *power_well)
1066 {
1067 enum dpio_phy phy;
1068 enum pipe pipe;
1069 uint32_t tmp;
1070
1071 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1072 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1073
1074 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1075 pipe = PIPE_A;
1076 phy = DPIO_PHY0;
1077 } else {
1078 pipe = PIPE_C;
1079 phy = DPIO_PHY1;
1080 }
1081
1082 /* since ref/cri clock was enabled */
1083 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1084 vlv_set_power_well(dev_priv, power_well, true);
1085
1086 /* Poll for phypwrgood signal */
1087 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1088 DRM_ERROR("Display PHY %d is not power up\n", phy);
1089
1090 mutex_lock(&dev_priv->sb_lock);
1091
1092 /* Enable dynamic power down */
1093 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1094 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1095 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1096 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1097
1098 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1099 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1100 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1101 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1102 } else {
1103 /*
1104 * Force the non-existing CL2 off. BXT does this
1105 * too, so maybe it saves some power even though
1106 * CL2 doesn't exist?
1107 */
1108 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1109 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1110 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1111 }
1112
1113 mutex_unlock(&dev_priv->sb_lock);
1114
1115 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1116 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1117
1118 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1119 phy, dev_priv->chv_phy_control);
1120
1121 assert_chv_phy_status(dev_priv);
1122 }
1123
1124 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1125 struct i915_power_well *power_well)
1126 {
1127 enum dpio_phy phy;
1128
1129 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1130 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1131
1132 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1133 phy = DPIO_PHY0;
1134 assert_pll_disabled(dev_priv, PIPE_A);
1135 assert_pll_disabled(dev_priv, PIPE_B);
1136 } else {
1137 phy = DPIO_PHY1;
1138 assert_pll_disabled(dev_priv, PIPE_C);
1139 }
1140
1141 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1142 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1143
1144 vlv_set_power_well(dev_priv, power_well, false);
1145
1146 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1147 phy, dev_priv->chv_phy_control);
1148
1149 assert_chv_phy_status(dev_priv);
1150 }
1151
1152 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1153 enum dpio_channel ch, bool override, unsigned int mask)
1154 {
1155 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1156 u32 reg, val, expected, actual;
1157
1158 if (ch == DPIO_CH0)
1159 reg = _CHV_CMN_DW0_CH0;
1160 else
1161 reg = _CHV_CMN_DW6_CH1;
1162
1163 mutex_lock(&dev_priv->sb_lock);
1164 val = vlv_dpio_read(dev_priv, pipe, reg);
1165 mutex_unlock(&dev_priv->sb_lock);
1166
1167 /*
1168 * This assumes !override is only used when the port is disabled.
1169 * All lanes should power down even without the override when
1170 * the port is disabled.
1171 */
1172 if (!override || mask == 0xf) {
1173 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1174 /*
1175 * If CH1 common lane is not active anymore
1176 * (eg. for pipe B DPLL) the entire channel will
1177 * shut down, which causes the common lane registers
1178 * to read as 0. That means we can't actually check
1179 * the lane power down status bits, but as the entire
1180 * register reads as 0 it's a good indication that the
1181 * channel is indeed entirely powered down.
1182 */
1183 if (ch == DPIO_CH1 && val == 0)
1184 expected = 0;
1185 } else if (mask != 0x0) {
1186 expected = DPIO_ANYDL_POWERDOWN;
1187 } else {
1188 expected = 0;
1189 }
1190
1191 if (ch == DPIO_CH0)
1192 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1193 else
1194 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1195 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1196
1197 WARN(actual != expected,
1198 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1199 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1200 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1201 reg, val);
1202 }
1203
1204 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1205 enum dpio_channel ch, bool override)
1206 {
1207 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1208 bool was_override;
1209
1210 mutex_lock(&power_domains->lock);
1211
1212 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1213
1214 if (override == was_override)
1215 goto out;
1216
1217 if (override)
1218 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1219 else
1220 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1221
1222 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1223
1224 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1225 phy, ch, dev_priv->chv_phy_control);
1226
1227 assert_chv_phy_status(dev_priv);
1228
1229 out:
1230 mutex_unlock(&power_domains->lock);
1231
1232 return was_override;
1233 }
1234
1235 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1236 bool override, unsigned int mask)
1237 {
1238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1239 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1240 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1241 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1242
1243 mutex_lock(&power_domains->lock);
1244
1245 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1246 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1247
1248 if (override)
1249 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1250 else
1251 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1252
1253 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1254
1255 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1256 phy, ch, mask, dev_priv->chv_phy_control);
1257
1258 assert_chv_phy_status(dev_priv);
1259
1260 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1261
1262 mutex_unlock(&power_domains->lock);
1263 }
1264
1265 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1266 struct i915_power_well *power_well)
1267 {
1268 enum pipe pipe = power_well->data;
1269 bool enabled;
1270 u32 state, ctrl;
1271
1272 mutex_lock(&dev_priv->rps.hw_lock);
1273
1274 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1275 /*
1276 * We only ever set the power-on and power-gate states, anything
1277 * else is unexpected.
1278 */
1279 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1280 enabled = state == DP_SSS_PWR_ON(pipe);
1281
1282 /*
1283 * A transient state at this point would mean some unexpected party
1284 * is poking at the power controls too.
1285 */
1286 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1287 WARN_ON(ctrl << 16 != state);
1288
1289 mutex_unlock(&dev_priv->rps.hw_lock);
1290
1291 return enabled;
1292 }
1293
1294 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1295 struct i915_power_well *power_well,
1296 bool enable)
1297 {
1298 enum pipe pipe = power_well->data;
1299 u32 state;
1300 u32 ctrl;
1301
1302 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1303
1304 mutex_lock(&dev_priv->rps.hw_lock);
1305
1306 #define COND \
1307 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1308
1309 if (COND)
1310 goto out;
1311
1312 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1313 ctrl &= ~DP_SSC_MASK(pipe);
1314 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1315 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1316
1317 if (wait_for(COND, 100))
1318 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1319 state,
1320 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1321
1322 #undef COND
1323
1324 out:
1325 mutex_unlock(&dev_priv->rps.hw_lock);
1326 }
1327
1328 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1329 struct i915_power_well *power_well)
1330 {
1331 WARN_ON_ONCE(power_well->data != PIPE_A);
1332
1333 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1334 }
1335
1336 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1337 struct i915_power_well *power_well)
1338 {
1339 WARN_ON_ONCE(power_well->data != PIPE_A);
1340
1341 chv_set_pipe_power_well(dev_priv, power_well, true);
1342
1343 vlv_display_power_well_init(dev_priv);
1344 }
1345
1346 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1347 struct i915_power_well *power_well)
1348 {
1349 WARN_ON_ONCE(power_well->data != PIPE_A);
1350
1351 vlv_display_power_well_deinit(dev_priv);
1352
1353 chv_set_pipe_power_well(dev_priv, power_well, false);
1354 }
1355
1356 /**
1357 * intel_display_power_get - grab a power domain reference
1358 * @dev_priv: i915 device instance
1359 * @domain: power domain to reference
1360 *
1361 * This function grabs a power domain reference for @domain and ensures that the
1362 * power domain and all its parents are powered up. Therefore users should only
1363 * grab a reference to the innermost power domain they need.
1364 *
1365 * Any power domain reference obtained by this function must have a symmetric
1366 * call to intel_display_power_put() to release the reference again.
1367 */
1368 void intel_display_power_get(struct drm_i915_private *dev_priv,
1369 enum intel_display_power_domain domain)
1370 {
1371 struct i915_power_domains *power_domains;
1372 struct i915_power_well *power_well;
1373 int i;
1374
1375 intel_runtime_pm_get(dev_priv);
1376
1377 power_domains = &dev_priv->power_domains;
1378
1379 mutex_lock(&power_domains->lock);
1380
1381 for_each_power_well(i, power_well, BIT(domain), power_domains) {
1382 if (!power_well->count++)
1383 intel_power_well_enable(dev_priv, power_well);
1384 }
1385
1386 power_domains->domain_use_count[domain]++;
1387
1388 mutex_unlock(&power_domains->lock);
1389 }
1390
1391 /**
1392 * intel_display_power_put - release a power domain reference
1393 * @dev_priv: i915 device instance
1394 * @domain: power domain to reference
1395 *
1396 * This function drops the power domain reference obtained by
1397 * intel_display_power_get() and might power down the corresponding hardware
1398 * block right away if this is the last reference.
1399 */
1400 void intel_display_power_put(struct drm_i915_private *dev_priv,
1401 enum intel_display_power_domain domain)
1402 {
1403 struct i915_power_domains *power_domains;
1404 struct i915_power_well *power_well;
1405 int i;
1406
1407 power_domains = &dev_priv->power_domains;
1408
1409 mutex_lock(&power_domains->lock);
1410
1411 WARN_ON(!power_domains->domain_use_count[domain]);
1412 power_domains->domain_use_count[domain]--;
1413
1414 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1415 WARN_ON(!power_well->count);
1416
1417 if (!--power_well->count && i915.disable_power_well)
1418 intel_power_well_disable(dev_priv, power_well);
1419 }
1420
1421 mutex_unlock(&power_domains->lock);
1422
1423 intel_runtime_pm_put(dev_priv);
1424 }
1425
1426 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1427 BIT(POWER_DOMAIN_PIPE_A) | \
1428 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1429 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
1430 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
1431 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1432 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1433 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1434 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1435 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1436 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1437 BIT(POWER_DOMAIN_PORT_CRT) | \
1438 BIT(POWER_DOMAIN_PLLS) | \
1439 BIT(POWER_DOMAIN_AUX_A) | \
1440 BIT(POWER_DOMAIN_AUX_B) | \
1441 BIT(POWER_DOMAIN_AUX_C) | \
1442 BIT(POWER_DOMAIN_AUX_D) | \
1443 BIT(POWER_DOMAIN_INIT))
1444 #define HSW_DISPLAY_POWER_DOMAINS ( \
1445 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1446 BIT(POWER_DOMAIN_INIT))
1447
1448 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1449 HSW_ALWAYS_ON_POWER_DOMAINS | \
1450 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1451 #define BDW_DISPLAY_POWER_DOMAINS ( \
1452 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1453 BIT(POWER_DOMAIN_INIT))
1454
1455 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1456 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1457
1458 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1459 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1460 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1461 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1462 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1463 BIT(POWER_DOMAIN_PORT_CRT) | \
1464 BIT(POWER_DOMAIN_AUX_B) | \
1465 BIT(POWER_DOMAIN_AUX_C) | \
1466 BIT(POWER_DOMAIN_INIT))
1467
1468 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1469 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1470 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1471 BIT(POWER_DOMAIN_AUX_B) | \
1472 BIT(POWER_DOMAIN_INIT))
1473
1474 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1475 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1476 BIT(POWER_DOMAIN_AUX_B) | \
1477 BIT(POWER_DOMAIN_INIT))
1478
1479 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1480 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1481 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1482 BIT(POWER_DOMAIN_AUX_C) | \
1483 BIT(POWER_DOMAIN_INIT))
1484
1485 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1486 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1487 BIT(POWER_DOMAIN_AUX_C) | \
1488 BIT(POWER_DOMAIN_INIT))
1489
1490 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1491 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1492 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1493 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1494 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1495 BIT(POWER_DOMAIN_AUX_B) | \
1496 BIT(POWER_DOMAIN_AUX_C) | \
1497 BIT(POWER_DOMAIN_INIT))
1498
1499 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1500 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1501 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1502 BIT(POWER_DOMAIN_AUX_D) | \
1503 BIT(POWER_DOMAIN_INIT))
1504
1505 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1506 .sync_hw = i9xx_always_on_power_well_noop,
1507 .enable = i9xx_always_on_power_well_noop,
1508 .disable = i9xx_always_on_power_well_noop,
1509 .is_enabled = i9xx_always_on_power_well_enabled,
1510 };
1511
1512 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1513 .sync_hw = chv_pipe_power_well_sync_hw,
1514 .enable = chv_pipe_power_well_enable,
1515 .disable = chv_pipe_power_well_disable,
1516 .is_enabled = chv_pipe_power_well_enabled,
1517 };
1518
1519 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1520 .sync_hw = vlv_power_well_sync_hw,
1521 .enable = chv_dpio_cmn_power_well_enable,
1522 .disable = chv_dpio_cmn_power_well_disable,
1523 .is_enabled = vlv_power_well_enabled,
1524 };
1525
1526 static struct i915_power_well i9xx_always_on_power_well[] = {
1527 {
1528 .name = "always-on",
1529 .always_on = 1,
1530 .domains = POWER_DOMAIN_MASK,
1531 .ops = &i9xx_always_on_power_well_ops,
1532 },
1533 };
1534
1535 static const struct i915_power_well_ops hsw_power_well_ops = {
1536 .sync_hw = hsw_power_well_sync_hw,
1537 .enable = hsw_power_well_enable,
1538 .disable = hsw_power_well_disable,
1539 .is_enabled = hsw_power_well_enabled,
1540 };
1541
1542 static const struct i915_power_well_ops skl_power_well_ops = {
1543 .sync_hw = skl_power_well_sync_hw,
1544 .enable = skl_power_well_enable,
1545 .disable = skl_power_well_disable,
1546 .is_enabled = skl_power_well_enabled,
1547 };
1548
1549 static struct i915_power_well hsw_power_wells[] = {
1550 {
1551 .name = "always-on",
1552 .always_on = 1,
1553 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1554 .ops = &i9xx_always_on_power_well_ops,
1555 },
1556 {
1557 .name = "display",
1558 .domains = HSW_DISPLAY_POWER_DOMAINS,
1559 .ops = &hsw_power_well_ops,
1560 },
1561 };
1562
1563 static struct i915_power_well bdw_power_wells[] = {
1564 {
1565 .name = "always-on",
1566 .always_on = 1,
1567 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1568 .ops = &i9xx_always_on_power_well_ops,
1569 },
1570 {
1571 .name = "display",
1572 .domains = BDW_DISPLAY_POWER_DOMAINS,
1573 .ops = &hsw_power_well_ops,
1574 },
1575 };
1576
1577 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1578 .sync_hw = vlv_power_well_sync_hw,
1579 .enable = vlv_display_power_well_enable,
1580 .disable = vlv_display_power_well_disable,
1581 .is_enabled = vlv_power_well_enabled,
1582 };
1583
1584 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1585 .sync_hw = vlv_power_well_sync_hw,
1586 .enable = vlv_dpio_cmn_power_well_enable,
1587 .disable = vlv_dpio_cmn_power_well_disable,
1588 .is_enabled = vlv_power_well_enabled,
1589 };
1590
1591 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1592 .sync_hw = vlv_power_well_sync_hw,
1593 .enable = vlv_power_well_enable,
1594 .disable = vlv_power_well_disable,
1595 .is_enabled = vlv_power_well_enabled,
1596 };
1597
1598 static struct i915_power_well vlv_power_wells[] = {
1599 {
1600 .name = "always-on",
1601 .always_on = 1,
1602 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1603 .ops = &i9xx_always_on_power_well_ops,
1604 },
1605 {
1606 .name = "display",
1607 .domains = VLV_DISPLAY_POWER_DOMAINS,
1608 .data = PUNIT_POWER_WELL_DISP2D,
1609 .ops = &vlv_display_power_well_ops,
1610 },
1611 {
1612 .name = "dpio-tx-b-01",
1613 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1614 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1615 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1616 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1617 .ops = &vlv_dpio_power_well_ops,
1618 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1619 },
1620 {
1621 .name = "dpio-tx-b-23",
1622 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1623 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1624 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1625 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1626 .ops = &vlv_dpio_power_well_ops,
1627 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1628 },
1629 {
1630 .name = "dpio-tx-c-01",
1631 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1632 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1633 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1634 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1635 .ops = &vlv_dpio_power_well_ops,
1636 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1637 },
1638 {
1639 .name = "dpio-tx-c-23",
1640 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1641 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1642 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1643 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1644 .ops = &vlv_dpio_power_well_ops,
1645 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1646 },
1647 {
1648 .name = "dpio-common",
1649 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1650 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1651 .ops = &vlv_dpio_cmn_power_well_ops,
1652 },
1653 };
1654
1655 static struct i915_power_well chv_power_wells[] = {
1656 {
1657 .name = "always-on",
1658 .always_on = 1,
1659 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1660 .ops = &i9xx_always_on_power_well_ops,
1661 },
1662 {
1663 .name = "display",
1664 /*
1665 * Pipe A power well is the new disp2d well. Pipe B and C
1666 * power wells don't actually exist. Pipe A power well is
1667 * required for any pipe to work.
1668 */
1669 .domains = VLV_DISPLAY_POWER_DOMAINS,
1670 .data = PIPE_A,
1671 .ops = &chv_pipe_power_well_ops,
1672 },
1673 {
1674 .name = "dpio-common-bc",
1675 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1676 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1677 .ops = &chv_dpio_cmn_power_well_ops,
1678 },
1679 {
1680 .name = "dpio-common-d",
1681 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1682 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1683 .ops = &chv_dpio_cmn_power_well_ops,
1684 },
1685 };
1686
1687 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1688 int power_well_id)
1689 {
1690 struct i915_power_well *power_well;
1691 bool ret;
1692
1693 power_well = lookup_power_well(dev_priv, power_well_id);
1694 ret = power_well->ops->is_enabled(dev_priv, power_well);
1695
1696 return ret;
1697 }
1698
1699 static struct i915_power_well skl_power_wells[] = {
1700 {
1701 .name = "always-on",
1702 .always_on = 1,
1703 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1704 .ops = &i9xx_always_on_power_well_ops,
1705 },
1706 {
1707 .name = "power well 1",
1708 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1709 .ops = &skl_power_well_ops,
1710 .data = SKL_DISP_PW_1,
1711 },
1712 {
1713 .name = "MISC IO power well",
1714 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1715 .ops = &skl_power_well_ops,
1716 .data = SKL_DISP_PW_MISC_IO,
1717 },
1718 {
1719 .name = "power well 2",
1720 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1721 .ops = &skl_power_well_ops,
1722 .data = SKL_DISP_PW_2,
1723 },
1724 {
1725 .name = "DDI A/E power well",
1726 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1727 .ops = &skl_power_well_ops,
1728 .data = SKL_DISP_PW_DDI_A_E,
1729 },
1730 {
1731 .name = "DDI B power well",
1732 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1733 .ops = &skl_power_well_ops,
1734 .data = SKL_DISP_PW_DDI_B,
1735 },
1736 {
1737 .name = "DDI C power well",
1738 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1739 .ops = &skl_power_well_ops,
1740 .data = SKL_DISP_PW_DDI_C,
1741 },
1742 {
1743 .name = "DDI D power well",
1744 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1745 .ops = &skl_power_well_ops,
1746 .data = SKL_DISP_PW_DDI_D,
1747 },
1748 };
1749
1750 static struct i915_power_well bxt_power_wells[] = {
1751 {
1752 .name = "always-on",
1753 .always_on = 1,
1754 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1755 .ops = &i9xx_always_on_power_well_ops,
1756 },
1757 {
1758 .name = "power well 1",
1759 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1760 .ops = &skl_power_well_ops,
1761 .data = SKL_DISP_PW_1,
1762 },
1763 {
1764 .name = "power well 2",
1765 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1766 .ops = &skl_power_well_ops,
1767 .data = SKL_DISP_PW_2,
1768 }
1769 };
1770
1771 #define set_power_wells(power_domains, __power_wells) ({ \
1772 (power_domains)->power_wells = (__power_wells); \
1773 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1774 })
1775
1776 /**
1777 * intel_power_domains_init - initializes the power domain structures
1778 * @dev_priv: i915 device instance
1779 *
1780 * Initializes the power domain structures for @dev_priv depending upon the
1781 * supported platform.
1782 */
1783 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1784 {
1785 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1786
1787 mutex_init(&power_domains->lock);
1788
1789 /*
1790 * The enabling order will be from lower to higher indexed wells,
1791 * the disabling order is reversed.
1792 */
1793 if (IS_HASWELL(dev_priv->dev)) {
1794 set_power_wells(power_domains, hsw_power_wells);
1795 } else if (IS_BROADWELL(dev_priv->dev)) {
1796 set_power_wells(power_domains, bdw_power_wells);
1797 } else if (IS_SKYLAKE(dev_priv->dev)) {
1798 set_power_wells(power_domains, skl_power_wells);
1799 } else if (IS_BROXTON(dev_priv->dev)) {
1800 set_power_wells(power_domains, bxt_power_wells);
1801 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1802 set_power_wells(power_domains, chv_power_wells);
1803 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1804 set_power_wells(power_domains, vlv_power_wells);
1805 } else {
1806 set_power_wells(power_domains, i9xx_always_on_power_well);
1807 }
1808
1809 return 0;
1810 }
1811
1812 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1813 {
1814 struct drm_device *dev = dev_priv->dev;
1815 struct device *device = &dev->pdev->dev;
1816
1817 if (!HAS_RUNTIME_PM(dev))
1818 return;
1819
1820 if (!intel_enable_rc6(dev))
1821 return;
1822
1823 /* Make sure we're not suspended first. */
1824 pm_runtime_get_sync(device);
1825 pm_runtime_disable(device);
1826 }
1827
1828 /**
1829 * intel_power_domains_fini - finalizes the power domain structures
1830 * @dev_priv: i915 device instance
1831 *
1832 * Finalizes the power domain structures for @dev_priv depending upon the
1833 * supported platform. This function also disables runtime pm and ensures that
1834 * the device stays powered up so that the driver can be reloaded.
1835 */
1836 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1837 {
1838 intel_runtime_pm_disable(dev_priv);
1839
1840 /* The i915.ko module is still not prepared to be loaded when
1841 * the power well is not enabled, so just enable it in case
1842 * we're going to unload/reload. */
1843 intel_display_set_init_power(dev_priv, true);
1844 }
1845
1846 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1847 {
1848 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1849 struct i915_power_well *power_well;
1850 int i;
1851
1852 mutex_lock(&power_domains->lock);
1853 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1854 power_well->ops->sync_hw(dev_priv, power_well);
1855 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1856 power_well);
1857 }
1858 mutex_unlock(&power_domains->lock);
1859 }
1860
1861 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1862 {
1863 struct i915_power_well *cmn_bc =
1864 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1865 struct i915_power_well *cmn_d =
1866 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1867
1868 /*
1869 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1870 * workaround never ever read DISPLAY_PHY_CONTROL, and
1871 * instead maintain a shadow copy ourselves. Use the actual
1872 * power well state and lane status to reconstruct the
1873 * expected initial value.
1874 */
1875 dev_priv->chv_phy_control =
1876 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1877 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1878 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1879 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1880 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1881
1882 /*
1883 * If all lanes are disabled we leave the override disabled
1884 * with all power down bits cleared to match the state we
1885 * would use after disabling the port. Otherwise enable the
1886 * override and set the lane powerdown bits accding to the
1887 * current lane status.
1888 */
1889 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1890 uint32_t status = I915_READ(DPLL(PIPE_A));
1891 unsigned int mask;
1892
1893 mask = status & DPLL_PORTB_READY_MASK;
1894 if (mask == 0xf)
1895 mask = 0x0;
1896 else
1897 dev_priv->chv_phy_control |=
1898 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1899
1900 dev_priv->chv_phy_control |=
1901 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1902
1903 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1904 if (mask == 0xf)
1905 mask = 0x0;
1906 else
1907 dev_priv->chv_phy_control |=
1908 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1909
1910 dev_priv->chv_phy_control |=
1911 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1912
1913 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1914 }
1915
1916 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1917 uint32_t status = I915_READ(DPIO_PHY_STATUS);
1918 unsigned int mask;
1919
1920 mask = status & DPLL_PORTD_READY_MASK;
1921
1922 if (mask == 0xf)
1923 mask = 0x0;
1924 else
1925 dev_priv->chv_phy_control |=
1926 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1927
1928 dev_priv->chv_phy_control |=
1929 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1930
1931 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1932 }
1933
1934 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1935
1936 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
1937 dev_priv->chv_phy_control);
1938 }
1939
1940 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1941 {
1942 struct i915_power_well *cmn =
1943 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1944 struct i915_power_well *disp2d =
1945 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1946
1947 /* If the display might be already active skip this */
1948 if (cmn->ops->is_enabled(dev_priv, cmn) &&
1949 disp2d->ops->is_enabled(dev_priv, disp2d) &&
1950 I915_READ(DPIO_CTL) & DPIO_CMNRST)
1951 return;
1952
1953 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1954
1955 /* cmnlane needs DPLL registers */
1956 disp2d->ops->enable(dev_priv, disp2d);
1957
1958 /*
1959 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1960 * Need to assert and de-assert PHY SB reset by gating the
1961 * common lane power, then un-gating it.
1962 * Simply ungating isn't enough to reset the PHY enough to get
1963 * ports and lanes running.
1964 */
1965 cmn->ops->disable(dev_priv, cmn);
1966 }
1967
1968 /**
1969 * intel_power_domains_init_hw - initialize hardware power domain state
1970 * @dev_priv: i915 device instance
1971 *
1972 * This function initializes the hardware power domain state and enables all
1973 * power domains using intel_display_set_init_power().
1974 */
1975 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1976 {
1977 struct drm_device *dev = dev_priv->dev;
1978 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1979
1980 power_domains->initializing = true;
1981
1982 if (IS_CHERRYVIEW(dev)) {
1983 mutex_lock(&power_domains->lock);
1984 chv_phy_control_init(dev_priv);
1985 mutex_unlock(&power_domains->lock);
1986 } else if (IS_VALLEYVIEW(dev)) {
1987 mutex_lock(&power_domains->lock);
1988 vlv_cmnlane_wa(dev_priv);
1989 mutex_unlock(&power_domains->lock);
1990 }
1991
1992 /* For now, we need the power well to be always enabled. */
1993 intel_display_set_init_power(dev_priv, true);
1994 intel_power_domains_resume(dev_priv);
1995 power_domains->initializing = false;
1996 }
1997
1998 /**
1999 * intel_aux_display_runtime_get - grab an auxiliary power domain reference
2000 * @dev_priv: i915 device instance
2001 *
2002 * This function grabs a power domain reference for the auxiliary power domain
2003 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2004 * parents are powered up. Therefore users should only grab a reference to the
2005 * innermost power domain they need.
2006 *
2007 * Any power domain reference obtained by this function must have a symmetric
2008 * call to intel_aux_display_runtime_put() to release the reference again.
2009 */
2010 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
2011 {
2012 intel_runtime_pm_get(dev_priv);
2013 }
2014
2015 /**
2016 * intel_aux_display_runtime_put - release an auxiliary power domain reference
2017 * @dev_priv: i915 device instance
2018 *
2019 * This function drops the auxiliary power domain reference obtained by
2020 * intel_aux_display_runtime_get() and might power down the corresponding
2021 * hardware block right away if this is the last reference.
2022 */
2023 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
2024 {
2025 intel_runtime_pm_put(dev_priv);
2026 }
2027
2028 /**
2029 * intel_runtime_pm_get - grab a runtime pm reference
2030 * @dev_priv: i915 device instance
2031 *
2032 * This function grabs a device-level runtime pm reference (mostly used for GEM
2033 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2034 *
2035 * Any runtime pm reference obtained by this function must have a symmetric
2036 * call to intel_runtime_pm_put() to release the reference again.
2037 */
2038 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2039 {
2040 struct drm_device *dev = dev_priv->dev;
2041 struct device *device = &dev->pdev->dev;
2042
2043 if (!HAS_RUNTIME_PM(dev))
2044 return;
2045
2046 pm_runtime_get_sync(device);
2047 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2048 }
2049
2050 /**
2051 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2052 * @dev_priv: i915 device instance
2053 *
2054 * This function grabs a device-level runtime pm reference (mostly used for GEM
2055 * code to ensure the GTT or GT is on).
2056 *
2057 * It will _not_ power up the device but instead only check that it's powered
2058 * on. Therefore it is only valid to call this functions from contexts where
2059 * the device is known to be powered up and where trying to power it up would
2060 * result in hilarity and deadlocks. That pretty much means only the system
2061 * suspend/resume code where this is used to grab runtime pm references for
2062 * delayed setup down in work items.
2063 *
2064 * Any runtime pm reference obtained by this function must have a symmetric
2065 * call to intel_runtime_pm_put() to release the reference again.
2066 */
2067 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2068 {
2069 struct drm_device *dev = dev_priv->dev;
2070 struct device *device = &dev->pdev->dev;
2071
2072 if (!HAS_RUNTIME_PM(dev))
2073 return;
2074
2075 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2076 pm_runtime_get_noresume(device);
2077 }
2078
2079 /**
2080 * intel_runtime_pm_put - release a runtime pm reference
2081 * @dev_priv: i915 device instance
2082 *
2083 * This function drops the device-level runtime pm reference obtained by
2084 * intel_runtime_pm_get() and might power down the corresponding
2085 * hardware block right away if this is the last reference.
2086 */
2087 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2088 {
2089 struct drm_device *dev = dev_priv->dev;
2090 struct device *device = &dev->pdev->dev;
2091
2092 if (!HAS_RUNTIME_PM(dev))
2093 return;
2094
2095 pm_runtime_mark_last_busy(device);
2096 pm_runtime_put_autosuspend(device);
2097 }
2098
2099 /**
2100 * intel_runtime_pm_enable - enable runtime pm
2101 * @dev_priv: i915 device instance
2102 *
2103 * This function enables runtime pm at the end of the driver load sequence.
2104 *
2105 * Note that this function does currently not enable runtime pm for the
2106 * subordinate display power domains. That is only done on the first modeset
2107 * using intel_display_set_init_power().
2108 */
2109 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2110 {
2111 struct drm_device *dev = dev_priv->dev;
2112 struct device *device = &dev->pdev->dev;
2113
2114 if (!HAS_RUNTIME_PM(dev))
2115 return;
2116
2117 pm_runtime_set_active(device);
2118
2119 /*
2120 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2121 * requirement.
2122 */
2123 if (!intel_enable_rc6(dev)) {
2124 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2125 return;
2126 }
2127
2128 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2129 pm_runtime_mark_last_busy(device);
2130 pm_runtime_use_autosuspend(device);
2131
2132 pm_runtime_put_autosuspend(device);
2133 }
2134
Linux kernel - Deliverables
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