2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
33 #include "intel_drv.h"
34 #include <drm/i915_powerwell.h>
39 * The i915 driver supports dynamic enabling and disabling of entire hardware
40 * blocks at runtime. This is especially important on the display side where
41 * software is supposed to control many power gates manually on recent hardware,
42 * since on the GT side a lot of the power management is done by the hardware.
43 * But even there some manual control at the device level is required.
45 * Since i915 supports a diverse set of platforms with a unified codebase and
46 * hardware engineers just love to shuffle functionality around between power
47 * domains there's a sizeable amount of indirection required. This file provides
48 * generic functions to the driver for grabbing and releasing references for
49 * abstract power domains. It then maps those to the actual power wells
50 * present for a given platform.
53 static struct i915_power_domains
*hsw_pwr
;
55 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
57 i < (power_domains)->power_well_count && \
58 ((power_well) = &(power_domains)->power_wells[i]); \
60 if ((power_well)->domains & (domain_mask))
62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
63 for (i = (power_domains)->power_well_count - 1; \
64 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
66 if ((power_well)->domains & (domain_mask))
69 * We should only use the power well if we explicitly asked the hardware to
70 * enable it, so check if it's enabled and also check if we've requested it to
73 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
74 struct i915_power_well
*power_well
)
76 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
77 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
81 * __intel_display_power_is_enabled - unlocked check for a power domain
82 * @dev_priv: i915 device instance
83 * @domain: power domain to check
85 * This is the unlocked version of intel_display_power_is_enabled() and should
86 * only be used from error capture and recovery code where deadlocks are
90 * True when the power domain is enabled, false otherwise.
92 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
93 enum intel_display_power_domain domain
)
95 struct i915_power_domains
*power_domains
;
96 struct i915_power_well
*power_well
;
100 if (dev_priv
->pm
.suspended
)
103 power_domains
= &dev_priv
->power_domains
;
107 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
108 if (power_well
->always_on
)
111 if (!power_well
->hw_enabled
) {
121 * intel_display_power_is_enabled - unlocked check for a power domain
122 * @dev_priv: i915 device instance
123 * @domain: power domain to check
125 * This function can be used to check the hw power domain state. It is mostly
126 * used in hardware state readout functions. Everywhere else code should rely
127 * upon explicit power domain reference counting to ensure that the hardware
128 * block is powered up before accessing it.
130 * Callers must hold the relevant modesetting locks to ensure that concurrent
131 * threads can't disable the power well while the caller tries to read a few
135 * True when the power domain is enabled, false otherwise.
137 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
138 enum intel_display_power_domain domain
)
140 struct i915_power_domains
*power_domains
;
143 power_domains
= &dev_priv
->power_domains
;
145 mutex_lock(&power_domains
->lock
);
146 ret
= __intel_display_power_is_enabled(dev_priv
, domain
);
147 mutex_unlock(&power_domains
->lock
);
153 * intel_display_set_init_power - set the initial power domain state
154 * @dev_priv: i915 device instance
155 * @enable: whether to enable or disable the initial power domain state
157 * For simplicity our driver load/unload and system suspend/resume code assumes
158 * that all power domains are always enabled. This functions controls the state
159 * of this little hack. While the initial power domain state is enabled runtime
160 * pm is effectively disabled.
162 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
165 if (dev_priv
->power_domains
.init_power_on
== enable
)
169 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
171 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
173 dev_priv
->power_domains
.init_power_on
= enable
;
177 * Starting with Haswell, we have a "Power Down Well" that can be turned off
178 * when not needed anymore. We have 4 registers that can request the power well
179 * to be enabled, and it will only be disabled if none of the registers is
180 * requesting it to be enabled.
182 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
184 struct drm_device
*dev
= dev_priv
->dev
;
187 * After we re-enable the power well, if we touch VGA register 0x3d5
188 * we'll get unclaimed register interrupts. This stops after we write
189 * anything to the VGA MSR register. The vgacon module uses this
190 * register all the time, so if we unbind our driver and, as a
191 * consequence, bind vgacon, we'll get stuck in an infinite loop at
192 * console_unlock(). So make here we touch the VGA MSR register, making
193 * sure vgacon can keep working normally without triggering interrupts
194 * and error messages.
196 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
197 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
198 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
200 if (IS_BROADWELL(dev
) || (INTEL_INFO(dev
)->gen
>= 9))
201 gen8_irq_power_well_post_enable(dev_priv
);
204 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
205 struct i915_power_well
*power_well
, bool enable
)
207 bool is_enabled
, enable_requested
;
210 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
211 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
212 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
215 if (!enable_requested
)
216 I915_WRITE(HSW_PWR_WELL_DRIVER
,
217 HSW_PWR_WELL_ENABLE_REQUEST
);
220 DRM_DEBUG_KMS("Enabling power well\n");
221 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
222 HSW_PWR_WELL_STATE_ENABLED
), 20))
223 DRM_ERROR("Timeout enabling power well\n");
224 hsw_power_well_post_enable(dev_priv
);
228 if (enable_requested
) {
229 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
230 POSTING_READ(HSW_PWR_WELL_DRIVER
);
231 DRM_DEBUG_KMS("Requesting to disable the power well\n");
236 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
237 struct i915_power_well
*power_well
)
239 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
242 * We're taking over the BIOS, so clear any requests made by it since
243 * the driver is in charge now.
245 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
246 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
249 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
250 struct i915_power_well
*power_well
)
252 hsw_set_power_well(dev_priv
, power_well
, true);
255 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
256 struct i915_power_well
*power_well
)
258 hsw_set_power_well(dev_priv
, power_well
, false);
261 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
262 struct i915_power_well
*power_well
)
266 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
267 struct i915_power_well
*power_well
)
272 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
273 struct i915_power_well
*power_well
, bool enable
)
275 enum punit_power_well power_well_id
= power_well
->data
;
280 mask
= PUNIT_PWRGT_MASK(power_well_id
);
281 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
282 PUNIT_PWRGT_PWR_GATE(power_well_id
);
284 mutex_lock(&dev_priv
->rps
.hw_lock
);
287 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
292 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
295 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
297 if (wait_for(COND
, 100))
298 DRM_ERROR("timout setting power well state %08x (%08x)\n",
300 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
305 mutex_unlock(&dev_priv
->rps
.hw_lock
);
308 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
309 struct i915_power_well
*power_well
)
311 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
314 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
315 struct i915_power_well
*power_well
)
317 vlv_set_power_well(dev_priv
, power_well
, true);
320 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
321 struct i915_power_well
*power_well
)
323 vlv_set_power_well(dev_priv
, power_well
, false);
326 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
327 struct i915_power_well
*power_well
)
329 int power_well_id
= power_well
->data
;
330 bool enabled
= false;
335 mask
= PUNIT_PWRGT_MASK(power_well_id
);
336 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
338 mutex_lock(&dev_priv
->rps
.hw_lock
);
340 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
342 * We only ever set the power-on and power-gate states, anything
343 * else is unexpected.
345 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
346 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
351 * A transient state at this point would mean some unexpected party
352 * is poking at the power controls too.
354 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
355 WARN_ON(ctrl
!= state
);
357 mutex_unlock(&dev_priv
->rps
.hw_lock
);
362 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
363 struct i915_power_well
*power_well
)
365 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
367 vlv_set_power_well(dev_priv
, power_well
, true);
369 spin_lock_irq(&dev_priv
->irq_lock
);
370 valleyview_enable_display_irqs(dev_priv
);
371 spin_unlock_irq(&dev_priv
->irq_lock
);
374 * During driver initialization/resume we can avoid restoring the
375 * part of the HW/SW state that will be inited anyway explicitly.
377 if (dev_priv
->power_domains
.initializing
)
380 intel_hpd_init(dev_priv
);
382 i915_redisable_vga_power_on(dev_priv
->dev
);
385 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
386 struct i915_power_well
*power_well
)
388 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
390 spin_lock_irq(&dev_priv
->irq_lock
);
391 valleyview_disable_display_irqs(dev_priv
);
392 spin_unlock_irq(&dev_priv
->irq_lock
);
394 vlv_set_power_well(dev_priv
, power_well
, false);
396 vlv_power_sequencer_reset(dev_priv
);
399 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
400 struct i915_power_well
*power_well
)
402 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
405 * Enable the CRI clock source so we can get at the
406 * display and the reference clock for VGA
407 * hotplug / manual detection.
409 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
410 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
411 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
413 vlv_set_power_well(dev_priv
, power_well
, true);
416 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
417 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
418 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
419 * b. The other bits such as sfr settings / modesel may all
422 * This should only be done on init and resume from S3 with
423 * both PLLs disabled, or we risk losing DPIO and PLL
426 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
429 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
430 struct i915_power_well
*power_well
)
434 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
436 for_each_pipe(dev_priv
, pipe
)
437 assert_pll_disabled(dev_priv
, pipe
);
439 /* Assert common reset */
440 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
442 vlv_set_power_well(dev_priv
, power_well
, false);
445 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
446 struct i915_power_well
*power_well
)
450 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
451 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
454 * Enable the CRI clock source so we can get at the
455 * display and the reference clock for VGA
456 * hotplug / manual detection.
458 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
460 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
461 DPLL_REFA_CLK_ENABLE_VLV
);
462 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
463 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
466 I915_WRITE(DPLL(PIPE_C
), I915_READ(DPLL(PIPE_C
)) |
467 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
469 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
470 vlv_set_power_well(dev_priv
, power_well
, true);
472 /* Poll for phypwrgood signal */
473 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
474 DRM_ERROR("Display PHY %d is not power up\n", phy
);
476 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) |
477 PHY_COM_LANE_RESET_DEASSERT(phy
));
480 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
481 struct i915_power_well
*power_well
)
485 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
486 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
488 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
490 assert_pll_disabled(dev_priv
, PIPE_A
);
491 assert_pll_disabled(dev_priv
, PIPE_B
);
494 assert_pll_disabled(dev_priv
, PIPE_C
);
497 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) &
498 ~PHY_COM_LANE_RESET_DEASSERT(phy
));
500 vlv_set_power_well(dev_priv
, power_well
, false);
503 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
504 struct i915_power_well
*power_well
)
506 enum pipe pipe
= power_well
->data
;
510 mutex_lock(&dev_priv
->rps
.hw_lock
);
512 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
514 * We only ever set the power-on and power-gate states, anything
515 * else is unexpected.
517 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
518 enabled
= state
== DP_SSS_PWR_ON(pipe
);
521 * A transient state at this point would mean some unexpected party
522 * is poking at the power controls too.
524 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
525 WARN_ON(ctrl
<< 16 != state
);
527 mutex_unlock(&dev_priv
->rps
.hw_lock
);
532 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
533 struct i915_power_well
*power_well
,
536 enum pipe pipe
= power_well
->data
;
540 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
542 mutex_lock(&dev_priv
->rps
.hw_lock
);
545 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
550 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
551 ctrl
&= ~DP_SSC_MASK(pipe
);
552 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
553 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
555 if (wait_for(COND
, 100))
556 DRM_ERROR("timout setting power well state %08x (%08x)\n",
558 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
563 mutex_unlock(&dev_priv
->rps
.hw_lock
);
566 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
567 struct i915_power_well
*power_well
)
569 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
572 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
573 struct i915_power_well
*power_well
)
575 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
576 power_well
->data
!= PIPE_B
&&
577 power_well
->data
!= PIPE_C
);
579 chv_set_pipe_power_well(dev_priv
, power_well
, true);
582 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
583 struct i915_power_well
*power_well
)
585 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
586 power_well
->data
!= PIPE_B
&&
587 power_well
->data
!= PIPE_C
);
589 chv_set_pipe_power_well(dev_priv
, power_well
, false);
592 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
593 struct i915_power_well
*power_well
)
595 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
597 if (power_well
->always_on
|| !i915
.disable_power_well
) {
604 if (enabled
!= (power_well
->count
> 0))
610 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
611 power_well
->name
, power_well
->always_on
, enabled
,
612 power_well
->count
, i915
.disable_power_well
);
616 * intel_display_power_get - grab a power domain reference
617 * @dev_priv: i915 device instance
618 * @domain: power domain to reference
620 * This function grabs a power domain reference for @domain and ensures that the
621 * power domain and all its parents are powered up. Therefore users should only
622 * grab a reference to the innermost power domain they need.
624 * Any power domain reference obtained by this function must have a symmetric
625 * call to intel_display_power_put() to release the reference again.
627 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
628 enum intel_display_power_domain domain
)
630 struct i915_power_domains
*power_domains
;
631 struct i915_power_well
*power_well
;
634 intel_runtime_pm_get(dev_priv
);
636 power_domains
= &dev_priv
->power_domains
;
638 mutex_lock(&power_domains
->lock
);
640 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
641 if (!power_well
->count
++) {
642 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
643 power_well
->ops
->enable(dev_priv
, power_well
);
644 power_well
->hw_enabled
= true;
647 check_power_well_state(dev_priv
, power_well
);
650 power_domains
->domain_use_count
[domain
]++;
652 mutex_unlock(&power_domains
->lock
);
656 * intel_display_power_put - release a power domain reference
657 * @dev_priv: i915 device instance
658 * @domain: power domain to reference
660 * This function drops the power domain reference obtained by
661 * intel_display_power_get() and might power down the corresponding hardware
662 * block right away if this is the last reference.
664 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
665 enum intel_display_power_domain domain
)
667 struct i915_power_domains
*power_domains
;
668 struct i915_power_well
*power_well
;
671 power_domains
= &dev_priv
->power_domains
;
673 mutex_lock(&power_domains
->lock
);
675 WARN_ON(!power_domains
->domain_use_count
[domain
]);
676 power_domains
->domain_use_count
[domain
]--;
678 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
679 WARN_ON(!power_well
->count
);
681 if (!--power_well
->count
&& i915
.disable_power_well
) {
682 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
683 power_well
->hw_enabled
= false;
684 power_well
->ops
->disable(dev_priv
, power_well
);
687 check_power_well_state(dev_priv
, power_well
);
690 mutex_unlock(&power_domains
->lock
);
692 intel_runtime_pm_put(dev_priv
);
695 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
697 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
698 BIT(POWER_DOMAIN_PIPE_A) | \
699 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
700 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
701 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
702 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
703 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
704 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
705 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
706 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
707 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
708 BIT(POWER_DOMAIN_PORT_CRT) | \
709 BIT(POWER_DOMAIN_PLLS) | \
710 BIT(POWER_DOMAIN_INIT))
711 #define HSW_DISPLAY_POWER_DOMAINS ( \
712 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
713 BIT(POWER_DOMAIN_INIT))
715 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
716 HSW_ALWAYS_ON_POWER_DOMAINS | \
717 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
718 #define BDW_DISPLAY_POWER_DOMAINS ( \
719 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
720 BIT(POWER_DOMAIN_INIT))
722 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
723 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
725 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
726 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
727 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
728 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
729 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
730 BIT(POWER_DOMAIN_PORT_CRT) | \
731 BIT(POWER_DOMAIN_INIT))
733 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
734 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
735 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
736 BIT(POWER_DOMAIN_INIT))
738 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
739 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
740 BIT(POWER_DOMAIN_INIT))
742 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
743 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
744 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
745 BIT(POWER_DOMAIN_INIT))
747 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
748 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
749 BIT(POWER_DOMAIN_INIT))
751 #define CHV_PIPE_A_POWER_DOMAINS ( \
752 BIT(POWER_DOMAIN_PIPE_A) | \
753 BIT(POWER_DOMAIN_INIT))
755 #define CHV_PIPE_B_POWER_DOMAINS ( \
756 BIT(POWER_DOMAIN_PIPE_B) | \
757 BIT(POWER_DOMAIN_INIT))
759 #define CHV_PIPE_C_POWER_DOMAINS ( \
760 BIT(POWER_DOMAIN_PIPE_C) | \
761 BIT(POWER_DOMAIN_INIT))
763 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
764 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
765 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
766 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
767 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
768 BIT(POWER_DOMAIN_INIT))
770 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
771 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
772 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
773 BIT(POWER_DOMAIN_INIT))
775 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
776 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
777 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
778 BIT(POWER_DOMAIN_INIT))
780 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
781 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
782 BIT(POWER_DOMAIN_INIT))
784 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
785 .sync_hw
= i9xx_always_on_power_well_noop
,
786 .enable
= i9xx_always_on_power_well_noop
,
787 .disable
= i9xx_always_on_power_well_noop
,
788 .is_enabled
= i9xx_always_on_power_well_enabled
,
791 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
792 .sync_hw
= chv_pipe_power_well_sync_hw
,
793 .enable
= chv_pipe_power_well_enable
,
794 .disable
= chv_pipe_power_well_disable
,
795 .is_enabled
= chv_pipe_power_well_enabled
,
798 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
799 .sync_hw
= vlv_power_well_sync_hw
,
800 .enable
= chv_dpio_cmn_power_well_enable
,
801 .disable
= chv_dpio_cmn_power_well_disable
,
802 .is_enabled
= vlv_power_well_enabled
,
805 static struct i915_power_well i9xx_always_on_power_well
[] = {
809 .domains
= POWER_DOMAIN_MASK
,
810 .ops
= &i9xx_always_on_power_well_ops
,
814 static const struct i915_power_well_ops hsw_power_well_ops
= {
815 .sync_hw
= hsw_power_well_sync_hw
,
816 .enable
= hsw_power_well_enable
,
817 .disable
= hsw_power_well_disable
,
818 .is_enabled
= hsw_power_well_enabled
,
821 static struct i915_power_well hsw_power_wells
[] = {
825 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
826 .ops
= &i9xx_always_on_power_well_ops
,
830 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
831 .ops
= &hsw_power_well_ops
,
835 static struct i915_power_well bdw_power_wells
[] = {
839 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
840 .ops
= &i9xx_always_on_power_well_ops
,
844 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
845 .ops
= &hsw_power_well_ops
,
849 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
850 .sync_hw
= vlv_power_well_sync_hw
,
851 .enable
= vlv_display_power_well_enable
,
852 .disable
= vlv_display_power_well_disable
,
853 .is_enabled
= vlv_power_well_enabled
,
856 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
857 .sync_hw
= vlv_power_well_sync_hw
,
858 .enable
= vlv_dpio_cmn_power_well_enable
,
859 .disable
= vlv_dpio_cmn_power_well_disable
,
860 .is_enabled
= vlv_power_well_enabled
,
863 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
864 .sync_hw
= vlv_power_well_sync_hw
,
865 .enable
= vlv_power_well_enable
,
866 .disable
= vlv_power_well_disable
,
867 .is_enabled
= vlv_power_well_enabled
,
870 static struct i915_power_well vlv_power_wells
[] = {
874 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
875 .ops
= &i9xx_always_on_power_well_ops
,
879 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
880 .data
= PUNIT_POWER_WELL_DISP2D
,
881 .ops
= &vlv_display_power_well_ops
,
884 .name
= "dpio-tx-b-01",
885 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
886 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
887 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
888 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
889 .ops
= &vlv_dpio_power_well_ops
,
890 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
893 .name
= "dpio-tx-b-23",
894 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
895 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
896 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
897 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
898 .ops
= &vlv_dpio_power_well_ops
,
899 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
902 .name
= "dpio-tx-c-01",
903 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
904 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
905 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
906 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
907 .ops
= &vlv_dpio_power_well_ops
,
908 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
911 .name
= "dpio-tx-c-23",
912 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
913 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
914 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
915 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
916 .ops
= &vlv_dpio_power_well_ops
,
917 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
920 .name
= "dpio-common",
921 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
922 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
923 .ops
= &vlv_dpio_cmn_power_well_ops
,
927 static struct i915_power_well chv_power_wells
[] = {
931 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
932 .ops
= &i9xx_always_on_power_well_ops
,
937 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
938 .data
= PUNIT_POWER_WELL_DISP2D
,
939 .ops
= &vlv_display_power_well_ops
,
943 .domains
= CHV_PIPE_A_POWER_DOMAINS
,
945 .ops
= &chv_pipe_power_well_ops
,
949 .domains
= CHV_PIPE_B_POWER_DOMAINS
,
951 .ops
= &chv_pipe_power_well_ops
,
955 .domains
= CHV_PIPE_C_POWER_DOMAINS
,
957 .ops
= &chv_pipe_power_well_ops
,
961 .name
= "dpio-common-bc",
963 * XXX: cmnreset for one PHY seems to disturb the other.
964 * As a workaround keep both powered on at the same
967 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
968 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
969 .ops
= &chv_dpio_cmn_power_well_ops
,
972 .name
= "dpio-common-d",
974 * XXX: cmnreset for one PHY seems to disturb the other.
975 * As a workaround keep both powered on at the same
978 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
979 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
980 .ops
= &chv_dpio_cmn_power_well_ops
,
984 .name
= "dpio-tx-b-01",
985 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
986 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
987 .ops
= &vlv_dpio_power_well_ops
,
988 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
991 .name
= "dpio-tx-b-23",
992 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
993 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
994 .ops
= &vlv_dpio_power_well_ops
,
995 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
998 .name
= "dpio-tx-c-01",
999 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1000 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1001 .ops
= &vlv_dpio_power_well_ops
,
1002 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
1005 .name
= "dpio-tx-c-23",
1006 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1007 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1008 .ops
= &vlv_dpio_power_well_ops
,
1009 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
1012 .name
= "dpio-tx-d-01",
1013 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
1014 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
1015 .ops
= &vlv_dpio_power_well_ops
,
1016 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_01
,
1019 .name
= "dpio-tx-d-23",
1020 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
1021 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
1022 .ops
= &vlv_dpio_power_well_ops
,
1023 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_23
,
1028 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
1029 enum punit_power_well power_well_id
)
1031 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1032 struct i915_power_well
*power_well
;
1035 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
1036 if (power_well
->data
== power_well_id
)
1043 #define set_power_wells(power_domains, __power_wells) ({ \
1044 (power_domains)->power_wells = (__power_wells); \
1045 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1049 * intel_power_domains_init - initializes the power domain structures
1050 * @dev_priv: i915 device instance
1052 * Initializes the power domain structures for @dev_priv depending upon the
1053 * supported platform.
1055 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
1057 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1059 mutex_init(&power_domains
->lock
);
1062 * The enabling order will be from lower to higher indexed wells,
1063 * the disabling order is reversed.
1065 if (IS_HASWELL(dev_priv
->dev
)) {
1066 set_power_wells(power_domains
, hsw_power_wells
);
1067 hsw_pwr
= power_domains
;
1068 } else if (IS_BROADWELL(dev_priv
->dev
)) {
1069 set_power_wells(power_domains
, bdw_power_wells
);
1070 hsw_pwr
= power_domains
;
1071 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1072 set_power_wells(power_domains
, chv_power_wells
);
1073 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
1074 set_power_wells(power_domains
, vlv_power_wells
);
1076 set_power_wells(power_domains
, i9xx_always_on_power_well
);
1082 static void intel_runtime_pm_disable(struct drm_i915_private
*dev_priv
)
1084 struct drm_device
*dev
= dev_priv
->dev
;
1085 struct device
*device
= &dev
->pdev
->dev
;
1087 if (!HAS_RUNTIME_PM(dev
))
1090 if (!intel_enable_rc6(dev
))
1093 /* Make sure we're not suspended first. */
1094 pm_runtime_get_sync(device
);
1095 pm_runtime_disable(device
);
1099 * intel_power_domains_fini - finalizes the power domain structures
1100 * @dev_priv: i915 device instance
1102 * Finalizes the power domain structures for @dev_priv depending upon the
1103 * supported platform. This function also disables runtime pm and ensures that
1104 * the device stays powered up so that the driver can be reloaded.
1106 void intel_power_domains_fini(struct drm_i915_private
*dev_priv
)
1108 intel_runtime_pm_disable(dev_priv
);
1110 /* The i915.ko module is still not prepared to be loaded when
1111 * the power well is not enabled, so just enable it in case
1112 * we're going to unload/reload. */
1113 intel_display_set_init_power(dev_priv
, true);
1118 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
1120 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1121 struct i915_power_well
*power_well
;
1124 mutex_lock(&power_domains
->lock
);
1125 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
1126 power_well
->ops
->sync_hw(dev_priv
, power_well
);
1127 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
1130 mutex_unlock(&power_domains
->lock
);
1133 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
1135 struct i915_power_well
*cmn
=
1136 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
1137 struct i915_power_well
*disp2d
=
1138 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
1140 /* If the display might be already active skip this */
1141 if (cmn
->ops
->is_enabled(dev_priv
, cmn
) &&
1142 disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
1143 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
1146 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1148 /* cmnlane needs DPLL registers */
1149 disp2d
->ops
->enable(dev_priv
, disp2d
);
1152 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1153 * Need to assert and de-assert PHY SB reset by gating the
1154 * common lane power, then un-gating it.
1155 * Simply ungating isn't enough to reset the PHY enough to get
1156 * ports and lanes running.
1158 cmn
->ops
->disable(dev_priv
, cmn
);
1162 * intel_power_domains_init_hw - initialize hardware power domain state
1163 * @dev_priv: i915 device instance
1165 * This function initializes the hardware power domain state and enables all
1166 * power domains using intel_display_set_init_power().
1168 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
1170 struct drm_device
*dev
= dev_priv
->dev
;
1171 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1173 power_domains
->initializing
= true;
1175 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
1176 mutex_lock(&power_domains
->lock
);
1177 vlv_cmnlane_wa(dev_priv
);
1178 mutex_unlock(&power_domains
->lock
);
1181 /* For now, we need the power well to be always enabled. */
1182 intel_display_set_init_power(dev_priv
, true);
1183 intel_power_domains_resume(dev_priv
);
1184 power_domains
->initializing
= false;
1188 * intel_aux_display_runtime_get - grab an auxilliary power domain reference
1189 * @dev_priv: i915 device instance
1191 * This function grabs a power domain reference for the auxiliary power domain
1192 * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
1193 * parents are powered up. Therefore users should only grab a reference to the
1194 * innermost power domain they need.
1196 * Any power domain reference obtained by this function must have a symmetric
1197 * call to intel_aux_display_runtime_put() to release the reference again.
1199 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
1201 intel_runtime_pm_get(dev_priv
);
1205 * intel_aux_display_runtime_put - release an auxilliary power domain reference
1206 * @dev_priv: i915 device instance
1208 * This function drops the auxilliary power domain reference obtained by
1209 * intel_aux_display_runtime_get() and might power down the corresponding
1210 * hardware block right away if this is the last reference.
1212 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
1214 intel_runtime_pm_put(dev_priv
);
1218 * intel_runtime_pm_get - grab a runtime pm reference
1219 * @dev_priv: i915 device instance
1221 * This function grabs a device-level runtime pm reference (mostly used for GEM
1222 * code to ensure the GTT or GT is on) and ensures that it is powered up.
1224 * Any runtime pm reference obtained by this function must have a symmetric
1225 * call to intel_runtime_pm_put() to release the reference again.
1227 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
1229 struct drm_device
*dev
= dev_priv
->dev
;
1230 struct device
*device
= &dev
->pdev
->dev
;
1232 if (!HAS_RUNTIME_PM(dev
))
1235 pm_runtime_get_sync(device
);
1236 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
1240 * intel_runtime_pm_get_noresume - grab a runtime pm reference
1241 * @dev_priv: i915 device instance
1243 * This function grabs a device-level runtime pm reference (mostly used for GEM
1244 * code to ensure the GTT or GT is on).
1246 * It will _not_ power up the device but instead only check that it's powered
1247 * on. Therefore it is only valid to call this functions from contexts where
1248 * the device is known to be powered up and where trying to power it up would
1249 * result in hilarity and deadlocks. That pretty much means only the system
1250 * suspend/resume code where this is used to grab runtime pm references for
1251 * delayed setup down in work items.
1253 * Any runtime pm reference obtained by this function must have a symmetric
1254 * call to intel_runtime_pm_put() to release the reference again.
1256 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
1258 struct drm_device
*dev
= dev_priv
->dev
;
1259 struct device
*device
= &dev
->pdev
->dev
;
1261 if (!HAS_RUNTIME_PM(dev
))
1264 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
1265 pm_runtime_get_noresume(device
);
1269 * intel_runtime_pm_put - release a runtime pm reference
1270 * @dev_priv: i915 device instance
1272 * This function drops the device-level runtime pm reference obtained by
1273 * intel_runtime_pm_get() and might power down the corresponding
1274 * hardware block right away if this is the last reference.
1276 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
1278 struct drm_device
*dev
= dev_priv
->dev
;
1279 struct device
*device
= &dev
->pdev
->dev
;
1281 if (!HAS_RUNTIME_PM(dev
))
1284 pm_runtime_mark_last_busy(device
);
1285 pm_runtime_put_autosuspend(device
);
1289 * intel_runtime_pm_enable - enable runtime pm
1290 * @dev_priv: i915 device instance
1292 * This function enables runtime pm at the end of the driver load sequence.
1294 * Note that this function does currently not enable runtime pm for the
1295 * subordinate display power domains. That is only done on the first modeset
1296 * using intel_display_set_init_power().
1298 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
)
1300 struct drm_device
*dev
= dev_priv
->dev
;
1301 struct device
*device
= &dev
->pdev
->dev
;
1303 if (!HAS_RUNTIME_PM(dev
))
1306 pm_runtime_set_active(device
);
1309 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1312 if (!intel_enable_rc6(dev
)) {
1313 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1317 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
1318 pm_runtime_mark_last_busy(device
);
1319 pm_runtime_use_autosuspend(device
);
1321 pm_runtime_put_autosuspend(device
);
1324 /* Display audio driver power well request */
1325 int i915_request_power_well(void)
1327 struct drm_i915_private
*dev_priv
;
1332 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
1334 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1337 EXPORT_SYMBOL_GPL(i915_request_power_well
);
1339 /* Display audio driver power well release */
1340 int i915_release_power_well(void)
1342 struct drm_i915_private
*dev_priv
;
1347 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
1349 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1352 EXPORT_SYMBOL_GPL(i915_release_power_well
);
1355 * Private interface for the audio driver to get CDCLK in kHz.
1357 * Caller must request power well using i915_request_power_well() prior to
1360 int i915_get_cdclk_freq(void)
1362 struct drm_i915_private
*dev_priv
;
1367 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
1370 return intel_ddi_get_cdclk_freq(dev_priv
);
1372 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq
);