2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
33 #include "intel_drv.h"
34 #include <drm/i915_powerwell.h>
36 static struct i915_power_domains
*hsw_pwr
;
38 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
40 i < (power_domains)->power_well_count && \
41 ((power_well) = &(power_domains)->power_wells[i]); \
43 if ((power_well)->domains & (domain_mask))
45 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
46 for (i = (power_domains)->power_well_count - 1; \
47 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
49 if ((power_well)->domains & (domain_mask))
52 * We should only use the power well if we explicitly asked the hardware to
53 * enable it, so check if it's enabled and also check if we've requested it to
56 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
57 struct i915_power_well
*power_well
)
59 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
60 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
63 bool intel_display_power_enabled_unlocked(struct drm_i915_private
*dev_priv
,
64 enum intel_display_power_domain domain
)
66 struct i915_power_domains
*power_domains
;
67 struct i915_power_well
*power_well
;
71 if (dev_priv
->pm
.suspended
)
74 power_domains
= &dev_priv
->power_domains
;
78 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
79 if (power_well
->always_on
)
82 if (!power_well
->hw_enabled
) {
91 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
92 enum intel_display_power_domain domain
)
94 struct i915_power_domains
*power_domains
;
97 power_domains
= &dev_priv
->power_domains
;
99 mutex_lock(&power_domains
->lock
);
100 ret
= intel_display_power_enabled_unlocked(dev_priv
, domain
);
101 mutex_unlock(&power_domains
->lock
);
107 * Starting with Haswell, we have a "Power Down Well" that can be turned off
108 * when not needed anymore. We have 4 registers that can request the power well
109 * to be enabled, and it will only be disabled if none of the registers is
110 * requesting it to be enabled.
112 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
114 struct drm_device
*dev
= dev_priv
->dev
;
117 * After we re-enable the power well, if we touch VGA register 0x3d5
118 * we'll get unclaimed register interrupts. This stops after we write
119 * anything to the VGA MSR register. The vgacon module uses this
120 * register all the time, so if we unbind our driver and, as a
121 * consequence, bind vgacon, we'll get stuck in an infinite loop at
122 * console_unlock(). So make here we touch the VGA MSR register, making
123 * sure vgacon can keep working normally without triggering interrupts
124 * and error messages.
126 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
127 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
128 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
130 if (IS_BROADWELL(dev
) || (INTEL_INFO(dev
)->gen
>= 9))
131 gen8_irq_power_well_post_enable(dev_priv
);
134 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
135 struct i915_power_well
*power_well
, bool enable
)
137 bool is_enabled
, enable_requested
;
140 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
141 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
142 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
145 if (!enable_requested
)
146 I915_WRITE(HSW_PWR_WELL_DRIVER
,
147 HSW_PWR_WELL_ENABLE_REQUEST
);
150 DRM_DEBUG_KMS("Enabling power well\n");
151 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
152 HSW_PWR_WELL_STATE_ENABLED
), 20))
153 DRM_ERROR("Timeout enabling power well\n");
156 hsw_power_well_post_enable(dev_priv
);
158 if (enable_requested
) {
159 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
160 POSTING_READ(HSW_PWR_WELL_DRIVER
);
161 DRM_DEBUG_KMS("Requesting to disable the power well\n");
166 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
167 struct i915_power_well
*power_well
)
169 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
172 * We're taking over the BIOS, so clear any requests made by it since
173 * the driver is in charge now.
175 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
176 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
179 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
180 struct i915_power_well
*power_well
)
182 hsw_set_power_well(dev_priv
, power_well
, true);
185 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
186 struct i915_power_well
*power_well
)
188 hsw_set_power_well(dev_priv
, power_well
, false);
191 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
192 struct i915_power_well
*power_well
)
196 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
197 struct i915_power_well
*power_well
)
202 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
203 struct i915_power_well
*power_well
, bool enable
)
205 enum punit_power_well power_well_id
= power_well
->data
;
210 mask
= PUNIT_PWRGT_MASK(power_well_id
);
211 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
212 PUNIT_PWRGT_PWR_GATE(power_well_id
);
214 mutex_lock(&dev_priv
->rps
.hw_lock
);
217 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
222 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
225 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
227 if (wait_for(COND
, 100))
228 DRM_ERROR("timout setting power well state %08x (%08x)\n",
230 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
235 mutex_unlock(&dev_priv
->rps
.hw_lock
);
238 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
239 struct i915_power_well
*power_well
)
241 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
244 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
245 struct i915_power_well
*power_well
)
247 vlv_set_power_well(dev_priv
, power_well
, true);
250 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
251 struct i915_power_well
*power_well
)
253 vlv_set_power_well(dev_priv
, power_well
, false);
256 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
257 struct i915_power_well
*power_well
)
259 int power_well_id
= power_well
->data
;
260 bool enabled
= false;
265 mask
= PUNIT_PWRGT_MASK(power_well_id
);
266 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
268 mutex_lock(&dev_priv
->rps
.hw_lock
);
270 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
272 * We only ever set the power-on and power-gate states, anything
273 * else is unexpected.
275 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
276 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
281 * A transient state at this point would mean some unexpected party
282 * is poking at the power controls too.
284 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
285 WARN_ON(ctrl
!= state
);
287 mutex_unlock(&dev_priv
->rps
.hw_lock
);
292 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
293 struct i915_power_well
*power_well
)
295 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
297 vlv_set_power_well(dev_priv
, power_well
, true);
299 spin_lock_irq(&dev_priv
->irq_lock
);
300 valleyview_enable_display_irqs(dev_priv
);
301 spin_unlock_irq(&dev_priv
->irq_lock
);
304 * During driver initialization/resume we can avoid restoring the
305 * part of the HW/SW state that will be inited anyway explicitly.
307 if (dev_priv
->power_domains
.initializing
)
310 intel_hpd_init(dev_priv
->dev
);
312 i915_redisable_vga_power_on(dev_priv
->dev
);
315 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
316 struct i915_power_well
*power_well
)
318 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
320 spin_lock_irq(&dev_priv
->irq_lock
);
321 valleyview_disable_display_irqs(dev_priv
);
322 spin_unlock_irq(&dev_priv
->irq_lock
);
324 vlv_set_power_well(dev_priv
, power_well
, false);
326 vlv_power_sequencer_reset(dev_priv
);
329 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
330 struct i915_power_well
*power_well
)
332 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
335 * Enable the CRI clock source so we can get at the
336 * display and the reference clock for VGA
337 * hotplug / manual detection.
339 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
340 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
341 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
343 vlv_set_power_well(dev_priv
, power_well
, true);
346 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
347 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
348 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
349 * b. The other bits such as sfr settings / modesel may all
352 * This should only be done on init and resume from S3 with
353 * both PLLs disabled, or we risk losing DPIO and PLL
356 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
359 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
360 struct i915_power_well
*power_well
)
364 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
366 for_each_pipe(dev_priv
, pipe
)
367 assert_pll_disabled(dev_priv
, pipe
);
369 /* Assert common reset */
370 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
372 vlv_set_power_well(dev_priv
, power_well
, false);
375 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
376 struct i915_power_well
*power_well
)
380 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
381 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
384 * Enable the CRI clock source so we can get at the
385 * display and the reference clock for VGA
386 * hotplug / manual detection.
388 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
390 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
391 DPLL_REFA_CLK_ENABLE_VLV
);
392 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
393 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
396 I915_WRITE(DPLL(PIPE_C
), I915_READ(DPLL(PIPE_C
)) |
397 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
);
399 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
400 vlv_set_power_well(dev_priv
, power_well
, true);
402 /* Poll for phypwrgood signal */
403 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
404 DRM_ERROR("Display PHY %d is not power up\n", phy
);
406 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) |
407 PHY_COM_LANE_RESET_DEASSERT(phy
));
410 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
411 struct i915_power_well
*power_well
)
415 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
416 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
418 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
420 assert_pll_disabled(dev_priv
, PIPE_A
);
421 assert_pll_disabled(dev_priv
, PIPE_B
);
424 assert_pll_disabled(dev_priv
, PIPE_C
);
427 I915_WRITE(DISPLAY_PHY_CONTROL
, I915_READ(DISPLAY_PHY_CONTROL
) &
428 ~PHY_COM_LANE_RESET_DEASSERT(phy
));
430 vlv_set_power_well(dev_priv
, power_well
, false);
433 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
434 struct i915_power_well
*power_well
)
436 enum pipe pipe
= power_well
->data
;
440 mutex_lock(&dev_priv
->rps
.hw_lock
);
442 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
444 * We only ever set the power-on and power-gate states, anything
445 * else is unexpected.
447 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
448 enabled
= state
== DP_SSS_PWR_ON(pipe
);
451 * A transient state at this point would mean some unexpected party
452 * is poking at the power controls too.
454 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
455 WARN_ON(ctrl
<< 16 != state
);
457 mutex_unlock(&dev_priv
->rps
.hw_lock
);
462 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
463 struct i915_power_well
*power_well
,
466 enum pipe pipe
= power_well
->data
;
470 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
472 mutex_lock(&dev_priv
->rps
.hw_lock
);
475 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
480 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
481 ctrl
&= ~DP_SSC_MASK(pipe
);
482 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
483 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
485 if (wait_for(COND
, 100))
486 DRM_ERROR("timout setting power well state %08x (%08x)\n",
488 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
493 mutex_unlock(&dev_priv
->rps
.hw_lock
);
496 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
497 struct i915_power_well
*power_well
)
499 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
502 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
503 struct i915_power_well
*power_well
)
505 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
506 power_well
->data
!= PIPE_B
&&
507 power_well
->data
!= PIPE_C
);
509 chv_set_pipe_power_well(dev_priv
, power_well
, true);
512 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
513 struct i915_power_well
*power_well
)
515 WARN_ON_ONCE(power_well
->data
!= PIPE_A
&&
516 power_well
->data
!= PIPE_B
&&
517 power_well
->data
!= PIPE_C
);
519 chv_set_pipe_power_well(dev_priv
, power_well
, false);
522 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
523 struct i915_power_well
*power_well
)
525 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
527 if (power_well
->always_on
|| !i915
.disable_power_well
) {
534 if (enabled
!= (power_well
->count
> 0))
540 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
541 power_well
->name
, power_well
->always_on
, enabled
,
542 power_well
->count
, i915
.disable_power_well
);
545 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
546 enum intel_display_power_domain domain
)
548 struct i915_power_domains
*power_domains
;
549 struct i915_power_well
*power_well
;
552 intel_runtime_pm_get(dev_priv
);
554 power_domains
= &dev_priv
->power_domains
;
556 mutex_lock(&power_domains
->lock
);
558 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
559 if (!power_well
->count
++) {
560 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
561 power_well
->ops
->enable(dev_priv
, power_well
);
562 power_well
->hw_enabled
= true;
565 check_power_well_state(dev_priv
, power_well
);
568 power_domains
->domain_use_count
[domain
]++;
570 mutex_unlock(&power_domains
->lock
);
573 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
574 enum intel_display_power_domain domain
)
576 struct i915_power_domains
*power_domains
;
577 struct i915_power_well
*power_well
;
580 power_domains
= &dev_priv
->power_domains
;
582 mutex_lock(&power_domains
->lock
);
584 WARN_ON(!power_domains
->domain_use_count
[domain
]);
585 power_domains
->domain_use_count
[domain
]--;
587 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
588 WARN_ON(!power_well
->count
);
590 if (!--power_well
->count
&& i915
.disable_power_well
) {
591 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
592 power_well
->hw_enabled
= false;
593 power_well
->ops
->disable(dev_priv
, power_well
);
596 check_power_well_state(dev_priv
, power_well
);
599 mutex_unlock(&power_domains
->lock
);
601 intel_runtime_pm_put(dev_priv
);
604 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
606 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
607 BIT(POWER_DOMAIN_PIPE_A) | \
608 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
609 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
610 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
611 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
612 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
613 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
614 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
615 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
616 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
617 BIT(POWER_DOMAIN_PORT_CRT) | \
618 BIT(POWER_DOMAIN_PLLS) | \
619 BIT(POWER_DOMAIN_INIT))
620 #define HSW_DISPLAY_POWER_DOMAINS ( \
621 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
622 BIT(POWER_DOMAIN_INIT))
624 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
625 HSW_ALWAYS_ON_POWER_DOMAINS | \
626 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
627 #define BDW_DISPLAY_POWER_DOMAINS ( \
628 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
629 BIT(POWER_DOMAIN_INIT))
631 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
632 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
634 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
635 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
636 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
637 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
638 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
639 BIT(POWER_DOMAIN_PORT_CRT) | \
640 BIT(POWER_DOMAIN_INIT))
642 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
643 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
644 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
645 BIT(POWER_DOMAIN_INIT))
647 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
648 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
649 BIT(POWER_DOMAIN_INIT))
651 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
652 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
653 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
654 BIT(POWER_DOMAIN_INIT))
656 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
657 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
658 BIT(POWER_DOMAIN_INIT))
660 #define CHV_PIPE_A_POWER_DOMAINS ( \
661 BIT(POWER_DOMAIN_PIPE_A) | \
662 BIT(POWER_DOMAIN_INIT))
664 #define CHV_PIPE_B_POWER_DOMAINS ( \
665 BIT(POWER_DOMAIN_PIPE_B) | \
666 BIT(POWER_DOMAIN_INIT))
668 #define CHV_PIPE_C_POWER_DOMAINS ( \
669 BIT(POWER_DOMAIN_PIPE_C) | \
670 BIT(POWER_DOMAIN_INIT))
672 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
673 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
674 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
675 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
676 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
677 BIT(POWER_DOMAIN_INIT))
679 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
680 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
681 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
682 BIT(POWER_DOMAIN_INIT))
684 #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
685 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
686 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
687 BIT(POWER_DOMAIN_INIT))
689 #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
690 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
691 BIT(POWER_DOMAIN_INIT))
693 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
694 .sync_hw
= i9xx_always_on_power_well_noop
,
695 .enable
= i9xx_always_on_power_well_noop
,
696 .disable
= i9xx_always_on_power_well_noop
,
697 .is_enabled
= i9xx_always_on_power_well_enabled
,
700 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
701 .sync_hw
= chv_pipe_power_well_sync_hw
,
702 .enable
= chv_pipe_power_well_enable
,
703 .disable
= chv_pipe_power_well_disable
,
704 .is_enabled
= chv_pipe_power_well_enabled
,
707 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
708 .sync_hw
= vlv_power_well_sync_hw
,
709 .enable
= chv_dpio_cmn_power_well_enable
,
710 .disable
= chv_dpio_cmn_power_well_disable
,
711 .is_enabled
= vlv_power_well_enabled
,
714 static struct i915_power_well i9xx_always_on_power_well
[] = {
718 .domains
= POWER_DOMAIN_MASK
,
719 .ops
= &i9xx_always_on_power_well_ops
,
723 static const struct i915_power_well_ops hsw_power_well_ops
= {
724 .sync_hw
= hsw_power_well_sync_hw
,
725 .enable
= hsw_power_well_enable
,
726 .disable
= hsw_power_well_disable
,
727 .is_enabled
= hsw_power_well_enabled
,
730 static struct i915_power_well hsw_power_wells
[] = {
734 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
735 .ops
= &i9xx_always_on_power_well_ops
,
739 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
740 .ops
= &hsw_power_well_ops
,
744 static struct i915_power_well bdw_power_wells
[] = {
748 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
749 .ops
= &i9xx_always_on_power_well_ops
,
753 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
754 .ops
= &hsw_power_well_ops
,
758 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
759 .sync_hw
= vlv_power_well_sync_hw
,
760 .enable
= vlv_display_power_well_enable
,
761 .disable
= vlv_display_power_well_disable
,
762 .is_enabled
= vlv_power_well_enabled
,
765 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
766 .sync_hw
= vlv_power_well_sync_hw
,
767 .enable
= vlv_dpio_cmn_power_well_enable
,
768 .disable
= vlv_dpio_cmn_power_well_disable
,
769 .is_enabled
= vlv_power_well_enabled
,
772 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
773 .sync_hw
= vlv_power_well_sync_hw
,
774 .enable
= vlv_power_well_enable
,
775 .disable
= vlv_power_well_disable
,
776 .is_enabled
= vlv_power_well_enabled
,
779 static struct i915_power_well vlv_power_wells
[] = {
783 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
784 .ops
= &i9xx_always_on_power_well_ops
,
788 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
789 .data
= PUNIT_POWER_WELL_DISP2D
,
790 .ops
= &vlv_display_power_well_ops
,
793 .name
= "dpio-tx-b-01",
794 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
795 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
796 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
797 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
798 .ops
= &vlv_dpio_power_well_ops
,
799 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
802 .name
= "dpio-tx-b-23",
803 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
804 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
805 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
806 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
807 .ops
= &vlv_dpio_power_well_ops
,
808 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
811 .name
= "dpio-tx-c-01",
812 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
813 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
814 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
815 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
816 .ops
= &vlv_dpio_power_well_ops
,
817 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
820 .name
= "dpio-tx-c-23",
821 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
822 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
823 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
824 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
825 .ops
= &vlv_dpio_power_well_ops
,
826 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
829 .name
= "dpio-common",
830 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
831 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
832 .ops
= &vlv_dpio_cmn_power_well_ops
,
836 static struct i915_power_well chv_power_wells
[] = {
840 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
841 .ops
= &i9xx_always_on_power_well_ops
,
846 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
847 .data
= PUNIT_POWER_WELL_DISP2D
,
848 .ops
= &vlv_display_power_well_ops
,
852 .domains
= CHV_PIPE_A_POWER_DOMAINS
,
854 .ops
= &chv_pipe_power_well_ops
,
858 .domains
= CHV_PIPE_B_POWER_DOMAINS
,
860 .ops
= &chv_pipe_power_well_ops
,
864 .domains
= CHV_PIPE_C_POWER_DOMAINS
,
866 .ops
= &chv_pipe_power_well_ops
,
870 .name
= "dpio-common-bc",
872 * XXX: cmnreset for one PHY seems to disturb the other.
873 * As a workaround keep both powered on at the same
876 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
877 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
878 .ops
= &chv_dpio_cmn_power_well_ops
,
881 .name
= "dpio-common-d",
883 * XXX: cmnreset for one PHY seems to disturb the other.
884 * As a workaround keep both powered on at the same
887 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
| CHV_DPIO_CMN_D_POWER_DOMAINS
,
888 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
889 .ops
= &chv_dpio_cmn_power_well_ops
,
893 .name
= "dpio-tx-b-01",
894 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
895 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
896 .ops
= &vlv_dpio_power_well_ops
,
897 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
900 .name
= "dpio-tx-b-23",
901 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
902 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
,
903 .ops
= &vlv_dpio_power_well_ops
,
904 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
907 .name
= "dpio-tx-c-01",
908 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
909 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
910 .ops
= &vlv_dpio_power_well_ops
,
911 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
914 .name
= "dpio-tx-c-23",
915 .domains
= VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
916 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
917 .ops
= &vlv_dpio_power_well_ops
,
918 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
921 .name
= "dpio-tx-d-01",
922 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
923 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
924 .ops
= &vlv_dpio_power_well_ops
,
925 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_01
,
928 .name
= "dpio-tx-d-23",
929 .domains
= CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS
|
930 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS
,
931 .ops
= &vlv_dpio_power_well_ops
,
932 .data
= PUNIT_POWER_WELL_DPIO_TX_D_LANES_23
,
937 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
938 enum punit_power_well power_well_id
)
940 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
941 struct i915_power_well
*power_well
;
944 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
945 if (power_well
->data
== power_well_id
)
952 #define set_power_wells(power_domains, __power_wells) ({ \
953 (power_domains)->power_wells = (__power_wells); \
954 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
957 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
959 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
961 mutex_init(&power_domains
->lock
);
964 * The enabling order will be from lower to higher indexed wells,
965 * the disabling order is reversed.
967 if (IS_HASWELL(dev_priv
->dev
)) {
968 set_power_wells(power_domains
, hsw_power_wells
);
969 hsw_pwr
= power_domains
;
970 } else if (IS_BROADWELL(dev_priv
->dev
)) {
971 set_power_wells(power_domains
, bdw_power_wells
);
972 hsw_pwr
= power_domains
;
973 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
974 set_power_wells(power_domains
, chv_power_wells
);
975 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
976 set_power_wells(power_domains
, vlv_power_wells
);
978 set_power_wells(power_domains
, i9xx_always_on_power_well
);
984 void intel_power_domains_remove(struct drm_i915_private
*dev_priv
)
989 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
991 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
992 struct i915_power_well
*power_well
;
995 mutex_lock(&power_domains
->lock
);
996 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
997 power_well
->ops
->sync_hw(dev_priv
, power_well
);
998 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
1001 mutex_unlock(&power_domains
->lock
);
1004 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
1006 struct i915_power_well
*cmn
=
1007 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
1008 struct i915_power_well
*disp2d
=
1009 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
1011 /* nothing to do if common lane is already off */
1012 if (!cmn
->ops
->is_enabled(dev_priv
, cmn
))
1015 /* If the display might be already active skip this */
1016 if (disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
1017 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
1020 DRM_DEBUG_KMS("toggling display PHY side reset\n");
1022 /* cmnlane needs DPLL registers */
1023 disp2d
->ops
->enable(dev_priv
, disp2d
);
1026 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1027 * Need to assert and de-assert PHY SB reset by gating the
1028 * common lane power, then un-gating it.
1029 * Simply ungating isn't enough to reset the PHY enough to get
1030 * ports and lanes running.
1032 cmn
->ops
->disable(dev_priv
, cmn
);
1035 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
1037 struct drm_device
*dev
= dev_priv
->dev
;
1038 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1040 power_domains
->initializing
= true;
1042 if (IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
)) {
1043 mutex_lock(&power_domains
->lock
);
1044 vlv_cmnlane_wa(dev_priv
);
1045 mutex_unlock(&power_domains
->lock
);
1048 /* For now, we need the power well to be always enabled. */
1049 intel_display_set_init_power(dev_priv
, true);
1050 intel_power_domains_resume(dev_priv
);
1051 power_domains
->initializing
= false;
1054 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
1056 intel_runtime_pm_get(dev_priv
);
1059 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
1061 intel_runtime_pm_put(dev_priv
);
1064 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
1066 struct drm_device
*dev
= dev_priv
->dev
;
1067 struct device
*device
= &dev
->pdev
->dev
;
1069 if (!HAS_RUNTIME_PM(dev
))
1072 pm_runtime_get_sync(device
);
1073 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
1076 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
1078 struct drm_device
*dev
= dev_priv
->dev
;
1079 struct device
*device
= &dev
->pdev
->dev
;
1081 if (!HAS_RUNTIME_PM(dev
))
1084 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
1085 pm_runtime_get_noresume(device
);
1088 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
1090 struct drm_device
*dev
= dev_priv
->dev
;
1091 struct device
*device
= &dev
->pdev
->dev
;
1093 if (!HAS_RUNTIME_PM(dev
))
1096 pm_runtime_mark_last_busy(device
);
1097 pm_runtime_put_autosuspend(device
);
1100 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
1102 struct drm_device
*dev
= dev_priv
->dev
;
1103 struct device
*device
= &dev
->pdev
->dev
;
1105 if (!HAS_RUNTIME_PM(dev
))
1108 pm_runtime_set_active(device
);
1111 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
1114 if (!intel_enable_rc6(dev
)) {
1115 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
1119 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
1120 pm_runtime_mark_last_busy(device
);
1121 pm_runtime_use_autosuspend(device
);
1123 pm_runtime_put_autosuspend(device
);
1126 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
1128 struct drm_device
*dev
= dev_priv
->dev
;
1129 struct device
*device
= &dev
->pdev
->dev
;
1131 if (!HAS_RUNTIME_PM(dev
))
1134 if (!intel_enable_rc6(dev
))
1137 /* Make sure we're not suspended first. */
1138 pm_runtime_get_sync(device
);
1139 pm_runtime_disable(device
);
1142 /* Display audio driver power well request */
1143 int i915_request_power_well(void)
1145 struct drm_i915_private
*dev_priv
;
1150 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
1152 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
1155 EXPORT_SYMBOL_GPL(i915_request_power_well
);
1157 /* Display audio driver power well release */
1158 int i915_release_power_well(void)
1160 struct drm_i915_private
*dev_priv
;
1165 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
1167 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
1170 EXPORT_SYMBOL_GPL(i915_release_power_well
);
1173 * Private interface for the audio driver to get CDCLK in kHz.
1175 * Caller must request power well using i915_request_power_well() prior to
1178 int i915_get_cdclk_freq(void)
1180 struct drm_i915_private
*dev_priv
;
1185 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
1188 return intel_ddi_get_cdclk_freq(dev_priv
);
1190 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq
);