2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
33 #include "intel_drv.h"
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
57 for_each_if ((power_well)->domains & (domain_mask))
59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
63 for_each_if ((power_well)->domains & (domain_mask))
65 bool intel_display_power_well_is_enabled(struct drm_i915_private
*dev_priv
,
69 intel_display_power_domain_str(enum intel_display_power_domain domain
)
72 case POWER_DOMAIN_PIPE_A
:
74 case POWER_DOMAIN_PIPE_B
:
76 case POWER_DOMAIN_PIPE_C
:
78 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
79 return "PIPE_A_PANEL_FITTER";
80 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
81 return "PIPE_B_PANEL_FITTER";
82 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
83 return "PIPE_C_PANEL_FITTER";
84 case POWER_DOMAIN_TRANSCODER_A
:
85 return "TRANSCODER_A";
86 case POWER_DOMAIN_TRANSCODER_B
:
87 return "TRANSCODER_B";
88 case POWER_DOMAIN_TRANSCODER_C
:
89 return "TRANSCODER_C";
90 case POWER_DOMAIN_TRANSCODER_EDP
:
91 return "TRANSCODER_EDP";
92 case POWER_DOMAIN_PORT_DDI_A_LANES
:
93 return "PORT_DDI_A_LANES";
94 case POWER_DOMAIN_PORT_DDI_B_LANES
:
95 return "PORT_DDI_B_LANES";
96 case POWER_DOMAIN_PORT_DDI_C_LANES
:
97 return "PORT_DDI_C_LANES";
98 case POWER_DOMAIN_PORT_DDI_D_LANES
:
99 return "PORT_DDI_D_LANES";
100 case POWER_DOMAIN_PORT_DDI_E_LANES
:
101 return "PORT_DDI_E_LANES";
102 case POWER_DOMAIN_PORT_DSI
:
104 case POWER_DOMAIN_PORT_CRT
:
106 case POWER_DOMAIN_PORT_OTHER
:
108 case POWER_DOMAIN_VGA
:
110 case POWER_DOMAIN_AUDIO
:
112 case POWER_DOMAIN_PLLS
:
114 case POWER_DOMAIN_AUX_A
:
116 case POWER_DOMAIN_AUX_B
:
118 case POWER_DOMAIN_AUX_C
:
120 case POWER_DOMAIN_AUX_D
:
122 case POWER_DOMAIN_GMBUS
:
124 case POWER_DOMAIN_INIT
:
126 case POWER_DOMAIN_MODESET
:
129 MISSING_CASE(domain
);
134 static void intel_power_well_enable(struct drm_i915_private
*dev_priv
,
135 struct i915_power_well
*power_well
)
137 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
138 power_well
->ops
->enable(dev_priv
, power_well
);
139 power_well
->hw_enabled
= true;
142 static void intel_power_well_disable(struct drm_i915_private
*dev_priv
,
143 struct i915_power_well
*power_well
)
145 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
146 power_well
->hw_enabled
= false;
147 power_well
->ops
->disable(dev_priv
, power_well
);
151 * We should only use the power well if we explicitly asked the hardware to
152 * enable it, so check if it's enabled and also check if we've requested it to
155 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
156 struct i915_power_well
*power_well
)
158 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
159 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
163 * __intel_display_power_is_enabled - unlocked check for a power domain
164 * @dev_priv: i915 device instance
165 * @domain: power domain to check
167 * This is the unlocked version of intel_display_power_is_enabled() and should
168 * only be used from error capture and recovery code where deadlocks are
172 * True when the power domain is enabled, false otherwise.
174 bool __intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
175 enum intel_display_power_domain domain
)
177 struct i915_power_domains
*power_domains
;
178 struct i915_power_well
*power_well
;
182 if (dev_priv
->pm
.suspended
)
185 power_domains
= &dev_priv
->power_domains
;
189 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
190 if (power_well
->always_on
)
193 if (!power_well
->hw_enabled
) {
203 * intel_display_power_is_enabled - check for a power domain
204 * @dev_priv: i915 device instance
205 * @domain: power domain to check
207 * This function can be used to check the hw power domain state. It is mostly
208 * used in hardware state readout functions. Everywhere else code should rely
209 * upon explicit power domain reference counting to ensure that the hardware
210 * block is powered up before accessing it.
212 * Callers must hold the relevant modesetting locks to ensure that concurrent
213 * threads can't disable the power well while the caller tries to read a few
217 * True when the power domain is enabled, false otherwise.
219 bool intel_display_power_is_enabled(struct drm_i915_private
*dev_priv
,
220 enum intel_display_power_domain domain
)
222 struct i915_power_domains
*power_domains
;
225 power_domains
= &dev_priv
->power_domains
;
227 mutex_lock(&power_domains
->lock
);
228 ret
= __intel_display_power_is_enabled(dev_priv
, domain
);
229 mutex_unlock(&power_domains
->lock
);
235 * intel_display_set_init_power - set the initial power domain state
236 * @dev_priv: i915 device instance
237 * @enable: whether to enable or disable the initial power domain state
239 * For simplicity our driver load/unload and system suspend/resume code assumes
240 * that all power domains are always enabled. This functions controls the state
241 * of this little hack. While the initial power domain state is enabled runtime
242 * pm is effectively disabled.
244 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
247 if (dev_priv
->power_domains
.init_power_on
== enable
)
251 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
253 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
255 dev_priv
->power_domains
.init_power_on
= enable
;
259 * Starting with Haswell, we have a "Power Down Well" that can be turned off
260 * when not needed anymore. We have 4 registers that can request the power well
261 * to be enabled, and it will only be disabled if none of the registers is
262 * requesting it to be enabled.
264 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
266 struct drm_device
*dev
= dev_priv
->dev
;
269 * After we re-enable the power well, if we touch VGA register 0x3d5
270 * we'll get unclaimed register interrupts. This stops after we write
271 * anything to the VGA MSR register. The vgacon module uses this
272 * register all the time, so if we unbind our driver and, as a
273 * consequence, bind vgacon, we'll get stuck in an infinite loop at
274 * console_unlock(). So make here we touch the VGA MSR register, making
275 * sure vgacon can keep working normally without triggering interrupts
276 * and error messages.
278 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
279 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
280 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
282 if (IS_BROADWELL(dev
))
283 gen8_irq_power_well_post_enable(dev_priv
,
284 1 << PIPE_C
| 1 << PIPE_B
);
287 static void hsw_power_well_pre_disable(struct drm_i915_private
*dev_priv
)
289 if (IS_BROADWELL(dev_priv
))
290 gen8_irq_power_well_pre_disable(dev_priv
,
291 1 << PIPE_C
| 1 << PIPE_B
);
294 static void skl_power_well_post_enable(struct drm_i915_private
*dev_priv
,
295 struct i915_power_well
*power_well
)
297 struct drm_device
*dev
= dev_priv
->dev
;
300 * After we re-enable the power well, if we touch VGA register 0x3d5
301 * we'll get unclaimed register interrupts. This stops after we write
302 * anything to the VGA MSR register. The vgacon module uses this
303 * register all the time, so if we unbind our driver and, as a
304 * consequence, bind vgacon, we'll get stuck in an infinite loop at
305 * console_unlock(). So make here we touch the VGA MSR register, making
306 * sure vgacon can keep working normally without triggering interrupts
307 * and error messages.
309 if (power_well
->data
== SKL_DISP_PW_2
) {
310 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
311 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
312 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
314 gen8_irq_power_well_post_enable(dev_priv
,
315 1 << PIPE_C
| 1 << PIPE_B
);
319 static void skl_power_well_pre_disable(struct drm_i915_private
*dev_priv
,
320 struct i915_power_well
*power_well
)
322 if (power_well
->data
== SKL_DISP_PW_2
)
323 gen8_irq_power_well_pre_disable(dev_priv
,
324 1 << PIPE_C
| 1 << PIPE_B
);
327 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
328 struct i915_power_well
*power_well
, bool enable
)
330 bool is_enabled
, enable_requested
;
333 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
334 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
335 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
338 if (!enable_requested
)
339 I915_WRITE(HSW_PWR_WELL_DRIVER
,
340 HSW_PWR_WELL_ENABLE_REQUEST
);
343 DRM_DEBUG_KMS("Enabling power well\n");
344 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
345 HSW_PWR_WELL_STATE_ENABLED
), 20))
346 DRM_ERROR("Timeout enabling power well\n");
347 hsw_power_well_post_enable(dev_priv
);
351 if (enable_requested
) {
352 hsw_power_well_pre_disable(dev_priv
);
353 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
354 POSTING_READ(HSW_PWR_WELL_DRIVER
);
355 DRM_DEBUG_KMS("Requesting to disable the power well\n");
360 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
361 BIT(POWER_DOMAIN_TRANSCODER_A) | \
362 BIT(POWER_DOMAIN_PIPE_B) | \
363 BIT(POWER_DOMAIN_TRANSCODER_B) | \
364 BIT(POWER_DOMAIN_PIPE_C) | \
365 BIT(POWER_DOMAIN_TRANSCODER_C) | \
366 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
367 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
368 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
369 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
370 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
371 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
372 BIT(POWER_DOMAIN_AUX_B) | \
373 BIT(POWER_DOMAIN_AUX_C) | \
374 BIT(POWER_DOMAIN_AUX_D) | \
375 BIT(POWER_DOMAIN_AUDIO) | \
376 BIT(POWER_DOMAIN_VGA) | \
377 BIT(POWER_DOMAIN_INIT))
378 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
379 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
380 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
381 BIT(POWER_DOMAIN_INIT))
382 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
383 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
384 BIT(POWER_DOMAIN_INIT))
385 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
386 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
387 BIT(POWER_DOMAIN_INIT))
388 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
389 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
390 BIT(POWER_DOMAIN_INIT))
391 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
392 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
393 BIT(POWER_DOMAIN_MODESET) | \
394 BIT(POWER_DOMAIN_AUX_A) | \
395 BIT(POWER_DOMAIN_INIT))
396 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
397 (POWER_DOMAIN_MASK & ~( \
398 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
399 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
400 BIT(POWER_DOMAIN_INIT))
402 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
403 BIT(POWER_DOMAIN_TRANSCODER_A) | \
404 BIT(POWER_DOMAIN_PIPE_B) | \
405 BIT(POWER_DOMAIN_TRANSCODER_B) | \
406 BIT(POWER_DOMAIN_PIPE_C) | \
407 BIT(POWER_DOMAIN_TRANSCODER_C) | \
408 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
409 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
410 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
411 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
412 BIT(POWER_DOMAIN_AUX_B) | \
413 BIT(POWER_DOMAIN_AUX_C) | \
414 BIT(POWER_DOMAIN_AUDIO) | \
415 BIT(POWER_DOMAIN_VGA) | \
416 BIT(POWER_DOMAIN_GMBUS) | \
417 BIT(POWER_DOMAIN_INIT))
418 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
419 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
420 BIT(POWER_DOMAIN_PIPE_A) | \
421 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
422 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
423 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
424 BIT(POWER_DOMAIN_AUX_A) | \
425 BIT(POWER_DOMAIN_PLLS) | \
426 BIT(POWER_DOMAIN_INIT))
427 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
428 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
429 BIT(POWER_DOMAIN_MODESET) | \
430 BIT(POWER_DOMAIN_AUX_A) | \
431 BIT(POWER_DOMAIN_INIT))
432 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
433 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
434 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
435 BIT(POWER_DOMAIN_INIT))
437 static void assert_can_enable_dc9(struct drm_i915_private
*dev_priv
)
439 struct drm_device
*dev
= dev_priv
->dev
;
441 WARN(!IS_BROXTON(dev
), "Platform doesn't support DC9.\n");
442 WARN((I915_READ(DC_STATE_EN
) & DC_STATE_EN_DC9
),
443 "DC9 already programmed to be enabled.\n");
444 WARN(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
,
445 "DC5 still not disabled to enable DC9.\n");
446 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on.\n");
447 WARN(intel_irqs_enabled(dev_priv
), "Interrupts not disabled yet.\n");
450 * TODO: check for the following to verify the conditions to enter DC9
451 * state are satisfied:
452 * 1] Check relevant display engine registers to verify if mode set
453 * disable sequence was followed.
454 * 2] Check if display uninitialize sequence is initialized.
458 static void assert_can_disable_dc9(struct drm_i915_private
*dev_priv
)
460 WARN(intel_irqs_enabled(dev_priv
), "Interrupts not disabled yet.\n");
461 WARN(!(I915_READ(DC_STATE_EN
) & DC_STATE_EN_DC9
),
462 "DC9 already programmed to be disabled.\n");
463 WARN(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
,
464 "DC5 still not disabled.\n");
467 * TODO: check for the following to verify DC9 state was indeed
468 * entered before programming to disable it:
469 * 1] Check relevant display engine registers to verify if mode
470 * set disable sequence was followed.
471 * 2] Check if display uninitialize sequence is initialized.
475 static void gen9_set_dc_state_debugmask(struct drm_i915_private
*dev_priv
)
479 mask
= DC_STATE_DEBUG_MASK_MEMORY_UP
;
481 if (IS_BROXTON(dev_priv
))
482 mask
|= DC_STATE_DEBUG_MASK_CORES
;
484 /* The below bit doesn't need to be cleared ever afterwards */
485 val
= I915_READ(DC_STATE_DEBUG
);
486 if ((val
& mask
) != mask
) {
488 I915_WRITE(DC_STATE_DEBUG
, val
);
489 POSTING_READ(DC_STATE_DEBUG
);
493 static void gen9_write_dc_state(struct drm_i915_private
*dev_priv
,
500 I915_WRITE(DC_STATE_EN
, state
);
502 /* It has been observed that disabling the dc6 state sometimes
503 * doesn't stick and dmc keeps returning old value. Make sure
504 * the write really sticks enough times and also force rewrite until
505 * we are confident that state is exactly what we want.
508 v
= I915_READ(DC_STATE_EN
);
511 I915_WRITE(DC_STATE_EN
, state
);
514 } else if (rereads
++ > 5) {
518 } while (rewrites
< 100);
521 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
524 /* Most of the times we need one retry, avoid spam */
526 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
530 static void gen9_set_dc_state(struct drm_i915_private
*dev_priv
, uint32_t state
)
535 mask
= DC_STATE_EN_UPTO_DC5
;
536 if (IS_BROXTON(dev_priv
))
537 mask
|= DC_STATE_EN_DC9
;
539 mask
|= DC_STATE_EN_UPTO_DC6
;
541 WARN_ON_ONCE(state
& ~mask
);
543 if (i915
.enable_dc
== 0)
544 state
= DC_STATE_DISABLE
;
545 else if (i915
.enable_dc
== 1 && state
> DC_STATE_EN_UPTO_DC5
)
546 state
= DC_STATE_EN_UPTO_DC5
;
548 val
= I915_READ(DC_STATE_EN
);
549 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
552 /* Check if DMC is ignoring our DC state requests */
553 if ((val
& mask
) != dev_priv
->csr
.dc_state
)
554 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
555 dev_priv
->csr
.dc_state
, val
& mask
);
560 gen9_write_dc_state(dev_priv
, val
);
562 dev_priv
->csr
.dc_state
= val
& mask
;
565 void bxt_enable_dc9(struct drm_i915_private
*dev_priv
)
567 assert_can_enable_dc9(dev_priv
);
569 DRM_DEBUG_KMS("Enabling DC9\n");
571 gen9_set_dc_state(dev_priv
, DC_STATE_EN_DC9
);
574 void bxt_disable_dc9(struct drm_i915_private
*dev_priv
)
576 assert_can_disable_dc9(dev_priv
);
578 DRM_DEBUG_KMS("Disabling DC9\n");
580 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
583 static void assert_csr_loaded(struct drm_i915_private
*dev_priv
)
585 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
586 "CSR program storage start is NULL\n");
587 WARN_ONCE(!I915_READ(CSR_SSP_BASE
), "CSR SSP Base Not fine\n");
588 WARN_ONCE(!I915_READ(CSR_HTP_SKL
), "CSR HTP Not fine\n");
591 static void assert_can_enable_dc5(struct drm_i915_private
*dev_priv
)
593 struct drm_device
*dev
= dev_priv
->dev
;
594 bool pg2_enabled
= intel_display_power_well_is_enabled(dev_priv
,
597 WARN_ONCE(!IS_SKYLAKE(dev
) && !IS_KABYLAKE(dev
),
598 "Platform doesn't support DC5.\n");
599 WARN_ONCE(!HAS_RUNTIME_PM(dev
), "Runtime PM not enabled.\n");
600 WARN_ONCE(pg2_enabled
, "PG2 not disabled to enable DC5.\n");
602 WARN_ONCE((I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5
),
603 "DC5 already programmed to be enabled.\n");
604 assert_rpm_wakelock_held(dev_priv
);
606 assert_csr_loaded(dev_priv
);
609 static void assert_can_disable_dc5(struct drm_i915_private
*dev_priv
)
612 * During initialization, the firmware may not be loaded yet.
613 * We still want to make sure that the DC enabling flag is cleared.
615 if (dev_priv
->power_domains
.initializing
)
618 assert_rpm_wakelock_held(dev_priv
);
621 static void gen9_enable_dc5(struct drm_i915_private
*dev_priv
)
623 assert_can_enable_dc5(dev_priv
);
625 DRM_DEBUG_KMS("Enabling DC5\n");
627 gen9_set_dc_state(dev_priv
, DC_STATE_EN_UPTO_DC5
);
630 static void assert_can_enable_dc6(struct drm_i915_private
*dev_priv
)
632 struct drm_device
*dev
= dev_priv
->dev
;
634 WARN_ONCE(!IS_SKYLAKE(dev
) && !IS_KABYLAKE(dev
),
635 "Platform doesn't support DC6.\n");
636 WARN_ONCE(!HAS_RUNTIME_PM(dev
), "Runtime PM not enabled.\n");
637 WARN_ONCE(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
638 "Backlight is not disabled.\n");
639 WARN_ONCE((I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC6
),
640 "DC6 already programmed to be enabled.\n");
642 assert_csr_loaded(dev_priv
);
645 static void assert_can_disable_dc6(struct drm_i915_private
*dev_priv
)
648 * During initialization, the firmware may not be loaded yet.
649 * We still want to make sure that the DC enabling flag is cleared.
651 if (dev_priv
->power_domains
.initializing
)
654 WARN_ONCE(!(I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC6
),
655 "DC6 already programmed to be disabled.\n");
658 static void gen9_disable_dc5_dc6(struct drm_i915_private
*dev_priv
)
660 assert_can_disable_dc5(dev_priv
);
662 if ((IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) &&
663 i915
.enable_dc
!= 0 && i915
.enable_dc
!= 1)
664 assert_can_disable_dc6(dev_priv
);
666 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
669 void skl_enable_dc6(struct drm_i915_private
*dev_priv
)
671 assert_can_enable_dc6(dev_priv
);
673 DRM_DEBUG_KMS("Enabling DC6\n");
675 gen9_set_dc_state(dev_priv
, DC_STATE_EN_UPTO_DC6
);
679 void skl_disable_dc6(struct drm_i915_private
*dev_priv
)
681 assert_can_disable_dc6(dev_priv
);
683 DRM_DEBUG_KMS("Disabling DC6\n");
685 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
688 static void skl_set_power_well(struct drm_i915_private
*dev_priv
,
689 struct i915_power_well
*power_well
, bool enable
)
691 uint32_t tmp
, fuse_status
;
692 uint32_t req_mask
, state_mask
;
693 bool is_enabled
, enable_requested
, check_fuse_status
= false;
695 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
696 fuse_status
= I915_READ(SKL_FUSE_STATUS
);
698 switch (power_well
->data
) {
700 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
701 SKL_FUSE_PG0_DIST_STATUS
), 1)) {
702 DRM_ERROR("PG0 not enabled\n");
707 if (!(fuse_status
& SKL_FUSE_PG1_DIST_STATUS
)) {
708 DRM_ERROR("PG1 in disabled state\n");
712 case SKL_DISP_PW_DDI_A_E
:
713 case SKL_DISP_PW_DDI_B
:
714 case SKL_DISP_PW_DDI_C
:
715 case SKL_DISP_PW_DDI_D
:
716 case SKL_DISP_PW_MISC_IO
:
719 WARN(1, "Unknown power well %lu\n", power_well
->data
);
723 req_mask
= SKL_POWER_WELL_REQ(power_well
->data
);
724 enable_requested
= tmp
& req_mask
;
725 state_mask
= SKL_POWER_WELL_STATE(power_well
->data
);
726 is_enabled
= tmp
& state_mask
;
728 if (!enable
&& enable_requested
)
729 skl_power_well_pre_disable(dev_priv
, power_well
);
732 if (!enable_requested
) {
733 WARN((tmp
& state_mask
) &&
734 !I915_READ(HSW_PWR_WELL_BIOS
),
735 "Invalid for power well status to be enabled, unless done by the BIOS, \
736 when request is to disable!\n");
737 I915_WRITE(HSW_PWR_WELL_DRIVER
, tmp
| req_mask
);
741 DRM_DEBUG_KMS("Enabling %s\n", power_well
->name
);
742 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
744 DRM_ERROR("%s enable timeout\n",
746 check_fuse_status
= true;
749 if (enable_requested
) {
750 I915_WRITE(HSW_PWR_WELL_DRIVER
, tmp
& ~req_mask
);
751 POSTING_READ(HSW_PWR_WELL_DRIVER
);
752 DRM_DEBUG_KMS("Disabling %s\n", power_well
->name
);
756 if (check_fuse_status
) {
757 if (power_well
->data
== SKL_DISP_PW_1
) {
758 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
759 SKL_FUSE_PG1_DIST_STATUS
), 1))
760 DRM_ERROR("PG1 distributing status timeout\n");
761 } else if (power_well
->data
== SKL_DISP_PW_2
) {
762 if (wait_for((I915_READ(SKL_FUSE_STATUS
) &
763 SKL_FUSE_PG2_DIST_STATUS
), 1))
764 DRM_ERROR("PG2 distributing status timeout\n");
768 if (enable
&& !is_enabled
)
769 skl_power_well_post_enable(dev_priv
, power_well
);
772 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
773 struct i915_power_well
*power_well
)
775 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
778 * We're taking over the BIOS, so clear any requests made by it since
779 * the driver is in charge now.
781 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
782 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
785 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
786 struct i915_power_well
*power_well
)
788 hsw_set_power_well(dev_priv
, power_well
, true);
791 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
792 struct i915_power_well
*power_well
)
794 hsw_set_power_well(dev_priv
, power_well
, false);
797 static bool skl_power_well_enabled(struct drm_i915_private
*dev_priv
,
798 struct i915_power_well
*power_well
)
800 uint32_t mask
= SKL_POWER_WELL_REQ(power_well
->data
) |
801 SKL_POWER_WELL_STATE(power_well
->data
);
803 return (I915_READ(HSW_PWR_WELL_DRIVER
) & mask
) == mask
;
806 static void skl_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
807 struct i915_power_well
*power_well
)
809 skl_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
811 /* Clear any request made by BIOS as driver is taking over */
812 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
815 static void skl_power_well_enable(struct drm_i915_private
*dev_priv
,
816 struct i915_power_well
*power_well
)
818 skl_set_power_well(dev_priv
, power_well
, true);
821 static void skl_power_well_disable(struct drm_i915_private
*dev_priv
,
822 struct i915_power_well
*power_well
)
824 skl_set_power_well(dev_priv
, power_well
, false);
827 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
*dev_priv
,
828 struct i915_power_well
*power_well
)
830 return (I915_READ(DC_STATE_EN
) & DC_STATE_EN_UPTO_DC5_DC6_MASK
) == 0;
833 static void gen9_dc_off_power_well_enable(struct drm_i915_private
*dev_priv
,
834 struct i915_power_well
*power_well
)
836 gen9_disable_dc5_dc6(dev_priv
);
839 static void gen9_dc_off_power_well_disable(struct drm_i915_private
*dev_priv
,
840 struct i915_power_well
*power_well
)
842 if ((IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) &&
843 i915
.enable_dc
!= 0 && i915
.enable_dc
!= 1)
844 skl_enable_dc6(dev_priv
);
846 gen9_enable_dc5(dev_priv
);
849 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
850 struct i915_power_well
*power_well
)
852 if (power_well
->count
> 0) {
853 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
855 if ((IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) &&
856 i915
.enable_dc
!= 0 &&
858 gen9_set_dc_state(dev_priv
, DC_STATE_EN_UPTO_DC6
);
860 gen9_set_dc_state(dev_priv
, DC_STATE_EN_UPTO_DC5
);
864 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
865 struct i915_power_well
*power_well
)
869 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
870 struct i915_power_well
*power_well
)
875 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
876 struct i915_power_well
*power_well
, bool enable
)
878 enum punit_power_well power_well_id
= power_well
->data
;
883 mask
= PUNIT_PWRGT_MASK(power_well_id
);
884 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
885 PUNIT_PWRGT_PWR_GATE(power_well_id
);
887 mutex_lock(&dev_priv
->rps
.hw_lock
);
890 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
895 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
898 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
900 if (wait_for(COND
, 100))
901 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
903 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
908 mutex_unlock(&dev_priv
->rps
.hw_lock
);
911 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
912 struct i915_power_well
*power_well
)
914 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
917 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
918 struct i915_power_well
*power_well
)
920 vlv_set_power_well(dev_priv
, power_well
, true);
923 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
924 struct i915_power_well
*power_well
)
926 vlv_set_power_well(dev_priv
, power_well
, false);
929 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
930 struct i915_power_well
*power_well
)
932 int power_well_id
= power_well
->data
;
933 bool enabled
= false;
938 mask
= PUNIT_PWRGT_MASK(power_well_id
);
939 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
941 mutex_lock(&dev_priv
->rps
.hw_lock
);
943 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
945 * We only ever set the power-on and power-gate states, anything
946 * else is unexpected.
948 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
949 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
954 * A transient state at this point would mean some unexpected party
955 * is poking at the power controls too.
957 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
958 WARN_ON(ctrl
!= state
);
960 mutex_unlock(&dev_priv
->rps
.hw_lock
);
965 static void vlv_display_power_well_init(struct drm_i915_private
*dev_priv
)
970 * Enable the CRI clock source so we can get at the
971 * display and the reference clock for VGA
972 * hotplug / manual detection. Supposedly DSI also
973 * needs the ref clock up and running.
975 * CHV DPLL B/C have some issues if VGA mode is enabled.
977 for_each_pipe(dev_priv
->dev
, pipe
) {
978 u32 val
= I915_READ(DPLL(pipe
));
980 val
|= DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
982 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
984 I915_WRITE(DPLL(pipe
), val
);
987 spin_lock_irq(&dev_priv
->irq_lock
);
988 valleyview_enable_display_irqs(dev_priv
);
989 spin_unlock_irq(&dev_priv
->irq_lock
);
992 * During driver initialization/resume we can avoid restoring the
993 * part of the HW/SW state that will be inited anyway explicitly.
995 if (dev_priv
->power_domains
.initializing
)
998 intel_hpd_init(dev_priv
);
1000 i915_redisable_vga_power_on(dev_priv
->dev
);
1003 static void vlv_display_power_well_deinit(struct drm_i915_private
*dev_priv
)
1005 spin_lock_irq(&dev_priv
->irq_lock
);
1006 valleyview_disable_display_irqs(dev_priv
);
1007 spin_unlock_irq(&dev_priv
->irq_lock
);
1009 /* make sure we're done processing display irqs */
1010 synchronize_irq(dev_priv
->dev
->irq
);
1012 vlv_power_sequencer_reset(dev_priv
);
1015 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
1016 struct i915_power_well
*power_well
)
1018 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
1020 vlv_set_power_well(dev_priv
, power_well
, true);
1022 vlv_display_power_well_init(dev_priv
);
1025 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
1026 struct i915_power_well
*power_well
)
1028 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
1030 vlv_display_power_well_deinit(dev_priv
);
1032 vlv_set_power_well(dev_priv
, power_well
, false);
1035 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
1036 struct i915_power_well
*power_well
)
1038 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
1040 /* since ref/cri clock was enabled */
1041 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1043 vlv_set_power_well(dev_priv
, power_well
, true);
1046 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1047 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1048 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1049 * b. The other bits such as sfr settings / modesel may all
1052 * This should only be done on init and resume from S3 with
1053 * both PLLs disabled, or we risk losing DPIO and PLL
1056 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1059 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
1060 struct i915_power_well
*power_well
)
1064 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
);
1066 for_each_pipe(dev_priv
, pipe
)
1067 assert_pll_disabled(dev_priv
, pipe
);
1069 /* Assert common reset */
1070 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) & ~DPIO_CMNRST
);
1072 vlv_set_power_well(dev_priv
, power_well
, false);
1075 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1077 static struct i915_power_well
*lookup_power_well(struct drm_i915_private
*dev_priv
,
1080 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1083 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
1084 struct i915_power_well
*power_well
;
1086 power_well
= &power_domains
->power_wells
[i
];
1087 if (power_well
->data
== power_well_id
)
1094 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1096 static void assert_chv_phy_status(struct drm_i915_private
*dev_priv
)
1098 struct i915_power_well
*cmn_bc
=
1099 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
1100 struct i915_power_well
*cmn_d
=
1101 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_D
);
1102 u32 phy_control
= dev_priv
->chv_phy_control
;
1104 u32 phy_status_mask
= 0xffffffff;
1108 * The BIOS can leave the PHY is some weird state
1109 * where it doesn't fully power down some parts.
1110 * Disable the asserts until the PHY has been fully
1111 * reset (ie. the power well has been disabled at
1114 if (!dev_priv
->chv_phy_assert
[DPIO_PHY0
])
1115 phy_status_mask
&= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH0
) |
1116 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 0) |
1117 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 1) |
1118 PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH1
) |
1119 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 0) |
1120 PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 1));
1122 if (!dev_priv
->chv_phy_assert
[DPIO_PHY1
])
1123 phy_status_mask
&= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1
, DPIO_CH0
) |
1124 PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 0) |
1125 PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 1));
1127 if (cmn_bc
->ops
->is_enabled(dev_priv
, cmn_bc
)) {
1128 phy_status
|= PHY_POWERGOOD(DPIO_PHY0
);
1130 /* this assumes override is only used to enable lanes */
1131 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH0
)) == 0)
1132 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH0
);
1134 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH1
)) == 0)
1135 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
);
1137 /* CL1 is on whenever anything is on in either channel */
1138 if (BITS_SET(phy_control
,
1139 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH0
) |
1140 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
)))
1141 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH0
);
1144 * The DPLLB check accounts for the pipe B + port A usage
1145 * with CL2 powered up but all the lanes in the second channel
1148 if (BITS_SET(phy_control
,
1149 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0
, DPIO_CH1
)) &&
1150 (I915_READ(DPLL(PIPE_B
)) & DPLL_VCO_ENABLE
) == 0)
1151 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY0
, DPIO_CH1
);
1153 if (BITS_SET(phy_control
,
1154 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0
, DPIO_CH0
)))
1155 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 0);
1156 if (BITS_SET(phy_control
,
1157 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0
, DPIO_CH0
)))
1158 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH0
, 1);
1160 if (BITS_SET(phy_control
,
1161 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0
, DPIO_CH1
)))
1162 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 0);
1163 if (BITS_SET(phy_control
,
1164 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0
, DPIO_CH1
)))
1165 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY0
, DPIO_CH1
, 1);
1168 if (cmn_d
->ops
->is_enabled(dev_priv
, cmn_d
)) {
1169 phy_status
|= PHY_POWERGOOD(DPIO_PHY1
);
1171 /* this assumes override is only used to enable lanes */
1172 if ((phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1
, DPIO_CH0
)) == 0)
1173 phy_control
|= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1
, DPIO_CH0
);
1175 if (BITS_SET(phy_control
,
1176 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1
, DPIO_CH0
)))
1177 phy_status
|= PHY_STATUS_CMN_LDO(DPIO_PHY1
, DPIO_CH0
);
1179 if (BITS_SET(phy_control
,
1180 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1
, DPIO_CH0
)))
1181 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 0);
1182 if (BITS_SET(phy_control
,
1183 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1
, DPIO_CH0
)))
1184 phy_status
|= PHY_STATUS_SPLINE_LDO(DPIO_PHY1
, DPIO_CH0
, 1);
1187 phy_status
&= phy_status_mask
;
1190 * The PHY may be busy with some initial calibration and whatnot,
1191 * so the power state can take a while to actually change.
1193 if (wait_for((tmp
= I915_READ(DISPLAY_PHY_STATUS
) & phy_status_mask
) == phy_status
, 10))
1194 WARN(phy_status
!= tmp
,
1195 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1196 tmp
, phy_status
, dev_priv
->chv_phy_control
);
1201 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
*dev_priv
,
1202 struct i915_power_well
*power_well
)
1208 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
1209 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
1211 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1219 /* since ref/cri clock was enabled */
1220 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1221 vlv_set_power_well(dev_priv
, power_well
, true);
1223 /* Poll for phypwrgood signal */
1224 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) & PHY_POWERGOOD(phy
), 1))
1225 DRM_ERROR("Display PHY %d is not power up\n", phy
);
1227 mutex_lock(&dev_priv
->sb_lock
);
1229 /* Enable dynamic power down */
1230 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW28
);
1231 tmp
|= DPIO_DYNPWRDOWNEN_CH0
| DPIO_CL1POWERDOWNEN
|
1232 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ
;
1233 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW28
, tmp
);
1235 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1236 tmp
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW6_CH1
);
1237 tmp
|= DPIO_DYNPWRDOWNEN_CH1
;
1238 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW6_CH1
, tmp
);
1241 * Force the non-existing CL2 off. BXT does this
1242 * too, so maybe it saves some power even though
1243 * CL2 doesn't exist?
1245 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW30
);
1246 tmp
|= DPIO_CL2_LDOFUSE_PWRENB
;
1247 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW30
, tmp
);
1250 mutex_unlock(&dev_priv
->sb_lock
);
1252 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(phy
);
1253 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1255 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1256 phy
, dev_priv
->chv_phy_control
);
1258 assert_chv_phy_status(dev_priv
);
1261 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
*dev_priv
,
1262 struct i915_power_well
*power_well
)
1266 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_BC
&&
1267 power_well
->data
!= PUNIT_POWER_WELL_DPIO_CMN_D
);
1269 if (power_well
->data
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
1271 assert_pll_disabled(dev_priv
, PIPE_A
);
1272 assert_pll_disabled(dev_priv
, PIPE_B
);
1275 assert_pll_disabled(dev_priv
, PIPE_C
);
1278 dev_priv
->chv_phy_control
&= ~PHY_COM_LANE_RESET_DEASSERT(phy
);
1279 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1281 vlv_set_power_well(dev_priv
, power_well
, false);
1283 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1284 phy
, dev_priv
->chv_phy_control
);
1286 /* PHY is fully reset now, so we can enable the PHY state asserts */
1287 dev_priv
->chv_phy_assert
[phy
] = true;
1289 assert_chv_phy_status(dev_priv
);
1292 static void assert_chv_phy_powergate(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1293 enum dpio_channel ch
, bool override
, unsigned int mask
)
1295 enum pipe pipe
= phy
== DPIO_PHY0
? PIPE_A
: PIPE_C
;
1296 u32 reg
, val
, expected
, actual
;
1299 * The BIOS can leave the PHY is some weird state
1300 * where it doesn't fully power down some parts.
1301 * Disable the asserts until the PHY has been fully
1302 * reset (ie. the power well has been disabled at
1305 if (!dev_priv
->chv_phy_assert
[phy
])
1309 reg
= _CHV_CMN_DW0_CH0
;
1311 reg
= _CHV_CMN_DW6_CH1
;
1313 mutex_lock(&dev_priv
->sb_lock
);
1314 val
= vlv_dpio_read(dev_priv
, pipe
, reg
);
1315 mutex_unlock(&dev_priv
->sb_lock
);
1318 * This assumes !override is only used when the port is disabled.
1319 * All lanes should power down even without the override when
1320 * the port is disabled.
1322 if (!override
|| mask
== 0xf) {
1323 expected
= DPIO_ALLDL_POWERDOWN
| DPIO_ANYDL_POWERDOWN
;
1325 * If CH1 common lane is not active anymore
1326 * (eg. for pipe B DPLL) the entire channel will
1327 * shut down, which causes the common lane registers
1328 * to read as 0. That means we can't actually check
1329 * the lane power down status bits, but as the entire
1330 * register reads as 0 it's a good indication that the
1331 * channel is indeed entirely powered down.
1333 if (ch
== DPIO_CH1
&& val
== 0)
1335 } else if (mask
!= 0x0) {
1336 expected
= DPIO_ANYDL_POWERDOWN
;
1342 actual
= val
>> DPIO_ANYDL_POWERDOWN_SHIFT_CH0
;
1344 actual
= val
>> DPIO_ANYDL_POWERDOWN_SHIFT_CH1
;
1345 actual
&= DPIO_ALLDL_POWERDOWN
| DPIO_ANYDL_POWERDOWN
;
1347 WARN(actual
!= expected
,
1348 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1349 !!(actual
& DPIO_ALLDL_POWERDOWN
), !!(actual
& DPIO_ANYDL_POWERDOWN
),
1350 !!(expected
& DPIO_ALLDL_POWERDOWN
), !!(expected
& DPIO_ANYDL_POWERDOWN
),
1354 bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv
, enum dpio_phy phy
,
1355 enum dpio_channel ch
, bool override
)
1357 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1360 mutex_lock(&power_domains
->lock
);
1362 was_override
= dev_priv
->chv_phy_control
& PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1364 if (override
== was_override
)
1368 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1370 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1372 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1374 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1375 phy
, ch
, dev_priv
->chv_phy_control
);
1377 assert_chv_phy_status(dev_priv
);
1380 mutex_unlock(&power_domains
->lock
);
1382 return was_override
;
1385 void chv_phy_powergate_lanes(struct intel_encoder
*encoder
,
1386 bool override
, unsigned int mask
)
1388 struct drm_i915_private
*dev_priv
= to_i915(encoder
->base
.dev
);
1389 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1390 enum dpio_phy phy
= vlv_dport_to_phy(enc_to_dig_port(&encoder
->base
));
1391 enum dpio_channel ch
= vlv_dport_to_channel(enc_to_dig_port(&encoder
->base
));
1393 mutex_lock(&power_domains
->lock
);
1395 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy
, ch
);
1396 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD(mask
, phy
, ch
);
1399 dev_priv
->chv_phy_control
|= PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1401 dev_priv
->chv_phy_control
&= ~PHY_CH_POWER_DOWN_OVRD_EN(phy
, ch
);
1403 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
1405 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1406 phy
, ch
, mask
, dev_priv
->chv_phy_control
);
1408 assert_chv_phy_status(dev_priv
);
1410 assert_chv_phy_powergate(dev_priv
, phy
, ch
, override
, mask
);
1412 mutex_unlock(&power_domains
->lock
);
1415 static bool chv_pipe_power_well_enabled(struct drm_i915_private
*dev_priv
,
1416 struct i915_power_well
*power_well
)
1418 enum pipe pipe
= power_well
->data
;
1422 mutex_lock(&dev_priv
->rps
.hw_lock
);
1424 state
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSS_MASK(pipe
);
1426 * We only ever set the power-on and power-gate states, anything
1427 * else is unexpected.
1429 WARN_ON(state
!= DP_SSS_PWR_ON(pipe
) && state
!= DP_SSS_PWR_GATE(pipe
));
1430 enabled
= state
== DP_SSS_PWR_ON(pipe
);
1433 * A transient state at this point would mean some unexpected party
1434 * is poking at the power controls too.
1436 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) & DP_SSC_MASK(pipe
);
1437 WARN_ON(ctrl
<< 16 != state
);
1439 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1444 static void chv_set_pipe_power_well(struct drm_i915_private
*dev_priv
,
1445 struct i915_power_well
*power_well
,
1448 enum pipe pipe
= power_well
->data
;
1452 state
= enable
? DP_SSS_PWR_ON(pipe
) : DP_SSS_PWR_GATE(pipe
);
1454 mutex_lock(&dev_priv
->rps
.hw_lock
);
1457 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1462 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
1463 ctrl
&= ~DP_SSC_MASK(pipe
);
1464 ctrl
|= enable
? DP_SSC_PWR_ON(pipe
) : DP_SSC_PWR_GATE(pipe
);
1465 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, ctrl
);
1467 if (wait_for(COND
, 100))
1468 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1470 vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
));
1475 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1478 static void chv_pipe_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
1479 struct i915_power_well
*power_well
)
1481 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1483 chv_set_pipe_power_well(dev_priv
, power_well
, power_well
->count
> 0);
1486 static void chv_pipe_power_well_enable(struct drm_i915_private
*dev_priv
,
1487 struct i915_power_well
*power_well
)
1489 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1491 chv_set_pipe_power_well(dev_priv
, power_well
, true);
1493 vlv_display_power_well_init(dev_priv
);
1496 static void chv_pipe_power_well_disable(struct drm_i915_private
*dev_priv
,
1497 struct i915_power_well
*power_well
)
1499 WARN_ON_ONCE(power_well
->data
!= PIPE_A
);
1501 vlv_display_power_well_deinit(dev_priv
);
1503 chv_set_pipe_power_well(dev_priv
, power_well
, false);
1507 __intel_display_power_get_domain(struct drm_i915_private
*dev_priv
,
1508 enum intel_display_power_domain domain
)
1510 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1511 struct i915_power_well
*power_well
;
1514 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
1515 if (!power_well
->count
++)
1516 intel_power_well_enable(dev_priv
, power_well
);
1519 power_domains
->domain_use_count
[domain
]++;
1523 * intel_display_power_get - grab a power domain reference
1524 * @dev_priv: i915 device instance
1525 * @domain: power domain to reference
1527 * This function grabs a power domain reference for @domain and ensures that the
1528 * power domain and all its parents are powered up. Therefore users should only
1529 * grab a reference to the innermost power domain they need.
1531 * Any power domain reference obtained by this function must have a symmetric
1532 * call to intel_display_power_put() to release the reference again.
1534 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
1535 enum intel_display_power_domain domain
)
1537 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1539 intel_runtime_pm_get(dev_priv
);
1541 mutex_lock(&power_domains
->lock
);
1543 __intel_display_power_get_domain(dev_priv
, domain
);
1545 mutex_unlock(&power_domains
->lock
);
1549 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1550 * @dev_priv: i915 device instance
1551 * @domain: power domain to reference
1553 * This function grabs a power domain reference for @domain and ensures that the
1554 * power domain and all its parents are powered up. Therefore users should only
1555 * grab a reference to the innermost power domain they need.
1557 * Any power domain reference obtained by this function must have a symmetric
1558 * call to intel_display_power_put() to release the reference again.
1560 bool intel_display_power_get_if_enabled(struct drm_i915_private
*dev_priv
,
1561 enum intel_display_power_domain domain
)
1563 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
1566 if (!intel_runtime_pm_get_if_in_use(dev_priv
))
1569 mutex_lock(&power_domains
->lock
);
1571 if (__intel_display_power_is_enabled(dev_priv
, domain
)) {
1572 __intel_display_power_get_domain(dev_priv
, domain
);
1578 mutex_unlock(&power_domains
->lock
);
1581 intel_runtime_pm_put(dev_priv
);
1587 * intel_display_power_put - release a power domain reference
1588 * @dev_priv: i915 device instance
1589 * @domain: power domain to reference
1591 * This function drops the power domain reference obtained by
1592 * intel_display_power_get() and might power down the corresponding hardware
1593 * block right away if this is the last reference.
1595 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
1596 enum intel_display_power_domain domain
)
1598 struct i915_power_domains
*power_domains
;
1599 struct i915_power_well
*power_well
;
1602 power_domains
= &dev_priv
->power_domains
;
1604 mutex_lock(&power_domains
->lock
);
1606 WARN(!power_domains
->domain_use_count
[domain
],
1607 "Use count on domain %s is already zero\n",
1608 intel_display_power_domain_str(domain
));
1609 power_domains
->domain_use_count
[domain
]--;
1611 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
1612 WARN(!power_well
->count
,
1613 "Use count on power well %s is already zero",
1616 if (!--power_well
->count
)
1617 intel_power_well_disable(dev_priv
, power_well
);
1620 mutex_unlock(&power_domains
->lock
);
1622 intel_runtime_pm_put(dev_priv
);
1625 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1626 BIT(POWER_DOMAIN_PIPE_A) | \
1627 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1628 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1629 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1630 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1631 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1632 BIT(POWER_DOMAIN_PORT_CRT) | \
1633 BIT(POWER_DOMAIN_PLLS) | \
1634 BIT(POWER_DOMAIN_AUX_A) | \
1635 BIT(POWER_DOMAIN_AUX_B) | \
1636 BIT(POWER_DOMAIN_AUX_C) | \
1637 BIT(POWER_DOMAIN_AUX_D) | \
1638 BIT(POWER_DOMAIN_GMBUS) | \
1639 BIT(POWER_DOMAIN_INIT))
1640 #define HSW_DISPLAY_POWER_DOMAINS ( \
1641 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1642 BIT(POWER_DOMAIN_INIT))
1644 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1645 HSW_ALWAYS_ON_POWER_DOMAINS | \
1646 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1647 #define BDW_DISPLAY_POWER_DOMAINS ( \
1648 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1649 BIT(POWER_DOMAIN_INIT))
1651 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1652 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1654 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1655 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1656 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1657 BIT(POWER_DOMAIN_PORT_CRT) | \
1658 BIT(POWER_DOMAIN_AUX_B) | \
1659 BIT(POWER_DOMAIN_AUX_C) | \
1660 BIT(POWER_DOMAIN_INIT))
1662 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1663 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1664 BIT(POWER_DOMAIN_AUX_B) | \
1665 BIT(POWER_DOMAIN_INIT))
1667 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1668 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1669 BIT(POWER_DOMAIN_AUX_B) | \
1670 BIT(POWER_DOMAIN_INIT))
1672 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1673 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1674 BIT(POWER_DOMAIN_AUX_C) | \
1675 BIT(POWER_DOMAIN_INIT))
1677 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1678 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1679 BIT(POWER_DOMAIN_AUX_C) | \
1680 BIT(POWER_DOMAIN_INIT))
1682 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1683 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1684 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1685 BIT(POWER_DOMAIN_AUX_B) | \
1686 BIT(POWER_DOMAIN_AUX_C) | \
1687 BIT(POWER_DOMAIN_INIT))
1689 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1690 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1691 BIT(POWER_DOMAIN_AUX_D) | \
1692 BIT(POWER_DOMAIN_INIT))
1694 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
1695 .sync_hw
= i9xx_always_on_power_well_noop
,
1696 .enable
= i9xx_always_on_power_well_noop
,
1697 .disable
= i9xx_always_on_power_well_noop
,
1698 .is_enabled
= i9xx_always_on_power_well_enabled
,
1701 static const struct i915_power_well_ops chv_pipe_power_well_ops
= {
1702 .sync_hw
= chv_pipe_power_well_sync_hw
,
1703 .enable
= chv_pipe_power_well_enable
,
1704 .disable
= chv_pipe_power_well_disable
,
1705 .is_enabled
= chv_pipe_power_well_enabled
,
1708 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
= {
1709 .sync_hw
= vlv_power_well_sync_hw
,
1710 .enable
= chv_dpio_cmn_power_well_enable
,
1711 .disable
= chv_dpio_cmn_power_well_disable
,
1712 .is_enabled
= vlv_power_well_enabled
,
1715 static struct i915_power_well i9xx_always_on_power_well
[] = {
1717 .name
= "always-on",
1719 .domains
= POWER_DOMAIN_MASK
,
1720 .ops
= &i9xx_always_on_power_well_ops
,
1724 static const struct i915_power_well_ops hsw_power_well_ops
= {
1725 .sync_hw
= hsw_power_well_sync_hw
,
1726 .enable
= hsw_power_well_enable
,
1727 .disable
= hsw_power_well_disable
,
1728 .is_enabled
= hsw_power_well_enabled
,
1731 static const struct i915_power_well_ops skl_power_well_ops
= {
1732 .sync_hw
= skl_power_well_sync_hw
,
1733 .enable
= skl_power_well_enable
,
1734 .disable
= skl_power_well_disable
,
1735 .is_enabled
= skl_power_well_enabled
,
1738 static const struct i915_power_well_ops gen9_dc_off_power_well_ops
= {
1739 .sync_hw
= gen9_dc_off_power_well_sync_hw
,
1740 .enable
= gen9_dc_off_power_well_enable
,
1741 .disable
= gen9_dc_off_power_well_disable
,
1742 .is_enabled
= gen9_dc_off_power_well_enabled
,
1745 static struct i915_power_well hsw_power_wells
[] = {
1747 .name
= "always-on",
1749 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
1750 .ops
= &i9xx_always_on_power_well_ops
,
1754 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
1755 .ops
= &hsw_power_well_ops
,
1759 static struct i915_power_well bdw_power_wells
[] = {
1761 .name
= "always-on",
1763 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
1764 .ops
= &i9xx_always_on_power_well_ops
,
1768 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
1769 .ops
= &hsw_power_well_ops
,
1773 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
1774 .sync_hw
= vlv_power_well_sync_hw
,
1775 .enable
= vlv_display_power_well_enable
,
1776 .disable
= vlv_display_power_well_disable
,
1777 .is_enabled
= vlv_power_well_enabled
,
1780 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
= {
1781 .sync_hw
= vlv_power_well_sync_hw
,
1782 .enable
= vlv_dpio_cmn_power_well_enable
,
1783 .disable
= vlv_dpio_cmn_power_well_disable
,
1784 .is_enabled
= vlv_power_well_enabled
,
1787 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
1788 .sync_hw
= vlv_power_well_sync_hw
,
1789 .enable
= vlv_power_well_enable
,
1790 .disable
= vlv_power_well_disable
,
1791 .is_enabled
= vlv_power_well_enabled
,
1794 static struct i915_power_well vlv_power_wells
[] = {
1796 .name
= "always-on",
1798 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
1799 .ops
= &i9xx_always_on_power_well_ops
,
1800 .data
= PUNIT_POWER_WELL_ALWAYS_ON
,
1804 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
1805 .data
= PUNIT_POWER_WELL_DISP2D
,
1806 .ops
= &vlv_display_power_well_ops
,
1809 .name
= "dpio-tx-b-01",
1810 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1811 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1812 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1813 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1814 .ops
= &vlv_dpio_power_well_ops
,
1815 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
1818 .name
= "dpio-tx-b-23",
1819 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1820 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1821 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1822 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1823 .ops
= &vlv_dpio_power_well_ops
,
1824 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
1827 .name
= "dpio-tx-c-01",
1828 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1829 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1830 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1831 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1832 .ops
= &vlv_dpio_power_well_ops
,
1833 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
1836 .name
= "dpio-tx-c-23",
1837 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
1838 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
1839 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
1840 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
1841 .ops
= &vlv_dpio_power_well_ops
,
1842 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
1845 .name
= "dpio-common",
1846 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
1847 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
1848 .ops
= &vlv_dpio_cmn_power_well_ops
,
1852 static struct i915_power_well chv_power_wells
[] = {
1854 .name
= "always-on",
1856 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
1857 .ops
= &i9xx_always_on_power_well_ops
,
1862 * Pipe A power well is the new disp2d well. Pipe B and C
1863 * power wells don't actually exist. Pipe A power well is
1864 * required for any pipe to work.
1866 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
1868 .ops
= &chv_pipe_power_well_ops
,
1871 .name
= "dpio-common-bc",
1872 .domains
= CHV_DPIO_CMN_BC_POWER_DOMAINS
,
1873 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
1874 .ops
= &chv_dpio_cmn_power_well_ops
,
1877 .name
= "dpio-common-d",
1878 .domains
= CHV_DPIO_CMN_D_POWER_DOMAINS
,
1879 .data
= PUNIT_POWER_WELL_DPIO_CMN_D
,
1880 .ops
= &chv_dpio_cmn_power_well_ops
,
1884 bool intel_display_power_well_is_enabled(struct drm_i915_private
*dev_priv
,
1887 struct i915_power_well
*power_well
;
1890 power_well
= lookup_power_well(dev_priv
, power_well_id
);
1891 ret
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
1896 static struct i915_power_well skl_power_wells
[] = {
1898 .name
= "always-on",
1900 .domains
= SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS
,
1901 .ops
= &i9xx_always_on_power_well_ops
,
1902 .data
= SKL_DISP_PW_ALWAYS_ON
,
1905 .name
= "power well 1",
1906 /* Handled by the DMC firmware */
1908 .ops
= &skl_power_well_ops
,
1909 .data
= SKL_DISP_PW_1
,
1912 .name
= "MISC IO power well",
1913 /* Handled by the DMC firmware */
1915 .ops
= &skl_power_well_ops
,
1916 .data
= SKL_DISP_PW_MISC_IO
,
1920 .domains
= SKL_DISPLAY_DC_OFF_POWER_DOMAINS
,
1921 .ops
= &gen9_dc_off_power_well_ops
,
1922 .data
= SKL_DISP_PW_DC_OFF
,
1925 .name
= "power well 2",
1926 .domains
= SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS
,
1927 .ops
= &skl_power_well_ops
,
1928 .data
= SKL_DISP_PW_2
,
1931 .name
= "DDI A/E power well",
1932 .domains
= SKL_DISPLAY_DDI_A_E_POWER_DOMAINS
,
1933 .ops
= &skl_power_well_ops
,
1934 .data
= SKL_DISP_PW_DDI_A_E
,
1937 .name
= "DDI B power well",
1938 .domains
= SKL_DISPLAY_DDI_B_POWER_DOMAINS
,
1939 .ops
= &skl_power_well_ops
,
1940 .data
= SKL_DISP_PW_DDI_B
,
1943 .name
= "DDI C power well",
1944 .domains
= SKL_DISPLAY_DDI_C_POWER_DOMAINS
,
1945 .ops
= &skl_power_well_ops
,
1946 .data
= SKL_DISP_PW_DDI_C
,
1949 .name
= "DDI D power well",
1950 .domains
= SKL_DISPLAY_DDI_D_POWER_DOMAINS
,
1951 .ops
= &skl_power_well_ops
,
1952 .data
= SKL_DISP_PW_DDI_D
,
1956 void skl_pw1_misc_io_init(struct drm_i915_private
*dev_priv
)
1958 struct i915_power_well
*well
;
1960 if (!(IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)))
1963 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_1
);
1964 intel_power_well_enable(dev_priv
, well
);
1966 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_MISC_IO
);
1967 intel_power_well_enable(dev_priv
, well
);
1970 void skl_pw1_misc_io_fini(struct drm_i915_private
*dev_priv
)
1972 struct i915_power_well
*well
;
1974 if (!(IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)))
1977 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_1
);
1978 intel_power_well_disable(dev_priv
, well
);
1980 well
= lookup_power_well(dev_priv
, SKL_DISP_PW_MISC_IO
);
1981 intel_power_well_disable(dev_priv
, well
);
1984 static struct i915_power_well bxt_power_wells
[] = {
1986 .name
= "always-on",
1988 .domains
= BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS
,
1989 .ops
= &i9xx_always_on_power_well_ops
,
1992 .name
= "power well 1",
1993 .domains
= BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS
,
1994 .ops
= &skl_power_well_ops
,
1995 .data
= SKL_DISP_PW_1
,
1999 .domains
= BXT_DISPLAY_DC_OFF_POWER_DOMAINS
,
2000 .ops
= &gen9_dc_off_power_well_ops
,
2001 .data
= SKL_DISP_PW_DC_OFF
,
2004 .name
= "power well 2",
2005 .domains
= BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS
,
2006 .ops
= &skl_power_well_ops
,
2007 .data
= SKL_DISP_PW_2
,
2012 sanitize_disable_power_well_option(const struct drm_i915_private
*dev_priv
,
2013 int disable_power_well
)
2015 if (disable_power_well
>= 0)
2016 return !!disable_power_well
;
2018 if (IS_BROXTON(dev_priv
)) {
2019 DRM_DEBUG_KMS("Disabling display power well support\n");
2026 #define set_power_wells(power_domains, __power_wells) ({ \
2027 (power_domains)->power_wells = (__power_wells); \
2028 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2032 * intel_power_domains_init - initializes the power domain structures
2033 * @dev_priv: i915 device instance
2035 * Initializes the power domain structures for @dev_priv depending upon the
2036 * supported platform.
2038 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
2040 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2042 i915
.disable_power_well
= sanitize_disable_power_well_option(dev_priv
,
2043 i915
.disable_power_well
);
2045 BUILD_BUG_ON(POWER_DOMAIN_NUM
> 31);
2047 mutex_init(&power_domains
->lock
);
2050 * The enabling order will be from lower to higher indexed wells,
2051 * the disabling order is reversed.
2053 if (IS_HASWELL(dev_priv
->dev
)) {
2054 set_power_wells(power_domains
, hsw_power_wells
);
2055 } else if (IS_BROADWELL(dev_priv
->dev
)) {
2056 set_power_wells(power_domains
, bdw_power_wells
);
2057 } else if (IS_SKYLAKE(dev_priv
->dev
) || IS_KABYLAKE(dev_priv
->dev
)) {
2058 set_power_wells(power_domains
, skl_power_wells
);
2059 } else if (IS_BROXTON(dev_priv
->dev
)) {
2060 set_power_wells(power_domains
, bxt_power_wells
);
2061 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
2062 set_power_wells(power_domains
, chv_power_wells
);
2063 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
2064 set_power_wells(power_domains
, vlv_power_wells
);
2066 set_power_wells(power_domains
, i9xx_always_on_power_well
);
2073 * intel_power_domains_fini - finalizes the power domain structures
2074 * @dev_priv: i915 device instance
2076 * Finalizes the power domain structures for @dev_priv depending upon the
2077 * supported platform. This function also disables runtime pm and ensures that
2078 * the device stays powered up so that the driver can be reloaded.
2080 void intel_power_domains_fini(struct drm_i915_private
*dev_priv
)
2082 struct device
*device
= &dev_priv
->dev
->pdev
->dev
;
2085 * The i915.ko module is still not prepared to be loaded when
2086 * the power well is not enabled, so just enable it in case
2087 * we're going to unload/reload.
2088 * The following also reacquires the RPM reference the core passed
2089 * to the driver during loading, which is dropped in
2090 * intel_runtime_pm_enable(). We have to hand back the control of the
2091 * device to the core with this reference held.
2093 intel_display_set_init_power(dev_priv
, true);
2095 /* Remove the refcount we took to keep power well support disabled. */
2096 if (!i915
.disable_power_well
)
2097 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
2100 * Remove the refcount we took in intel_runtime_pm_enable() in case
2101 * the platform doesn't support runtime PM.
2103 if (!HAS_RUNTIME_PM(dev_priv
))
2104 pm_runtime_put(device
);
2107 static void intel_power_domains_sync_hw(struct drm_i915_private
*dev_priv
)
2109 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2110 struct i915_power_well
*power_well
;
2113 mutex_lock(&power_domains
->lock
);
2114 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
) {
2115 power_well
->ops
->sync_hw(dev_priv
, power_well
);
2116 power_well
->hw_enabled
= power_well
->ops
->is_enabled(dev_priv
,
2119 mutex_unlock(&power_domains
->lock
);
2122 static void skl_display_core_init(struct drm_i915_private
*dev_priv
,
2125 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2128 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
2130 /* enable PCH reset handshake */
2131 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
2132 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
2134 /* enable PG1 and Misc I/O */
2135 mutex_lock(&power_domains
->lock
);
2136 skl_pw1_misc_io_init(dev_priv
);
2137 mutex_unlock(&power_domains
->lock
);
2142 skl_init_cdclk(dev_priv
);
2144 if (dev_priv
->csr
.dmc_payload
&& intel_csr_load_program(dev_priv
))
2145 gen9_set_dc_state_debugmask(dev_priv
);
2148 static void skl_display_core_uninit(struct drm_i915_private
*dev_priv
)
2150 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2152 gen9_set_dc_state(dev_priv
, DC_STATE_DISABLE
);
2154 skl_uninit_cdclk(dev_priv
);
2156 /* The spec doesn't call for removing the reset handshake flag */
2157 /* disable PG1 and Misc I/O */
2158 mutex_lock(&power_domains
->lock
);
2159 skl_pw1_misc_io_fini(dev_priv
);
2160 mutex_unlock(&power_domains
->lock
);
2163 static void chv_phy_control_init(struct drm_i915_private
*dev_priv
)
2165 struct i915_power_well
*cmn_bc
=
2166 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
2167 struct i915_power_well
*cmn_d
=
2168 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_D
);
2171 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2172 * workaround never ever read DISPLAY_PHY_CONTROL, and
2173 * instead maintain a shadow copy ourselves. Use the actual
2174 * power well state and lane status to reconstruct the
2175 * expected initial value.
2177 dev_priv
->chv_phy_control
=
2178 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS
, DPIO_PHY0
) |
2179 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS
, DPIO_PHY1
) |
2180 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY0
, DPIO_CH0
) |
2181 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY0
, DPIO_CH1
) |
2182 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR
, DPIO_PHY1
, DPIO_CH0
);
2185 * If all lanes are disabled we leave the override disabled
2186 * with all power down bits cleared to match the state we
2187 * would use after disabling the port. Otherwise enable the
2188 * override and set the lane powerdown bits accding to the
2189 * current lane status.
2191 if (cmn_bc
->ops
->is_enabled(dev_priv
, cmn_bc
)) {
2192 uint32_t status
= I915_READ(DPLL(PIPE_A
));
2195 mask
= status
& DPLL_PORTB_READY_MASK
;
2199 dev_priv
->chv_phy_control
|=
2200 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH0
);
2202 dev_priv
->chv_phy_control
|=
2203 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY0
, DPIO_CH0
);
2205 mask
= (status
& DPLL_PORTC_READY_MASK
) >> 4;
2209 dev_priv
->chv_phy_control
|=
2210 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0
, DPIO_CH1
);
2212 dev_priv
->chv_phy_control
|=
2213 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY0
, DPIO_CH1
);
2215 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0
);
2217 dev_priv
->chv_phy_assert
[DPIO_PHY0
] = false;
2219 dev_priv
->chv_phy_assert
[DPIO_PHY0
] = true;
2222 if (cmn_d
->ops
->is_enabled(dev_priv
, cmn_d
)) {
2223 uint32_t status
= I915_READ(DPIO_PHY_STATUS
);
2226 mask
= status
& DPLL_PORTD_READY_MASK
;
2231 dev_priv
->chv_phy_control
|=
2232 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1
, DPIO_CH0
);
2234 dev_priv
->chv_phy_control
|=
2235 PHY_CH_POWER_DOWN_OVRD(mask
, DPIO_PHY1
, DPIO_CH0
);
2237 dev_priv
->chv_phy_control
|= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1
);
2239 dev_priv
->chv_phy_assert
[DPIO_PHY1
] = false;
2241 dev_priv
->chv_phy_assert
[DPIO_PHY1
] = true;
2244 I915_WRITE(DISPLAY_PHY_CONTROL
, dev_priv
->chv_phy_control
);
2246 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2247 dev_priv
->chv_phy_control
);
2250 static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv
)
2252 struct i915_power_well
*cmn
=
2253 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
);
2254 struct i915_power_well
*disp2d
=
2255 lookup_power_well(dev_priv
, PUNIT_POWER_WELL_DISP2D
);
2257 /* If the display might be already active skip this */
2258 if (cmn
->ops
->is_enabled(dev_priv
, cmn
) &&
2259 disp2d
->ops
->is_enabled(dev_priv
, disp2d
) &&
2260 I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
2263 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2265 /* cmnlane needs DPLL registers */
2266 disp2d
->ops
->enable(dev_priv
, disp2d
);
2269 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2270 * Need to assert and de-assert PHY SB reset by gating the
2271 * common lane power, then un-gating it.
2272 * Simply ungating isn't enough to reset the PHY enough to get
2273 * ports and lanes running.
2275 cmn
->ops
->disable(dev_priv
, cmn
);
2279 * intel_power_domains_init_hw - initialize hardware power domain state
2280 * @dev_priv: i915 device instance
2282 * This function initializes the hardware power domain state and enables all
2283 * power domains using intel_display_set_init_power().
2285 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
, bool resume
)
2287 struct drm_device
*dev
= dev_priv
->dev
;
2288 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2290 power_domains
->initializing
= true;
2292 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
2293 skl_display_core_init(dev_priv
, resume
);
2294 } else if (IS_CHERRYVIEW(dev
)) {
2295 mutex_lock(&power_domains
->lock
);
2296 chv_phy_control_init(dev_priv
);
2297 mutex_unlock(&power_domains
->lock
);
2298 } else if (IS_VALLEYVIEW(dev
)) {
2299 mutex_lock(&power_domains
->lock
);
2300 vlv_cmnlane_wa(dev_priv
);
2301 mutex_unlock(&power_domains
->lock
);
2304 /* For now, we need the power well to be always enabled. */
2305 intel_display_set_init_power(dev_priv
, true);
2306 /* Disable power support if the user asked so. */
2307 if (!i915
.disable_power_well
)
2308 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
2309 intel_power_domains_sync_hw(dev_priv
);
2310 power_domains
->initializing
= false;
2314 * intel_power_domains_suspend - suspend power domain state
2315 * @dev_priv: i915 device instance
2317 * This function prepares the hardware power domain state before entering
2318 * system suspend. It must be paired with intel_power_domains_init_hw().
2320 void intel_power_domains_suspend(struct drm_i915_private
*dev_priv
)
2323 * Even if power well support was disabled we still want to disable
2324 * power wells while we are system suspended.
2326 if (!i915
.disable_power_well
)
2327 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
2329 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
2330 skl_display_core_uninit(dev_priv
);
2334 * intel_runtime_pm_get - grab a runtime pm reference
2335 * @dev_priv: i915 device instance
2337 * This function grabs a device-level runtime pm reference (mostly used for GEM
2338 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2340 * Any runtime pm reference obtained by this function must have a symmetric
2341 * call to intel_runtime_pm_put() to release the reference again.
2343 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
2345 struct drm_device
*dev
= dev_priv
->dev
;
2346 struct device
*device
= &dev
->pdev
->dev
;
2348 pm_runtime_get_sync(device
);
2350 atomic_inc(&dev_priv
->pm
.wakeref_count
);
2351 assert_rpm_wakelock_held(dev_priv
);
2355 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2356 * @dev_priv: i915 device instance
2358 * This function grabs a device-level runtime pm reference if the device is
2359 * already in use and ensures that it is powered up.
2361 * Any runtime pm reference obtained by this function must have a symmetric
2362 * call to intel_runtime_pm_put() to release the reference again.
2364 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private
*dev_priv
)
2366 struct drm_device
*dev
= dev_priv
->dev
;
2367 struct device
*device
= &dev
->pdev
->dev
;
2369 if (IS_ENABLED(CONFIG_PM
)) {
2370 int ret
= pm_runtime_get_if_in_use(device
);
2373 * In cases runtime PM is disabled by the RPM core and we get
2374 * an -EINVAL return value we are not supposed to call this
2375 * function, since the power state is undefined. This applies
2376 * atm to the late/early system suspend/resume handlers.
2378 WARN_ON_ONCE(ret
< 0);
2383 atomic_inc(&dev_priv
->pm
.wakeref_count
);
2384 assert_rpm_wakelock_held(dev_priv
);
2390 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2391 * @dev_priv: i915 device instance
2393 * This function grabs a device-level runtime pm reference (mostly used for GEM
2394 * code to ensure the GTT or GT is on).
2396 * It will _not_ power up the device but instead only check that it's powered
2397 * on. Therefore it is only valid to call this functions from contexts where
2398 * the device is known to be powered up and where trying to power it up would
2399 * result in hilarity and deadlocks. That pretty much means only the system
2400 * suspend/resume code where this is used to grab runtime pm references for
2401 * delayed setup down in work items.
2403 * Any runtime pm reference obtained by this function must have a symmetric
2404 * call to intel_runtime_pm_put() to release the reference again.
2406 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
2408 struct drm_device
*dev
= dev_priv
->dev
;
2409 struct device
*device
= &dev
->pdev
->dev
;
2411 assert_rpm_wakelock_held(dev_priv
);
2412 pm_runtime_get_noresume(device
);
2414 atomic_inc(&dev_priv
->pm
.wakeref_count
);
2418 * intel_runtime_pm_put - release a runtime pm reference
2419 * @dev_priv: i915 device instance
2421 * This function drops the device-level runtime pm reference obtained by
2422 * intel_runtime_pm_get() and might power down the corresponding
2423 * hardware block right away if this is the last reference.
2425 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
2427 struct drm_device
*dev
= dev_priv
->dev
;
2428 struct device
*device
= &dev
->pdev
->dev
;
2430 assert_rpm_wakelock_held(dev_priv
);
2431 if (atomic_dec_and_test(&dev_priv
->pm
.wakeref_count
))
2432 atomic_inc(&dev_priv
->pm
.atomic_seq
);
2434 pm_runtime_mark_last_busy(device
);
2435 pm_runtime_put_autosuspend(device
);
2439 * intel_runtime_pm_enable - enable runtime pm
2440 * @dev_priv: i915 device instance
2442 * This function enables runtime pm at the end of the driver load sequence.
2444 * Note that this function does currently not enable runtime pm for the
2445 * subordinate display power domains. That is only done on the first modeset
2446 * using intel_display_set_init_power().
2448 void intel_runtime_pm_enable(struct drm_i915_private
*dev_priv
)
2450 struct drm_device
*dev
= dev_priv
->dev
;
2451 struct device
*device
= &dev
->pdev
->dev
;
2453 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
2454 pm_runtime_mark_last_busy(device
);
2457 * Take a permanent reference to disable the RPM functionality and drop
2458 * it only when unloading the driver. Use the low level get/put helpers,
2459 * so the driver's own RPM reference tracking asserts also work on
2460 * platforms without RPM support.
2462 if (!HAS_RUNTIME_PM(dev
)) {
2463 pm_runtime_dont_use_autosuspend(device
);
2464 pm_runtime_get_sync(device
);
2466 pm_runtime_use_autosuspend(device
);
2470 * The core calls the driver load handler with an RPM reference held.
2471 * We drop that here and will reacquire it during unloading in
2472 * intel_power_domains_fini().
2474 pm_runtime_put_autosuspend(device
);